WO2017128854A1 - 移位寄存器及其驱动方法、驱动电路和显示装置 - Google Patents

移位寄存器及其驱动方法、驱动电路和显示装置 Download PDF

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Publication number
WO2017128854A1
WO2017128854A1 PCT/CN2016/107973 CN2016107973W WO2017128854A1 WO 2017128854 A1 WO2017128854 A1 WO 2017128854A1 CN 2016107973 W CN2016107973 W CN 2016107973W WO 2017128854 A1 WO2017128854 A1 WO 2017128854A1
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WIPO (PCT)
Prior art keywords
transistor
pull
signal
node
pole
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PCT/CN2016/107973
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English (en)
French (fr)
Inventor
古宏刚
邵贤杰
宋洁
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京东方科技集团股份有限公司
合肥京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/527,819 priority Critical patent/US10394372B2/en
Publication of WO2017128854A1 publication Critical patent/WO2017128854A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/0418—Control or interface arrangements specially adapted for digitisers for error correction or compensation, e.g. based on parallax, calibration or alignment
    • G06F3/04184—Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a shift register, a driving method thereof, a driving circuit, and a display device.
  • the driver of the display panel mainly includes a data driver and a gate driver.
  • the first stage shift register is connected to a gate line, and the driving signal is input through a plurality of cascaded gate drivers to realize progressive scanning of the pixel array.
  • the touch display panel is mainly divided into an external type and an embedded type.
  • the existing in-cell touch display panel is divided into an In Cell touch display panel and an On Cell touch display panel.
  • the On Cell touch display panel places the sensor on the outside of the display panel and attaches a protective glass.
  • the In Cell touch display substrate usually has sensors disposed on the array substrate side, or on the array substrate and the color film substrate side, and then forms a display panel, thereby implementing a touch function.
  • the In Cell touch display panel performs data transmission by scanning to implement the touch function.
  • the driving signal and the touch signal may interfere with each other, thereby affecting the touch function.
  • the present invention provides a shift register for a touch display panel, a driving method thereof, a driving circuit, and a display device, which are used to solve the mutual difference between the driving signal and the touch signal of the touch display panel in the prior art. Interference, which affects the touch function.
  • the present invention provides a shift register comprising:
  • a pull-up unit connected to the input end, the first voltage end, the second voltage end, the third voltage end, the second signal end, the reset end, the output end, the pull-down node, and the pull-up node, respectively, according to the input end And an input signal of the second signal end and the reset end and a potential of the pull-down node control a potential of the pull-up node;
  • a pull-down unit respectively connected to the first signal end, the third voltage end, the pull-up node, and the pull-down node, for controlling the potential of the pull-down node according to the input signal of the first signal end and the potential of the pull-up node;
  • the output unit is respectively connected to the third voltage end, the first signal end, the second signal end, the output end, the pull-down node, and the pull-up node, and is configured to input signals according to the first signal end and the second signal end, and The potential of the pull-down node and the pull-up node controls an output signal of the output.
  • the pull-up unit includes:
  • the input module is respectively connected to the input end, the first voltage end, and the pull-up node, and is configured to control a potential of the pull-up node according to an input signal of the input end;
  • a pull-up module is respectively connected to the third voltage terminal, the second signal terminal, the output terminal, the pull-down node, and the pull-up node, and is configured to control the pull-up according to the input signal of the second signal terminal and the potential of the pull-down node The potential of the node;
  • the reset module is respectively connected to the second voltage terminal, the reset terminal and the pull-up node, and is configured to control the potential of the pull-up node according to the input signal of the reset terminal.
  • the pull-down unit includes a sixth transistor and a second capacitor
  • a gate of the sixth transistor is connected to the pull-up node, a first pole of the sixth transistor is connected to the pull-down node, and a second pole of the sixth transistor is connected to the third voltage terminal;
  • the second capacitor is connected in parallel between the pull-down node and the first signal end.
  • the output unit includes a third transistor, a fourth transistor, and a fifth transistor;
  • a gate of the third transistor is connected to the pull-up node, a first pole of the third transistor is connected to the first signal end, and a second pole of the third transistor is connected to the output end;
  • a gate of the fourth transistor is connected to the second signal end, a first pole of the fourth transistor is connected to the output end, and a second pole of the fourth transistor is connected to the third voltage end ;
  • a gate of the fifth transistor is connected to the pull-down node, a first pole of the fifth transistor is connected to the output end, and a second pole of the fifth transistor is opposite to the third The voltage terminals are connected.
  • the input module includes a first transistor, a gate of the first transistor is connected to the input end, and a first pole of the first transistor is connected to the first voltage end, the first A second pole of the transistor is coupled to the pull up node.
  • the reset module includes a second transistor, a gate of the second transistor is connected to the reset end, a first pole of the second transistor is connected to the pull-up node, and the second transistor The second pole is connected to the second voltage terminal.
  • the input module includes a first transistor
  • the reset module includes a second transistor
  • a gate of one of the first transistor and the second transistor is connected to the input end
  • the one transistor is a first pole is connected to the first voltage end
  • a second pole of the one transistor is connected to the pull-up node
  • a gate of the other of the first transistor and the second transistor is connected to the reset terminal, a first pole of the other transistor is connected to the pull-up node, and the other transistor is The diode is connected to the second voltage terminal.
  • the pull-up module includes a seventh transistor, an eighth transistor, a ninth transistor, and a first capacitor;
  • a gate of the seventh transistor is connected to the pull-down node, a first pole of the seventh transistor is connected to the third voltage terminal, and a second pole of the seventh transistor is connected to the pull-up node;
  • a gate of the eighth transistor is connected to a first pole of the ninth transistor, a first pole of the eighth transistor is connected to the pull-up node, and a second pole of the eighth transistor is opposite to the first Two signal terminals are connected;
  • a gate of the ninth transistor is connected to the pull-up node, and a second pole of the ninth transistor is connected to the second signal end;
  • the first capacitor is connected in parallel between the pull-up node and the output terminal.
  • the pull-up module includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and a first capacitor;
  • a gate of the seventh transistor is connected to the pull-down node, a first pole of the seventh transistor is connected to the third voltage terminal, and a second pole of the seventh transistor is connected to the pull-up node;
  • a gate of the eighth transistor is connected to a first pole of the ninth transistor, a first pole of the eighth transistor is connected to a second pole of the tenth transistor, and a second pole of the eighth transistor Connected to the second signal end;
  • a gate of the ninth transistor is connected to the pull-up node, and a second pole of the ninth transistor is connected to the second signal end;
  • a gate of the tenth transistor is connected to a first pole of the ninth transistor, and a first pole of the tenth transistor is connected to the pull-up node;
  • the first capacitor is connected in parallel between the pull-up node and the output terminal.
  • the present invention also provides a driving method of a shift register, wherein the shift register includes any one of the above shift registers, the first voltage terminal is at a high level, and the second voltage terminal is at a low level, The third voltage terminal is at a low level, and the driving method includes:
  • the input signal of the first signal end is a low level, the input signal of the input end is a high level, the input signal of the reset end is a low level, and the input signal of the second signal end is a low level;
  • the input signal of the first signal end is a high level
  • the input signal of the input end is a low level
  • the input signal of the reset end is a low level
  • the input signal of the second signal end is a low level
  • the input signal of the first signal end is a low level
  • the input signal of the input end is a low level
  • the input signal of the reset end is a high level
  • the input signal of the second signal end is a low level
  • the input signal of the first signal end is a high level
  • the input signal of the input end is a low level
  • the input signal of the reset end is a low level
  • the input signal of the second signal end is a low level
  • the input signal of the first signal end is a low level
  • the input signal of the input end is a low level
  • the input signal of the reset end is a low level
  • the input signal of the second signal end is a low level
  • the between the first phase and the second phase includes:
  • the input signal of the first signal end is a low level
  • the input signal of the input end is a low level
  • the input signal of the reset end is a low level
  • the input signal of the second signal end is a high level
  • the present invention also provides a driving circuit comprising a plurality of stages of any of the above shift registers;
  • the input end of the shift register is connected to the output end of the shift register of the previous stage, and the output end of the shift register is connected to the reset end of the shift register of the previous stage.
  • the output of the other shift register is connected to the input end of the shift register of the next stage, and the reset end of the shift register is connected to the output end of the shift register of the next stage.
  • the present invention also provides a display device including the above drive circuit.
  • the shift register for a touch display panel, a driving method thereof, a driving circuit, and a display device provided by the present invention
  • the shift register includes a pull-up unit, a pull-down unit, and an output unit
  • the pull-up unit is The input signals of the input terminal, the second signal terminal and the reset terminal, and the potential of the pull-down node control the potential of the pull-up node
  • the pull-down unit is configured according to the input signal of the first signal terminal and the upper a potential of the pull node controls a potential of the pull-down node
  • the output unit controls the output end according to an input signal of the first signal end and the second signal end and a potential of the pull-down node and the pull-up node output signal.
  • the second signal end can be regarded as a switching end of the touch signal and the display driving signal, and when the touch signal is transmitted, the second signal end is at a high level, and the driving signal is stored; After the touch signal is completed, the second signal terminal is at a low level, and the driving signal continues to scan, thereby preventing the touch signal and the driving signal from interfering with each other. Therefore, the technical solution provided by the present invention can be compatible with the array substrate driving function of the In Cell touch display panel and the traditional array substrate row driving function, thereby realizing the touch driving function and the display driving function switching, thereby ensuring the realization of the touch display panel. High-precision touch function can also be realized under the premise of high-resolution display function.
  • FIG. 1 is a schematic structural diagram of a shift register according to Embodiment 1 of the present invention.
  • FIG. 2 is a first specific structural diagram of the shift register shown in FIG. 1;
  • FIG. 3 is a second specific structural diagram of the shift register shown in FIG. 1;
  • FIG. 4 is a third specific structural diagram of the shift register shown in FIG. 1;
  • FIG. 5 is a fourth specific structural diagram of the shift register shown in FIG. 1; FIG.
  • FIG. 6 is a flowchart of a driving method of a shift register according to Embodiment 2 of the present invention.
  • FIG. 7 is a timing chart of operation of a shift register according to Embodiment 2 of the present invention.
  • FIG. 9 is a timing chart showing an operation of another shift register according to Embodiment 2 of the present invention.
  • FIG. 10 is a schematic structural diagram of a driving circuit according to Embodiment 3 of the present invention.
  • FIG. 1 is a schematic structural diagram of a shift register according to Embodiment 1 of the present invention.
  • the shift register includes a pull-up unit 101, a pull-down unit 102, and an output unit 103.
  • the pull-up unit 101 is respectively connected to an input terminal, a first voltage terminal VDD, a second voltage terminal VSS, and a The three voltage terminals VGL, the second signal terminal SW, the reset terminal Reset, the output terminal Output, the pull-down node PD, and the pull-up node PU are connected, and the pull-down unit 102 is respectively connected to the first signal terminal CLK, the third voltage terminal VGL, and the pull-up device.
  • the node PU and the pull-down node PD are connected, and the output unit 103 is respectively connected to the third voltage terminal VGL, the first signal terminal CLK, the second signal terminal SW, the output terminal Output, the pull-down node PD, and the pull-up node PU.
  • the pull-up unit 101 controls the potential of the pull-up node PU according to an input signal of the input terminal Input, the second signal terminal SW and the reset terminal Reset, and a potential of the pull-down node PD
  • the pull-down The unit 102 controls the potential of the pull-down node PD according to the input signal of the first signal terminal CLK and the potential of the pull-up node PU
  • the output unit 103 is configured according to the first signal terminal CLK and the second signal.
  • Input signal of the terminal SW and the pull-down node PD and the pull-up The potential of the node PU controls the output signal of the output Output.
  • the technical solution provided by the embodiment provides a display driving signal for storing when the touch signal is transmitted, and after the touch signal is completely transmitted, the display driving signal continues to scan, thereby avoiding touching.
  • the control signal and the drive signal interfere with each other. Therefore, the technical solution provided by the embodiment can be compatible with the array substrate driving function of the In Cell touch display panel and the traditional array substrate row driving function, thereby implementing the touch driving function and the display driving function switching, thereby ensuring that the touch display panel is High-precision touch function can also be realized under the premise of realizing high-resolution display function.
  • FIG. 2 is a first specific structural diagram of the shift register shown in FIG. 1.
  • the pull-up unit 101 includes an input module 104, a pull-up module 105, and a reset module 106.
  • the input module 104 is respectively connected to an input terminal Input, a first voltage terminal VDD, and a pull-up node PU.
  • the pull-up module 105 is respectively connected to the third voltage terminal VGL, the second signal terminal SW, the output terminal Output, the pull-down node PD, and the pull-up node PU, and the reset module 106 is respectively connected to the second voltage terminal VSS, the reset terminal Reset, and Pull-up node PU connection.
  • the input module 104 controls the potential of the pull-up node PU according to the input signal of the input terminal Input
  • the pull-up module 105 controls the input according to the input signal of the second signal terminal SW and the potential of the pull-down node PD.
  • the reset module 106 controls the potential of the pull-up node PU according to the input signal of the reset terminal Reset.
  • the pull-down unit 102 includes a sixth transistor M6 and a second capacitor C2.
  • a gate of the sixth transistor M6 is connected to the pull-up node PU, a first pole of the sixth transistor M6 is connected to the pull-down node PD, and a second pole of the sixth transistor M6 is opposite to the first
  • the three voltage terminals VGL are connected, and the second capacitor C2 is connected in parallel between the pull-down node PD and the first signal terminal CLK.
  • the output unit 103 includes a third transistor M3, a fourth transistor M4, and a fifth transistor M5.
  • a gate of the third transistor M3 is connected to the pull-up node PU, a first pole of the third transistor M3 is connected to the first signal terminal CLK, and a second pole of the third transistor M3 is The output terminal Output is connected, the gate of the fourth transistor M4 is connected to the second signal terminal SW, the first pole of the fourth transistor M4 is connected to the output terminal Output, and the fourth transistor M4 is a second pole and the third voltage terminal VGL Connected, the gate of the fifth transistor M5 is connected to the pull-down node PD, the first pole of the fifth transistor M5 is connected to the output terminal Output, the second pole of the fifth transistor M5 is The third voltage terminal VGL is connected.
  • the input module 104 includes a first transistor M1, a gate of the first transistor M1 is connected to the input terminal Input, a first pole of the first transistor M1 and the first voltage terminal VDD Connected, the second pole of the first transistor M1 is connected to the pull-up node PU.
  • the reset module 106 includes a second transistor M2, a gate of the second transistor M2 is connected to the reset terminal Reset, and a first pole of the second transistor M2 is connected to the pull-up node PU, The second pole of the two transistor M2 is connected to the second voltage terminal VSS.
  • the pull-up module 105 includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a first capacitor C1.
  • a gate of the seventh transistor M7 is connected to the pull-down node PD
  • a first pole of the seventh transistor M7 is connected to the third voltage terminal VGL
  • a second pole of the seventh transistor M7 is a pull-up node PU is connected
  • a gate of the eighth transistor M8 is connected to a first pole of the ninth transistor M9
  • a first pole of the eighth transistor M8 is connected to the pull-up node PU
  • a second pole of the eight transistor M8 is connected to the second signal terminal SW
  • a gate of the ninth transistor M9 is connected to the pull-up node PU
  • a second pole of the ninth transistor M9 is opposite to the second
  • the signal terminal SW is connected
  • the first capacitor C1 is connected in parallel between the pull-up node PU and the output terminal Output.
  • the input module 104 and the reset module 106 are two modules symmetrically arranged with respect to the pull-up node PU. Therefore, for a gate driving circuit composed of a plurality of cascaded shift registers, bidirectional scanning of the gate driving circuit can be easily realized.
  • FIG. 3 is a second specific structural diagram of the shift register shown in FIG. 1, which shows a shift register opposite to the scanning direction shown in FIG. 2.
  • the input module 104 includes a second transistor M2, a gate of the second transistor M2 is connected to the input terminal Input, and a first pole of the second transistor M2 is connected to the first voltage.
  • the terminal VDD is connected, and the second pole of the second transistor M2 is connected to the pull-up node PU.
  • the reset module 106 includes a first transistor M1, the gate of the first transistor M1 is connected to the reset terminal Reset, the first pole of the first transistor M1 is connected to the pull-up node PU, and the second pole of the first transistor M1 is The second voltage terminal VSS is connected.
  • FIG. 4 is a third specific structural diagram of the shift register shown in FIG. 1
  • FIG. 5 is a fourth specific structural diagram of the shift register shown in FIG. 1. Similar to Figures 2 and 3, Figures 4 and 5 show two shift registers with opposite scan directions, respectively.
  • the difference between the shift register shown in FIG. 4 and the shift register shown in FIG. 2 is that the shift register shown in FIG. 4 adds the tenth transistor M10.
  • the difference between the shift register shown in FIG. 5 and the shift register shown in FIG. 3 is that the shift register shown in FIG. 5 adds the tenth transistor M10.
  • the pull-up module 105 includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, and a first capacitor C1.
  • a gate of the seventh transistor M7 is connected to the pull-down node PD, a first pole of the seventh transistor M7 is connected to the third voltage terminal VGL, and a second pole of the seventh transistor M7 is a pull-up node PU is connected, a gate of the eighth transistor M8 is connected to a first pole of the ninth transistor M9, and a first pole of the eighth transistor M8 is connected to a second pole of the tenth transistor M10 a second pole of the eighth transistor M8 is connected to the second signal terminal SW, a gate of the ninth transistor M9 is connected to the pull-up node PU, and a second pole of the ninth transistor M9 is The second signal terminal SW is connected, the gate of the tenth transistor M10 is connected to the first pole of the ninth transistor M9, and the first pole of the tenth transistor M10 is connected to the pull-up node PU.
  • the first capacitor C1 is connected in parallel between the pull-up node PU and the output terminal Output.
  • the function of the tenth transistor M10 is to avoid or reduce the influence of the coupling effect generated when the input signal of the second signal terminal SW changes on the potential of the pull-up node PU.
  • the shift register provided in this embodiment includes a pull-up unit, a pull-down unit, and an output unit, and the pull-up unit inputs an input signal according to the input end, the second signal end, and the reset end, and a potential of the pull-down node.
  • Controlling a potential of the pull-up node, the pull-down unit controlling a potential of the pull-down node according to an input signal of the first signal end and a potential of the pull-up node, and the output unit is configured according to the first signal end An input signal of the second signal end and a potential of the pull-down node and the pull-up node Controlling the output signal of the output.
  • the technical solution provided by the embodiment provides a display driving signal for storing when the touch signal is transmitted, and after the touch signal is completely transmitted, the display driving signal continues to scan, thereby avoiding touching.
  • the control signal and the drive signal interfere with each other. Therefore, the technical solution provided by the embodiment can be compatible with the array substrate driving function of the In Cell touch display panel and the traditional array substrate row driving function, thereby implementing the touch driving function and the display driving function switching, thereby ensuring that the touch display panel is High-precision touch function can also be realized under the premise of realizing high-resolution display function.
  • the input module and the reset module are symmetric structures with respect to the pull-up node, and thus the gate drive circuit composed of a plurality of cascaded shift registers can be easily The bidirectional scanning of the gate drive circuit is achieved.
  • FIG. 6 is a flowchart of a driving method of a shift register according to Embodiment 2 of the present invention.
  • the shift register includes the shift register provided in the first embodiment.
  • This embodiment is described in detail by taking the shift register shown in FIG. 2 as an example.
  • the operation principle of the shift register shown in FIG. 3-5 is basically the same as that of the shift register shown in FIG. 2.
  • the input signal of the first voltage terminal VDD is a high level
  • the input signal of the second voltage terminal VSS is a low level
  • the input signal of the third voltage terminal VGL is a low level.
  • the driving method of the shift register includes:
  • step 1001 the input signal of the first signal end is a low level, the input signal of the input end is a high level, the input signal of the reset end is a low level, and the input signal of the second signal end is a low level. Level.
  • FIG. 7 is a timing chart of operation of a shift register according to Embodiment 2 of the present invention.
  • the input signal of the first signal terminal CLK is low level
  • the input signal of the input terminal Input is high level
  • the input signal of the reset terminal Reset is low level
  • the input signal of the second signal terminal SW is Low level.
  • the first transistor M1 is turned on, and the first voltage terminal VDD charges the first capacitor C1 through the first transistor M1, so that the pull-up node PU is pulled high.
  • the pull-up node PU is at a high level, so that the sixth transistor M6 is turned on.
  • the third voltage terminal VGL pulls the pull-down node PD low.
  • the pull-down node PD is at a low level to turn off the fifth transistor M5 and the seventh transistor M7, thereby ensuring the stability of the signal output.
  • step 1002 the second stage, the input signal of the first signal end is a high level, the input signal of the input end is a low level, the input signal of the reset end is a low level, and the input signal of the second signal end is a low level. Level.
  • the input signal of the first signal terminal CLK is a high level
  • the input signal of the input terminal Input is a low level
  • the input signal of the reset terminal Reset is a low level
  • the input signal of the second signal terminal SW is a low level.
  • the eighth transistor M8, the fourth transistor M4, and the first transistor M1 are turned off, the pull-up node PU continues to maintain the high level, and the third transistor M3 remains in the on state. Since the first signal terminal CLK is at a high level, at this time, the pull-up node PU amplifies the voltage of the pull-up node PU due to the bootstrapping effect, and the output terminal Output outputs a high level. At this time, the pull-up node PU is at a high potential, and the sixth transistor M6 is still in an on state, so that the fifth transistor M5 and the seventh transistor M7 are turned off, thereby ensuring the stability of the signal output.
  • step 1003 the third stage, the input signal of the first signal end is a low level, the input signal of the input end is a low level, the input signal of the reset end is a high level, and the input signal of the second signal end is a low level. Level.
  • the input signal of the first signal terminal CLK is a low level
  • the input signal of the input terminal Input is a low level
  • the input signal of the reset terminal Reset is a high level
  • the input signal of the second signal terminal SW is a low level.
  • the second transistor M2 is turned on, and the low level of the second voltage terminal VSS pulls the pull-up node PU low to the low level, and the third transistor M3 is turned off.
  • step 1004 the fourth stage, the input signal of the first signal end is a high level, the input signal of the input end is a low level, the input signal of the reset end is a low level, and the input signal of the second signal end is a low level. Level.
  • the input signal of the first signal terminal CLK is a high level
  • the input signal of the input terminal Input is a low level
  • the input signal of the reset terminal Reset is a low level
  • the input signal of the second signal terminal SW is a low level.
  • the pull-up node PU is at a low level
  • the sixth transistor M6 is turned off, so that the pull-down node PD is pulled high to the high level
  • the fifth transistor M5 is turned on to perform noise cancellation on the output.
  • the pull-down node PD is at a high level
  • the seventh transistor M7 is turned on, thereby performing noise cancellation on the pull-up node PU.
  • step 1005 the fifth stage, the input signal of the first signal end is a low level, the input signal of the input end is a low level, the input signal of the reset end is a low level, and the input signal of the second signal end is a low level. Level.
  • the input signal of the first signal terminal CLK is a low level
  • the input signal of the input terminal Input is a low level
  • the input signal of the reset terminal Reset is a low level
  • the input signal of the second signal terminal SW is a low level.
  • the sixth transistor M6 is turned off
  • the pull-down node PD is at a low level
  • the seventh transistor M7 and the fifth transistor M5 are turned off, thereby ensuring the stability of the signal output.
  • FIG. 8 is a timing chart showing the operation of the shift register in the prior art.
  • the current working sequence is: the input signal of the first signal terminal CLK is low level, the input signal of the input terminal Input is low level, the input signal of the reset terminal Reset is low level, and the second The input signal of the signal terminal SW is low.
  • the pull-up node PU is at a high level
  • the pull-down node PD is at a low level
  • the second transistor M2 and the seventh transistor M7 are turned off, but the second transistor M2 and the seventh transistor M7 have a leakage phenomenon, such a leakage phenomenon Pulling down the voltage of the pull-up node PU may cause the output register to have no output voltage or the output voltage is too low.
  • FIG. 9 is a timing chart showing the operation of another shift register according to Embodiment 2 of the present invention.
  • the first stage and the second stage include: a touch stage, an input signal of the first signal end CLK is a low level, and an input signal of the input end input is low.
  • the level, the input signal of the reset terminal Reset is a low level, and the input signal of the second signal terminal SW is a high level.
  • the pull-up node PU is at a high level
  • the eighth transistor M8 is turned on with the ninth transistor M9
  • the high level of the second signal terminal SW is supplementally charged to the first capacitor C1, thereby avoiding the second transistor M2 and the first transistor
  • the leakage phenomenon of the seven-transistor M7 pulls down the voltage of the pull-up node PU, causing a problem that the shift register has no output voltage or the output voltage is too low.
  • the touch signal is transmitted during the touch phase, and the pull-up node PU is high.
  • Level the pull-down node PD is low level, because the second signal terminal SW is at a high level, the fourth transistor M4 is turned on, thereby performing noise cancellation on the output terminal, and the touch signal is transmitted at the time, and no driving signal is performed.
  • the driving signal continues to scan, thereby preventing the touch signal and the driving signal from interfering with each other.
  • the shift register includes a pull-up unit, a pull-down unit, and an output unit
  • the pull-up unit is configured according to the input end, the second signal end, and the The input signal of the reset terminal and the potential of the pull-down node control the potential of the pull-up node
  • the pull-down unit controls the potential of the pull-down node according to the input signal of the first signal end and the potential of the pull-up node
  • the output unit controls an output signal of the output terminal according to input signals of the first signal end and the second signal end and potentials of the pull-down node and the pull-up node.
  • the technical solution provided in this embodiment is a touch stage in which the touch signal is transmitted, the second signal end is at a high level, and the display driving signal is stored, and after the touch signal is completed, the second signal end is at a low level.
  • the display driving signal continues to scan, thereby preventing the touch signal and the driving signal from interfering with each other. Therefore, the technical solution provided by the embodiment can be compatible with the array substrate driving function of the In Cell touch display panel and the traditional array substrate row driving function, thereby implementing the touch driving function and the display driving function switching, thereby ensuring that the touch display panel is High-precision touch function can also be realized under the premise of realizing high-resolution display function.
  • FIG. 10 is a schematic structural diagram of a driving circuit according to Embodiment 3 of the present invention. As shown in FIG. 10, the driving circuit includes a shift register provided in the first embodiment. For details, refer to the description of Embodiment 1, and details are not described herein again.
  • the input end of the other shift register is connected to the output end of the shift register of the previous stage, and the output end of the shift register is shifted from the upper stage.
  • the reset terminal of the register is connected.
  • the output of the other shift register is connected to the input end of the shift register of the next stage, and the reset end of the shift register is connected to the output end of the shift register of the next stage.
  • the shift register includes a pull-up unit, a pull-down unit and an output unit, the pull-up unit controlling a potential of the pull-up node according to an input signal of the input terminal, the second signal terminal, and the reset terminal, and a potential of the pull-down node, the pull-down unit Controlling, according to the input signal of the first signal end and the potential of the pull-up node, the potential of the pull-down node, the output unit according to the input signal of the first signal end and the second signal end, and the pull-down node And the potential of the pull-up node controls the output signal of the output.
  • the technical solution provided in this embodiment stores the driving signal when the touch signal is transmitted, and after the touch signal is completed, the driving signal continues to scan, thereby avoiding the touch signal and driving.
  • the signals interfere with each other. Therefore, the technical solution provided by the embodiment can be compatible with the array substrate driving function of the In Cell touch display panel and the traditional array substrate row driving function, thereby implementing the touch driving function and the display driving function switching, thereby ensuring that the touch display panel is High-precision touch function can also be realized under the premise of realizing high-resolution display function.
  • the present embodiment provides a display device, which includes the driving circuit provided in the third embodiment.
  • a display device which includes the driving circuit provided in the third embodiment.
  • the shift register includes a pull-up unit, a pull-down unit, and an output unit, and the pull-up unit inputs signals according to the input end, the second signal end, and the reset end. And controlling, by the potential of the pull-down node, a potential of the pull-up node, wherein the pull-down unit controls a potential of the pull-down node according to an input signal of the first signal end and a potential of the pull-up node, where the output unit is configured according to The input signals of the first signal terminal and the second signal terminal and the potentials of the pull-down node and the pull-up node control an output signal of the output terminal.
  • the technical solution provided in this embodiment stores the driving signal when the touch signal is transmitted, and after the touch signal is completed, the driving signal continues to scan, thereby avoiding the touch signal and driving.
  • the signals interfere with each other. Therefore, the technical solution provided by the embodiment can be compatible with the array substrate driving function of the In Cell touch display panel and the traditional array substrate row driving function, thereby implementing the touch driving function and the display driving function switching, thereby ensuring that the touch display panel is Under the premise of realizing high-resolution display function, Achieve high-precision touch functions.

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Abstract

一种移位寄存器及其驱动方法、驱动电路和显示装置，移位寄存器包括上拉单元（101）、下拉单元（102）和输出单元（103），上拉单元（101）根据输入端、第二信号端和复位端的输入信号以及下拉节点的电位控制上拉节点的电位，下拉单元（102）根据第一信号端的输入信号和上拉节点的电位控制下拉节点的电位，输出单元（103）根据第一信号端和第二信号端的输入信号以及下拉节点和上拉节点的电位控制输出端的输出信号。触控信号进行传输时，驱动信号进行存储，在触控信号完成传输之后，驱动信号继续进行扫描，从而避免触控信号与驱动信号相互干扰。

Description

移位寄存器及其驱动方法、驱动电路和显示装置 技术领域
本发明涉及显示技术领域，尤其涉及一种移位寄存器及其驱动方法、驱动电路和显示装置。
背景技术
显示面板的驱动器主要包括数据驱动器和栅极驱动器。在栅极驱动器中，一级移位寄存器连接一条栅线，通过多个级联的栅极驱动器输入驱动信号来实现像素阵列的逐行扫描。
随着触摸屏技术的发展，集成有触控功能和显示功能的触控显示面板受到了越来越多的关注。触控显示面板主要分为外挂式和内嵌式两种。现有的内嵌式触控显示面板分为In Cell触控显示面板和On Cell触控显示面板。On Cell触控显示面板将传感器设置在显示面板的外侧，然后贴附保护玻璃。In Cell触控显示基板通常将传感器设置在阵列基板侧，或者阵列基板和彩膜基板侧，然后形成显示面板，从而实现触摸功能。目前，In Cell触控显示面板通过扫描方式进行数据传输，以实现触控功能。然而，驱动信号与触控信号可能相互干扰，从而影响触控功能。
发明内容
为解决上述问题，本发明提供一种用于触控显示面板的移位寄存器及其驱动方法、驱动电路和显示装置，用于解决现有技术中触控显示面板的驱动信号与触控信号相互干扰，从而影响触控功能的问题。
为此，本发明提供一种移位寄存器，包括：
上拉单元，分别与输入端、第一电压端、第二电压端、第三电压端、第二信号端、复位端、输出端、下拉节点以及上拉节点连接，用于根据所述输入端、所述第二信号端和所述复位端的输入信号以及所述下拉节点的电位控制所述上拉节点的电位；
下拉单元，分别与第一信号端、第三电压端、上拉节点以及下拉节点连接，用于根据所述第一信号端的输入信号和所述上拉节点的电位控制所述下拉节点的电位；
输出单元，分别与第三电压端、第一信号端、第二信号端、输出端、下拉节点以及上拉节点连接，用于根据所述第一信号端和所述第二信号端的输入信号以及所述下拉节点和所述上拉节点的电位控制所述输出端的输出信号。
可选的，所述上拉单元包括：
输入模块，分别与输入端、第一电压端以及上拉节点连接，用于根据所述输入端的输入信号控制所述上拉节点的电位；
上拉模块，分别与第三电压端、第二信号端、输出端、下拉节点以及上拉节点连接，用于根据所述第二信号端的输入信号以及所述下拉节点的电位控制所述上拉节点的电位；
复位模块，分别与第二电压端、复位端以及上拉节点连接，用于根据所述复位端的输入信号控制所述上拉节点的电位。
可选的，所述下拉单元包括第六晶体管和第二电容；
所述第六晶体管的栅极与所述上拉节点连接，所述第六晶体管的第一极与所述下拉节点连接，所述第六晶体管的第二极与所述第三电压端连接；
所述第二电容并联于所述下拉节点与所述第一信号端之间。
可选的，所述输出单元包括第三晶体管、第四晶体管与第五晶体管；
所述第三晶体管的栅极与所述上拉节点连接，所述第三晶体管的第一极与所述第一信号端连接，所述第三晶体管的第二极与所述输出端连接；
所述第四晶体管的栅极与所述第二信号端连接，所述第四晶体管的第一极与所述输出端连接，所述第四晶体管的第二极与所述第三电压端连接；
所述第五晶体管的栅极与所述下拉节点连接，所述第五晶体管的第一极与所述输出端连接，所述第五晶体管的第二极与所述第三 电压端连接。
可选的，所述输入模块包括第一晶体管，所述第一晶体管的栅极与所述输入端连接，所述第一晶体管的第一极与所述第一电压端连接，所述第一晶体管的第二极与所述上拉节点连接。
可选的，所述复位模块包括第二晶体管，所述第二晶体管的栅极与所述复位端连接，所述第二晶体管的第一极与所述上拉节点连接，所述第二晶体管的第二极与所述第二电压端连接。
可选的，所述输入模块包括第一晶体管，所述复位模块包括第二晶体管，所述第一晶体管和第二晶体管中的一个晶体管的栅极与所述输入端连接，所述一个晶体管的第一极与所述第一电压端连接，所述一个晶体管的第二极与所述上拉节点连接，
所述第一晶体管和所述第二晶体管中的另一个晶体管的栅极与所述复位端连接，所述另一个晶体管的第一极与所述上拉节点连接，所述另一个晶体管的第二极与所述第二电压端连接。
可选的，所述上拉模块包括第七晶体管、第八晶体管、第九晶体管以及第一电容；
所述第七晶体管的栅极与所述下拉节点连接，所述第七晶体管的第一极与所述第三电压端连接，所述第七晶体管的第二极与所述上拉节点连接；
所述第八晶体管的栅极与所述第九晶体管的第一极连接，所述第八晶体管的第一极与所述上拉节点连接，所述第八晶体管的第二极与所述第二信号端连接；
所述第九晶体管的栅极与所述上拉节点连接，所述第九晶体管的第二极与所述第二信号端连接；
所述第一电容并联于所述上拉节点与所述输出端之间。
可选的，所述上拉模块包括第七晶体管、第八晶体管、第九晶体管、第十晶体管以及第一电容；
所述第七晶体管的栅极与所述下拉节点连接，所述第七晶体管的第一极与所述第三电压端连接，所述第七晶体管的第二极与所述上拉节点连接；
所述第八晶体管的栅极与所述第九晶体管的第一极连接，所述第八晶体管的第一极与所述第十晶体管的第二极连接，所述第八晶体管的第二极与所述第二信号端连接；
所述第九晶体管的栅极与所述上拉节点连接，所述第九晶体管的第二极与所述第二信号端连接；
所述第十晶体管的栅极与所述第九晶体管的第一极连接，所述第十晶体管的第一极与所述上拉节点连接；
所述第一电容并联于所述上拉节点与所述输出端之间。
本发明还提供一种移位寄存器的驱动方法，所述移位寄存器包括上述任一移位寄存器，所述第一电压端为高电平，所述第二电压端为低电平，所述第三电压端为低电平，所述驱动方法包括：
第一阶段，所述第一信号端的输入信号为低电平，所述输入端的输入信号为高电平，复位端的输入信号为低电平，所述第二信号端的输入信号为低电平；
第二阶段，所述第一信号端的输入信号为高电平，所述输入端的输入信号为低电平，复位端的输入信号为低电平，所述第二信号端的输入信号为低电平；
第三阶段，所述第一信号端的输入信号为低电平，所述输入端的输入信号为低电平，复位端的输入信号为高电平，所述第二信号端的输入信号为低电平；
第四阶段，所述第一信号端的输入信号为高电平，所述输入端的输入信号为低电平，复位端的输入信号为低电平，所述第二信号端的输入信号为低电平；
第五阶段，所述第一信号端的输入信号为低电平，所述输入端的输入信号为低电平，复位端的输入信号为低电平，所述第二信号端的输入信号为低电平。
可选的，所述第一阶段与所述第二阶段之间包括：
触控阶段，所述第一信号端的输入信号为低电平，所述输入端的输入信号为低电平，复位端的输入信号为低电平，所述第二信号端的输入信号为高电平。
本发明还提供一种驱动电路，包括多级上述任一移位寄存器；
除第一级移位寄存器之外，其余所述移位寄存器的输入端与上一级移位寄存器的输出端连接，所述移位寄存器的输出端与上一级移位寄存器的复位端连接；
除最后一级移位寄存器之外，其余所述移位寄存器的输出端与下一级移位寄存器的输入端连接，所述移位寄存器的复位端与下一级移位寄存器的输出端连接。
本发明还提供一种显示装置，包括上述驱动电路。
本发明具有下述有益效果：
本发明提供的用于触控显示面板的移位寄存器及其驱动方法、驱动电路和显示装置之中，所述移位寄存器包括上拉单元、下拉单元和输出单元，所述上拉单元根据所述输入端、所述第二信号端和所述复位端的输入信号以及所述下拉节点的电位控制所述上拉节点的电位，所述下拉单元根据所述第一信号端的输入信号和所述上拉节点的电位控制所述下拉节点的电位，所述输出单元根据所述第一信号端和所述第二信号端的输入信号以及所述下拉节点和所述上拉节点的电位控制所述输出端的输出信号。本发明提供的技术方案中，第二信号端可以视为触控信号和显示驱动信号的切换端，在触控信号进行传输时，所述第二信号端为高电平，驱动信号进行存储；在触控信号完成传输之后，所述第二信号端为低电平，驱动信号继续进行扫描，从而避免触控信号与驱动信号相互干扰。因此，本发明提供的技术方案可以兼容In Cell触控显示面板的阵列基板行驱动功能和传统的阵列基板行驱动功能，实现触控驱动功能和显示驱动功能切换，从而保证触控显示面板在实现高分辨率显示功能的前提下，还能够实现高精度的触控功能。
附图说明
图1为本发明实施例一提供的一种移位寄存器的结构示意图；
图2为图1所示移位寄存器的第一种具体结构示意图；
图3为图1所示移位寄存器的第二种具体结构示意图；
图4为图1所示移位寄存器的第三种具体结构示意图；
图5为图1所示移位寄存器的第四种具体结构示意图；
图6为本发明实施例二提供的一种移位寄存器的驱动方法的流程图；
图7为本发明实施例二提供的一种移位寄存器的工作时序图；
图8为现有技术之中移位寄存器的工作时序图；
图9为本发明实施例二提供的另一种移位寄存器的工作时序图；
图10为本发明实施例三提供的一种驱动电路的结构示意图。
具体实施方式
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图对本发明提供的移位寄存器及其驱动方法、驱动电路和显示装置进行详细描述。
实施例一
图1为本发明实施例一提供的一种移位寄存器的结构示意图。如图1所示，所述移位寄存器包括上拉单元101、下拉单元102和输出单元103，所述上拉单元101分别与输入端Input、第一电压端VDD、第二电压端VSS、第三电压端VGL、第二信号端SW、复位端Reset、输出端Output、下拉节点PD以及上拉节点PU连接，所述下拉单元102分别与第一信号端CLK、第三电压端VGL、上拉节点PU以及下拉节点PD连接，所述输出单元103分别与第三电压端VGL、第一信号端CLK、第二信号端SW、输出端Output、下拉节点PD以及上拉节点PU连接。所述上拉单元101根据所述输入端Input、所述第二信号端SW和所述复位端Reset的输入信号以及所述下拉节点PD的电位控制所述上拉节点PU的电位，所述下拉单元102根据所述第一信号端CLK的输入信号和所述上拉节点PU的电位控制所述下拉节点PD的电位，所述输出单元103根据所述第一信号端CLK和所述第二信号端SW的输入信号以及所述下拉节点PD和所述上拉 节点PU的电位控制所述输出端Output的输出信号。通过控制第二信号端SW的电平，本实施例提供的技术方案在触控信号进行传输时，显示驱动信号进行存储，在触控信号完成传输之后，显示驱动信号继续进行扫描，从而避免触控信号与驱动信号相互干扰。因此，本实施例提供的技术方案可以兼容In Cell触控显示面板的阵列基板行驱动功能和传统的阵列基板行驱动功能，实现触控驱动功能和显示驱动功能切换，从而保证触控显示面板在实现高分辨率显示功能的前提下，还能够实现高精度的触控功能。
图2为图1所示移位寄存器的第一种具体结构示意图。如图2所示，所述上拉单元101包括输入模块104、上拉模块105和复位模块106，所述输入模块104分别与输入端Input、第一电压端VDD以及上拉节点PU连接，所述上拉模块105分别与第三电压端VGL、第二信号端SW、输出端Output、下拉节点PD以及上拉节点PU连接，所述复位模块106分别与第二电压端VSS、复位端Reset以及上拉节点PU连接。所述输入模块104根据所述输入端Input的输入信号控制所述上拉节点PU的电位，上拉模块105根据所述第二信号端SW的输入信号以及所述下拉节点PD的电位控制所述上拉节点PU的电位，复位模块106根据所述复位端Reset的输入信号控制所述上拉节点PU的电位。
本实施例中，所述下拉单元102包括第六晶体管M6和第二电容C2。所述第六晶体管M6的栅极与所述上拉节点PU连接，所述第六晶体管M6的第一极与所述下拉节点PD连接，所述第六晶体管M6的第二极与所述第三电压端VGL连接，所述第二电容C2并联于所述下拉节点PD与所述第一信号端CLK之间。可选的，所述输出单元103包括第三晶体管M3、第四晶体管M4与第五晶体管M5。所述第三晶体管M3的栅极与所述上拉节点PU连接，所述第三晶体管M3的第一极与所述第一信号端CLK连接，所述第三晶体管M3的第二极与所述输出端Output连接，所述第四晶体管M4的栅极与所述第二信号端SW连接，所述第四晶体管M4的第一极与所述输出端Output连接，所述第四晶体管M4的第二极与所述第三电压端VGL 连接，所述第五晶体管M5的栅极与所述下拉节点PD连接，所述第五晶体管M5的第一极与所述输出端Output连接，所述第五晶体管M5的第二极与所述第三电压端VGL连接。
参见图2，所述输入模块104包括第一晶体管M1，所述第一晶体管M1的栅极与所述输入端Input连接，所述第一晶体管M1的第一极与所述第一电压端VDD连接，所述第一晶体管M1的第二极与所述上拉节点PU连接。所述复位模块106包括第二晶体管M2，所述第二晶体管M2的栅极与所述复位端Reset连接，所述第二晶体管M2的第一极与所述上拉节点PU连接，所述第二晶体管M2的第二极与所述第二电压端VSS连接。
本实施例中，所述上拉模块105包括第七晶体管M7、第八晶体管M8、第九晶体管M9以及第一电容C1。所述第七晶体管M7的栅极与所述下拉节点PD连接，所述第七晶体管M7的第一极与所述第三电压端VGL连接，所述第七晶体管M7的第二极与所述上拉节点PU连接，所述第八晶体管M8的栅极与所述第九晶体管M9的第一极连接，所述第八晶体管M8的第一极与所述上拉节点PU连接，所述第八晶体管M8的第二极与所述第二信号端SW连接，所述第九晶体管M9的栅极与所述上拉节点PU连接，所述第九晶体管M9的第二极与所述第二信号端SW连接，所述第一电容C1并联于所述上拉节点PU与所述输出端Output之间。
在图2所示的实施例中，可以看出，所述输入模块104和所述复位模块106为相对于所述上拉节点PU对称设置的两个模块。因此，对于由多个级联的移位寄存器构成的栅极驱动电路而言，可以容易地实现该栅极驱动电路的双向扫描。
与图2所示的扫描方向不同，图3为图1所示移位寄存器的第二种具体结构示意图，其示出了与图2所示的扫描方向相反的移位寄存器。如图3所示，所述输入模块104包括第二晶体管M2，所述第二晶体管M2的栅极与所述输入端Input连接，所述第二晶体管M2的第一极与所述第一电压端VDD连接，所述第二晶体管M2的第二极与所述上拉节点PU连接。所述复位模块106包括第一晶体管 M1，所述第一晶体管M1的栅极与所述复位端Reset连接，所述第一晶体管M1的第一极与所述上拉节点PU连接，所述第一晶体管M1的第二极与所述第二电压端VSS连接。
图4为图1所示移位寄存器的第三种具体结构示意图，图5为图1所示移位寄存器的第四种具体结构示意图。与图2和图3类似，图4和图5分别示出了扫描方向相反的两种移位寄存器。图4示出的移位寄存器与图2示出的移位寄存器之间的区别在于，图4示出的移位寄存器增加了第十晶体管M10。同理，图5示出的移位寄存器与图3示出的移位寄存器之间的区别在于，图5示出的移位寄存器增加了第十晶体管M10。具体来说，所述上拉模块105包括第七晶体管M7、第八晶体管M8、第九晶体管M9、第十晶体管M10以及第一电容C1。所述第七晶体管M7的栅极与所述下拉节点PD连接，所述第七晶体管M7的第一极与所述第三电压端VGL连接，所述第七晶体管M7的第二极与所述上拉节点PU连接，所述第八晶体管M8的栅极与所述第九晶体管M9的第一极连接，所述第八晶体管M8的第一极与所述第十晶体管M10的第二极连接，所述第八晶体管M8的第二极与所述第二信号端SW连接，所述第九晶体管M9的栅极与所述上拉节点PU连接，所述第九晶体管M9的第二极与所述第二信号端SW连接，所述第十晶体管M10的栅极与所述第九晶体管M9的第一极连接，所述第十晶体管M10的第一极与所述上拉节点PU连接，所述第一电容C1并联于所述上拉节点PU与所述输出端Output之间。所述第十晶体管M10的作用是避免或减小第二信号端SW的输入信号变化时产生的耦合作用对上拉节点PU的电位的影响。
本实施例提供的移位寄存器包括上拉单元、下拉单元和输出单元，所述上拉单元根据所述输入端、所述第二信号端和所述复位端的输入信号以及所述下拉节点的电位控制所述上拉节点的电位，所述下拉单元根据所述第一信号端的输入信号和所述上拉节点的电位控制所述下拉节点的电位，所述输出单元根据所述第一信号端和所述第二信号端的输入信号以及所述下拉节点和所述上拉节点的电位 控制所述输出端的输出信号。通过控制第二信号端SW的电平，本实施例提供的技术方案在触控信号进行传输时，显示驱动信号进行存储，在触控信号完成传输之后，显示驱动信号继续进行扫描，从而避免触控信号与驱动信号相互干扰。因此，本实施例提供的技术方案可以兼容In Cell触控显示面板的阵列基板行驱动功能和传统的阵列基板行驱动功能，实现触控驱动功能和显示驱动功能切换，从而保证触控显示面板在实现高分辨率显示功能的前提下，还能够实现高精度的触控功能。另外，本发明实施例中的移位寄存器中，输入模块和复位模块为相对于上拉节点的对称结构，因此对于由多个级联的移位寄存器构成的栅极驱动电路而言，可以容易地实现该栅极驱动电路的双向扫描。
实施例二
图6为本发明实施例二提供的一种移位寄存器的驱动方法的流程图。如图6所示，所述移位寄存器包括实施例一提供的移位寄存器，具体内容可参照实施例一的描述，此处不再赘述。本实施例以图2所示的移位寄存器为例进行详细说明，图3-5所示的移位寄存器的工作原理与图2所示的移位寄存器基本相同。
本实施例中，所述第一电压端VDD的输入信号为高电平，所述第二电压端VSS的输入信号为低电平，所述第三电压端VGL的输入信号为低电平，所述移位寄存器的驱动方法包括：
步骤1001、第一阶段，所述第一信号端的输入信号为低电平，所述输入端的输入信号为高电平，复位端的输入信号为低电平，所述第二信号端的输入信号为低电平。
图7为本发明实施例二提供的一种移位寄存器的工作时序图。如图7所示，第一信号端CLK的输入信号为低电平，输入端Input的输入信号为高电平，复位端Reset的输入信号为低电平，第二信号端SW的输入信号为低电平。此时，第一晶体管M1导通，第一电压端VDD通过第一晶体管M1给第一电容C1充电，使得上拉节点PU拉高为高电平。上拉节点PU为高电平，使得第六晶体管M6导通， 第三电压端VGL将下拉节点PD下拉为低电平。下拉节点PD为低电平使得第五晶体管M5和第七晶体管M7断开，从而保证信号输出的稳定性。
步骤1002、第二阶段，所述第一信号端的输入信号为高电平，所述输入端的输入信号为低电平，复位端的输入信号为低电平，所述第二信号端的输入信号为低电平。
本实施例中，第一信号端CLK的输入信号为高电平，输入端Input的输入信号为低电平，复位端Reset的输入信号为低电平，第二信号端SW的输入信号为低电平。此时，第八晶体管M8、第四晶体管M4以及第一晶体管M1断开，上拉节点PU继续保持高电平，第三晶体管M3保持导通状态。由于第一信号端CLK为高电平，此时上拉节点PU由于自举效应(bootstrapping)放大上拉节点PU的电压，输出端Output输出高电平。此时，上拉节点PU为高电位，第六晶体管M6仍处于导通状态，使得第五晶体管M5和第七晶体管M7断开，从而保证信号输出的稳定性。
步骤1003、第三阶段，所述第一信号端的输入信号为低电平，所述输入端的输入信号为低电平，复位端的输入信号为高电平，所述第二信号端的输入信号为低电平。
本实施例中，第一信号端CLK的输入信号为低电平，输入端Input的输入信号为低电平，复位端Reset的输入信号为高电平，第二信号端SW的输入信号为低电平。此时，第二晶体管M2导通，第二电压端VSS的低电平将上拉节点PU拉低为低电平，第三晶体管M3断开。
步骤1004、第四阶段，所述第一信号端的输入信号为高电平，所述输入端的输入信号为低电平，复位端的输入信号为低电平，所述第二信号端的输入信号为低电平。
本实施例中，第一信号端CLK的输入信号为高电平，输入端Input的输入信号为低电平，复位端Reset的输入信号为低电平，第二信号端SW的输入信号为低电平。此时，上拉节点PU为低电平，第六晶体管M6断开，使得下拉节点PD拉高为高电平，第五晶体管 M5导通，从而对输出端Output进行放噪。同时，下拉节点PD为高电平，第七晶体管M7导通，从而对上拉节点PU进行放噪。通过上述放噪行为，使得第一信号端CLK产生的耦合噪声电压得以消除，从而实现输出端Output的低电平输出，保证信号输出的稳定性。
步骤1005、第五阶段，所述第一信号端的输入信号为低电平，所述输入端的输入信号为低电平，复位端的输入信号为低电平，所述第二信号端的输入信号为低电平。
本实施例中，第一信号端CLK的输入信号为低电平，输入端Input的输入信号为低电平，复位端Reset的输入信号为低电平，第二信号端SW的输入信号为低电平。此时，第六晶体管M6断开，下拉节点PD为低电平，第七晶体管M7和第五晶体管M5断开，从而保证信号输出的稳定性。
图8为现有技术之中移位寄存器的工作时序图。如图8所示，现有的工作时序为：第一信号端CLK的输入信号为低电平，输入端Input的输入信号为低电平，复位端Reset的输入信号为低电平，第二信号端SW的输入信号为低电平。此时，上拉节点PU为高电平，下拉节点PD为低电平，第二晶体管M2和第七晶体管M7断开，但是第二晶体管M2和第七晶体管M7存在漏电现象，这种漏电现象会拉低上拉节点PU的电压，可能导致移位寄存器出现无输出电压或者输出电压过低的问题。为此，本实施例在第二信号端SW提供高电平对第一电容C1进行补充充电。图9为本发明实施例二提供的另一种移位寄存器的工作时序图。如图9所示，所述第一阶段与所述第二阶段之间包括：触控阶段，所述第一信号端CLK的输入信号为低电平，所述输入端Input的输入信号为低电平，复位端Reset的输入信号为低电平，所述第二信号端SW的输入信号为高电平。此时，上拉节点PU为高电平，第八晶体管M8与第九晶体管M9导通，第二信号端SW的高电平对第一电容C1进行补充充电，从而避免第二晶体管M2和第七晶体管M7的漏电现象拉低上拉节点PU的电压，导致移位寄存器出现无输出电压或者输出电压过低的问题。
本实施例中，触控信号在触控阶段进行传输，上拉节点PU为高 电平，下拉节点PD为低电平，由于第二信号端SW为高电平，第四晶体管M4导通，从而对输出端Output进行放噪，此时触控信号进行传输，没有驱动信号进行传输，在触控信号完成传输之后，驱动信号继续进行扫描，从而避免触控信号与驱动信号相互干扰。
本实施例提供的移位寄存器的驱动方法之中，所述移位寄存器包括上拉单元、下拉单元和输出单元，所述上拉单元根据所述输入端、所述第二信号端和所述复位端的输入信号以及所述下拉节点的电位控制所述上拉节点的电位，所述下拉单元根据所述第一信号端的输入信号和所述上拉节点的电位控制所述下拉节点的电位，所述输出单元根据所述第一信号端和所述第二信号端的输入信号以及所述下拉节点和所述上拉节点的电位控制所述输出端的输出信号。本实施例提供的技术方案在触控信号进行传输的触控阶段，第二信号端为高电平，显示驱动信号进行存储，而在触控信号完成传输之后，第二信号端为低电平，显示驱动信号继续进行扫描，从而避免触控信号与驱动信号相互干扰。因此，本实施例提供的技术方案可以兼容In Cell触控显示面板的阵列基板行驱动功能和传统的阵列基板行驱动功能，实现触控驱动功能和显示驱动功能切换，从而保证触控显示面板在实现高分辨率显示功能的前提下，还能够实现高精度的触控功能。
实施例三
图10为本发明实施例三提供的一种驱动电路的结构示意图。如图10所示，所述驱动电路包括多级实施例一提供的移位寄存器，具体内容可参照实施例一的描述，此处不再赘述。
本实施例中，除第一级移位寄存器之外，其余所述移位寄存器的输入端与上一级移位寄存器的输出端连接，所述移位寄存器的输出端与上一级移位寄存器的复位端连接。除最后一级移位寄存器之外，其余所述移位寄存器的输出端与下一级移位寄存器的输入端连接，所述移位寄存器的复位端与下一级移位寄存器的输出端连接。
本实施例提供的驱动电路之中，所述移位寄存器包括上拉单元、 下拉单元和输出单元，所述上拉单元根据所述输入端、所述第二信号端和所述复位端的输入信号以及所述下拉节点的电位控制所述上拉节点的电位，所述下拉单元根据所述第一信号端的输入信号和所述上拉节点的电位控制所述下拉节点的电位，所述输出单元根据所述第一信号端和所述第二信号端的输入信号以及所述下拉节点和所述上拉节点的电位控制所述输出端的输出信号。通过控制第二信号端的电平，本实施例提供的技术方案在触控信号进行传输时，驱动信号进行存储，在触控信号完成传输之后，驱动信号继续进行扫描，从而避免触控信号与驱动信号相互干扰。因此，本实施例提供的技术方案可以兼容In Cell触控显示面板的阵列基板行驱动功能和传统的阵列基板行驱动功能，实现触控驱动功能和显示驱动功能切换，从而保证触控显示面板在实现高分辨率显示功能的前提下，还能够实现高精度的触控功能。
实施例四
本实施例提供一种显示装置，包括实施例三提供的驱动电路，具体内容可参照实施例一的描述，此处不再赘述。
本实施例提供的显示装置之中，所述移位寄存器包括上拉单元、下拉单元和输出单元，所述上拉单元根据所述输入端、所述第二信号端和所述复位端的输入信号以及所述下拉节点的电位控制所述上拉节点的电位，所述下拉单元根据所述第一信号端的输入信号和所述上拉节点的电位控制所述下拉节点的电位，所述输出单元根据所述第一信号端和所述第二信号端的输入信号以及所述下拉节点和所述上拉节点的电位控制所述输出端的输出信号。通过控制第二信号端的电平，本实施例提供的技术方案在触控信号进行传输时，驱动信号进行存储，在触控信号完成传输之后，驱动信号继续进行扫描，从而避免触控信号与驱动信号相互干扰。因此，本实施例提供的技术方案可以兼容In Cell触控显示面板的阵列基板行驱动功能和传统的阵列基板行驱动功能，实现触控驱动功能和显示驱动功能切换，从而保证触控显示面板在实现高分辨率显示功能的前提下，还能够 实现高精度的触控功能。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (13)

  1. 一种移位寄存器，包括：
    上拉单元，分别与输入端、第一电压端、第二电压端、第三电压端、第二信号端、复位端、输出端、下拉节点以及上拉节点连接，用于根据所述输入端、所述第二信号端和所述复位端的输入信号以及所述下拉节点的电位控制所述上拉节点的电位；
    下拉单元，分别与第一信号端、第三电压端、上拉节点以及下拉节点连接，用于根据所述第一信号端的输入信号和所述上拉节点的电位控制所述下拉节点的电位；
    输出单元，分别与第三电压端、第一信号端、第二信号端、输出端、下拉节点以及上拉节点连接，用于根据所述第一信号端和所述第二信号端的输入信号以及所述下拉节点和所述上拉节点的电位控制所述输出端的输出信号。
  2. 根据权利要求1所述的移位寄存器，其中，所述上拉单元包括：
    输入模块，分别与输入端、第一电压端以及上拉节点连接，用于根据所述输入端的输入信号控制所述上拉节点的电位；
    上拉模块，分别与第三电压端、第二信号端、输出端、下拉节点以及上拉节点连接，用于根据所述第二信号端的输入信号以及所述下拉节点的电位控制所述上拉节点的电位；
    复位模块，分别与第二电压端、复位端以及上拉节点连接，用于根据所述复位端的输入信号控制所述上拉节点的电位。
  3. 根据权利要求2所述的移位寄存器，其中，所述下拉单元包括第六晶体管和第二电容；
    所述第六晶体管的栅极与所述上拉节点连接，所述第六晶体管的第一极与所述下拉节点连接，所述第六晶体管的第二极与所述第三电压端连接；
    所述第二电容并联于所述下拉节点与所述第一信号端之间。
  4. 根据权利要求3所述的移位寄存器，其中，所述输出单元包括第三晶体管、第四晶体管与第五晶体管；
    所述第三晶体管的栅极与所述上拉节点连接，所述第三晶体管的第一极与所述第一信号端连接，所述第三晶体管的第二极与所述输出端连接；
    所述第四晶体管的栅极与所述第二信号端连接，所述第四晶体管的第一极与所述输出端连接，所述第四晶体管的第二极与所述第三电压端连接；
    所述第五晶体管的栅极与所述下拉节点连接，所述第五晶体管的第一极与所述输出端连接，所述第五晶体管的第二极与所述第三电压端连接。
  5. 根据权利要求4所述的移位寄存器，其中，所述输入模块包括第一晶体管，所述第一晶体管的栅极与所述输入端连接，所述第一晶体管的第一极与所述第一电压端连接，所述第一晶体管的第二极与所述上拉节点连接。
  6. 根据权利要求4所述的移位寄存器，其中，所述复位模块包括第二晶体管，所述第二晶体管的栅极与所述复位端连接，所述第二晶体管的第一极与所述上拉节点连接，所述第二晶体管的第二极与所述第二电压端连接。
  7. 根据权利要求4所述的移位寄存器，其中，所述输入模块包括第一晶体管，所述复位模块包括第二晶体管，所述第一晶体管和第二晶体管中的一个晶体管的栅极与所述输入端连接，所述一个晶体管的第一极与所述第一电压端连接，所述一个晶体管的第二极与所述上拉节点连接，
    所述第一晶体管和所述第二晶体管中的另一个晶体管的栅极与 所述复位端连接，所述另一个晶体管的第一极与所述上拉节点连接，所述另一个晶体管的第二极与所述第二电压端连接。
  8. 根据权利要求5至7中任一项所述的移位寄存器，其中，所述上拉模块包括第七晶体管、第八晶体管、第九晶体管以及第一电容；
    所述第七晶体管的栅极与所述下拉节点连接，所述第七晶体管的第一极与所述第三电压端连接，所述第七晶体管的第二极与所述上拉节点连接；
    所述第八晶体管的栅极与所述第九晶体管的第一极连接，所述第八晶体管的第一极与所述上拉节点连接，所述第八晶体管的第二极与所述第二信号端连接；
    所述第九晶体管的栅极与所述上拉节点连接，所述第九晶体管的第二极与所述第二信号端连接；
    所述第一电容并联于所述上拉节点与所述输出端之间。
  9. 根据权利要求5至7中任一项所述的移位寄存器，其特征在于，所述上拉模块包括第七晶体管、第八晶体管、第九晶体管、第十晶体管以及第一电容；
    所述第七晶体管的栅极与所述下拉节点连接，所述第七晶体管的第一极与所述第三电压端连接，所述第七晶体管的第二极与所述上拉节点连接；
    所述第八晶体管的栅极与所述第九晶体管的第一极连接，所述第八晶体管的第一极与所述第十晶体管的第二极连接，所述第八晶体管的第二极与所述第二信号端连接；
    所述第九晶体管的栅极与所述上拉节点连接，所述第九晶体管的第二极与所述第二信号端连接；
    所述第十晶体管的栅极与所述第九晶体管的第一极连接，所述第十晶体管的第一极与所述上拉节点连接；
    所述第一电容并联于所述上拉节点与所述输出端之间。
  10. 一种移位寄存器的驱动方法，其中，所述移位寄存器包括权利要求1-9任一所述的移位寄存器，所述第一电压端为高电平，所述第二电压端为低电平，所述第三电压端为低电平；
    所述移位寄存器的驱动方法包括：
    第一阶段，所述第一信号端的输入信号为低电平，所述输入端的输入信号为高电平，复位端的输入信号为低电平，所述第二信号端的输入信号为低电平；
    第二阶段，所述第一信号端的输入信号为高电平，所述输入端的输入信号为低电平，复位端的输入信号为低电平，所述第二信号端的输入信号为低电平；
    第三阶段，所述第一信号端的输入信号为低电平，所述输入端的输入信号为低电平，复位端的输入信号为高电平，所述第二信号端的输入信号为低电平；
    第四阶段，所述第一信号端的输入信号为高电平，所述输入端的输入信号为低电平，复位端的输入信号为低电平，所述第二信号端的输入信号为低电平；
    第五阶段，所述第一信号端的输入信号为低电平，所述输入端的输入信号为低电平，复位端的输入信号为低电平，所述第二信号端的输入信号为低电平。
  11. 根据权利要求10所述的移位寄存器的驱动方法，其中，所述第一阶段与所述第二阶段之间包括：
    触控阶段，所述第一信号端的输入信号为低电平，所述输入端的输入信号为低电平，复位端的输入信号为低电平，所述第二信号端的输入信号为高电平。
  12. 一种驱动电路，包括多级权利要求1-9任一项所述的移位寄存器；
    除第一级移位寄存器之外，其余所述移位寄存器的输入端与上 一级移位寄存器的输出端连接，所述移位寄存器的输出端与上一级移位寄存器的复位端连接；
    除最后一级移位寄存器之外，其余所述移位寄存器的输出端与下一级移位寄存器的输入端连接，所述移位寄存器的复位端与下一级移位寄存器的输出端连接。
  13. 一种显示装置，包括权利要求12所述的驱动电路。
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