WO2018028008A1 - Goa电路 - Google Patents

Goa电路 Download PDF

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Publication number
WO2018028008A1
WO2018028008A1 PCT/CN2016/097305 CN2016097305W WO2018028008A1 WO 2018028008 A1 WO2018028008 A1 WO 2018028008A1 CN 2016097305 W CN2016097305 W CN 2016097305W WO 2018028008 A1 WO2018028008 A1 WO 2018028008A1
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WIPO (PCT)
Prior art keywords
thin film
film transistor
gate
electrically connected
node
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PCT/CN2016/097305
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English (en)
French (fr)
Inventor
李亚锋
Original Assignee
武汉华星光电技术有限公司
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Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to JP2019507227A priority Critical patent/JP2019526824A/ja
Priority to EP16912463.3A priority patent/EP3499495B1/en
Priority to KR1020197006420A priority patent/KR102178652B1/ko
Priority to US15/128,420 priority patent/US10043473B2/en
Publication of WO2018028008A1 publication Critical patent/WO2018028008A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a GOA circuit.
  • LCD Liquid crystal display
  • PDAs personal digital assistants
  • digital cameras computer screens or laptop screens, etc.
  • GOA technology (Gate Driver on Array) is an array substrate row driving technology.
  • the original array process of the liquid crystal display panel is used to fabricate a horizontal scanning line driving circuit on a substrate around the display area, so that it can replace the external integrated circuit board ( (Integrated Circuit, IC) to complete the horizontal scanning line drive.
  • IC integrated circuit board
  • GOA technology can reduce the bonding process of external ICs, have the opportunity to increase productivity and reduce product cost, and can make LCD panels more suitable for making narrow borders or no borders. Display product.
  • FIG. 1 is a circuit diagram of a conventional GOA circuit including a cascaded multi-level GOA unit: each GOA unit includes: a forward-reverse scan control module 100, an output module 200, and The node control module 300 is configured to be a positive integer.
  • the forward-reverse scan control module 100 includes: a first thin film transistor T1, and a gate of the first thin film transistor T1 is electrically connected to The gate scan driving signal G(n-2) of the upper n-2th GOA unit, the source is connected to the forward scanning control signal U2D, and the drain is electrically connected to the first node H(n);
  • the gate of the third thin film transistor T3 is electrically connected to the gate scan driving signal G(n+2) of the n+th stage GOA unit of the next two stages, and the source is connected to the reverse scan control.
  • the signal D2U, the drain is electrically connected to the first node H(n);
  • the output unit 200 includes: a second thin film transistor T2, and the gate of the second thin film transistor T2 is electrically connected to the second node Q(n)
  • the source is connected to the mth clock signal CK(m), and the drain is electrically connected to the gate scan driving signal G(n) of the nth stage GOA unit; a capacitor C1, one end of the first capacitor C1 is electrically connected to the second node Q(n), and the other end is electrically connected to the gate scan driving signal G(n) of the nth stage GOA unit;
  • the module 300 includes: a fourth thin film transistor T4, the gate of the fourth thin film transistor T4 is electrically connected to the third node P(n), and the source is electrically connected to the gate scan driving signal G of the nth stage GOA unit.
  • the drain is connected to the constant voltage low potential VGL;
  • the fifth thin film transistor T5, the gate of the fifth thin film transistor T5 is connected to the constant voltage high potential VGH, and the source is electrically Connected to the first node H(n), the drain is electrically connected to the second node Q(n);
  • the sixth thin film transistor T6, the gate of the sixth thin film transistor T6 is electrically connected to the third node P ( n), the source is electrically connected to the first node H(n), the drain is connected to the constant voltage low potential VGL;
  • the seventh thin film transistor T7, the gate of the seventh thin film transistor T7 is electrically connected to the first node H(n), the source is electrically connected to the third node P(n), the drain is connected to the constant voltage low potential VGL;
  • the eighth thin film transistor T8, the gate of the eighth thin film transistor T8 is connected to the m+th Two clock signals CK(m+2), the source is connected to the constant voltage high potential VGH, the drain is electrically connected
  • the first thin film transistor T1 and the third thin film transistor T3 form a forward-reverse scan control unit 100, and the first thin film transistor T1 and the third thin film transistor T3 need to be respectively connected to the forward scan.
  • the control signal U2D and the reverse scan control signal D2U in the forward scan, the forward scan control signal U2D is at a high level, the reverse scan control signal D2U is at a low level; and in the reverse scan, the reverse scan control signal D2U is High level, the forward scan control signal U2D is low.
  • an integrated circuit has the function of outputting the control signal, which limits the selectable range of the IC, and at the same time, due to the presence of the forward scan control signal U2D and the reverse scan control signal D2U, the wiring (Layout) design is also not conducive to the implementation of narrow-framed liquid crystal displays.
  • the present invention provides a GOA circuit comprising: a plurality of cascaded GOA units, each of the GOA units including: a forward-reverse scan control module electrically connected to the forward-reverse scan control module An output module, a pull-down module electrically connected to the output module, and a pull-down control module electrically connected to the forward-reverse scan control module, the output module, and the pull-down module;
  • n and m be positive integers, except for the first level and the last level of the GOA unit, in the nth level GOA unit:
  • the forward/reverse scan control module accesses a gate scan driving signal of the n-1th stage GOA unit of the upper stage, a gate scan driving signal of the n+1th stage GOA unit of the next stage, and a first constant piezoelectric position And for outputting the first constant piezoelectric position to the output module according to the gate scan driving signal of the upper n-1th GOA unit or the gate scan driving signal of the next n+1th GOA unit, thereby controlling the
  • the output unit is turned on to implement forward scanning or reverse scanning of the GOA circuit;
  • the output module is configured to output an nth-level gate scan drive during the action of the nth stage GOA unit Dynamic signal
  • the pull-down module is configured to pull down a potential of the n-th gate scan driving signal during a non-active period of the n-th stage GOA unit;
  • the pull-down control module is configured to close the pull-down module and maintain the output module open during the action of the n-th stage GOA unit, and open the pull-down module and close the output module during the inactive period of the n-th GOA unit.
  • the forward-reverse scan control module includes: a first thin film transistor, a gate of the first thin film transistor is connected to a gate scan driving signal of a first-stage n-1th GOA unit, and a source is connected to the first constant a piezoelectric bit, the drain is electrically connected to the first node; and a third thin film transistor, the gate of the third thin film transistor is connected to a gate scan driving signal of the n+1th GOA unit of the next stage, and the source is connected Into the first constant piezoelectric position, the drain is electrically connected to the first node;
  • the output unit includes: a second thin film transistor, a gate of the second thin film transistor is electrically connected to the second node, a source is connected to the mth clock signal, and a drain is connected to the gate of the nth stage GOA unit Scanning a driving signal; a first capacitor, one end of the first capacitor is electrically connected to the second node, and the other end is connected to the gate scan driving signal of the nth stage GOA unit;
  • the pull-down module includes: a fourth thin film transistor, a gate of the fourth thin film transistor is electrically connected to the third node, a source is connected to a gate scan driving signal of the nth stage GOA unit, and a drain is connected to the second a constant voltage; and a second capacitor, one end of the second capacitor is electrically connected to the third node, and the other end is connected to the second constant piezoelectric position;
  • the pull-down control module includes: a sixth thin film transistor, a gate of the sixth thin film transistor is electrically connected to the third node, a source is electrically connected to the first node, and a drain is connected to the second constant piezoelectric position; a thin film transistor, the gate of the seventh thin film transistor is electrically connected to the first node, the source is electrically connected to the third node, the drain is connected to the second constant voltage; and the eighth thin film transistor is The gate of the eight thin film transistor is connected to the m+2th clock signal, the source is connected to the first constant piezoelectric position, and the drain is electrically connected to the third node;
  • the GOA unit further includes a voltage stabilizing module, the voltage stabilizing module includes: a fifth thin film transistor, a gate of the fifth thin film transistor is connected to the first constant piezoelectric position, and the source is electrically connected to the first node, and the drain Very electrically connected to the second node;
  • the first constant piezoelectric potential is opposite to the potential of the second constant piezoelectric potential.
  • the gate of the first thin film transistor is connected to a circuit start signal.
  • the gate of the third thin film transistor is connected to the circuit start signal.
  • the mth clock signal is the third clock signal, the m+2th clock signal is the first clock signal;
  • the mth clock signal is the fourth clock signal, the m+2th clock signal Is the second clock signal.
  • the first, second, third, and fourth clock signals have the same pulse period, and the falling edge of the previous clock signal is generated simultaneously with the rising edge of the next clock signal.
  • Each of the thin film transistors is an N-type thin film transistor, the first constant piezoelectric potential is a constant voltage high potential, and the second constant piezoelectric potential is a constant voltage low potential.
  • Each of the thin film transistors is a P-type thin film transistor, the first constant piezoelectric potential is a constant voltage low potential, and the second constant piezoelectric potential is a constant voltage high potential.
  • Each of the thin film transistors is an amorphous silicon thin film transistor, a low temperature polysilicon thin film transistor, or an oxide semiconductor thin film transistor.
  • the present invention also provides a GOA circuit, comprising: a plurality of cascaded GOA units, each of the GOA units comprising: a forward-reverse scan control module, and an electrical connection output module with the forward-reverse scan control module a pull-down module electrically connected to the output module, and a pull-down control module electrically connected to the forward-reverse scan control module, the output module, and the pull-down module;
  • n and m be positive integers, except for the first level and the last level of the GOA unit, in the nth level GOA unit:
  • the forward/reverse scan control module accesses a gate scan driving signal of the n-1th stage GOA unit of the upper stage, a gate scan driving signal of the n+1th stage GOA unit of the next stage, and a first constant piezoelectric position And for outputting the first constant piezoelectric position to the output module according to the gate scan driving signal of the upper n-1th GOA unit or the gate scan driving signal of the next n+1th GOA unit, thereby controlling the
  • the output unit is turned on to implement forward scanning or reverse scanning of the GOA circuit;
  • the output module is configured to output a gate scan driving signal of the nth stage GOA unit during the action of the nth stage GOA unit;
  • the pull-down module is configured to pull down a potential of a gate scan driving signal of the n-th stage GOA unit during a non-active period of the n-th stage GOA unit;
  • the pull-down control module is configured to close the pull-down module and maintain the output module open during the action of the n-th stage GOA unit, open the pull-down module and close the output module during the inactive period of the n-th GOA unit;
  • the forward-reverse scan control module includes: a first thin film transistor, a gate of the first thin film transistor is connected to a gate scan driving signal of a first-stage n-1th GOA unit, and a source is connected to the first a constant piezoelectric position, the drain is electrically connected to the first node; and a third thin film transistor, the gate of the third thin film transistor is connected to the gate scan driving signal of the n+1th GOA unit of the next stage, the source The pole is connected to the first constant piezoelectric position, and the drain is electrically connected to the first node;
  • the output unit includes: a second thin film transistor, a gate of the second thin film transistor is electrically connected to the second node, a source is connected to the mth clock signal, and a drain is connected to the gate of the nth stage GOA unit a scan driving signal; and a first capacitor, one end of the first capacitor is electrically connected to the other end of the second node, and the gate scan driving signal of the nth stage GOA unit is connected;
  • the pull-down module includes: a fourth thin film transistor, a gate of the fourth thin film transistor is electrically connected to the third node, and a source is electrically connected to a gate scan driving signal of the nth stage GOA unit, and the drain is connected. a second constant piezoelectric position; and a second capacitor, one end of the second capacitor is electrically connected to the third node, and the other end is connected to the second constant piezoelectric position;
  • the pull-down control module includes: a sixth thin film transistor, a gate of the sixth thin film transistor is electrically connected to the third node, a source is electrically connected to the first node, and a drain is connected to the second constant piezoelectric position; a thin film transistor, the gate of the seventh thin film transistor is electrically connected to the first node, the source is electrically connected to the third node, the drain is connected to the second constant voltage; and the eighth thin film transistor is The gate of the eight thin film transistor is connected to the m+2th clock signal, the source is connected to the first constant piezoelectric position, and the drain is electrically connected to the third node;
  • the GOA circuit further includes a voltage stabilizing module, the voltage stabilizing module includes: a fifth thin film transistor, a gate of the fifth thin film transistor is connected to the first constant piezoelectric position, and the source is electrically connected to the first node, and the drain Very electrically connected to the second node;
  • the first constant piezoelectric potential is opposite to the potential of the second constant piezoelectric potential
  • a gate of the first thin film transistor is connected to a circuit start signal
  • the gate of the third thin film transistor is connected to the circuit start signal
  • Each of the thin film transistors is an amorphous silicon thin film transistor, a low temperature polysilicon thin film transistor, or an oxide semiconductor thin film transistor.
  • the present invention provides a GOA circuit.
  • the forward and reverse scan control module of the GOA circuit includes a first thin film transistor and a third thin film transistor.
  • the gate of the first thin film transistor is electrically connected to the upper surface.
  • a gate scan driving signal of the first n-1th stage GOA unit the source is connected to the first constant piezoelectric level, the drain is electrically connected to the first node, and the gate of the third thin film transistor is electrically connected to the lower
  • the gate scan driving signal of the first n+1th GOA unit the source is connected to the first constant piezoelectric position, and the drain is electrically connected to the first node, and the GOA circuit can be controlled by the two thin film transistors. Switching between scans reduces the number of control signals compared to the prior art without increasing the thin film transistors and capacitors, and can expand the selection range of the IC, thereby facilitating the realization of a narrow bezel of the liquid crystal display.
  • 1 is a circuit diagram of a conventional GOA circuit
  • FIG. 2 is a circuit diagram of a GOA circuit of the present invention
  • FIG. 3 is a circuit diagram of a first stage GOA unit of the GOA circuit of the present invention.
  • FIG. 4 is a circuit diagram of a final stage GOA unit of the GOA circuit of the present invention.
  • Figure 6 is a timing chart of the reverse scan of the GOA circuit of the present invention.
  • the present invention provides a GOA circuit, including: a plurality of cascaded GOA units, each of the GOA units includes: a forward-reverse scan control module 100, and the forward-reverse scan control module 100 a connection output module 200, a pull-down module (300) electrically connected to the output module 200, and a pull-down control module 400 electrically connected to the forward-reverse scan control module 100, the output module 200, and the pull-down module 300;
  • n and m be positive integers, except for the first level and the last level of the GOA unit, in the nth level GOA unit:
  • the forward/reverse scan control module 100 accesses the gate scan driving signal G(n-1) of the upper n-1th stage GOA unit and the gate scan driving signal of the n+1th stage GOA unit of the next stage. G(n+1), and a first constant piezoelectric position for driving the gate drive signal G(n-1) or the next n+1th GOA unit according to the upper n-1th GOA unit.
  • the gate scan driving signal G(n+1) outputs a first constant piezoelectric position to the output module 200, thereby controlling the output unit 200 to be turned on to implement forward scanning or reverse scanning of the GOA circuit;
  • the output module 200 is configured to output a gate scan driving signal G(n) of the nth stage GOA unit during the action of the nth stage GOA unit;
  • the pull-down module 300 is configured to pull down a potential of a gate scan driving signal G(n) of the n-th stage GOA unit during an inactive period of the n-th stage GOA unit;
  • the pull-down control module 400 is configured to close the pull-down module 300 during the action of the n-th stage GOA unit and maintain the output module 200 open, and open during the inactive period of the n-th GOA unit The module 300 is pulled and the output module 200 is turned off.
  • the forward-reverse scan control module 100 includes: a first thin film transistor T1, and a gate of the first thin film transistor T1 is connected to a gate scan driving signal G of an upper n-1th stage GOA unit ( N-1), the source is connected to the first constant piezoelectric position, the drain is electrically connected to the first node H(n); and the third thin film transistor T3 is connected to the gate of the third thin film transistor T3.
  • the gate of the n+1th stage GOA unit scans the driving signal G(n+1), the source is connected to the first constant voltage, and the drain is electrically connected to the first node H(n);
  • the output unit 200 includes a second thin film transistor T2.
  • the gate of the second thin film transistor T2 is electrically connected to the second node Q(n), and the source is connected to the mth clock signal CK(m).
  • a pole is connected to the gate scan driving signal G(n) of the nth stage GOA unit; and a first capacitor C1, one end of the first capacitor C1 is electrically connected to the second node Q(n), and the other end is connected to the first a gate scan driving signal G(n) of the n-stage GOA unit;
  • the pull-down module 300 includes: a fourth thin film transistor T4, the gate of the fourth thin film transistor T4 is electrically connected to the third node P(n), and the source is connected to the gate scan driving signal of the nth stage GOA unit. G(n), the drain is connected to the second constant voltage; and the second capacitor C2 is electrically connected to the third node P(n) and the other end is connected to the second constant voltage ;
  • the pull-down control module 400 includes a sixth thin film transistor T6.
  • the gate of the sixth thin film transistor T6 is electrically connected to the third node P(n), and the source is electrically connected to the first node H(n).
  • the drain is connected to the second constant voltage; the seventh thin film transistor T7, the gate of the seventh thin film transistor T7 is electrically connected to the first node H(n), and the source is electrically connected to the third node P(n).
  • the drain is connected to the second constant piezoelectric potential; the eighth thin film transistor T8, the gate of the eighth thin film transistor T8 is connected to the m+2th clock signal CK(m+2), and the source is connected to the first Constant piezoelectric position, the drain is electrically connected to the third node P(n);
  • the GOA circuit further includes a voltage stabilizing module 500, the voltage stabilizing module 500 includes: a fifth thin film transistor T5, the gate of the fifth thin film transistor T5 is connected to the first constant piezoelectric position, and the source is electrically connected. At the first node H(n), the drain is electrically connected to the second node Q(n).
  • the first constant piezoelectric potential is opposite to the potential of the second constant piezoelectric potential.
  • the gate of the first thin film transistor T1 is connected to the circuit start signal STV.
  • the gate of the third thin film transistor T3 is connected to the circuit start signal STV.
  • the foregoing clock signals include four: a first, a second, a third, and a fourth clock signal; and when the mth clock signal CK(m) is a third clock signal, The M+2 clock signal CK(m+2) is the first clock signal; when the mth clock signal CK(m) is the fourth clock signal, the m+2th clock signal CK(m) +2) is the second clock signal.
  • the first, second, third, and fourth clock signals have the same pulse period, and the falling edge of the previous clock signal is simultaneously generated with the rising edge of the next clock signal, that is, the first
  • the first pulse signal of the clock signal is first generated, and the first pulse signal of the second clock signal is generated while the first pulse signal of the first clock signal ends, and the second clock signal is generated
  • the first pulse signal of the third clock signal is generated while the end of one pulse signal, and the first pulse of the fourth clock signal is ended while the first pulse signal of the third clock signal ends.
  • the signal is generated, and the second pulse signal of the first clock signal is generated while the first pulse signal of the fourth clock signal ends.
  • each of the thin film transistors may be an N-type thin film transistor or a P-type thin film transistor.
  • the first constant piezoelectric position is a constant voltage.
  • the high potential VGH the second constant piezoelectric position is the constant voltage low potential VGL.
  • the first constant piezoelectric potential is a constant voltage low potential VGL
  • the second constant piezoelectric potential is a constant voltage high potential VGH.
  • Each of the thin film transistors shown in FIG. 2 is an N-type thin film transistor.
  • each of the thin film transistors may be selected from various types of thin film transistors such as an amorphous silicon thin film transistor, a low temperature polysilicon thin film transistor, and an oxide semiconductor thin film transistor.
  • the GOA circuit N-type thin film transistor
  • Phase 1 pre-charging phase: in this phase, the gate scan driving signal G(n-1) of the n-1th stage GOA cell is high, the first thin film transistor T1 is turned on, and the first node H(n) is pre- Charging to a high potential, the seventh thin film transistor T7 is turned on, the third node P(n) is pulled down to a constant voltage low potential VGL, and the fifth thin film transistor T5 is always turned on by the constant voltage high potential VGH, the second node Q (n) is also precharged to a high potential;
  • the gate scan driving signal G(n) outputs a high potential phase: in this stage, the gate scan driving signal G(n-1) of the n-1th stage GOA cell is lowered to a low potential, and the first thin film transistor T1 Turning off, the second node Q(n) is kept at a high potential by the holding action of the first capacitor C1, the second thin film transistor T2 is turned on, the mth clock signal CK(m) provides a high potential, and the gate scan driving signal G ( n) outputting a high potential and passing it to the gate of the first thin film transistor T1 of the n+1th stage GOA cell of the next stage to realize the level transfer of the forward scan;
  • Phase 3 the gate scan driving signal G(n) outputs a low potential phase: in this phase, the second node Q(n) is maintained at a high potential by the first capacitor C1, and the second thin film transistor T2 is turned on, The low potential of the m clock signals CK(m) is output via the gate scan driving signal G(n);
  • Phase 4 the second node Q(n) pull-down phase: in this phase, the m+2th clock signal CK(m+2) provides a high potential, the eighth thin film transistor T8 is turned on, and the third node P(n) ) is charged to high Potential, the sixth thin film transistor T6 is turned on, the first and second nodes H(n), Q(n) are pulled down to a constant voltage low potential VGL;
  • Phase 5 second node Q(n) and gate scan driving signal G(n) low potential sustaining phase: when the first node H(n) becomes low potential, the seventh thin film transistor T7 is in an off state, when the first When the m+2 clock signal CK(m+2) jumps to a high potential, the eighth thin film transistor T8 is turned on, and the third node P(n) is charged to a high potential, then the fourth thin film transistor T4 and the sixth thin film transistor T6 is in an on state, which can ensure that the low potential of the second node Q(n) and the gate scan driving signal G(n) is stable, and the second capacitor C2 has a certain high potential to the third node P(n). Keep it alive.
  • FIG. 6 is a reverse scan timing diagram of the GOA circuit of the present invention, and the working process is different from the forward scanning in that it scans through the third thin film transistor T3, and the scanning sequence is the last one.
  • the level is scanned to the first stage, that is, the signal output from the gate scan driving signal of the next stage GOA unit is transmitted to the gate of the third thin film transistor T3 of the upper stage GOA unit to drive the upper stage GOA unit to start outputting.
  • the rest are the same as the forward scan, and will not be described here.
  • the GOA circuit of the present invention does not require an IC to provide a forward scan control signal and a reverse scan control signal, and does not increase a thin film transistor or a capacitor, and also ensures that the GOA circuit has a forward and reverse scan function. It expands the selectable IC range of the GOA circuit, which is beneficial to realize the narrow border of the liquid crystal display.
  • the present invention provides a GOA circuit.
  • the forward and reverse scan control module of the GOA circuit includes a first thin film transistor and a third thin film transistor.
  • the gate of the first thin film transistor is electrically connected to the previous one.
  • a gate scan driving signal of the level n-1th GOA unit the source is connected to the first constant piezoelectric level, the drain is electrically connected to the first node, and the gate of the third thin film transistor is electrically connected to the next
  • the gate scan driving signal of the n+1th stage GOA unit the source is connected to the first constant voltage bit, and the drain is electrically connected to the first node, and the GOA circuit can be controlled in the forward and reverse directions by the two thin film transistors. Switching between scans reduces the number of control signals compared to the prior art without increasing the thin film transistors and capacitors, and can expand the selection range of the IC, which is advantageous for realizing a narrow bezel of the liquid crystal display.

Abstract

一种GOA电路，该GOA电路的正反向扫描控制模块（100）包括第一薄膜晶体管（T1）以及第三薄膜晶体管（T3），所述第一薄膜晶体管（T1）的栅极电性连接于上一级第n-1级GOA单元的栅极扫描驱动信号G（n-1），源极接入第一恒压电位，漏极电性连接于第一节点H（n），所述第三薄膜晶体管（T3）的栅极电性连接于下一级第n+1级GOA单元的栅极扫描驱动信号G（n+1），源极接入第一恒压电位，漏极电性连接于第一节点H（n），通过该两个薄膜晶体管即可控制GOA电路在正反向扫描之间进行切换，相比于现有技术减少了两个控制信号的同时并不增加薄膜晶体管和电容，能够扩大IC的选择范围，有利于实现液晶显示器的窄边框。

Description

GOA电路 技术领域
本发明涉及显示技术领域，尤其涉及一种GOA电路。
背景技术
液晶显示器(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。如：液晶电视、移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等，在平板显示领域中占主导地位。
GOA技术(Gate Driver on Array)即阵列基板行驱动技术，是运用液晶显示面板的原有阵列制程将水平扫描线的驱动电路制作在显示区周围的基板上，使之能替代外接集成电路板((Integrated Circuit，IC)来完成水平扫描线的驱动。GOA技术能减少外接IC的焊接(bonding)工序，有机会提升产能并降低产品成本，而且可以使液晶显示面板更适合制作窄边框或无边框的显示产品。
请参阅图1，图1为现有的一种GOA电路的电路图，该GOA电路包括级联的多级GOA单元：每个GOA单元均包括：正反向扫描控制模块100、输出模块200、及节点控制模块300，设n为正整数，在第n级GOA单元中，所述正反向扫描控制模块100包括：第一薄膜晶体管T1，所述第一薄膜晶体管T1的栅极电性连接于上两级第n-2级GOA单元的栅极扫描驱动信号G(n-2)，源极接入正向扫描控制信号U2D，漏极电性连接于第一节点H(n)；以及第三薄膜晶体管T3，所述第三薄膜晶体管T3的栅极电性连接于下两级第n+2级GOA单元的栅极扫描驱动信号G(n+2)，源极接入反向扫描控制信号D2U，漏极电性连接于第一节点H(n)；所述输出单元200包括：第二薄膜晶体管T2，所述第二薄膜晶体管T2的栅极电性连接于第二节点Q(n)，源极接入第m条时钟信号CK(m)，漏极电性连接于第n级GOA单元的栅极扫描驱动信号G(n)；以及第一电容C1，所述第一电容C1的一端电性连接于第二节点Q(n)，另一端电性连接于第n级GOA单元的栅极扫描驱动信号G(n)；所述节点控制模块300包括：第四薄膜晶体管T4，所述第四薄膜晶体管T4的栅极电性连接于第三节点P(n)，源极电性连接于第n级GOA单元的栅极扫描驱动信号G(n)，漏极接入恒压低电位VGL；第五薄膜晶体管T5，所述第五薄膜晶体管T5的栅极接入恒压高电位VGH，源极电 性连接于第一节点H(n)，漏极电性连接于第二节点Q(n)；第六薄膜晶体管T6，所述第六薄膜晶体管T6的栅极电性连接于第三节点P(n)，源极电性连接于第一节点H(n)，漏极接入恒压低电位VGL；第七薄膜晶体管T7，所述第七薄膜晶体管T7的栅极电性连接于第一节点H(n)，源极电性连接于第三节点P(n)，漏极接入恒压低电位VGL；第八薄膜晶体管T8，所述第八薄膜晶体管T8的栅极接入第m+2条时钟信号CK(m+2)，源极接入恒压高电位VGH，漏极电性连接于第三节点P(n)；以及第二电容C2，所述第二电容C2的一端电性连接于第三节点P(n)，另一端接入恒压低电位VGL。
图1所示的现有的GOA电路中，第一薄膜晶体管T1和第三薄膜晶体管T3形成正反向扫描控制单元100，第一薄膜晶体管T1和第三薄膜晶体管T3需要分别接入正向扫描控制信号U2D以及反向扫描控制信号D2U，正向扫描时，正向扫描控制信号U2D为高电平，反向扫描控制信号D2U为低电平；反向扫描时，反向扫描控制信号D2U为高电平，正向扫描控制信号U2D为低电平。而这种方式就需要集成电路(Integrated Circuit，IC)具有输出该控制信号的功能，限制了IC的可选择范围，同时由于正向扫描控制信号U2D以及反向扫描控制信号D2U的存在，在布线(Layout)设计时也不利于窄边框液晶显示器的实现。
发明内容
本发明的目的在于提供一种GOA电路，无需提供正向扫描控制信号和反向扫描控制信号即可实现正反向扫描，有利于实现液晶显示器的窄边框。
为实现上述目的，本发明提供了一种GOA电路，包括：级联的多个GOA单元，每个GOA单元均包括：正反向扫描控制模块、与所述正反向扫描控制模块电性连接输出模块、与所述输出模块电性连接的下拉模块、与所述正反向扫描控制模块、输出模块和下拉模块均电性连接的下拉控制模块；
设n和m均为正整数，除第一级、与最后一级GOA单元外，在第n级GOA单元中：
所述正反向扫描控制模块接入上一级第n-1级GOA单元的栅极扫描驱动信号、下一级第n+1级GOA单元的栅极扫描驱动信号、以及第一恒压电位，用于根据上一级第n-1级GOA单元的栅极扫描驱动信号或下一级第n+1级GOA单元的栅极扫描驱动信号向输出模块输出第一恒压电位，进而控制所述输出单元打开，实现GOA电路正向扫描或反向扫描；
所述输出模块用于在第n级GOA单元作用期间输出第n级栅极扫描驱 动信号；
所述下拉模块用于在第n级GOA单元的非作用期间下拉所述第n级栅极扫描驱动信号的电位；
所述下拉控制模块用于在第n级GOA单元的作用期间关闭下拉模块并维持输出模块打开，在第n级GOA单元的非作用期间打开下拉模块并关闭输出模块。
所述正反向扫描控制模块包括：第一薄膜晶体管，所述第一薄膜晶体管的栅极接入上一级第n-1级GOA单元的栅极扫描驱动信号，源极接入第一恒压电位，漏极电性连接于第一节点；以及第三薄膜晶体管，所述第三薄膜晶体管的栅极接入下一级第n+1级GOA单元的栅极扫描驱动信号，源极接入第一恒压电位，漏极电性连接于第一节点；
所述输出单元包括：第二薄膜晶体管，所述第二薄膜晶体管的栅极电性连接于第二节点，源极接入第m条时钟信号，漏极接入第n级GOA单元的栅极扫描驱动信号；第一电容，所述第一电容的一端电性连接于第二节点，另一端接入第n级GOA单元的栅极扫描驱动信号；
所述下拉模块包括：第四薄膜晶体管，所述第四薄膜晶体管的栅极电性连接于第三节点，源极接入第n级GOA单元的栅极扫描驱动信号，漏极接入第二恒压电位；以及第二电容，所述第二电容的一端电性连接于第三节点，另一端接入第二恒压电位；
所述下拉控制模块包括：第六薄膜晶体管，所述第六薄膜晶体管的栅极电性连接于第三节点，源极电性连接于第一节点，漏极接入第二恒压电位；第七薄膜晶体管，所述第七薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第三节点，漏极接入第二恒压电位；以及第八薄膜晶体管，所述第八薄膜晶体管的栅极接入第m+2条时钟信号，源极接入第一恒压电位，漏极电性连接于第三节点；
所述GOA单元还包括稳压模块，所述稳压模块包括：第五薄膜晶体管，所述第五薄膜晶体管的栅极接入第一恒压电位，源极电性连接于第一节点，漏极电性连接于第二节点；
所述第一恒压电位与第二恒压电位的电位相反。
在第一级GOA单元中，所述第一薄膜晶体管的栅极接入电路起始信号。
在最后一级GOA单元中，所述第三薄膜晶体管的栅极接入电路起始信号。
包括四条时钟信号：第一、第二、第三、及第四条时钟信号；当所述 第m条时钟信号为第三条时钟信号时，第m+2条时钟信号为第一条时钟信号；当所述第m条时钟信号为第四条时钟信号时，第m+2条时钟信号为第二条时钟信号。
所述第一、第二、第三、及第四条时钟信号的脉冲周期相同，前一条时钟信号的下降沿与后一条时钟信号的上升沿同时产生。
所述各个薄膜晶体管均为N型薄膜晶体管，所述第一恒压电位为恒压高电位，第二恒压电位为恒压低电位。
所述各个薄膜晶体管均为P型薄膜晶体管，所述第一恒压电位为恒压低电位，第二恒压电位为恒压高电位。
所述各个薄膜晶体管均为非晶硅薄膜晶体管、低温多晶硅薄膜晶体管、或氧化物半导体薄膜晶体管。
本发明还提供一种GOA电路，包括：级联的多个GOA单元，每个GOA单元均包括：正反向扫描控制模块、与所述正反向扫描控制模块电性连接输出模块、与所述输出模块电性连接的下拉模块、与所述正反向扫描控制模块、输出模块和下拉模块均电性连接的下拉控制模块；
设n和m均为正整数，除第一级、与最后一级GOA单元外，在第n级GOA单元中：
所述正反向扫描控制模块接入上一级第n-1级GOA单元的栅极扫描驱动信号、下一级第n+1级GOA单元的栅极扫描驱动信号、以及第一恒压电位，用于根据上一级第n-1级GOA单元的栅极扫描驱动信号或下一级第n+1级GOA单元的栅极扫描驱动信号向输出模块输出第一恒压电位，进而控制所述输出单元打开，实现GOA电路正向扫描或反向扫描；
所述输出模块用于在第n级GOA单元作用期间输出第n级GOA单元的栅极扫描驱动信号；
所述下拉模块用于在第n级GOA单元的非作用期间下拉所述第n级GOA单元的栅极扫描驱动信号的电位；
所述下拉控制模块用于在第n级GOA单元的作用期间关闭下拉模块并维持输出模块打开，在第n级GOA单元的非作用期间打开下拉模块并关闭输出模块；
其中，所述正反向扫描控制模块包括：第一薄膜晶体管，所述第一薄膜晶体管的栅极接入上一级第n-1级GOA单元的栅极扫描驱动信号，源极接入第一恒压电位，漏极电性连接于第一节点；以及第三薄膜晶体管，所述第三薄膜晶体管的栅极接入下一级第n+1级GOA单元的栅极扫描驱动信号，源极接入第一恒压电位，漏极电性连接于第一节点；
所述输出单元包括：第二薄膜晶体管，所述第二薄膜晶体管的栅极电性连接于第二节点，源极接入第m条时钟信号，漏极接入第n级GOA单元的栅极扫描驱动信号；以及第一电容，所述第一电容的一端电性连接于第二节点另一端接入第n级GOA单元的栅极扫描驱动信号；
所述下拉模块包括：第四薄膜晶体管，所述第四薄膜晶体管的栅极电性连接于第三节点，源极电性连接于第n级GOA单元的栅极扫描驱动信号，漏极接入第二恒压电位；以及第二电容，所述第二电容的一端电性连接于第三节点，另一端接入第二恒压电位；
所述下拉控制模块包括：第六薄膜晶体管，所述第六薄膜晶体管的栅极电性连接于第三节点，源极电性连接于第一节点，漏极接入第二恒压电位；第七薄膜晶体管，所述第七薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第三节点，漏极接入第二恒压电位；以及第八薄膜晶体管，所述第八薄膜晶体管的栅极接入第m+2条时钟信号，源极接入第一恒压电位，漏极电性连接于第三节点；
所述GOA电路还包括稳压模块，所述稳压模块包括：第五薄膜晶体管，所述第五薄膜晶体管的栅极接入第一恒压电位，源极电性连接于第一节点，漏极电性连接于第二节点；
所述第一恒压电位与第二恒压电位的电位相反；
其中，在第一级GOA单元中，所述第一薄膜晶体管的栅极接入电路起始信号；
其中，在最后一级GOA单元中，所述第三薄膜晶体管的栅极接入电路起始信号；
其中，所述各个薄膜晶体管均为非晶硅薄膜晶体管、低温多晶硅薄膜晶体管、或氧化物半导体薄膜晶体管。
本发明的有益效果：本发明提供了一种GOA电路，该GOA电路的正反向扫描控制模块包括第一薄膜晶体管以及第三薄膜晶体管，所述第一薄膜晶体管的栅极电性连接于上一级第n-1级GOA单元的栅极扫描驱动信号，源极接入第一恒压电位，漏极电性连接于第一节点，所述第三薄膜晶体管的栅极电性连接于下一级第n+1级GOA单元的栅极扫描驱动信号，源极接入第一恒压电位，漏极电性连接于第一节点，通过该两个薄膜晶体管即可控制GOA电路在正反向扫描之间进行切换，相比于现有技术减少了两个控制信号的同时并不增加薄膜晶体管和电容，能够扩大IC的选择范围，有利于实现液晶显示器的窄边框。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为现有的一种GOA电路的电路图；
图2为本发明的GOA电路的电路图；
图3为本发明的GOA电路的第一级GOA单元的电路图；
图4为本发明的GOA电路的最后一级GOA单元的电路图；
图5为本发明的GOA电路的正向扫描时序图；
图6为本发明的GOA电路的反向扫描时序图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图2，本发明提供一种GOA电路，包括：级联的多个GOA单元，每个GOA单元均包括：正反向扫描控制模块100、与所述正反向扫描控制模块100电性连接输出模块200、与所述输出模块200电性连接的下拉模块(300)、与所述正反向扫描控制模块100、输出模块200和下拉模块300均电性连接的下拉控制模块400；
设n和m均为正整数，除第一级、与最后一级GOA单元外，在第n级GOA单元中：
所述正反向扫描控制模块100接入上一级第n-1级GOA单元的栅极扫描驱动信号G(n-1)、下一级第n+1级GOA单元的栅极扫描驱动信号G(n+1)、以及第一恒压电位，用于根据上一级第n-1级GOA单元的栅极扫描驱动信号G(n-1)或下一级第n+1级GOA单元的栅极扫描驱动信号G(n+1)向输出模块200输出第一恒压电位，进而控制所述输出单元200打开，实现GOA电路正向扫描或反向扫描；
所述输出模块200用于在第n级GOA单元作用期间输出第n级GOA单元的栅极扫描驱动信号G(n)；
所述下拉模块300用于在第n级GOA单元的非作用期间下拉所述第n级GOA单元的栅极扫描驱动信号G(n)的电位；
所述下拉控制模块400用于在第n级GOA单元的作用期间关闭下拉模块300并维持输出模块200打开，在第n级GOA单元的非作用期间打开下 拉模块300并关闭输出模块200。
具体地，所述正反向扫描控制模块100包括：第一薄膜晶体管T1，所述第一薄膜晶体管T1的栅极接入上一级第n-1级GOA单元的栅极扫描驱动信号G(n-1)，源极接入第一恒压电位，漏极电性连接于第一节点H(n)；以及第三薄膜晶体管T3，所述第三薄膜晶体管T3的栅极接入下一级第n+1级GOA单元的栅极扫描驱动信号G(n+1)，源极接入第一恒压电位，漏极电性连接于第一节点H(n)；
所述输出单元200包括：第二薄膜晶体管T2，所述第二薄膜晶体管T2的栅极电性连接于第二节点Q(n)，源极接入第m条时钟信号CK(m)，漏极接入第n级GOA单元的栅极扫描驱动信号G(n)；以及第一电容C1，所述第一电容C1的一端电性连接于第二节点Q(n)，另一端接入第n级GOA单元的栅极扫描驱动信号G(n)；
所述下拉模块300包括：第四薄膜晶体管T4，所述第四薄膜晶体管T4的栅极电性连接于第三节点P(n)，源极接入第n级GOA单元的栅极扫描驱动信号G(n)，漏极接入第二恒压电位；以及第二电容C2，所述第二电容C2的一端电性连接于第三节点P(n)，另一端接入第二恒压电位；
所述下拉控制模块400包括：第六薄膜晶体管T6，所述第六薄膜晶体管T6的栅极电性连接于第三节点P(n)，源极电性连接于第一节点H(n)，漏极接入第二恒压电位；第七薄膜晶体管T7，所述第七薄膜晶体管T7的栅极电性连接于第一节点H(n)，源极电性连接于第三节点P(n)，漏极接入第二恒压电位；第八薄膜晶体管T8，所述第八薄膜晶体管T8的栅极接入第m+2条时钟信号CK(m+2)，源极接入第一恒压电位，漏极电性连接于第三节点P(n)；
此外，所述GOA电路还包括稳压模块500，所述稳压模块500包括：第五薄膜晶体管T5，所述第五薄膜晶体管T5的栅极接入第一恒压电位，源极电性连接于第一节点H(n)，漏极电性连接于第二节点Q(n)。
所述第一恒压电位与第二恒压电位的电位相反。
具体地，请参阅图3，在第一级GOA单元中，所述第一薄膜晶体管T1的栅极接入电路起始信号STV。请参阅图4，在最后一级GOA单元中，所述第三薄膜晶体管T3的栅极接入电路起始信号STV。
需要说明的是，上述时钟信号共包括四条：分别为第一、第二、第三、及第四条时钟信；当所述第m条时钟信号CK(m)为第三条时钟信号时，第M+2条时钟信号CK(m+2)为第一条时钟信号；当所述第m条时钟信号CK(m)为第四条时钟信号时，第m+2条时钟信号CK(m+2)为第二条时钟信号。
特别地，所述第一、第二、第三、及第四条时钟信号的脉冲周期相同，所前一条时钟信号的下降沿与后一条时钟信号的上升沿同时产生，即所述第一条时钟信号的第一个脉冲信号首先产生，所述第一时钟信号的第一个脉冲信号结束的同时所述第二条时钟信号的第一个脉冲信号产生，所述第二条时钟信号的第一个脉冲信号结束的同时所述第三条时钟信号的第一个脉冲信号产生，所述第三条时钟信号的第一个脉冲信号结束的同时所述第四条时钟信号的第一个脉冲信号产生，所述第四条时钟信号的第一个脉冲信号结束的同时所述第一条时钟信号的第二个脉冲信号产生。
可选地，所述各个薄膜晶体管可以均为N型薄膜晶体管，也可以均为P型薄膜晶体管，当所述各个薄膜晶体管均为N型薄膜晶体管时，所述第一恒压电位为恒压高电位VGH，第二恒压电位为恒压低电位VGL。当所述各个薄膜晶体管均为P型薄膜晶体管时，所述第一恒压电位为恒压低电位VGL，第二恒压电位为恒压高电位VGH。图2所示的各个薄膜晶体管均为N型薄膜晶体管。
可选地，所述各个薄膜晶体管可选择非晶硅薄膜晶体管、低温多晶硅薄膜晶体管、及氧化物半导体薄膜晶体管等各种类型的薄膜晶体管。
请参阅图5，正向扫描时，所述GOA电路(N型薄膜晶体管)的工作过程如下：
阶段1、预充电阶段：此阶段中第n-1级GOA单元的栅极扫描驱动信号G(n-1)为高电位，第一薄膜晶体管T1导通，第一节点H(n)被预充电至高电位，第七薄膜晶体管T7导通，第三节点P(n)被拉低至恒压低电位VGL，第五薄膜晶体管T5受恒压高电位VGH的控制始终导通，第二节点Q(n)也被预充电至高电位；
阶段2、栅极扫描驱动信号G(n)输出高电位阶段：在此阶段中第n-1级GOA单元的栅极扫描驱动信号G(n-1)降低为低电位，第一薄膜晶体管T1关闭，第二节点Q(n)受第一电容C1的保持作用保持为高电位，第二薄膜晶体管T2导通，第m条时钟信号CK(m)提供高电位，栅极扫描驱动信号G(n)输出高电位，并传递至下一级第n+1级GOA单元的第一薄膜晶体管T1的栅极，以实现正向扫描的级传；
阶段3、栅极扫描驱动信号G(n)输出低电位阶段：在此阶段中第二节点Q(n)受第一电容C1保持作用仍保持为高电位，第二薄膜晶体管T2导通，第m条时钟信号CK(m)的低电位经由栅极扫描驱动信号G(n)输出；
阶段4、第二节点Q(n)拉低阶段：在此阶段中，第m+2条时钟信号CK(m+2)提供高电位，第八薄膜晶体管T8导通，第三节点P(n)被充电至高 电位，第六薄膜晶体管T6导通，第一和第二节点H(n)、Q(n)被拉低至恒压低电位VGL；
阶段5、第二节点Q(n)及栅极扫描驱动信号G(n)低电位维持阶段：当第一节点H(n)变为低电位后，第七薄膜晶体管T7处于截止状态，当第m+2条时钟信号CK(m+2)跳变为高电位时第八薄膜晶体管T8导通，第三节点P(n)点被充电至高电位，那么第四薄膜晶体管T4和第六薄膜晶体管T6均处于导通的状态，可以保证第二节点Q(n)及栅极扫描驱动信号G(n)的低电位稳定，同时第二电容C2对第三节点P(n)的高电位具有一定的保持作用。
相应地，请参阅图6，图6为本发明的GOA电路的反向扫描时序图，其工作过程与正向扫描不同点在于，其通过第三薄膜晶体管T3进行扫描控制，扫描顺序为最后一级向第一级扫描，也就说，下一级GOA单元的栅极扫描驱动信号输出的信号传递至上一级GOA单元的第三薄膜晶体管T3的栅极，以驱动上一级GOA单元开始输出，其余均与正向扫描相同，此处不再赘述。
可见，本发明的GOA电路相比于现有技术，不需要IC提供正向扫描控制信号和反向扫描控制信号，也没有增加薄膜晶体管或电容，同时也能保证GOA电路具备正反向扫描功能，扩大了GOA电路可选择的IC范围，有利于实现液晶显示器的窄边框。
综上所述，本发明提供了一种GOA电路，该GOA电路的正反向扫描控制模块包括第一薄膜晶体管以及第三薄膜晶体管，所述第一薄膜晶体管的栅极电性连接于上一级第n-1级GOA单元的栅极扫描驱动信号，源极接入第一恒压电位，漏极电性连接于第一节点，所述第三薄膜晶体管的栅极电性连接于下一级第n+1级GOA单元的栅极扫描驱动信号，源极接入第一恒压电位，漏极电性连接于第一节点，通过该两个薄膜晶体管即可控制GOA电路在正反向扫描之间进行切换，相比于现有技术减少了两个控制信号的同时并不增加薄膜晶体管和电容，能够扩大IC的选择范围，有利于实现液晶显示器的窄边框。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (14)

  1. 一种GOA电路，包括：级联的多个GOA单元，每个GOA单元均包括：正反向扫描控制模块、与所述正反向扫描控制模块电性连接输出模块、与所述输出模块电性连接的下拉模块、与所述正反向扫描控制模块、输出模块和下拉模块均电性连接的下拉控制模块；
    设n和m均为正整数，除第一级、与最后一级GOA单元外，在第n级GOA单元中：
    所述正反向扫描控制模块接入上一级第n-1级GOA单元的栅极扫描驱动信号、下一级第n+1级GOA单元的栅极扫描驱动信号、以及第一恒压电位，用于根据上一级第n-1级GOA单元的栅极扫描驱动信号或下一级第n+1级GOA单元的栅极扫描驱动信号向输出模块输出第一恒压电位，进而控制所述输出单元打开，实现GOA电路正向扫描或反向扫描；
    所述输出模块用于在第n级GOA单元作用期间输出第n级GOA单元的栅极扫描驱动信号；
    所述下拉模块用于在第n级GOA单元的非作用期间下拉所述第n级GOA单元的栅极扫描驱动信号的电位；
    所述下拉控制模块用于在第n级GOA单元的作用期间关闭下拉模块并维持输出模块打开，在第n级GOA单元的非作用期间打开下拉模块并关闭输出模块。
  2. 如权利要求1所述的GOA电路，其中，所述正反向扫描控制模块包括：第一薄膜晶体管，所述第一薄膜晶体管的栅极接入上一级第n-1级GOA单元的栅极扫描驱动信号，源极接入第一恒压电位，漏极电性连接于第一节点；以及第三薄膜晶体管，所述第三薄膜晶体管的栅极接入下一级第n+1级GOA单元的栅极扫描驱动信号，源极接入第一恒压电位，漏极电性连接于第一节点；
    所述输出单元包括：第二薄膜晶体管，所述第二薄膜晶体管的栅极电性连接于第二节点，源极接入第m条时钟信号，漏极接入第n级GOA单元的栅极扫描驱动信号；以及第一电容，所述第一电容的一端电性连接于第二节点另一端接入第n级GOA单元的栅极扫描驱动信号；
    所述下拉模块包括：第四薄膜晶体管，所述第四薄膜晶体管的栅极电性连接于第三节点，源极电性连接于第n级GOA单元的栅极扫描驱动信号，漏极接入第二恒压电位；以及第二电容，所述第二电容的一端电性连接于 第三节点，另一端接入第二恒压电位；
    所述下拉控制模块包括：第六薄膜晶体管，所述第六薄膜晶体管的栅极电性连接于第三节点，源极电性连接于第一节点，漏极接入第二恒压电位；第七薄膜晶体管，所述第七薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第三节点，漏极接入第二恒压电位；以及第八薄膜晶体管，所述第八薄膜晶体管的栅极接入第m+2条时钟信号，源极接入第一恒压电位，漏极电性连接于第三节点；
    所述GOA电路还包括稳压模块，所述稳压模块包括：第五薄膜晶体管，所述第五薄膜晶体管的栅极接入第一恒压电位，源极电性连接于第一节点，漏极电性连接于第二节点；
    所述第一恒压电位与第二恒压电位的电位相反。
  3. 如权利要求2所述的GOA电路，其中，在第一级GOA单元中，所述第一薄膜晶体管的栅极接入电路起始信号。
  4. 如权利要求2所述的GOA电路，其中，在最后一级GOA单元中，所述第三薄膜晶体管的栅极接入电路起始信号。
  5. 如权利要求2所述的GOA电路，包括四条时钟信号：第一、第二、第三、及第四条时钟信号；当所述第m条时钟信号为第三条时钟信号时，第m+2条时钟信号为第一条时钟信号；当所述第m条时钟信号为第四条时钟信号时，第M+2条时钟信号为第二条时钟信号。
  6. 如权利要求5所述的GOA电路，其中，所述第一、第二、第三、及第四条时钟信号的脉冲周期相同，前一条时钟信号的下降沿与后一条时钟信号的上升沿同时产生。
  7. 如权利要求2所述的GOA电路，其中，所述各个薄膜晶体管均为N型薄膜晶体管，所述第一恒压电位为恒压高电位，第二恒压电位为恒压低电位。
  8. 如权利要求2所述的GOA电路，其中，所述各个薄膜晶体管均为P型薄膜晶体管，所述第一恒压电位为恒压低电位，第二恒压电位为恒压高电位。
  9. 如权利要求2所述的GOA电路，其中，所述各个薄膜晶体管均为非晶硅薄膜晶体管、低温多晶硅薄膜晶体管、或氧化物半导体薄膜晶体管。
  10. 一种GOA电路，包括：级联的多个GOA单元，每个GOA单元均包括：正反向扫描控制模块、与所述正反向扫描控制模块电性连接输出模块、与所述输出模块电性连接的下拉模块、与所述正反向扫描控制模块、输出模块和下拉模块均电性连接的下拉控制模块；
    设n和m均为正整数，除第一级、与最后一级GOA单元外，在第n级GOA单元中：
    所述正反向扫描控制模块接入上一级第n-1级GOA单元的栅极扫描驱动信号、下一级第n+1级GOA单元的栅极扫描驱动信号、以及第一恒压电位，用于根据上一级第n-1级GOA单元的栅极扫描驱动信号或下一级第n+1级GOA单元的栅极扫描驱动信号向输出模块输出第一恒压电位，进而控制所述输出单元打开，实现GOA电路正向扫描或反向扫描；
    所述输出模块用于在第n级GOA单元作用期间输出第n级GOA单元的栅极扫描驱动信号；
    所述下拉模块用于在第n级GOA单元的非作用期间下拉所述第n级GOA单元的栅极扫描驱动信号的电位；
    所述下拉控制模块用于在第n级GOA单元的作用期间关闭下拉模块并维持输出模块打开，在第n级GOA单元的非作用期间打开下拉模块并关闭输出模块；
    其中，所述正反向扫描控制模块包括：第一薄膜晶体管，所述第一薄膜晶体管的栅极接入上一级第n-1级GOA单元的栅极扫描驱动信号，源极接入第一恒压电位，漏极电性连接于第一节点；以及第三薄膜晶体管，所述第三薄膜晶体管的栅极接入下一级第n+1级GOA单元的栅极扫描驱动信号，源极接入第一恒压电位，漏极电性连接于第一节点；
    所述输出单元包括：第二薄膜晶体管，所述第二薄膜晶体管的栅极电性连接于第二节点，源极接入第m条时钟信号，漏极接入第n级GOA单元的栅极扫描驱动信号；以及第一电容，所述第一电容的一端电性连接于第二节点另一端接入第n级GOA单元的栅极扫描驱动信号；
    所述下拉模块包括：第四薄膜晶体管，所述第四薄膜晶体管的栅极电性连接于第三节点，源极电性连接于第n级GOA单元的栅极扫描驱动信号，漏极接入第二恒压电位；以及第二电容，所述第二电容的一端电性连接于第三节点，另一端接入第二恒压电位；
    所述下拉控制模块包括：第六薄膜晶体管，所述第六薄膜晶体管的栅极电性连接于第三节点，源极电性连接于第一节点，漏极接入第二恒压电位；第七薄膜晶体管，所述第七薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第三节点，漏极接入第二恒压电位；以及第八薄膜晶体管，所述第八薄膜晶体管的栅极接入第m+2条时钟信号，源极接入第一恒压电位，漏极电性连接于第三节点；
    所述GOA电路还包括稳压模块，所述稳压模块包括：第五薄膜晶体管， 所述第五薄膜晶体管的栅极接入第一恒压电位，源极电性连接于第一节点，漏极电性连接于第二节点；
    所述第一恒压电位与第二恒压电位的电位相反；
    其中，在第一级GOA单元中，所述第一薄膜晶体管的栅极接入电路起始信号；
    其中，在最后一级GOA单元中，所述第三薄膜晶体管的栅极接入电路起始信号；
    其中，所述各个薄膜晶体管均为非晶硅薄膜晶体管、低温多晶硅薄膜晶体管、或氧化物半导体薄膜晶体管。
  11. 如权利要求10所述的GOA电路，包括四条时钟信号：第一、第二、第三、及第四条时钟信号；当所述第m条时钟信号为第三条时钟信号时，第m+2条时钟信号为第一条时钟信号；当所述第m条时钟信号为第四条时钟信号时，第M+2条时钟信号为第二条时钟信号。
  12. 如权利要求11所述的GOA电路，其中，所述第一、第二、第三、及第四条时钟信号的脉冲周期相同，前一条时钟信号的下降沿与后一条时钟信号的上升沿同时产生。
  13. 如权利要求10所述的GOA电路，其中，所述各个薄膜晶体管均为N型薄膜晶体管，所述第一恒压电位为恒压高电位，第二恒压电位为恒压低电位。
  14. 如权利要求10所述的GOA电路，其中，所述各个薄膜晶体管均为P型薄膜晶体管，所述第一恒压电位为恒压低电位，第二恒压电位为恒压高电位。
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