WO2018000945A1 - 移位寄存器单元、其驱动方法、栅极驱动电路及显示装置 - Google Patents

移位寄存器单元、其驱动方法、栅极驱动电路及显示装置 Download PDF

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Publication number
WO2018000945A1
WO2018000945A1 PCT/CN2017/083694 CN2017083694W WO2018000945A1 WO 2018000945 A1 WO2018000945 A1 WO 2018000945A1 CN 2017083694 W CN2017083694 W CN 2017083694W WO 2018000945 A1 WO2018000945 A1 WO 2018000945A1
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WIPO (PCT)
Prior art keywords
signal
node
switching transistor
output
module
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PCT/CN2017/083694
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English (en)
French (fr)
Inventor
董殿正
张斌
田明
张强
王光兴
张衎
陈鹏名
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to US15/577,740 priority Critical patent/US10467937B2/en
Publication of WO2018000945A1 publication Critical patent/WO2018000945A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0219—Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a shift register unit, a driving method thereof, a gate driving circuit, and a display device.
  • a gate driving signal is generally supplied to a gate of each thin film transistor (TFT) of the pixel region by a gate driving circuit.
  • the gate driving circuit can be integrated on the array substrate of the display panel by an array process, that is, a Gate Driver on Array (GOA) process, which not only saves cost but also symmetrical on both sides of the display panel.
  • GOA Gate Driver on Array
  • the current of the TFT that controls the clock signal CLK to be loaded to the signal output terminal is larger, the size of the TFT is larger, and the parasitic capacitance of the TFT is larger.
  • the potential of the clock signal CLK input to the source of the TFT changes from a low level to a high level, since the TFT has a large parasitic capacitance, the potential of the gate of the TFT also rises, thereby causing the
  • the clock signal CLK input from the source of the TFT is mistakenly supplied to the signal output terminal connected to the drain of the TFT, and the display panel may be defective in display or black screen.
  • an embodiment of the present invention provides a shift register unit and a driving side thereof.
  • the method, the gate driving circuit and the display device are used to avoid the problem that the TFT that controls the clock signal being loaded to the signal output terminal is turned on by mistake.
  • an embodiment of the present invention provides a shift register unit, including: an input module, a reset module, a control module, a pull-down module, and an output module; wherein:
  • the first control end of the input module and the input end of the input module are respectively connected to a signal input end, and the second control end of the input module is connected to the first clock signal end, and the output end of the input module is a node is connected to provide the signal of the signal input end to the first node under the control of the first clock signal end and the signal input end respectively;
  • the control end of the reset module is connected to the reset signal end, the input end of the reset module is connected to the reference signal end, the first output end of the reset module is connected to the first node, and the second end of the reset module
  • the output end is connected to the signal output end, and is configured to provide the signal of the reference signal end to the first node and the signal output end respectively under the control of the reset signal end;
  • the first control end of the control module is connected to the first node, the first input end of the control module is connected to the reference signal end, and the first output end of the control module is connected to the second node.
  • the second control end of the control module and the second input end of the control module are respectively connected to the first clock signal end, and the second output end of the control module is connected to the second node for Providing a signal of the reference signal end to the second node under control of the first node and providing a signal of the first clock signal end to the second node under control of the first clock signal end;
  • a first control end of the output module is connected to the first node, a first input end of the output module is connected to a second clock signal end, and a first output end of the output module is connected to the signal output end
  • the second control end of the output module is connected to the second node, the second input end of the output module is connected to the reference signal end, and the second output end of the output module is connected to the first node Connected, the third output end of the output module is connected to the signal output end, and is configured to provide a signal of the second clock signal end to the signal output end under the control of the first node, and in the The signals of the reference signal end are respectively provided to the first node and the signal output end under the control of the second node;
  • the two ends of the pull-down module are respectively connected to the first clock signal end and the first node, and are configured to pull down the potential of the first node when the potential of the second clock signal terminal rises.
  • the pull-down module specifically includes: a first capacitor
  • Both ends of the first capacitor are respectively connected to the first clock signal end and the first node.
  • the output module specifically includes: a first output module and a second output module; wherein:
  • the control end of the first output module is connected to the first node, the input end of the first output module is connected to the second clock signal end, and the output end of the first output module and the signal output Connected to the end, for providing the signal of the second clock signal end to the signal output end under the control of the first node;
  • the control end of the second output module is connected to the second node, the input end of the second output module is connected to the reference signal end, and the first output end of the second output module is connected to the first Connected to the node, the second output end of the second output module is connected to the signal output end, and is configured to provide the signal of the reference signal end to the first node and the node respectively under the control of the second node Said signal output.
  • the first output module specifically includes: a first switching transistor and a second capacitor; wherein:
  • a gate of the first switching transistor is connected to the first node, a source of the first switching transistor is connected to the second clock signal end, a drain of the first switching transistor and the signal output Connected to each other;
  • the second capacitor is coupled between a gate and a drain of the first switching transistor.
  • a ratio of a capacitance value of the first capacitor to a capacitance value of the second capacitor ranges from 0.8 to 1.2.
  • the second output module specifically includes: a second switching transistor and a third switching transistor; wherein:
  • a gate of the second switching transistor is connected to the second node, a source of the second switching transistor is connected to the reference signal terminal, and a drain of the second switching transistor is connected to the first node ;
  • a gate of the third switching transistor is connected to the second node, a source of the third switching transistor is connected to the reference signal end, and a drain of the third switching transistor is connected to the signal output end .
  • the output module further includes: a third output module
  • the control end of the third output module is connected to the first clock signal end, the input end of the third output module is connected to the reference signal end, and the output end of the third output module and the signal output The terminals are connected to provide a signal of the reference signal end to the signal output terminal under the control of the first clock signal end.
  • the third output module specifically includes: a fourth switching transistor
  • a gate of the fourth switching transistor is connected to the first clock signal end, a source of the fourth switching transistor is connected to the reference signal terminal, a drain of the fourth switching transistor and the signal output Connected to the end.
  • the input module specifically includes: a fifth switching transistor and a sixth switching transistor; wherein:
  • a gate and a source of the fifth switching transistor are respectively connected to the signal input end, and a drain of the fifth switching transistor is connected to the first node;
  • a gate of the sixth switching transistor is connected to the first clock signal end, a source of the sixth switching transistor is connected to the signal input end, and a drain of the sixth switching transistor is connected to the first Nodes are connected.
  • the reset module specifically includes: a seventh switching transistor and an eighth switching transistor; wherein:
  • a gate of the seventh switching transistor is connected to the reset signal terminal, a source of the seventh switching transistor is connected to the reference signal terminal, and a drain of the seventh switching transistor is connected to the first node ;
  • a gate of the eighth switching transistor is connected to the reset signal terminal, a source of the eighth switching transistor is connected to the reference signal terminal, and a drain of the eighth switching transistor is connected to the signal output terminal .
  • control module specifically includes: a first control module and a second control module; wherein:
  • the control end of the first control module is connected to the first node, the input end of the first control module is connected to the reference signal end, and the output end of the first control module is connected to the second node And for providing the signal of the reference signal end to the second node under the control of the first node;
  • the control end and the input end of the second control module are respectively connected to the first clock signal end, and the output end of the second control module is connected to the second node, and is used at the first clock signal end.
  • the signal of the first clock signal end is provided to the second node under control.
  • the first control module specifically includes: a ninth switching transistor and a tenth switching transistor; wherein:
  • a gate of the ninth switching transistor is connected to the first node, a source of the ninth switching transistor is connected to the reference signal terminal, and a drain of the ninth switching transistor is connected to the second node ;
  • the gate of the tenth switching transistor is connected to the first node, the source of the tenth switching transistor is connected to the reference signal end, and the drain of the tenth switching transistor is connected to the third node.
  • the second control module specifically includes: an eleventh switching transistor and a twelfth switching transistor; wherein:
  • a gate and a source of the eleventh switching transistor are respectively connected to the first clock signal end, and a drain of the eleventh switching transistor is connected to the third node;
  • a gate of the twelfth switching transistor is connected to the third node, a source of the twelfth switching transistor is connected to the first clock signal end, and a drain of the twelfth switching transistor is The second node is connected.
  • the embodiment of the present invention further provides a gate driving circuit, comprising: a plurality of the above-mentioned shift register units provided by the embodiment of the present invention; wherein:
  • each of the shift register units of each stage are respectively connected to the reset signal end of the shift register unit adjacent thereto;
  • the signal input terminal of the first stage shift register unit is connected to the frame start signal end.
  • the embodiment of the invention further provides a display device comprising the above-mentioned gate driving circuit provided by the embodiment of the invention.
  • the embodiment of the invention further provides a driving method of a shift register unit, comprising:
  • the signal of the signal input end is supplied to the first node under the control of the signal input end, and the signal of the second clock signal end is supplied to the signal output end under the control of the first node; at the first clock The signal of the first clock signal end is provided to the second node under the control of the signal end, and the signal of the reference signal end is respectively provided to the first node and the signal output end under the control of the second node;
  • a signal of the second clock signal end is provided to the signal output end under the control of the first node, and the signal of the reference signal end is provided to the Said second node;
  • the signals of the reference signal end are respectively supplied to the first node and the signal output end under the control of the reset signal end; the first clock signal is controlled under the control of the first clock signal end The signal of the terminal is provided to the second node, and the signal of the reference signal end is respectively provided to the first node and the signal output end under the control of the second node;
  • the potential of the second clock signal terminal rises, the potential of the first node is pulled down; and the signal of the first clock signal end is supplied to the And a second node, where the signal of the reference signal end is separately provided to the first node and the signal output end under the control of the second node.
  • the method further includes:
  • a signal of the reference signal terminal is supplied to the signal output terminal under the control of the first clock signal terminal.
  • the shift register unit, the driving method thereof, the gate driving circuit and the display device provided by the embodiment of the invention further comprise: an input module, a reset module, a control module, a pull-down module and an output module; A control end is connected to the first node, and the first input end is connected to the second clock signal end, the first output end and the signal output end Connected; the two ends of the pull-down module are respectively connected to the first clock signal end and the first node; when the potential of the second clock signal terminal rises, the potential of the first node also rises, at this time, due to the first clock signal The potential of the terminal is lowered.
  • the pull-down module can pull down the potential of the first node through the first clock signal end, thereby avoiding that the potential of the first node also rises when the potential of the second clock signal rises, and the second clock is mistakenly
  • the signal at the signal end is supplied to the signal output, which causes various display defects.
  • 1a is a schematic structural diagram of a shift register unit according to an embodiment of the present invention.
  • 1b is a second schematic structural diagram of a shift register unit according to an embodiment of the present invention.
  • FIG. 1c is a third schematic structural diagram of a shift register unit according to an embodiment of the present disclosure.
  • FIG. 1 is a fourth schematic structural diagram of a shift register unit according to an embodiment of the present disclosure.
  • 2a is a schematic structural diagram of a shift register unit according to an embodiment of the present disclosure
  • 2b is a second schematic structural diagram of a shift register unit according to an embodiment of the present invention.
  • 3a is a third schematic structural diagram of a shift register unit according to an embodiment of the present invention.
  • FIG. 3b is a fourth schematic structural diagram of a shift register unit according to an embodiment of the present disclosure.
  • FIG. 4 is a timing diagram of input and output of the shift register unit shown in FIG. 3a;
  • FIG. 5 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present invention.
  • a shift register unit as shown in FIG. 1a - FIG. 1d, includes: an input module 1, a reset module 2, a control module 3, a pull-down module 4, and an output module 5;
  • the first control terminal 1a of the input module 1 and the input terminal 1b of the input module 1 are respectively connected to the signal input terminal Input, the second control terminal 1c of the input module 1 is connected to the first clock signal terminal CLKB, and the output terminal 1d of the input module 1 Connected to the first node P1.
  • Input module 1 For supplying the signal of the signal input terminal Input to the first node P1 under the control of the first clock signal terminal CLKB and the signal input terminal Input respectively;
  • the control terminal 2a of the reset module 2 is connected to the reset signal terminal Reset
  • the input terminal 2b of the reset module 2 is connected to the reference signal terminal Vref
  • the first output terminal 2c of the reset module 2 is connected to the first node P1
  • the second module of the reset module 2 is The output terminal 2d is connected to the signal output terminal Output.
  • the reset module 2 is configured to provide the signal of the reference signal terminal Vref to the first node P1 and the signal output terminal Output respectively under the control of the reset signal terminal Reset;
  • the first control terminal 3a of the control module 3 is connected to the first node P1, the first input terminal 3b of the control module 3 is connected to the reference signal terminal Vref, and the first output terminal 3c of the control module 3 is connected to the second node P2, and the control module
  • the second control terminal 3d of the 3 and the second input terminal 3e of the control module 3 are respectively connected to the first clock signal terminal CLKB, and the second output terminal 3f of the control module 3 is connected to the second node P2.
  • the control module 3 is configured to provide the signal of the reference signal terminal Vref to the second node P2 under the control of the first node P1 and provide the signal of the first clock signal terminal CLKB to the second under the control of the first clock signal terminal CLKB.
  • the first control terminal 5a of the output module 5 is connected to the first node P1
  • the first input terminal 5b of the output module 5 is connected to the second clock signal terminal CLK
  • the first output terminal 5c of the output module 5 is connected to the signal output terminal Output.
  • the second control terminal 5d of the output module 5 is connected to the second node P2
  • the second input terminal 5e of the output module 5 is connected to the reference signal terminal Vref
  • the second output terminal 5f of the output module 5 is connected to the first node P1
  • the output module is
  • the third output terminal 5g of 5 is connected to the signal output terminal Output.
  • the output module 5 is configured to provide the signal of the second clock signal terminal CLK to the signal output terminal Output under the control of the first node P1 and the signal of the reference signal terminal Vref to the first node under the control of the second node P2, respectively.
  • One end 4a of the pull-down module 4 is connected to the first clock signal terminal CLKB, and the other end 4b of the pull-down module 4 is connected to the first node P1 for pulling down the first node P1 when the potential of the second clock signal terminal CLK rises. Potential.
  • the first control terminal 5a of the output module 5 is connected to the first node P1, and the first input terminal 5b of the output module 5 is connected to the second clock signal terminal CLK, and the output module 5 is The first output terminal 5c is connected to the signal output terminal Output; the one end 4a of the pull-down module 4 is connected to the first clock signal terminal CLKB, and the other end 4b of the pull-down module 4 is connected to the first node P1; the potential of the second clock signal terminal CLK When rising, the potential of the first node P1 also rises, at this time, due to the first clock signal end The potential of the CLKB is lowered.
  • the pull-down module 4 can lower the potential of the first node P1 through the first clock signal terminal CLKB, so that the potential of the first node P1 is more stable, thereby avoiding the potential rise of the CLK at the second clock signal terminal CLK.
  • the signal of the second clock signal terminal CLK is erroneously supplied to the signal output terminal Output, resulting in various display failures.
  • the potential of the reference signal terminal Vref is a low potential.
  • the pull-down module 4 may specifically include: a first capacitor C1; a first capacitor Both ends of C1 are respectively connected to the first clock signal terminal CLKB and the first node P1.
  • the potential of the first node P1 when the potential of the second clock signal terminal CLK rises, the potential of the first node P1 also rises, and at this time, due to the first clock signal The potential of the terminal CLKB is lowered, and the potential of the first node P1 can be pulled down by the bootstrap action of the first capacitor C1. Thus, the potential of the first node P1 can be prevented from rising when the potential of the second clock signal terminal CLK rises.
  • the signal of the second clock signal terminal CLK is supplied to the signal output terminal Output with high error and causes various display defects.
  • the above is only a specific structure of the pull-down module 4 in the shift register unit.
  • the specific structure of the pull-down module 4 is not limited to the above-mentioned structure provided by the embodiment of the present invention, and may be other structures known to those skilled in the art. , not limited here.
  • the output module 5 may specifically include: a first output module 51 and a second output module 52; wherein: the first output The control terminal 51a of the module 51 (corresponding to 5a in FIG. 1a) is connected to the first node P1, and the input terminal 51b of the first output module 51 (corresponding to 5b in FIG. 1a) is connected to the second clock signal terminal CLK.
  • An output terminal 51c of the output module 51 (corresponding to 5c in FIG.
  • the control terminal 52a of the second output module 52 (corresponding to 5d in FIG. 1a) is connected to the second node P2, and the input terminal 52b of the second output module 52 (corresponding to 5e in FIG. 1a) is connected to the reference signal terminal Vref.
  • the first output end 52c of the second output module 52 (equivalent to 5f) in FIG. 1a is connected to the first node P1, and the second output terminal 52d of the second output module 52 (corresponding to 5g in FIG. 1a) is connected to the signal output terminal for control under the control of the second node P2.
  • the signals of the reference signal terminal Vref are supplied to the first node P1 and the signal output terminal Output, respectively.
  • the first output module 51 specifically includes: a first switching transistor T1 and a first a capacitor C2; wherein: the gate of the first switching transistor T1 is connected to the first node P1, the source of the first switching transistor T1 is connected to the second clock signal terminal CLK, and the drain and signal output end of the first switching transistor T1 Output is connected; the second capacitor C2 is connected between the gate and the drain of the first switching transistor T1.
  • the first switching transistor T1 may be an N-type transistor, or, as shown in FIG. 2b and FIG. 3b, the first The switching transistor T1 can also be a P-type transistor, which is not limited herein.
  • the first switching transistor T1 as an N-type transistor as an example, when the potential of the first node P1 is low, the first switching transistor T1 is in an off state, and when the potential of the second clock signal terminal CLK is at a high potential, The current of a switching transistor T1 is large, the size of the first switching transistor T1 is large, and the parasitic capacitance of the first switching transistor T1 is large, which causes the potential of the first node P1 to be pulled high, and because of the second clock signal end The charging of the second capacitor C2 by CLK causes the potential of the first node P1 to be pulled high again. At this time, since the potential of the first clock signal terminal CLKB is low, the bootstrap action of the first capacitor C1 can be pulled down.
  • the potential of the first node P1 such that the potential of the first node P1 also rises when the potential of the second clock signal terminal CLK rises, so that the first switching transistor T1 is turned on by mistake and the second clock signal terminal CLK is mistakenly
  • the signal is supplied to the signal output Output, which causes various display defects.
  • the first switching transistor T1 is in an on state, and the second clock signal terminal CLK is connected to the signal output terminal Output; when the potential of the second clock signal terminal CLK is high, The signal output terminal Output outputs a high potential voltage signal.
  • the potential of the signal output terminal rises to further increase the potential of the first node P1. High, the charging ability of the first switching transistor T1 can be further improved to ensure the charging time of the pixel; when the potential of the second clock signal terminal CLK is low, the potential of the signal output terminal Output is low.
  • the above is only an example of the specific junction of the first output module 51 in the shift register unit.
  • the specific structure of the first output module 51 is not limited to the above-mentioned structure provided by the embodiment of the present invention, and may be other structures known to those skilled in the art, which is not limited herein.
  • the ratio of the capacitance value of the first capacitor to the capacitance value of the second capacitor may be controlled in a range of 0.8 to 1.2.
  • the ratio of the capacitance value of the first capacitor to the capacitance value of the second capacitor may be appropriately adjusted according to an actual situation, which is not limited herein.
  • the second output module 52 may specifically include: a second switching transistor T2 and a third switching transistor T3; wherein: the gate of the second switching transistor T2 is connected to the second node P2, the source of the second switching transistor T2 is connected to the reference signal terminal Vref, and the drain of the second switching transistor T2 is connected to the first node P1 is connected; the gate of the third switching transistor T3 is connected to the second node P2, the source of the third switching transistor T3 is connected to the reference signal terminal Vref, and the drain of the third switching transistor T3 is connected to the signal output terminal Output.
  • the second switching transistor T2 and the third switching transistor T3 may be N-type transistors, or, as shown in FIG. 2b and FIG. As shown in FIG. 3b, the second switching transistor T2 and the third switching transistor T3 may also be P-type transistors, which are not limited herein.
  • the second switching transistor T2 and the third switching transistor T3 as N-type transistors as an example, when the potential of the second node P2 is high, the second switching transistor T2 and the third switching transistor T3 are in an on state, and the reference signal is used.
  • the terminal Vref is respectively connected with the first node P1 and the signal output terminal, so that the potential of the first node P1 and the signal output terminal is low, and the reference signal terminal Vref respectively denoises the first node P1 and the signal output terminal. In this way, the noise of the signal outputted by the signal output terminal Output of the shift register unit can be reduced, and the stability of the signal outputted by the signal output terminal Output can be ensured.
  • the above is only a specific structure of the second output module 52 in the shift register unit.
  • the specific structure of the second output module 52 is not limited to the above-mentioned structure provided by the embodiment of the present invention, and may also be a person skilled in the art. Other structures that are known are not limited herein.
  • the output module 5 may further include: a third output module 53; and a third output module 53.
  • the control terminal 53a is connected to the first clock signal terminal CLKB
  • the input terminal 53b of the third output module 53 (also corresponding to 5e in FIG. 1a) is connected to the reference signal terminal Vref
  • the output terminal 53c of the third output module 53 is connected to the signal.
  • the output terminal is connected to provide a signal of the reference signal terminal Vref to the signal output terminal Output under the control of the first clock signal terminal CLKB; thus, the third output module 53 can be pulled down at the control of the first clock signal terminal CLKB.
  • the potential of the signal output terminal can further reduce the noise of the signal outputted by the signal output terminal and ensure the stability of the signal outputted by the signal output terminal Output.
  • the third output module 53 may specifically include: a fourth switching transistor T4; and a fourth switching transistor T4.
  • the gate is connected to the first clock signal terminal CLKB, the source of the fourth switching transistor T4 is connected to the reference signal terminal Vref, and the drain of the fourth switching transistor T4 is connected to the signal output terminal Output.
  • the fourth switching transistor T4 may be an N-type transistor, or, as shown in FIG. 3b, the fourth switching transistor T4 may also be The P-type transistor is not limited herein. Taking the fourth switching transistor T4 as an N-type transistor as an example, when the potential of the first clock signal terminal CLKB is high, the fourth switching transistor T4 is in an on state, and the reference signal terminal Vref is connected to the signal output terminal Output.
  • the potential of the signal output terminal is low, and the reference signal terminal Vref denoises the signal output terminal, so that the noise of the signal outputted by the signal output terminal of the shift register unit can be reduced, and the signal outputted by the signal output terminal is guaranteed. Stability.
  • the above is only a specific structure of the third output module 53 in the shift register unit.
  • the specific structure of the third output module 53 is not limited to the above-mentioned structure provided by the embodiment of the present invention, and may also be a person skilled in the art. Other structures that are known are not limited herein.
  • the input module 1 may specifically include: a fifth switching transistor T5 and a sixth a switching transistor T6; wherein: a gate and a source of the fifth switching transistor T5 are respectively connected to the signal input terminal Input, a drain of the fifth switching transistor T5 is connected to the first node P1; and a gate of the sixth switching transistor T6 A clock signal terminal CLKB is connected, a source of the sixth switching transistor T6 is connected to the signal input terminal Input, and a drain of the sixth switching transistor T6 is connected to the first node P1.
  • the fifth switching transistor T5 and the sixth switching transistor T6 may be N-type transistors, or, as shown in FIG. 2b and FIG. As shown in FIG. 3b, the fifth switching transistor T5 and the sixth switching transistor T6 may also be P-type transistors, which are not limited herein.
  • the fifth switching transistor T5 and the sixth switching transistor T6 as N-type transistors as an example, when the potential of the signal input terminal Input is high, the fifth switching transistor T5 is in an on state, and the signal input terminal Input is connected to the first node.
  • P1 is connected to make the potential of the first node P1 high; when the potential of the first clock signal terminal CLKB is high, the sixth switching transistor T6 is in an on state, and the signal input terminal Input is connected to the first node P1; When the potential of the signal input terminal Input is low, the potential of the first node P1 is made low, and when the potential of the signal input terminal Input is high, the potential of the first node P1 is made high.
  • the above is only a specific structure of the input module 1 in the shift register unit.
  • the specific structure of the input module 1 is not limited to the above structure provided by the embodiment of the present invention, and may be other structures known to those skilled in the art. , not limited here.
  • the reset module 2 may specifically include: a seventh switching transistor T7 and an eighth The switching transistor T8; wherein: the gate of the seventh switching transistor T7 is connected to the reset signal terminal Reset, the source of the seventh switching transistor T7 is connected to the reference signal terminal Vref, and the drain of the seventh switching transistor T7 is connected to the first node P1.
  • the gate of the eighth switching transistor T8 is connected to the reset signal terminal Reset, the source of the eighth switching transistor T8 is connected to the reference signal terminal Vref, and the drain of the eighth switching transistor T8 is connected to the signal output terminal Output.
  • the seventh switching transistor T7 and the eighth switching transistor T8 may be N-type transistors, or, as shown in FIG. 2b and FIG. As shown in FIG. 3b, the seventh switching transistor T7 and the eighth switching transistor T8 may also be P-type transistors, which are not limited herein. Taking the seventh switching transistor T7 and the eighth switching transistor T8 as N-type transistors as an example, when the potential of the reset signal terminal Reset is high, the seventh switching transistor T7 and the eighth switching transistor T8 are in an on state, and the reference signal is used.
  • the terminal Vref is respectively connected with the first node P1 and the signal output terminal, so that the potential of the first node P1 and the signal output terminal is low, and the reference signal terminal Vref respectively denoises the first node P1 and the signal output terminal. In this way, the noise of the signal outputted by the signal output terminal of the shift register unit can be reduced, and the signal output can be ensured. The stability of the signal output by the terminal Output.
  • the above is only a specific structure of the reset module 2 in the shift register unit.
  • the specific structure of the reset module 2 is not limited to the above structure provided by the embodiment of the present invention, and may be other structures known to those skilled in the art. , not limited here.
  • the control module 3 may specifically include: a first control module 31 and a second control module 32; wherein: the first control The control terminal 31a of the module 31 (corresponding to 3a in FIG. 1a) is connected to the first node P1, and the input terminal 31b of the first control module 31 (corresponding to 3b in FIG. 1a) is connected to the reference signal terminal Vref (equivalent to The output terminal 31c (corresponding to 3c in FIG. 1a) of FIG.
  • the control terminal 32a (corresponding to 3d in FIG. 1a) of the second control module 32 and the input terminal 32b (corresponding to 3e in FIG. 1a) of the second control module 32 are respectively connected to the first clock signal terminal CLKB, and the second control module An output terminal 32c (corresponding to 3f in FIG. 1a) is connected to the second node P2 for supplying the signal of the first clock signal terminal CLKB to the second node P2 under the control of the first clock signal terminal CLKB.
  • the first control module 31 may specifically include: a ninth switching transistor T9 and a tenth switching transistor T10; wherein: a gate of the ninth switching transistor T9 is connected to the first node P1, a source of the ninth switching transistor T9 is connected to the reference signal terminal Vref, and a drain of the ninth switching transistor T9 is connected to the second node P2 is connected; the gate of the tenth switching transistor T10 is connected to the first node P1, the source of the tenth switching transistor T10 is connected to the reference signal terminal Vref, and the drain of the tenth switching transistor T10 is connected to the third node P3.
  • the ninth switching transistor T9 and the tenth switching transistor T10 may be N-type transistors, or, as shown in FIG. 2b and FIG. As shown in FIG. 3b, the ninth switching transistor T9 and the tenth switching transistor T10 may also be P-type transistors, which are not limited herein.
  • the ninth switching transistor T9 and the tenth switching transistor T10 as N-type transistors as an example, when the potential of the first node P1 is high, the ninth switching transistor T9 and the tenth switching transistor T10 are in an on state, and the reference signal is used.
  • the terminal Vref is connected to the second node P2 such that the potential of the second node P2 is low, and the reference signal terminal Vref performs noise reduction on the second node P2.
  • the above is only a specific structure of the first control module 31 in the shift register unit.
  • the specific structure of the first control module 31 is not limited to the above-mentioned structure provided by the embodiment of the present invention, and may also be a person skilled in the art. Other structures that are known are not limited herein.
  • the second control module 32 may specifically include: an eleventh switching transistor T11. And a twelfth switching transistor T12; wherein: the gate and the source of the eleventh switching transistor T11 are respectively connected to the first clock signal terminal CLKB, and the drain of the eleventh switching transistor T11 is connected to the third node P3; The gate of the second switching transistor T12 is connected to the third node P3, the source of the twelfth switching transistor T12 is connected to the first clock signal terminal CLKB, and the drain of the twelfth switching transistor T12 is connected to the second node P2.
  • the eleventh switching transistor T11 and the twelfth switching transistor T12 may be N-type transistors, or, as shown in FIG. 2b. As shown in FIG. 3b, the eleventh switching transistor T11 and the twelfth switching transistor T12 may also be P-type transistors, which are not limited herein.
  • the eleventh switching transistor T11 and the twelfth switching transistor T12 as N-type transistors as an example, when the potential of the first clock signal terminal CLKB is high, the eleventh switching transistor T11 is in an on state, and the first clock is The signal terminal CLKB is connected to the third node P3, so that the potential of the third node P3 is high. At this time, the twelfth switching transistor T12 is in an on state, and the first clock signal terminal CLKB is connected to the second node P2, so that The potential of the second node P2 is high.
  • the above is only a specific structure of the second control module 32 in the shift register unit.
  • the specific structure of the second control module 32 is not limited to the above structure provided by the embodiment of the present invention, and may also be a person skilled in the art. Other structures that are known are not limited herein.
  • the first to the twelfth switching transistors T1 to T12 may each adopt an N type.
  • the first switching transistor T1 to the twelfth switching transistor T12 may each adopt a P-type transistor; This is not limited.
  • the switching transistor mentioned in the above embodiments of the present invention may be a thin film.
  • the TFT Thin Film Transistor
  • MOS Metal Oxide Semiconductor
  • the source and the drain of these switching transistors can be switched according to the type of the transistor and the input signal, and no specific distinction is made here.
  • an embodiment of the present invention further provides a driving method of a shift register unit, including:
  • the signal input signal is provided to the first node under the control of the signal input end, and the signal of the second clock signal end is supplied to the signal output end under the control of the first node; under the control of the first clock signal end Providing the signal of the first clock signal end to the second node, and providing the signal of the reference signal end to the first node and the signal output end respectively under the control of the second node;
  • the signal of the second clock signal end is provided to the signal output end under the control of the first node, and the signal of the reference signal end is provided to the second node under the control of the first node;
  • the signals of the reference signal end are respectively supplied to the first node and the signal output end under the control of the reset signal end; and the signal of the first clock signal end is provided to the second node under the control of the first clock signal end, The signals of the reference signal end are respectively supplied to the first node and the signal output end under the control of the two nodes;
  • the signal of the first clock signal end is provided to the second node under the control of the first clock signal end
  • the signal of the reference signal end is respectively provided to the first node and under the control of the second node.
  • the signal output end can lower the potential of the first node and the signal output end; under the control of the reset signal end, the signals of the reference signal end are respectively supplied to the first node and the signal output end, and the potentials of the first node and the signal output end can be pulled down; In this way, the noise of the signal outputted from the signal output terminal of the shift register unit can be reduced, and the stability of the signal outputted from the signal output terminal can be ensured; and when the potential of the second clock signal terminal rises, the potential of the first node is also caused.
  • the method further includes:
  • the signal of the reference signal terminal is supplied to the signal output terminal under the control of the first clock signal terminal; thus, the potential of the low signal output terminal can be pulled down at the control of the first clock signal terminal, thereby being further reduced
  • the noise of the signal output from the signal output ensures the stability of the signal output from the signal output.
  • the operation of the above-described shift register unit provided by the embodiment of the present invention will be described below by taking the first switching transistor T1 to the twelfth switching transistor T12 as N-type transistors as an example.
  • the first to twelfth switching transistors T1 to T12 are N-type transistors, and each of the N-type transistors is turned on under a high potential, and is turned off at a low potential.
  • the effective pulse signal of the input signal terminal Input, the first clock signal terminal CLKB and the reset signal terminal Reset is a high potential signal
  • the signal of the reference signal terminal Vref is a low potential signal.
  • the input/output timing diagram corresponding to FIG. 3a is as shown in FIG. 4. Specifically, four stages t1 to t4 in the input/output timing diagram shown in FIG. 4 are selected. In the following description, 1 indicates a high potential, and 0 indicates a low potential.
  • the first switch signal terminal CLKB is connected to the third node P3, so that the potential of the third node P3 is Potential, the twelfth switching transistor T12 is turned on, connecting the first clock signal terminal CLKB with the second node P2, so that the potential of the second node P2 is high, and at this time, the second switching transistor T2 and the third switching transistor T3 Turning on, connecting the reference signal terminal Vref to the first node P1 and the signal output terminal Output, respectively, so that the first node P1 and the signal output terminal Output The potential of the potential is low, and the reference signal terminal Vref respectively denoises the first node P1 and the signal output terminal Output;
  • the twelfth switching transistor T12 is turned on, and the first clock signal terminal CLKB is connected to the second node P2, so that the potential of the second node P2 is high.
  • the second switching transistor T2 and the third switching transistor T3 are turned on, and the reference signal terminal Vref is respectively connected to the first node P1 and the signal output terminal Output, so that the potential of the first node P1 and the signal output terminal Output
  • the reference signal terminal Vref respectively denoises the first node P1 and the signal output terminal Output
  • the fourth switching transistor T4 is turned on, and the reference signal terminal Vref signal is The output terminal is connected so that the potential of the signal output terminal is low, and the reference signal terminal Vref is connected to the signal output terminal. Output for noise reduction;
  • the signal output Output will always output a low voltage signal until the next frame arrives.
  • the above description is based on the case where the first switching transistor T1 to the twelfth switching transistor T12 are both N-type transistors. Specifically, the working principle and the above-mentioned first working principle of the first switching transistor T1 to the twelfth switching transistor T12 are P-type transistors. The operation principle of the N-type transistors of a switching transistor T1 to a twelfth switching transistor T12 is similar, and will not be described herein.
  • an embodiment of the present invention further provides a gate driving circuit.
  • the method includes: cascading a plurality of the above-mentioned shift register units provided by the embodiment of the present invention: SR(1), SR (2)...SR(n)...SR(N-1), SR(N) (total of N shift register units, 1 ⁇ n ⁇ N);
  • the signal input terminal Input of the first stage shift register unit SR(1) is connected to the frame start signal terminal STV.
  • each of the shift register units in the above-mentioned gate driving circuit provided by the embodiment of the present invention is identical in function and structure to the above-described shift register unit provided by the embodiment of the present invention, and the repeated description thereof will not be repeated.
  • an embodiment of the present invention further provides a display device, including the above-mentioned gate driving circuit provided by the embodiment of the present invention, which may be: a mobile phone, a tablet computer, a television, a display, a notebook computer, and a digital device. Any product or component that has a display function, such as a photo frame or a navigator.
  • a display device including the above-mentioned gate driving circuit provided by the embodiment of the present invention, which may be: a mobile phone, a tablet computer, a television, a display, a notebook computer, and a digital device. Any product or component that has a display function, such as a photo frame or a navigator.
  • the display device reference may be made to the embodiment of the above-described gate driving circuit, and the repeated description is omitted.
  • the embodiment of the invention provides a shift register unit, a driving method thereof, a gate driving circuit and a display device.
  • the shift register unit comprises: an input module, a reset module, a control module, a pull-down module and an output module; and an output module
  • the first control end is connected to the first node, the first input end is connected to the second clock signal end, and the first output end is connected to the signal output end; the two ends of the pull-down module are respectively connected with the first clock signal end and the first node;
  • the pull-down module can pull down the first node through the first clock signal end.
  • the potential is such that the potential of the first node also rises when the potential of the second clock signal rises, and the signal of the second clock signal is erroneously supplied to the signal output terminal, thereby causing various display defects.

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Abstract

一种移位寄存器单元、其驱动方法、栅极驱动电路及显示装置，该移位寄存器单元包括：输入模块（1）、复位模块（2）、控制模块（3）、下拉模块（4）和输出模块（5）；输出模块（5）的第一控制端（5a）与第一节点（P1）相连，其第一输入端（5b）与第二时钟信号端（CLK）相连，其第一输出端（5c）与信号输出端（Output）相连；下拉模块（4）的两端（4a，4b）分别与第一时钟信号端（CLKB）和第一节点（P1）相连；下拉模块（4）可以通过第一时钟信号端（CLKB）拉低第一节点（P1）的电位，从而可以避免在第二时钟信号端（CLK）的电位升高时第一节点（P1）的电位也升高而误将第二时钟信号端（CLK）的信号提供给信号输出端（Output）进而导致各种显示不良。

Description

移位寄存器单元、其驱动方法、栅极驱动电路及显示装置
相关申请
本申请要求2016年6月30日提交的、申请号为201610512805.3的中国专利申请的优先权，该申请的全部内容通过引用并入本文。
技术领域
本发明涉及显示技术领域，尤其涉及一种移位寄存器单元、其驱动方法、栅极驱动电路及显示装置。
背景技术
在显示面板中，通常通过栅极驱动电路向像素区域的各个薄膜晶体管(TFT，Thin Film Transistor)的栅极提供栅极驱动信号。栅极驱动电路可以通过阵列工艺集成在显示面板的阵列基板上，即阵列基板行驱动(Gate Driver on Array，GOA)工艺，这种集成工艺不仅节省了成本，而且可以做到显示面板两边对称的美观设计，同时，也省去了栅极驱动电路的绑定区域以及扇出的布线空间，从而可以实现窄边框的设计；并且，这种集成工艺还可以省去栅极扫描线方向的绑定工艺，从而提高了产能和良率。
目前，现有的栅极驱动电路中的每级移位寄存器单元中，控制时钟信号CLK加载到信号输出端Output的TFT的电流较大，该TFT的尺寸较大，该TFT的寄生电容较大。在该TFT的源极输入的时钟信号CLK的电位由低电平变为高电平时，由于该TFT具有较大的寄生电容，会导致该TFT的栅极的电位也升高，从而会导致该TFT误开启，这样，会误将该TFT的源极输入的时钟信号CLK提供给与该TFT的漏极相连的信号输出端Output，进而会使显示面板出现画面异常、黑屏等显示不良。
因此，如何避免控制时钟信号加载到信号输出端的TFT误开启，是本领域技术人员亟需解决的技术问题。
发明内容
有鉴于此，本发明实施例提供了一种移位寄存器单元、其驱动方 法、栅极驱动电路及显示装置，用以避免控制时钟信号加载到信号输出端的TFT误开启的问题。
因此，本发明实施例提供了一种移位寄存器单元，包括：输入模块、复位模块、控制模块、下拉模块和输出模块；其中：
所述输入模块的第一控制端和所述输入模块的输入端分别与信号输入端相连，所述输入模块的第二控制端与第一时钟信号端相连，所述输入模块的输出端与第一节点相连，用于分别在所述第一时钟信号端和所述信号输入端的控制下将所述信号输入端的信号提供给所述第一节点；
所述复位模块的控制端与复位信号端相连，所述复位模块的输入端与参考信号端相连，所述复位模块的第一输出端与所述第一节点相连，所述复位模块的第二输出端与信号输出端相连，用于在所述复位信号端的控制下将所述参考信号端的信号分别提供给所述第一节点和所述信号输出端；
所述控制模块的第一控制端与所述第一节点相连，所述控制模块的第一输入端与所述参考信号端相连，所述控制模块的第一输出端与第二节点相连，所述控制模块的第二控制端和所述控制模块的第二输入端分别与所述第一时钟信号端相连，所述控制模块的第二输出端与所述第二节点相连，用于在所述第一节点的控制下将所述参考信号端的信号提供给所述第二节点以及在所述第一时钟信号端的控制下将所述第一时钟信号端的信号提供给所述第二节点；
所述输出模块的第一控制端与所述第一节点相连，所述输出模块的第一输入端与第二时钟信号端相连，所述输出模块的第一输出端与所述信号输出端相连，所述输出模块的第二控制端与所述第二节点相连，所述输出模块的第二输入端与所述参考信号端相连，所述输出模块的第二输出端与所述第一节点相连，所述输出模块的第三输出端与所述信号输出端相连，用于在所述第一节点的控制下将所述第二时钟信号端的信号提供给所述信号输出端以及在所述第二节点的控制下将所述参考信号端的信号分别提供给所述第一节点和所述信号输出端；
所述下拉模块的两端分别与所述第一时钟信号端和所述第一节点相连，用于在所述第二时钟信号端的电位升高时拉低所述第一节点的电位。
在一种可能的实现方式中，在本发明实施例提供的上述移位寄存器单元中，所述下拉模块，具体包括：第一电容；
所述第一电容的两端分别与所述第一时钟信号端和所述第一节点相连。
在一种可能的实现方式中，在本发明实施例提供的上述移位寄存器单元中，所述输出模块，具体包括：第一输出模块和第二输出模块；其中：
所述第一输出模块的控制端与所述第一节点相连，所述第一输出模块的输入端与所述第二时钟信号端相连，所述第一输出模块的输出端与所述信号输出端相连，用于在所述第一节点的控制下将所述第二时钟信号端的信号提供给所述信号输出端；
所述第二输出模块的控制端与所述第二节点相连，所述第二输出模块的输入端与所述参考信号端相连，所述第二输出模块的第一输出端与所述第一节点相连，所述第二输出模块的第二输出端与所述信号输出端相连，用于在所述第二节点的控制下将所述参考信号端的信号分别提供给所述第一节点和所述信号输出端。
在一种可能的实现方式中，在本发明实施例提供的上述移位寄存器单元中，所述第一输出模块，具体包括：第一开关晶体管和第二电容；其中：
所述第一开关晶体管的栅极与所述第一节点相连，所述第一开关晶体管的源极与所述第二时钟信号端相连，所述第一开关晶体管的漏极与所述信号输出端相连；
所述第二电容连接于所述第一开关晶体管的栅极和漏极之间。
在一种可能的实现方式中，在本发明实施例提供的上述移位寄存器单元中，所述第一电容的电容值与所述第二电容的电容值的比值的范围为0.8至1.2。
在一种可能的实现方式中，在本发明实施例提供的上述移位寄存器单元中，所述第二输出模块，具体包括：第二开关晶体管和第三开关晶体管；其中：
所述第二开关晶体管的栅极与所述第二节点相连，所述第二开关晶体管的源极与所述参考信号端相连，所述第二开关晶体管的漏极与所述第一节点相连；
所述第三开关晶体管的栅极与所述第二节点相连，所述第三开关晶体管的源极与所述参考信号端相连，所述第三开关晶体管的漏极与所述信号输出端相连。
在一种可能的实现方式中，在本发明实施例提供的上述移位寄存器单元中，所述输出模块，还包括：第三输出模块；
所述第三输出模块的控制端与所述第一时钟信号端相连，所述第三输出模块的输入端与所述参考信号端相连，所述第三输出模块的输出端与所述信号输出端相连，用于在所述第一时钟信号端的控制下将所述参考信号端的信号提供给所述信号输出端。
在一种可能的实现方式中，在本发明实施例提供的上述移位寄存器单元中，所述第三输出模块，具体包括：第四开关晶体管；
所述第四开关晶体管的栅极与所述第一时钟信号端相连，所述第四开关晶体管的源极与所述参考信号端相连，所述第四开关晶体管的漏极与所述信号输出端相连。
在一种可能的实现方式中，在本发明实施例提供的上述移位寄存器单元中，所述输入模块，具体包括：第五开关晶体管和第六开关晶体管；其中：
所述第五开关晶体管的栅极和源极分别与所述信号输入端相连，所述第五开关晶体管的漏极与所述第一节点相连；
所述第六开关晶体管的栅极与所述第一时钟信号端相连，所述第六开关晶体管的源极与所述信号输入端相连，所述第六开关晶体管的漏极与所述第一节点相连。
在一种可能的实现方式中，在本发明实施例提供的上述移位寄存器单元中，所述复位模块，具体包括：第七开关晶体管和第八开关晶体管；其中：
所述第七开关晶体管的栅极与所述复位信号端相连，所述第七开关晶体管的源极与所述参考信号端相连，所述第七开关晶体管的漏极与所述第一节点相连；
所述第八开关晶体管的栅极与所述复位信号端相连，所述第八开关晶体管的源极与所述参考信号端相连，所述第八开关晶体管的漏极与所述信号输出端相连。
在一种可能的实现方式中，在本发明实施例提供的上述移位寄存 器单元中，所述控制模块，具体包括：第一控制模块和第二控制模块；其中：
所述第一控制模块的控制端与所述第一节点相连，所述第一控制模块的输入端与所述参考信号端相连，所述第一控制模块的输出端与所述第二节点相连，用于在所述第一节点的控制下将所述参考信号端的信号提供给所述第二节点；
所述第二控制模块的控制端和输入端分别与所述第一时钟信号端相连，所述第二控制模块的输出端与所述第二节点相连，用于在所述第一时钟信号端的控制下将所述第一时钟信号端的信号提供给所述第二节点。
在一种可能的实现方式中，在本发明实施例提供的上述移位寄存器单元中，所述第一控制模块，具体包括：第九开关晶体管和第十开关晶体管；其中：
所述第九开关晶体管的栅极与所述第一节点相连，所述第九开关晶体管的源极与所述参考信号端相连，所述第九开关晶体管的漏极与所述第二节点相连；
所述第十开关晶体管的栅极与所述第一节点相连，所述第十开关晶体管的源极与所述参考信号端相连，所述第十开关晶体管的漏极与第三节点相连。
在一种可能的实现方式中，在本发明实施例提供的上述移位寄存器单元中，所述第二控制模块，具体包括：第十一开关晶体管和第十二开关晶体管；其中：
所述第十一开关晶体管的栅极和源极分别与所述第一时钟信号端相连，所述第十一开关晶体管的漏极与所述第三节点相连；
所述第十二开关晶体管的栅极与所述第三节点相连，所述第十二开关晶体管的源极与所述第一时钟信号端相连，所述第十二开关晶体管的漏极与所述第二节点相连。
本发明实施例还提供了一种栅极驱动电路，包括：级联的多个本发明实施例提供的上述移位寄存器单元；其中：
除第一级移位寄存器单元之外，其余每一级移位寄存器单元的信号输出端分别和与其相邻的上一级移位寄存器单元的复位信号端相连；
除最后一级移位寄存器单元之外，其余每一级移位寄存器单元的信号输出端分别和与其相邻的下一级移位寄存器单元的信号输入端相连；
第一级移位寄存器单元的信号输入端与帧起始信号端相连。
本发明实施例还提供了一种显示装置，包括：本发明实施例提供的上述栅极驱动电路。
本发明实施例还提供了一种移位寄存器单元的驱动方法，包括：
在第一阶段，在信号输入端的控制下将所述信号输入端的信号提供给第一节点，在所述第一节点的控制下将第二时钟信号端的信号提供给信号输出端；在第一时钟信号端的控制下将所述第一时钟信号端的信号提供给第二节点，在所述第二节点的控制下将参考信号端的信号分别提供给所述第一节点和所述信号输出端；
在第二阶段，在所述第一节点的控制下将所述第二时钟信号端的信号提供给所述信号输出端，在所述第一节点的控制下将所述参考信号端的信号提供给所述第二节点；
在第三阶段，在复位信号端的控制下将所述参考信号端的信号分别提供给所述第一节点和所述信号输出端；在所述第一时钟信号端的控制下将所述第一时钟信号端的信号提供给所述第二节点，在所述第二节点的控制下将所述参考信号端的信号分别提供给所述第一节点和所述信号输出端；
在第四阶段，在所述第二时钟信号端的电位升高时拉低所述第一节点的电位；在所述第一时钟信号端的控制下将所述第一时钟信号端的信号提供给所述第二节点，在所述第二节点的控制下将所述参考信号端的信号分别提供给所述第一节点和所述信号输出端。
在一种可能的实现方式中，在本发明实施例提供的上述驱动方法中，还包括：
在第一阶段和第三阶段，在所述第一时钟信号端的控制下将所述参考信号端的信号提供给所述信号输出端。
本发明实施例提供的上述移位寄存器单元、其驱动方法、栅极驱动电路及显示装置，该移位寄存器单元包括：输入模块、复位模块、控制模块、下拉模块和输出模块；输出模块的第一控制端与第一节点相连，第一输入端与第二时钟信号端相连，第一输出端与信号输出端 相连；下拉模块的两端分别与第一时钟信号端和第一节点相连；在第二时钟信号端的电位升高时，会导致第一节点的电位也升高，此时，由于第一时钟信号端的电位降低，因此，下拉模块可以通过第一时钟信号端拉低第一节点的电位，从而可以避免在第二时钟信号端的电位升高时第一节点的电位也升高而误将第二时钟信号端的信号提供给信号输出端进而导致各种显示不良。
附图说明
图1a为本发明实施例提供的移位寄存器单元的结构示意图之一；
图1b为本发明实施例提供的移位寄存器单元的结构示意图之二；
图1c为本发明实施例提供的移位寄存器单元的结构示意图之三；
图1d为本发明实施例提供的移位寄存器单元的结构示意图之四；
图2a为本发明实施例提供的移位寄存器单元的具体结构示意图之一；
图2b为本发明实施例提供的移位寄存器单元的具体结构示意图之二；
图3a为本发明实施例提供的移位寄存器单元的具体结构示意图之三；
图3b为本发明实施例提供的移位寄存器单元的具体结构示意图之四；
图4为图3a所示的移位寄存器单元的输入输出时序图；
图5为本发明实施例提供的栅极驱动电路的结构示意图。
具体实施方式
下面结合附图，对本发明实施例提供的移位寄存器单元、其驱动方法、栅极驱动电路及显示装置的具体实施方式进行详细地说明。
本发明实施例提供的一种移位寄存器单元，如图1a-图1d所示，包括：输入模块1、复位模块2、控制模块3、下拉模块4和输出模块5；其中：
输入模块1的第一控制端1a和输入模块1的输入端1b分别与信号输入端Input相连，输入模块1的第二控制端1c与第一时钟信号端CLKB相连，输入模块1的输出端1d与第一节点P1相连。输入模块1 用于分别在第一时钟信号端CLKB和信号输入端Input的控制下将信号输入端Input的信号提供给第一节点P1；
复位模块2的控制端2a与复位信号端Reset相连，复位模块2的输入端2b与参考信号端Vref相连，复位模块2的第一输出端2c与第一节点P1相连，复位模块2的第二输出端2d与信号输出端Output相连。复位模块2用于在复位信号端Reset的控制下将参考信号端Vref的信号分别提供给第一节点P1和信号输出端Output；
控制模块3的第一控制端3a与第一节点P1相连，控制模块3的第一输入端3b与参考信号端Vref相连，控制模块3的第一输出端3c与第二节点P2相连，控制模块3的第二控制端3d和控制模块3的第二输入端3e分别与第一时钟信号端CLKB相连，控制模块3的第二输出端3f与第二节点P2相连。控制模块3用于在第一节点P1的控制下将参考信号端Vref的信号提供给第二节点P2以及在第一时钟信号端CLKB的控制下将第一时钟信号端CLKB的信号提供给第二节点P2；
输出模块5的第一控制端5a与第一节点P1相连，输出模块5的第一输入端5b与第二时钟信号端CLK相连，输出模块5的第一输出端5c与信号输出端Output相连，输出模块5的第二控制端5d与第二节点P2相连，输出模块5的第二输入端5e与参考信号端Vref相连，输出模块5的第二输出端5f与第一节点P1相连，输出模块5的第三输出端5g与信号输出端Output相连。输出模块5用于在第一节点P1的控制下将第二时钟信号端CLK的信号提供给信号输出端Output以及在第二节点P2的控制下将参考信号端Vref的信号分别提供给第一节点P1和信号输出端Output；
下拉模块4的一端4a和第一时钟信号端CLKB相连，下拉模块4的另一端4b和第一节点P1相连，用于在第二时钟信号端CLK的电位升高时拉低第一节点P1的电位。
本发明实施例提供的上述移位寄存器单元，输出模块5的第一控制端5a与第一节点P1相连，输出模块5的第一输入端5b与第二时钟信号端CLK相连，输出模块5的第一输出端5c与信号输出端Output相连；下拉模块4的一端4a和第一时钟信号端CLKB相连，下拉模块4的另一端4b和第一节点P1相连；在第二时钟信号端CLK的电位升高时，会导致第一节点P1的电位也升高，此时，由于第一时钟信号端 CLKB的电位降低，因此，下拉模块4可以通过第一时钟信号端CLKB拉低第一节点P1的电位，使第一节点P1的电位更加稳定，从而可以避免在第二时钟信号端CLK的电位升高时第一节点P1的电位也升高而误将第二时钟信号端CLK的信号提供给信号输出端Output进而导致各种显示不良。
在具体实施时，本发明实施例提供的上述移位寄存器单元中，参考信号端Vref的电位为低电位。
下面结合具体实施例，对本发明进行详细说明。需要说明的是，本实施例中是为了更好的解释本发明，但不限制本发明。
在具体实施时，在本发明实施例提供的上述移位寄存器单元中，如图2a、图2b、图3a和图3b所示，下拉模块4，具体可以包括：第一电容C1；第一电容C1的两端分别与第一时钟信号端CLKB和第一节点P1相连。
具体地，在本发明实施例提供的上述移位寄存器单元中，在第二时钟信号端CLK的电位升高时，会导致第一节点P1的电位也升高，此时，由于第一时钟信号端CLKB的电位降低，通过第一电容C1的自举作用，可以拉低第一节点P1的电位，这样，可以避免在第二时钟信号端CLK的电位升高时第一节点P1的电位也升高而误将第二时钟信号端CLK的信号提供给信号输出端Output进而导致各种显示不良。
以上仅是举例说明移位寄存器单元中下拉模块4的具体结构，在具体实施时，下拉模块4的具体结构不限于本发明实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
在具体实施时，在本发明实施例提供的上述移位寄存器单元中，如图1b所示，输出模块5，具体可以包括：第一输出模块51和第二输出模块52；其中：第一输出模块51的控制端51a(相当于图1a中的5a)与第一节点P1相连，第一输出模块51的输入端51b(相当于图1a中的5b)与第二时钟信号端CLK相连，第一输出模块51的输出端51c(相当于图1a中的5c)与信号输出端Output相连，用于在第一节点P1的控制下将第二时钟信号端CLK的信号提供给信号输出端Output；第二输出模块52的控制端52a(相当于图1a中的5d)与第二节点P2相连，第二输出模块52的输入端52b(相当于图1a中的5e)与参考信号端Vref相连，第二输出模块52的第一输出端52c(相当于 图1a中的5f)与第一节点P1相连，第二输出模块52的第二输出端52d(相当于图1a中的5g)与信号输出端Output相连，用于在第二节点P2的控制下将参考信号端Vref的信号分别提供给第一节点P1和信号输出端Output。
在具体实施时，在本发明实施例提供的上述移位寄存器单元中，如图2a、图2b、图3a和图3b所示，第一输出模块51，具体包括：第一开关晶体管T1和第二电容C2；其中：第一开关晶体管T1的栅极与第一节点P1相连，第一开关晶体管T1的源极与第二时钟信号端CLK相连，第一开关晶体管T1的漏极与信号输出端Output相连；第二电容C2连接于第一开关晶体管T1的栅极和漏极之间。
具体地，在本发明实施例提供的上述移位寄存器单元中，如图2a和图3a所示，第一开关晶体管T1可以为N型晶体管，或者，如图2b和图3b所示，第一开关晶体管T1也可以为P型晶体管，在此不作限定。以第一开关晶体管T1为N型晶体管为例，在第一节点P1的电位为低电位时，第一开关晶体管T1处于截止状态，在第二时钟信号端CLK的电位为高电位时，由于第一开关晶体管T1的电流较大，第一开关晶体管T1的尺寸较大，第一开关晶体管T1的寄生电容较大，会导致第一节点P1的电位被拉高，并且，由于第二时钟信号端CLK向第二电容C2充电，会导致第一节点P1的电位再次被拉高，此时，由于第一时钟信号端CLKB的电位为低电位，通过第一电容C1的自举作用，可以拉低第一节点P1的电位，这样，可以避免在第二时钟信号端CLK的电位升高时第一节点P1的电位也升高而使第一开关晶体管T1误开启从而误将第二时钟信号端CLK的信号提供给信号输出端Output进而导致各种显示不良。在第一节点P1的电位为高电位时，第一开关晶体管T1处于导通状态，将第二时钟信号端CLK与信号输出端Output连接；在第二时钟信号端CLK的电位为高电位时，信号输出端Output输出高电位的电压信号，由于第二电容C2的自举作用和第一开关晶体管T1的寄生电容的存在，信号输出端Output的电位升高会使第一节点P1的电位进一步升高，可以进一步地提高第一开关晶体管T1的充电能力，保证像素的充电时间；在第二时钟信号端CLK的电位为低电位时，信号输出端Output的电位为低电位。
以上仅是举例说明移位寄存器单元中第一输出模块51的具体结 构，在具体实施时，第一输出模块51的具体结构不限于本发明实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
在具体实施时，在本发明实施例提供的上述移位寄存器单元中，可以将第一电容的电容值与第二电容的电容值的比值控制在0.8至1.2范围。具体地，可以根据实际情况对第一电容的电容值与第二电容的电容值的比值进行适当调整，在此不做限定。
在具体实施时，在本发明实施例提供的上述移位寄存器单元中，如图2a、图2b、图3a和图3b所示，第二输出模块52，具体可以包括：第二开关晶体管T2和第三开关晶体管T3；其中：第二开关晶体管T2的栅极与第二节点P2相连，第二开关晶体管T2的源极与参考信号端Vref相连，第二开关晶体管T2的漏极与第一节点P1相连；第三开关晶体管T3的栅极与第二节点P2相连，第三开关晶体管T3的源极与参考信号端Vref相连，第三开关晶体管T3的漏极与信号输出端Output相连。
具体地，在本发明实施例提供的上述移位寄存器单元中，如图2a和图3a所示，第二开关晶体管T2和第三开关晶体管T3可以为N型晶体管，或者，如图2b和图3b所示，第二开关晶体管T2和第三开关晶体管T3也可以为P型晶体管，在此不作限定。以第二开关晶体管T2和第三开关晶体管T3为N型晶体管为例，在第二节点P2的电位为高电位时，第二开关晶体管T2和第三开关晶体管T3处于导通状态，将参考信号端Vref分别与第一节点P1和信号输出端Output连接，使第一节点P1和信号输出端Output的电位为低电位，参考信号端Vref分别对第一节点P1和信号输出端Output进行降噪，这样，可以降低移位寄存器单元的信号输出端Output输出的信号的噪声，保证信号输出端Output输出的信号的稳定性。
以上仅是举例说明移位寄存器单元中第二输出模块52的具体结构，在具体实施时，第二输出模块52的具体结构不限于本发明实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
较佳地，在本发明实施例提供的上述移位寄存器单元中，如图1c所示，输出模块5，还可以包括：第三输出模块53；第三输出模块53 的控制端53a与第一时钟信号端CLKB相连，第三输出模块53的输入端53b(也相当于图1a中的5e)与参考信号端Vref相连，第三输出模块53的输出端53c与信号输出端Output相连，用于在第一时钟信号端CLKB的控制下将参考信号端Vref的信号提供给信号输出端Output；这样，第三输出模块53可以在第一时钟信号端CLKB的控制下拉低信号输出端Output的电位，从而可以进一步地降低信号输出端Output输出的信号的噪声，保证信号输出端Output输出的信号的稳定性。
在具体实施时，在本发明实施例提供的上述移位寄存器单元中，如图3a和图3b所示，第三输出模块53，具体可以包括：第四开关晶体管T4；第四开关晶体管T4的栅极与第一时钟信号端CLKB相连，第四开关晶体管T4的源极与参考信号端Vref相连，第四开关晶体管T4的漏极与信号输出端Output相连。
具体地，在本发明实施例提供的上述移位寄存器单元中，如图3a所示，第四开关晶体管T4可以为N型晶体管，或者，如图3b所示，第四开关晶体管T4也可以为P型晶体管，在此不作限定。以第四开关晶体管T4为N型晶体管为例，在第一时钟信号端CLKB的电位为高电位时，第四开关晶体管T4处于导通状态，将参考信号端Vref与信号输出端Output连接，使信号输出端Output的电位为低电位，参考信号端Vref对信号输出端Output进行降噪，这样，可以降低移位寄存器单元的信号输出端Output输出的信号的噪声，保证信号输出端Output输出的信号的稳定性。
以上仅是举例说明移位寄存器单元中第三输出模块53的具体结构，在具体实施时，第三输出模块53的具体结构不限于本发明实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
在具体实施时，在本发明实施例提供的上述移位寄存器单元中，如图2a、图2b、图3a和图3b所示，输入模块1，具体可以包括：第五开关晶体管T5和第六开关晶体管T6；其中：第五开关晶体管T5的栅极和源极分别与信号输入端Input相连，第五开关晶体管T5的漏极与第一节点P1相连；第六开关晶体管T6的栅极与第一时钟信号端CLKB相连，第六开关晶体管T6的源极与信号输入端Input相连，第六开关晶体管T6的漏极与第一节点P1相连。
具体地，在本发明实施例提供的上述移位寄存器单元中，如图2a和图3a所示，第五开关晶体管T5和第六开关晶体管T6可以为N型晶体管，或者，如图2b和图3b所示，第五开关晶体管T5和第六开关晶体管T6也可以为P型晶体管，在此不作限定。以第五开关晶体管T5和第六开关晶体管T6为N型晶体管为例，在信号输入端Input的电位为高电位时，第五开关晶体管T5处于导通状态，将信号输入端Input与第一节点P1连接，使第一节点P1的电位为高电位；在第一时钟信号端CLKB的电位为高电位时，第六开关晶体管T6处于导通状态，将信号输入端Input与第一节点P1连接；在信号输入端Input的电位为低电位时，使第一节点P1的电位为低电位，在信号输入端Input的电位为高电位时，使第一节点P1的电位为高电位。
以上仅是举例说明移位寄存器单元中输入模块1的具体结构，在具体实施时，输入模块1的具体结构不限于本发明实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
在具体实施时，在本发明实施例提供的上述移位寄存器单元中，如图2a、图2b、图3a和图3b所示，复位模块2，具体可以包括：第七开关晶体管T7和第八开关晶体管T8；其中：第七开关晶体管T7的栅极与复位信号端Reset相连，第七开关晶体管T7的源极与参考信号端Vref相连，第七开关晶体管T7的漏极与第一节点P1相连；第八开关晶体管T8的栅极与复位信号端Reset相连，第八开关晶体管T8的源极与参考信号端Vref相连，第八开关晶体管T8的漏极与信号输出端Output相连。
具体地，在本发明实施例提供的上述移位寄存器单元中，如图2a和图3a所示，第七开关晶体管T7和第八开关晶体管T8可以为N型晶体管，或者，如图2b和图3b所示，第七开关晶体管T7和第八开关晶体管T8也可以为P型晶体管，在此不作限定。以第七开关晶体管T7和第八开关晶体管T8为N型晶体管为例，在复位信号端Reset的电位为高电位时，第七开关晶体管T7和第八开关晶体管T8处于导通状态，将参考信号端Vref分别与第一节点P1和信号输出端Output连接，使第一节点P1和信号输出端Output的电位为低电位，参考信号端Vref分别对第一节点P1和信号输出端Output进行降噪，这样，可以降低移位寄存器单元的信号输出端Output输出的信号的噪声，保证信号输出 端Output输出的信号的稳定性。
以上仅是举例说明移位寄存器单元中复位模块2的具体结构，在具体实施时，复位模块2的具体结构不限于本发明实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
在具体实施时，在本发明实施例提供的上述移位寄存器单元中，如图1d所示，控制模块3，具体可以包括：第一控制模块31和第二控制模块32；其中：第一控制模块31的控制端31a(相当于图1a中的3a)与第一节点P1相连，第一控制模块31的输入端31b(相当于图1a中的3b)与参考信号端Vref相连，(相当于图1a中的3a)输出端31c(相当于图1a中的3c)与第二节点P2相连，用于在第一节点P1的控制下将参考信号端Vref的信号提供给第二节点P2；第二控制模块32的控制端32a(相当于图1a中的3d)和第二控制模块32的输入端32b(相当于图1a中的3e)分别与第一时钟信号端CLKB相连，第二控制模块32的输出端32c(相当于图1a中的3f)与第二节点P2相连，用于在第一时钟信号端CLKB的控制下将第一时钟信号端CLKB的信号提供给第二节点P2。
在具体实施时，在本发明实施例提供的上述移位寄存器单元中，如图2a、图2b、图3a和图3b所示，第一控制模块31，具体可以包括：第九开关晶体管T9和第十开关晶体管T10；其中：第九开关晶体管T9的栅极与第一节点P1相连，第九开关晶体管T9的源极与参考信号端Vref相连，第九开关晶体管T9的漏极与第二节点P2相连；第十开关晶体管T10的栅极与第一节点P1相连，第十开关晶体管T10的源极与参考信号端Vref相连，第十开关晶体管T10的漏极与第三节点P3相连。
具体地，在本发明实施例提供的上述移位寄存器单元中，如图2a和图3a所示，第九开关晶体管T9和第十开关晶体管T10可以为N型晶体管，或者，如图2b和图3b所示，第九开关晶体管T9和第十开关晶体管T10也可以为P型晶体管，在此不作限定。以第九开关晶体管T9和第十开关晶体管T10为N型晶体管为例，在第一节点P1的电位为高电位时，第九开关晶体管T9和第十开关晶体管T10处于导通状态，将参考信号端Vref与第二节点P2连接，使第二节点P2的电位为低电位，参考信号端Vref对第二节点P2进行降噪。
以上仅是举例说明移位寄存器单元中第一控制模块31的具体结构，在具体实施时，第一控制模块31的具体结构不限于本发明实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
在具体实施时，在本发明实施例提供的上述移位寄存器单元中，如图2a、图2b、图3a和图3b所示，第二控制模块32，具体可以包括：第十一开关晶体管T11和第十二开关晶体管T12；其中：第十一开关晶体管T11的栅极和源极分别与第一时钟信号端CLKB相连，第十一开关晶体管T11的漏极与第三节点P3相连；第十二开关晶体管T12的栅极与第三节点P3相连，第十二开关晶体管T12的源极与第一时钟信号端CLKB相连，第十二开关晶体管T12的漏极与第二节点P2相连。
具体地，在本发明实施例提供的上述移位寄存器单元中，如图2a和图3a所示，第十一开关晶体管T11和第十二开关晶体管T12可以为N型晶体管，或者，如图2b和图3b所示，第十一开关晶体管T11和第十二开关晶体管T12也可以为P型晶体管，在此不作限定。以第十一开关晶体管T11和第十二开关晶体管T12为N型晶体管为例，在第一时钟信号端CLKB的电位为高电位时，第十一开关晶体管T11处于导通状态，将第一时钟信号端CLKB与第三节点P3连接，使第三节点P3的电位为高电位，此时，第十二开关晶体管T12处于导通状态，将第一时钟信号端CLKB与第二节点P2连接，使第二节点P2的电位为高电位。
以上仅是举例说明移位寄存器单元中第二控制模块32的具体结构，在具体实施时，第二控制模块32的具体结构不限于本发明实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
在具体实施时，当信号输入端Input、第一时钟信号端CLKB和复位信号端Reset输入的有效脉冲信号为高电位信号时，第一开关晶体管T1至第十二开关晶体管T12可以均采用N型晶体管；当信号输入端Input、第一时钟信号端CLKB和复位信号端Reset输入的有效脉冲信号为低电位信号时，第一开关晶体管T1至第十二开关晶体管T12可以均采用P型晶体管；在此不做限定。
需要说明的是本发明上述实施例中提到的开关晶体管可以是薄膜 晶体管(TFT，Thin Film Transistor)，也可以是金属氧化物半导体场效应管(简称MOS，Metal Oxide Semiconductor)，在此不做限定。在具体实施中，这些开关晶体管的源极和漏极根据晶体管类型以及输入信号的不同，其功能可以S换，在此不做具体区分。
针对本发明实施例提供的上述移位寄存器单元，本发明实施例还提供了一种移位寄存器单元的驱动方法，包括：
在第一阶段，在信号输入端的控制下将信号输入端的信号提供给第一节点，在第一节点的控制下将第二时钟信号端的信号提供给信号输出端；在第一时钟信号端的控制下将第一时钟信号端的信号提供给第二节点，在第二节点的控制下将参考信号端的信号分别提供给第一节点和信号输出端；
在第二阶段，在第一节点的控制下将第二时钟信号端的信号提供给信号输出端，在第一节点的控制下将参考信号端的信号提供给第二节点；
在第三阶段，在复位信号端的控制下将参考信号端的信号分别提供给第一节点和信号输出端；在第一时钟信号端的控制下将第一时钟信号端的信号提供给第二节点，在第二节点的控制下将参考信号端的信号分别提供给第一节点和信号输出端；
在第四阶段，在第二时钟信号端的电位升高时拉低第一节点的电位；在第一时钟信号端的控制下将第一时钟信号端的信号提供给第二节点，在第二节点的控制下将参考信号端的信号分别提供给第一节点和信号输出端。
本发明实施例提供的上述驱动方法，在第一时钟信号端的控制下将第一时钟信号端的信号提供给第二节点，在第二节点的控制下将参考信号端的信号分别提供给第一节点和信号输出端，可以拉低第一节点和信号输出端的电位；在复位信号端的控制下将参考信号端的信号分别提供给第一节点和信号输出端，可以拉低第一节点和信号输出端的电位；这样，可以降低移位寄存器单元的信号输出端输出的信号的噪声，保证信号输出端输出的信号的稳定性；并且，在第二时钟信号端的电位升高时，会导致第一节点的电位也升高，此时，由于第一时钟信号端的电位降低，因此，可以通过第一时钟信号端拉低第一节点的电位，从而可以避免在第二时钟信号端的电位升高时第一节点的电 位也升高而误将第二时钟信号端的信号提供给信号输出端进而导致各种显示不良。
较佳地，在本发明实施例提供的上述驱动方法中，还包括：
在第一阶段和第三阶段，在第一时钟信号端的控制下将参考信号端的信号提供给信号输出端；这样，可以在第一时钟信号端的控制下拉低信号输出端的电位，从而可以进一步地降低信号输出端输出的信号的噪声，保证信号输出端输出的信号的稳定性。
下面以第一开关晶体管T1至第十二开关晶体管T12均为N型晶体管为例，对本发明实施例提供的上述移位寄存器单元的工作过程作以描述。例如，在图3a所示的移位寄存器单元中，第一开关晶体管T1至第十二开关晶体管T12均为N型晶体管，各N型晶体管在高电位作用下导通，在低电位作用下截止；输入信号端Input、第一时钟信号端CLKB和复位信号端Reset的有效脉冲信号为高电位信号，参考信号端Vref的信号为低电位信号。图3a对应的输入输出时序图如图4所示，具体地，选取如图4所示的输入输出时序图中的t1～t4四个阶段。下述描述中以1表示高电位，0表示低电位。
在第一阶段t1，Input＝1，Reset＝0，CLK＝0，CLKB＝1，由于复位信号端Reset的电位为低电位，第七开关晶体管T7和第八开关晶体管T8截止；由于信号输入端Input的电位为高电位，第五开关晶体管T5导通，将信号输入端Input与第一节点P1连接，使第一节点P1的电位为高电位，此时，对第二电容C2充电，第一开关晶体管T1导通，将第二时钟信号端CLK与信号输出端Output连接，由于第二时钟信号端CLK的电位为低电位，使信号输出端Output的电位仍为低电位；由于第一时钟信号端CLKB的电位为高电位，第四开关晶体管T4导通，将参考信号端Vref与信号输出端Output连接，使信号输出端Output的电位为低电位，参考信号端Vref对信号输出端Output进行降噪；由于第一时钟信号端CLKB的电位为高电位，第十一开关晶体管T11导通，将第一时钟信号端CLKB与第三节点P3连接，使第三节点P3的电位为高电位，第十二开关晶体管T12导通，将第一时钟信号端CLKB与第二节点P2连接，使第二节点P2的电位为高电位，此时，第二开关晶体管T2和第三开关晶体管T3导通，将参考信号端Vref分别与第一节点P1和信号输出端Output连接，使第一节点P1和信号输出端Output 的电位为低电位，参考信号端Vref分别对第一节点P1和信号输出端Output进行降噪；
在第二阶段t2，Input＝0，Reset＝0，CLK＝1，CLKB＝0，由于信号输入端Input的电位为低电位，第五开关晶体管T5截止；由于复位信号端Reset的电位为低电位，第七开关晶体管T7和第八开关晶体管T8截止；由于第一时钟信号端CLKB的电位为低电位，第四开关晶体管T4、第六开关晶体管T6、第十一开关晶体管T11和第十二开关晶体管T12截止；由于第二电容C2的作用，第一节点P1仍保持高电位，由于第二时钟信号端CLK的电位为高电位，使信号输出端Output的电位为高电位；由于第二电容C2的自举作用和第一开关晶体管T1的寄生电容的存在，信号输出端Output的电位升高会使第一节点P1的电位进一步升高，可以进一步地提高第一开关晶体管T1的充电能力，保证像素的充电时间；由于第一节点P1的电位为高电位，第九开关晶体管T9和第十开关晶体管T10导通，将参考信号端Vref与第二节点P2连接，使第二节点P2的电位为低电位，参考信号端Vref对第二节点P2进行降噪；
在第三阶段t3，Input＝0，Reset＝1，CLK＝0，CLKB＝1，由于信号输入端Input的电位为低电位，第五开关晶体管T5截止；由于复位信号端Reset的电位为高电位，第七开关晶体管T7和第八开关晶体管T8导通，将参考信号端Vref分别与第一节点P1和信号输出端Output连接，使第一节点P1和信号输出端Output的电位为低电位，参考信号端Vref分别对第一节点P1和信号输出端Output进行降噪；由于第一时钟信号端CLKB的电位为高电位，第十一开关晶体管T11导通，将第一时钟信号端CLKB与第三节点P3连接，使第三节点P3的电位为高电位，此时，第十二开关晶体管T12导通，将第一时钟信号端CLKB与第二节点P2连接，使第二节点P2的电位为高电位，此时，第二开关晶体管T2和第三开关晶体管T3导通，将参考信号端Vref分别与第一节点P1和信号输出端Output连接，使第一节点P1和信号输出端Output的电位为低电位，参考信号端Vref分别对第一节点P1和信号输出端Output进行降噪；由于第一时钟信号端CLKB的电位为高电位，第四开关晶体管T4导通，将参考信号端Vref信号输出端Output连接，使信号输出端Output的电位为低电位，参考信号端Vref对信号输出端 Output进行降噪；
在第四阶段t4，Input＝0，Reset＝0，CLK＝1、CLKB＝0和CLK＝0、CLKB＝1保持交替变化，在CLK＝1、CLKB＝0时，由于第一时钟信号端CLKB的电位为低电位，因此，第二节点P2的电位为低电位，第二开关晶体管T2处于截止状态，第一节点P1没有放电路径，此时，第二时钟信号端CLK的电位为高电位，由于第一开关晶体管T1的栅极与源极之间的寄生电容较大，会导致第一节点P1的电位被拉高，并且，由于第二时钟信号端CLK向第二电容C2充电，会导致第一节点P1的电位再次被拉高，此时，由于第一时钟信号端CLKB的电位为低电位，通过第一电容C1的自举作用，可以拉低第一节点P1的电位，这样，可以避免在第二时钟信号端CLK的电位升高时第一节点P1的电位也升高而使第一开关晶体管T1误开启从而误将第二时钟信号端CLK的信号提供给信号输出端Output进而导致各种显示不良；在CLK＝0、CLKB＝1时，由于第一时钟信号端CLKB的电位为高电位，因此，第二节点P2的电位为高电位，第二开关晶体管T2导通，将参考信号端Vref与第一节点P1连接，使第一节点P1的电位为低电位，参考信号端Vref对第一节点P1进行降噪，使第一节点P1的电位保持稳定。
在后续时间段，信号输出端Output将一直输出低电位的电压信号，直到下一帧的到来。
上述是以第一开关晶体管T1至第十二开关晶体管T12均为N型晶体管为例进行说明，具体对于第一开关晶体管T1至第十二开关晶体管T12均为P型晶体管的工作原理与上述第一开关晶体管T1至第十二开关晶体管T12均为N型晶体管的工作原理相似，在此不再赘述。
基于同一发明构思，本发明实施例还提供了一种栅极驱动电路，如图5所示，包括：级联的多个本发明实施例提供的上述移位寄存器单元：SR(1)、SR(2)…SR(n)…SR(N-1)、SR(N)(共N个移位寄存器单元，1≤n≤N)；其中：
除第一级移位寄存器单元SR(1)之外，其余每一级移位寄存器单元SR(n)的信号输出端Output_n(1≤n≤N)分别和与其相邻的上一级移位寄存器单元SR(n-1)的复位信号端Reset相连；
除最后一级移位寄存器单元SR(N)之外，其余每一级移位寄存器单元SR(n)的信号输出端Output_n(1≤n≤N)分别和与其相邻的下一级 移位寄存器单元SR(n+1)的信号输入端Input相连；
第一级移位寄存器单元SR(1)的信号输入端Input与帧起始信号端STV相连。
具体地，本发明实施例提供的上述栅极驱动电路中的每个移位寄存器单元与本发明实施例提供的上述移位寄存器单元在功能和结构上均相同，重复之处不再赘述。
基于同一发明构思，本发明实施例还提供了一种显示装置，包括本发明实施例提供的上述栅极驱动电路，该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置的实施可以参见上述栅极驱动电路的实施例，重复之处不再赘述。
本发明实施例提供的一种移位寄存器单元、其驱动方法、栅极驱动电路及显示装置，该移位寄存器单元包括：输入模块、复位模块、控制模块、下拉模块和输出模块；输出模块的第一控制端与第一节点相连，第一输入端与第二时钟信号端相连，第一输出端与信号输出端相连；下拉模块的两端分别与第一时钟信号端和第一节点相连；在第二时钟信号端的电位升高时，会导致第一节点的电位也升高，此时，由于第一时钟信号端的电位降低，因此，下拉模块可以通过第一时钟信号端拉低第一节点的电位，从而可以避免在第二时钟信号端的电位升高时第一节点的电位也升高而误将第二时钟信号端的信号提供给信号输出端进而导致各种显示不良。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (17)

  1. 一种移位寄存器单元，其特征在于，包括：输入模块、复位模块、控制模块、下拉模块和输出模块；其中：
    所述输入模块的第一控制端和所述输入模块的输入端分别与信号输入端相连，所述输入模块的第二控制端与第一时钟信号端相连，所述输入模块的输出端与第一节点相连，用于分别在所述第一时钟信号端和所述信号输入端的控制下将所述信号输入端的信号提供给所述第一节点；
    所述复位模块的控制端与复位信号端相连，所述复位模块的输入端与参考信号端相连，所述复位模块的第一输出端与所述第一节点相连，所述复位模块的第二输出端与信号输出端相连，用于在所述复位信号端的控制下将所述参考信号端的信号分别提供给所述第一节点和所述信号输出端；
    所述控制模块的第一控制端与所述第一节点相连，所述控制模块的第一输入端与所述参考信号端相连，所述控制模块的第一输出端与第二节点相连，所述控制模块的第二控制端和所述控制模块的第二输入端分别与所述第一时钟信号端相连，所述控制模块的第二输出端与所述第二节点相连，用于在所述第一节点的控制下将所述参考信号端的信号提供给所述第二节点以及在所述第一时钟信号端的控制下将所述第一时钟信号端的信号提供给所述第二节点；
    所述输出模块的第一控制端与所述第一节点相连，所述输出模块的第一输入端与第二时钟信号端相连，所述输出模块的第一输出端与所述信号输出端相连，所述输出模块的第二控制端与所述第二节点相连，所述输出模块的第二输入端与所述参考信号端相连，所述输出模块的第二输出端与所述第一节点相连，所述输出模块的第三输出端与所述信号输出端相连，用于在所述第一节点的控制下将所述第二时钟信号端的信号提供给所述信号输出端以及在所述第二节点的控制下将所述参考信号端的信号分别提供给所述第一节点和所述信号输出端；
    所述下拉模块的两端分别与所述第一时钟信号端和所述第一节点相连，用于在所述第二时钟信号端的电位升高时拉低所述第一节点的电位。
  2. 如权利要求1所述的移位寄存器单元，其特征在于，所述下拉模块，具体包括：第一电容；
    所述第一电容的两端分别与所述第一时钟信号端和所述第一节点相连。
  3. 如权利要求2所述的移位寄存器单元，其特征在于，所述输出模块，具体包括：第一输出模块和第二输出模块；其中：
    所述第一输出模块的控制端与所述第一节点相连，所述第一输出模块的输入端与所述第二时钟信号端相连，所述第一输出模块的输出端与所述信号输出端相连，用于在所述第一节点的控制下将所述第二时钟信号端的信号提供给所述信号输出端；
    所述第二输出模块的控制端与所述第二节点相连，所述第二输出模块的输入端与所述参考信号端相连，所述第二输出模块的第一输出端与所述第一节点相连，所述第二输出模块的第二输出端与所述信号输出端相连，用于在所述第二节点的控制下将所述参考信号端的信号分别提供给所述第一节点和所述信号输出端。
  4. 如权利要求3所述的移位寄存器单元，其特征在于，所述第一输出模块，具体包括：第一开关晶体管和第二电容；其中：
    所述第一开关晶体管的栅极与所述第一节点相连，所述第一开关晶体管的源极与所述第二时钟信号端相连，所述第一开关晶体管的漏极与所述信号输出端相连；
    所述第二电容连接于所述第一开关晶体管的栅极和漏极之间。
  5. 如权利要求4所述的移位寄存器单元，其特征在于，所述第一电容的电容值与所述第二电容的电容值的比值的范围为0.8至1.2。
  6. 如权利要求3所述的移位寄存器单元，其特征在于，所述第二输出模块，具体包括：第二开关晶体管和第三开关晶体管；其中：
    所述第二开关晶体管的栅极与所述第二节点相连，所述第二开关晶体管的源极与所述参考信号端相连，所述第二开关晶体管的漏极与所述第一节点相连；
    所述第三开关晶体管的栅极与所述第二节点相连，所述第三开关晶体管的源极与所述参考信号端相连，所述第三开关晶体管的漏极与所述信号输出端相连。
  7. 如权利要求3所述的移位寄存器单元，其特征在于，所述输出 模块，还包括：第三输出模块；
    所述第三输出模块的控制端与所述第一时钟信号端相连，所述第三输出模块的输入端与所述参考信号端相连，所述第三输出模块的输出端与所述信号输出端相连，用于在所述第一时钟信号端的控制下将所述参考信号端的信号提供给所述信号输出端。
  8. 如权利要求7所述的移位寄存器单元，其特征在于，所述第三输出模块，具体包括：第四开关晶体管；
    所述第四开关晶体管的栅极与所述第一时钟信号端相连，所述第四开关晶体管的源极与所述参考信号端相连，所述第四开关晶体管的漏极与所述信号输出端相连。
  9. 如权利要求1所述的移位寄存器单元，其特征在于，所述输入模块，具体包括：第五开关晶体管和第六开关晶体管；其中：
    所述第五开关晶体管的栅极和源极分别与所述信号输入端相连，所述第五开关晶体管的漏极与所述第一节点相连；
    所述第六开关晶体管的栅极与所述第一时钟信号端相连，所述第六开关晶体管的源极与所述信号输入端相连，所述第六开关晶体管的漏极与所述第一节点相连。
  10. 如权利要求1所述的移位寄存器单元，其特征在于，所述复位模块，具体包括：第七开关晶体管和第八开关晶体管；其中：
    所述第七开关晶体管的栅极与所述复位信号端相连，所述第七开关晶体管的源极与所述参考信号端相连，所述第七开关晶体管的漏极与所述第一节点相连；
    所述第八开关晶体管的栅极与所述复位信号端相连，所述第八开关晶体管的源极与所述参考信号端相连，所述第八开关晶体管的漏极与所述信号输出端相连。
  11. 如权利要求1所述的移位寄存器单元，其特征在于，所述控制模块，具体包括：第一控制模块和第二控制模块；其中：
    所述第一控制模块的控制端与所述第一节点相连，所述第一控制模块的输入端与所述参考信号端相连，所述第一控制模块的输出端与所述第二节点相连，用于在所述第一节点的控制下将所述参考信号端的信号提供给所述第二节点；
    所述第二控制模块的控制端和输入端分别与所述第一时钟信号端 相连，所述第二控制模块的输出端与所述第二节点相连，用于在所述第一时钟信号端的控制下将所述第一时钟信号端的信号提供给所述第二节点。
  12. 如权利要求11所述的移位寄存器单元，其特征在于，所述第一控制模块，具体包括：第九开关晶体管和第十开关晶体管；其中：
    所述第九开关晶体管的栅极与所述第一节点相连，所述第九开关晶体管的源极与所述参考信号端相连，所述第九开关晶体管的漏极与所述第二节点相连；
    所述第十开关晶体管的栅极与所述第一节点相连，所述第十开关晶体管的源极与所述参考信号端相连，所述第十开关晶体管的漏极与第三节点相连。
  13. 如权利要求11所述的移位寄存器单元，其特征在于，所述第二控制模块，具体包括：第十一开关晶体管和第十二开关晶体管；其中：
    所述第十一开关晶体管的栅极和源极分别与所述第一时钟信号端相连，所述第十一开关晶体管的漏极与所述第三节点相连；
    所述第十二开关晶体管的栅极与所述第三节点相连，所述第十二开关晶体管的源极与所述第一时钟信号端相连，所述第十二开关晶体管的漏极与所述第二节点相连。
  14. 一种栅极驱动电路，其特征在于，包括：级联的多个如权利要求1-13任一项所述的移位寄存器单元；其中：
    除第一级移位寄存器单元之外，其余每一级移位寄存器单元的信号输出端分别和与其相邻的上一级移位寄存器单元的复位信号端相连；
    除最后一级移位寄存器单元之外，其余每一级移位寄存器单元的信号输出端分别和与其相邻的下一级移位寄存器单元的信号输入端相连；
    第一级移位寄存器单元的信号输入端与帧起始信号端相连。
  15. 一种显示装置，其特征在于，包括：如权利要求14所述的栅极驱动电路。
  16. 一种如权利要求1-13任一项所述的移位寄存器单元的驱动方法，其特征在于，包括：
    在第一阶段，在信号输入端的控制下将所述信号输入端的信号提供给第一节点，在所述第一节点的控制下将第二时钟信号端的信号提供给信号输出端；在第一时钟信号端的控制下将所述第一时钟信号端的信号提供给第二节点，在所述第二节点的控制下将参考信号端的信号分别提供给所述第一节点和所述信号输出端；
    在第二阶段，在所述第一节点的控制下将所述第二时钟信号端的信号提供给所述信号输出端，在所述第一节点的控制下将所述参考信号端的信号提供给所述第二节点；
    在第三阶段，在复位信号端的控制下将所述参考信号端的信号分别提供给所述第一节点和所述信号输出端；在所述第一时钟信号端的控制下将所述第一时钟信号端的信号提供给所述第二节点，在所述第二节点的控制下将所述参考信号端的信号分别提供给所述第一节点和所述信号输出端；
    在第四阶段，在所述第二时钟信号端的电位升高时拉低所述第一节点的电位；在所述第一时钟信号端的控制下将所述第一时钟信号端的信号提供给所述第二节点，在所述第二节点的控制下将所述参考信号端的信号分别提供给所述第一节点和所述信号输出端。
  17. 如权利要求16所述的驱动方法，其特征在于，还包括：
    在第一阶段和第三阶段，在所述第一时钟信号端的控制下将所述参考信号端的信号提供给所述信号输出端。
PCT/CN2017/083694 2016-06-30 2017-05-10 移位寄存器单元、其驱动方法、栅极驱动电路及显示装置 WO2018000945A1 (zh)

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