WO2017185590A1 - 移位寄存器单元、栅极驱动电路及其驱动方法和显示装置 - Google Patents

移位寄存器单元、栅极驱动电路及其驱动方法和显示装置 Download PDF

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WO2017185590A1
WO2017185590A1 PCT/CN2016/099181 CN2016099181W WO2017185590A1 WO 2017185590 A1 WO2017185590 A1 WO 2017185590A1 CN 2016099181 W CN2016099181 W CN 2016099181W WO 2017185590 A1 WO2017185590 A1 WO 2017185590A1
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Prior art keywords
pull
voltage
terminal
transistor
node
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PCT/CN2016/099181
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English (en)
French (fr)
Inventor
商广良
姚星
韩承佑
高玉杰
张元波
陈明
田正牧
董学
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京东方科技集团股份有限公司
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Priority to US15/541,639 priority Critical patent/US10217391B2/en
Publication of WO2017185590A1 publication Critical patent/WO2017185590A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a shift register unit, a gate driving circuit, a driving method thereof, and a display device.
  • the gate drive circuit includes a plurality of shift register units, each shift register unit providing a gate drive signal for a corresponding one of the plurality of gate lines on the array substrate.
  • the time allocated to each row of pixels in the display device is fixed. During this fixed time, it is necessary to complete the charging of the pixel and the reset of the gate drive signal. For a display device having a higher resolution, the reset time of the gate drive signal is longer, resulting in a shorter charging time for each row of pixels. This is detrimental to the charging of the pixels.
  • Embodiments of the present disclosure provide a shift register unit, a gate driving circuit, a driving method thereof, and a display device.
  • the proposed shift register unit can output a gate drive signal having a shortened reset time.
  • a shift register unit having a duty cycle including an input phase, an output phase, a reset phase, and a hold phase
  • the shift register unit comprising: an input module configured to be The input stage transmits an input signal to the pull-up node to pull the voltage of the pull-up node high; the output module is configured to a) transmit a clock signal to the output as the gate turn-on voltage at the output stage and The voltage of the pull-up node is further pulled up by a predetermined amount, and b) transmitting the clock signal to the output terminal during the reset phase to pull the voltage of the output terminal to a reference voltage and to pull up the pull-up node The voltage is pulled low by the predetermined amount; the first reset module is configured to further pull the pulled down voltage of the pull-up node to the reference voltage in response to the first reset signal in the reset phase; a first pull-down control module configured to, in response to the first pull-down control signal, a) change a pulled-down voltage of the
  • a gate driving circuit comprising a plurality of cascaded shift register units as described in the first aspect.
  • a display device comprising the gate drive circuit of any of the second aspects.
  • a method of driving a gate driving circuit including a plurality of shift register units, the method comprising: performing an input phase for each of the plurality of shift register units, Wherein the input signal is transmitted to the pull-up node to pull the voltage of the pull-up node high; an output phase is performed, wherein the clock signal is transmitted to the output as a gate turn-on voltage and the voltage of the pull-up node is further pulled up a predetermined amount; performing a reset phase, wherein the clock signal is transmitted to the output terminal to pull the voltage of the output terminal to a reference voltage and pull the voltage of the pull-up node lower by the predetermined amount, in response to the a reset signal further pulling the pulled down voltage of the pull-up node to the reference voltage, and changing the pulled low voltage of the output terminal from the reference voltage to a first pull-down control signal to a gate turn-off voltage, the reference voltage being less than the gate turn-off voltage; and performing a hold phase, wherein the pull
  • FIG. 1 schematically shows a block diagram of a shift register unit in accordance with an embodiment of the present disclosure
  • FIG. 2 schematically shows a waveform diagram illustrating a decrease in reset time of a gate drive signal
  • FIG. 3 shows an example circuit diagram of the shift register unit shown in FIG. 1;
  • FIG. 4 is a timing chart showing an operation of an example circuit of the shift register unit shown in FIG. 3;
  • FIG. 5 schematically illustrates a block diagram of a gate drive circuit in accordance with an embodiment of the present disclosure.
  • FIG. 6 schematically illustrates a block diagram of a display device in accordance with an embodiment of the present disclosure.
  • a shift register unit includes an input module 1, an output module 2, a first reset module 3, and a first pull-down control module 4.
  • One duty cycle of the shift register unit includes an input phase t1, an output phase t2, a reset phase t3, and a hold phase t4.
  • the input module 1 is configured to transmit an input signal Input to the pull-up node PU during the input phase t1 to pull the voltage of the pull-up node PU high.
  • the output module 2 is configured to a) transmit a clock signal CLK to the output as the gate turn-on voltage and further increase the voltage of the pull-up node PU by a predetermined amount at the output stage t2, and b)
  • the reset phase t3 transmits the clock signal CLK to the output terminal to pull the voltage of the output terminal to the reference voltage Vref1 and pull the voltage of the pull-up node PU lower by the predetermined amount.
  • the low level of the clock signal CLK is the reference voltage Vref1.
  • the first reset module 3 is configured to further pull the pulled down voltage of the pull-up node PU to the reference voltage Vref1 in response to the first reset signal Rst1 in the reset phase t3.
  • the first pull-down control module 4 is configured to change the pulled low voltage of the output terminal from the reference voltage Vref1 to the gate turn-off voltage Vref2 in the reset phase t3 in response to the first pull-down control signal VHD1 .
  • the reference voltage Vref1 is smaller than the gate turn-off voltage Vref2, and the first pull-down control signal VHD1 has a phase difference of 180 degrees from the clock signal CLK.
  • the first pull-down control module 4 is further configured to maintain the voltage of the pull-up node PU at the reference voltage Vref1 and maintain the voltage of the output terminal at the gate turn-off voltage Vref2 during the hold phase t4 .
  • the output of the output of the shift register unit at each stage is combined into a gate drive signal "Output".
  • the gate drive signal "Output” is held at the gate turn-off voltage Vref2, enabling the display device to operate in a stable state.
  • the gate driving signal is first pulled down from the high level VGH to the reference voltage Vref1 which is smaller than the gate-off voltage Vref2, and then changed to the gate-off voltage Vref2.
  • the gate drive signal falls to a predetermined value (for example, 10% (VGH - Vref2)) in a shorter time than being directly pulled down to the gate turn-off voltage Vref2, thereby achieving a fast reset.
  • the reset time ⁇ t2 is smaller than the reset time ⁇ t1.
  • the shortened reset time of the gate drive signal ensures the charging time of the pixel.
  • the shift register unit further includes a second pull-down control module 5 configured to cause the pull-up node in response to the second pull-down control signal VHD2 during the hold phase t4
  • the voltage of the PU is maintained at the reference voltage Vref1 and the gate drive signal "Output" is held at the gate turn-off voltage Vref2.
  • the second pull-down control signal VHD2 has a phase opposite to the phase of the first pull-down control signal VHD1.
  • the second pull-down control module 5 has the same function as the first pull-down control module 4, that is, the voltage of the pull-up node PU is maintained at the reference voltage Vref1 under the control of the respective pull-down control signals, and The gate drive signal "Output" is held at the gate turn-off voltage Vref2. Since the phase of the first pull-down control signal VHD1 and the second pull-down control signal VHD2 are opposite, the first pull-down control module 4 and the second pull-down control module 5 alternately operate so that at any point in the hold phase t4, the pull-up is performed.
  • the voltage of the node PU is always maintained at the reference voltage Vref1, and the gate drive signal "Output" is always maintained at the gate turn-off voltage Vref2. This avoids the uncertainty of the gate drive signal "Output" due to the suspension of the output.
  • the gate drive signal "Output" may be avoided by maintaining the first pull-down control signal VHD1 at a high level. Certainty.
  • the shift register unit further includes a carry module 6 and a carry pull down module 7.
  • the carry module 6 is configured to a) transmit the clock signal CLK to the carry end as a carry signal "Carry Out” at the output stage t2, and b) transmit the clock signal CLK to the reset stage t3
  • the carry terminal is configured to pull the voltage of the carry terminal to the reference voltage Vref1.
  • the carry pull-down module 7 is configured to a) maintain the pulled low voltage of the carry terminal at the reference voltage Vref1 during the reset phase t3, and b) during the hold phase t4 The voltage at the carry terminal is maintained at the reference voltage Vref1.
  • the gate drive signal "Output” and the carry signal “Carry Out” are provided at separate output and carry ends, respectively, such that they do not affect each other.
  • the carry signal "Carry Out” of the current shift register unit is supplied as the input signal Input of the other shift register unit, and is not driven by the gate of the current shift register unit.
  • the power consumption of the shift register unit can be reduced by selecting a transistor having a low power consumption to drive the output of the gate drive signal "Output” and the carry signal "Carry Out".
  • the gate drive signal "Output” can also be used as the carry signal "Carry Out". This is advantageous in reducing the frame of the display device.
  • the shift register unit further includes a second reset module 8 configured to pull the voltage of the carry terminal to the reference voltage Vref1 in response to the second reset signal Rst2 during the reset phase t3.
  • the presence of the second reset module 8 enables the voltage at the carry terminal to be pulled down to the reference voltage Vref1 more quickly.
  • the input module 1 includes a first transistor T1.
  • the control terminal and the first terminal of the first transistor T1 both receive the input signal Input, and the second end of the first transistor T1 is connected to the pull-up node PU.
  • the input signal Input controls the first transistor T1 to be turned on, and pulls up the voltage of the pull-up node PU.
  • the output module 2 includes a second transistor T2.
  • the control terminal of the second transistor T2 is connected to the pull-up node PU, the first terminal of the second transistor T2 receives the clock signal CLK, and the second terminal (ie, the output terminal) of the second transistor T2 outputs the gate drive signal "Output" .
  • the voltage of the pull-up node PU controls the second transistor T2 to be turned on, and the high level of the clock signal CLK is transferred to the output terminal. Due to the bootstrap of the parasitic capacitance (eg, gate-drain parasitic capacitance and gate-source parasitic capacitance) in the second transistor T2, the voltage of the pull-up node PU is further pulled up by a predetermined amount.
  • the parasitic capacitance eg, gate-drain parasitic capacitance and gate-source parasitic capacitance
  • the transition of the clock signal CLK from the high level to the low level causes the voltage of the pull-up node PU to be pulled down by a predetermined amount, but is still high.
  • the parasitic capacitance in the second transistor T2 may couple a noise signal, for example due to the high level of the clock signal CLK, to the pull up node PU.
  • the shift register unit may further include a capacitor C1.
  • One end of the capacitor C1 is connected to the second end of the second transistor T2, and the other end of the capacitor C1 is connected to the pull-up node PU. That is, the capacitor C1 is connected in parallel with the parasitic capacitance. From the perspective of the pull-up node PU, the capacitance of the PU side of the pull-up node increases, thereby reducing the influence of noise from the clock signal CLK on the voltage of the pull-up node PU. This can enhance the anti-interference ability of the shift register unit.
  • the first reset module 3 includes a third transistor T3.
  • the control terminal of the third transistor T3 receives the first reset signal Rst1, the first terminal of the third transistor T3 is connected to the pull-up node PU, and the second terminal of the third transistor T3 is connected to the signal line for supplying the reference voltage Vref1.
  • the first reset signal Rst1 controls the third transistor T3 to be turned on, so that the pull-up node PU is in communication with the signal line supplying the reference voltage Vref1, thereby pulling the voltage of the pull-up node PU to the reference. Voltage Vref1.
  • the first pull-down control module 4 includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9.
  • the control terminal and the first terminal of the fourth transistor T4 both receive the first pull-down control signal VHD1, and the second terminal of the fourth transistor T4 is connected to the control terminal of the fifth transistor T5 and the first terminal of the sixth transistor T6.
  • the first end of the fifth transistor T5 receives the first pull-down control signal VHD1, and the second end of the fifth transistor T5 is connected to the first pull-down node PD1.
  • the control terminal of the sixth transistor T6 is connected to the pull-up node PU, and the second terminal of the sixth transistor T6 is connected to a signal line for supplying the reference voltage Vref1.
  • the control terminal of the seventh transistor T7 is connected to the pull-up node PU, the first end of the seventh transistor T7 is connected to the first pull-down node PD1, and the second end of the seventh transistor T7 is connected to the signal line for supplying the reference voltage Vref1. connection.
  • the control terminal of the eighth transistor T8 is connected to the first pull-down node PD1, the first end of the eighth transistor T8 is connected to the pull-up node PU, and the second end of the eighth transistor T8 is connected to the signal line for supplying the reference voltage Vref1. connection.
  • the control terminal of the ninth transistor T9 is connected to the first pull-down node PD1, the first terminal of the ninth transistor T9 is connected to the second terminal of the second transistor T2, and the second terminal of the ninth transistor T9 is used for providing the gate
  • the signal line of the shutdown voltage Vref2 is connected.
  • the first pull-down control signal VHD1 controls the fourth transistor T4 to be turned on.
  • the sixth transistor T6 and the seventh transistor T7 are turned on. Due to the aspect ratio design of the fourth transistor T4 and the sixth transistor T6, the voltage of the second terminal of the fourth transistor T4 is still at a low level.
  • the voltage of the pull-up node PU is pulled down to the reference voltage Vref1, so that the sixth transistor T6 and the seventh transistor T7 are turned off.
  • the turned-on fourth transistor T4 controls the fifth transistor T5 to be turned on, so that the voltage of the first pull-down node PD1 becomes a high level. Therefore, the eighth transistor T8 is turned on to pull the voltage of the pull-up node PU to the reference voltage Vref1, and the ninth transistor T9 is turned on to change the voltage of the second terminal of the second transistor T2 from the reference voltage Vref1 to the gate turn-off voltage. Vref2.
  • the eighth transistor T8 is turned on to maintain the voltage of the pull-up node PU at the reference voltage Vref1
  • the ninth transistor T9 is turned on to maintain the second terminal voltage of the second transistor T2 at the gate-off voltage Vref2.
  • the eighth transistor T8 and the third transistor T3 both function to pull down the voltage of the pull-up node PU to the reference voltage Vref1, so that the voltage of the pull-up node PU can be pulled down more quickly.
  • the first pull-down control module 4 may further include a tenth transistor T10 and an eleventh transistor T11.
  • the control terminal of the tenth transistor T10 receives the input signal Input, the first end of the tenth transistor T10 is connected to the second end of the fourth transistor T4, and the second end of the tenth transistor T10 is connected with the signal line for supplying the reference voltage Vref1 connection.
  • the control terminal of the eleventh transistor T11 receives the input signal Input, the first end of the eleventh transistor T11 is connected to the first pull-down node PD1, and the second end of the eleventh transistor T11 is coupled with the signal for supplying the reference voltage Vref1. Wire connection.
  • the input signal Input also controls the tenth transistor T10 and the eleventh transistor T11 to be turned on. Due to the aspect ratio design of the fourth transistor T4 and the tenth transistor T10, the voltage of the second terminal of the fourth transistor T4 is still at a low level and the fifth transistor T5 is turned off. Turning on the eleventh transistor T11 pulls the voltage of the first pull-down node PD1 to the reference voltage Vref1.
  • the input signal Input pulls down the voltage of the first pull-down node PD1, thereby preventing the eighth transistor T8 and the ninth transistor T9 from being turned on to affect the pull-up node PU and the output terminal.
  • the case of voltage This improves the reliability of the shift register unit.
  • the second pull-down control module 5 includes a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, and a seventeenth transistor T17.
  • the control end of the twelfth transistor T12 is connected to the second pull-down node PD2, the first end of the twelfth transistor T12 is connected to the second end of the second transistor T2, and the second end of the twelfth transistor T12 is provided for providing The signal line of the gate turn-off voltage Vref2 is connected.
  • the control terminal of the thirteenth transistor T13 and the first terminal of the thirteenth transistor T13 both receive the second pull-down control signal VHD2, and the second end of the thirteenth transistor T13 is connected to the control terminal of the fourteenth transistor T14 and the fifteenth The first end of transistor T15.
  • the first end of the fourteenth transistor T14 receives the second pull-down control signal VHD2, and the second end of the fourteenth transistor T14 is connected to the second pull-down node PD2.
  • the control terminal of the fifteenth transistor T15 is connected to the pull-up node PU, and the second terminal of the fifteenth transistor T15 is connected to a signal line for supplying the reference voltage Vref1.
  • the control terminal of the sixteenth transistor T16 is connected to the pull-up node PU, the first end of the sixteenth transistor T16 is connected to the second pull-down node PD2, and the second end of the sixteenth transistor T16 is connected to the reference voltage Vref1. Signal line connection.
  • the control terminal of the seventeenth transistor T17 is connected to the second pull-down node PD2, the first end of the seventeenth transistor T17 is connected to the pull-up node PU, and the second end of the seventeenth transistor T17 is connected to the reference voltage Vref1. Signal line connection.
  • the high level of the pull-up node PU can control both the fifteenth transistor T15 and the sixteenth transistor T16 to be turned on. Due to the aspect ratio design of the thirteenth transistor T13 and the fifteenth transistor T15, the voltage of the second terminal of the thirteenth transistor T13 is still at a low level, so that the fourteenth transistor T14 is turned off.
  • the turned-on sixteenth transistor T16 pulls the voltage of the second pull-down node PD2 down to the reference voltage Vref1. Therefore, at the output stage t2, the voltage of the second pull-down node PD2 cannot turn on the twelfth transistor T12 and the seventeenth transistor T17, thereby avoiding the influence on the voltage of the pull-up node PU and the output terminal.
  • the thirteenth transistor T13 and the fourteenth transistor T14 are turned on, so that the voltage of the second pull-down node PD2 is at a high level, and the twelfth transistor T12 And the seventeenth transistor T17 is turned on.
  • the twelfth transistor T12 is turned on to maintain the voltage of the second terminal of the second transistor T2 at the gate turn-off voltage Vref2, and the seventeenth transistor T17 is turned on to maintain the voltage of the pull-up node PU at the reference voltage Vref1.
  • the second pull-down control module 5 may further include an eighteenth transistor T18 and a nineteenth transistor T19.
  • the control terminal of the eighteenth transistor T18 receives the input signal Input, The first end of the eighteenth transistor T18 is connected to the second end of the thirteenth transistor T13, the second end of the eighteenth transistor T18 is connected to the signal line for supplying the reference voltage Vref1; the control end of the nineteenth transistor T19 Receiving the input signal Input, the first end of the nineteenth transistor T19 is connected to the second pull-down node PD2, and the second end of the nineteenth transistor T19 is connected to the signal line for supplying the reference voltage Vref1.
  • the input signal Input also controls the eighteenth transistor T18 and the nineteenth transistor T19 to be turned on. Due to the aspect ratio design of the thirteenth transistor T13 and the eighteenth transistor T18, the voltage of the second terminal of the thirteenth transistor T13 is still at a low level and the fourteenth transistor T14 is turned off. The nineteenth transistor T19 is turned on to pull the voltage of the second pull-down node PD2 to the reference voltage Vref1.
  • the input signal Input pulls down the voltage of the second pull-down plus point, thereby preventing the twelfth transistor T12 and the seventeenth transistor T17 from being turned on to affect the pull-up node PU and the output terminal.
  • the case of voltage This improves the reliability of the shift register unit.
  • the carry module 6 includes a twentieth transistor T20.
  • the control terminal of the twentieth transistor T20 is connected to the pull-up node PU, the first terminal of the twentieth transistor T20 receives the clock signal CLK, and the second terminal of the twentieth transistor T20 (ie, the carry terminal) outputs a carry signal "Carry" Out".
  • the voltage of the pull-up node PU controls the twentieth transistor T20 to be turned on, and the high level of the clock signal CLK is output to the second end of the twentieth transistor T20 as a carry signal.
  • the voltage of the pull-up node PU continues to control the twentieth transistor T20 to be turned on, and the low level (reference voltage Vref1) of the clock signal CLK is output to the twentieth transistor T20.
  • the carry pull-down module 7 includes a twenty-first transistor T21 and a twenty-second transistor T22.
  • the control end of the twenty-first transistor T21 is connected to the first pull-down node PD1
  • the first end of the twenty-first transistor T21 is connected to the second end of the twentieth transistor T20
  • the second end of the twenty-first transistor T21 The terminal is connected to a signal line for supplying the reference voltage Vref1.
  • the control end of the twenty-second transistor T22 is connected to the second pull-down node PD2, the first end of the twenty-second transistor T22 is connected to the second end of the twentieth transistor T20, and the second end of the twenty-second transistor T22 It is connected to a signal line for supplying the reference voltage Vref1.
  • the high level of the first pull-down node PD1 controls the twenty-first transistor T21 is turned on, and the voltage of the second terminal of the twentieth transistor T20 is held at the reference voltage Vref1.
  • the high level of the first pull-down node PD1 controls the twenty-first transistor T21 to be turned on, and the high level of the second pull-down node PD2 controls the twenty-second transistor T22 to be turned on.
  • the voltage of the second terminal of the twentieth transistor T20 is held at the reference voltage Vref1.
  • the second reset module 8 includes a twenty-third transistor T23.
  • the control terminal of the twenty-third transistor T23 receives the second reset signal Rst2, the first end of the twenty-third transistor T23 is connected to the second end of the twentieth transistor T20, and the second end of the twenty-third transistor T23 is A signal line connection for supplying the reference voltage Vref1.
  • the second reset signal Rst2 controls the 23rd transistor T23 to be turned on, and pulls the voltage of the carry terminal to the reference voltage Vref1.
  • the cooperation of the twenty-third transistor T23 and the twenty-first transistor T21 enables the voltage at the carry terminal to be pulled down to the reference voltage Vref1 more quickly.
  • the first to twenty-third transistors T1 to T23 are described and illustrated as N-type transistors.
  • P-type transistors and corresponding timing signals can be used to achieve the same functionality.
  • the gate voltage for turning on the P-type transistor is a low level voltage
  • the gate voltage for turning off the P-type transistor is a high level voltage.
  • FIG. 5 there is shown a gate drive circuit including a plurality of cascaded shift register units in accordance with an embodiment of the present disclosure.
  • the details of the shift register unit have been described in detail above and will not be described here.
  • FIG. 5 shows an exemplary cascade of multiple shift register units.
  • the carry signal “Carry Out” output from the nth shift register unit is supplied as the input signal Input of the n+kth shift register unit.
  • the carry signal “Carry Out” output from the nth shift register unit is supplied as the first reset signal Rst1 of the n-kth shift register unit.
  • the carry signal “Carry Out” output from the n+1th shift register unit is supplied as the second reset signal Rst2 of the n-kth shift register unit.
  • the carry signal “Carry Out” output from the n+1th shift register unit is supplied as the first reset signal Rst1 of the n+1th-kth shift register unit.
  • n is an integer greater than or equal to 4
  • k is an integer less than n and greater than or equal to 3.
  • the shift register units GOA1 to GOA6 respectively connect the first to sixth clock signal lines, that is, receive the first to sixth clock signals CLK1 to CLK6, respectively.
  • GOA1 to GOA6 are connected to the same first pull-down control signal line. That is, the same first pull-down control signal VHD1 is received.
  • GOA1 to GOA6 are connected to the same second pull-down control signal line, that is, receive the same second pull-down control signal VHD2.
  • GOA1 to GOA6 are connected to the same signal line for supplying the reference voltage Vref1, that is, receiving the same reference voltage Vref1.
  • GOA1 to GOA6 are connected to the same signal line for supplying the gate-off voltage Vref2, that is, receiving the same gate-off voltage Vref2.
  • the frame start signal STV is supplied as an input signal Input of GOA1 to GOA3.
  • the outputs of GOA1 to GOA6 provide corresponding gate drive signals "Output" for the corresponding gate lines.
  • the carry signal "Carry Out” output from GOA1 is supplied as the input signal Input of GOA4.
  • the carry signal “Carry Out” output from the GOA 4 is supplied as the first reset signal Rst1 of the GOA 1.
  • the carry signal “Carry Out” output from the GOA 5 is supplied as the second reset signal Rst2 of the GOA 1.
  • the carry signal "Carry Out” of the GOA2 output is supplied as the input signal Input of the GOA 5.
  • the carry signal “Carry Out” output from the GOA 5 is supplied as the first reset signal Rst1 of the GOA 2.
  • the carry signal “Carry Out” output from the GOA 6 is supplied as the second reset signal Rst2 of the GOA 2.
  • the carry signal "Carry Out” of the GOA3 output is supplied as the input signal Input of the GOA 6.
  • the carry signal "Carry Out” output from the GOA 6 is supplied as the first reset signal Rst1 of the GOA 3.
  • the carry signal output from the next shift register unit (not shown) of the GOA 6 is supplied as the second reset signal Rst2 of the GOA 3.
  • Embodiments of the present disclosure also provide a method of driving a gate driving circuit including a plurality of shift register cells. Referring to Figures 1 and 4, the method includes performing the following steps for each shift register unit.
  • the input module 1 transmits the input signal Input to the pull-up node PU to pull the voltage of the pull-up node PU high.
  • the output module 2 transmits the clock signal CLK to the output terminal as the gate turn-on voltage and further pulls the voltage of the pull-up node PU by a predetermined amount.
  • the output module 2 transmits a clock signal CLK to the output terminal to pull the voltage at the output terminal to the reference voltage Vref1 and pull the voltage of the pull-up node PU down by the predetermined amount.
  • the first reset module 3 further pulls the pulled down voltage of the pull-up node PU to the reference voltage Vref1 in response to the first reset signal Rst1.
  • the first pull-down control module 4 rings The pulled-down voltage at the output terminal should be changed from the reference voltage Vref1 to the gate-off voltage Vref2 at the first pull-down control signal VHD1.
  • the first pull-down control module 4 maintains the voltage of the pull-up node PU at the reference voltage Vref1 and the voltage of the output terminal at the gate-off voltage Vref2 in response to the first pull-down control signal VHD1.
  • the gate drive signal is first pulled down from the high level VGH to the reference voltage Vref1 which is smaller than the gate turn-off voltage Vref2, and then changed to the gate turn-off voltage Vref2.
  • the gate drive signal falls to a predetermined value (for example, 10% (VGH - Vref2)) in a shorter time than being directly pulled down to the gate turn-off voltage Vref2, thereby achieving a fast reset.
  • the gate drive signal "Output" is held at the gate turn-off voltage Vref2, enabling the display device to operate in a stable state.
  • FIG. 6 is a schematic diagram of a display device 100 in accordance with an embodiment of the present disclosure.
  • the display device 100 includes a display panel 110 for displaying an image, a data driving circuit 120 for outputting a data voltage to the display panel 110, and a gate driving circuit 130 for outputting a gate voltage to the display panel 110.
  • the gate driving circuit 130 may be the gate driving circuit described in the above embodiment, and a detailed description thereof is omitted herein.
  • Examples of the display panel 110 include a liquid crystal display panel and an organic light emitting diode display panel.
  • the data driving circuit 120 and the gate driving circuit 130 may be integrated on the display panel 110.
  • at least one of data drive circuit 120 and gate drive circuit 130 can form a separate chip.

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Abstract

一种移位寄存器单元、栅极驱动电路（130）及其驱动方法、以及显示装置（100）。移位寄存器单元具有包括输入阶段（t1）、输出阶段（t2）、复位阶段（t3）和保持阶段（t4）的工作周期。复位阶段（t3），将时钟信号（CLK）传送到输出端以将输出端的电压拉低至基准电压（Vref1），随后将输出端的被拉低的电压由基准电压（Vref1）改变至栅极关断电压（Vref2）。保持阶段（t4），使输出端的电压保持在栅极关断电压（Vref2）。基准电压（Vref1）小于栅极关断电压（Vref2）。

Description

移位寄存器单元、栅极驱动电路及其驱动方法和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种移位寄存器单元、栅极驱动电路及其驱动方法、以及显示装置。
背景技术
随着显示技术的不断发展，越来越多的显示装置采用阵列基板行驱动(Gate On Array，GOA)技术，其中将栅极驱动电路集成在阵列基板的非显示区域上，从而缩小了显示装置的边框宽度。栅极驱动电路包括若干个移位寄存器单元，每个移位寄存器单元为阵列基板上的多条栅线中的对应一条提供栅极驱动信号。
分配到显示装置中每一行像素的时间是固定的。在该固定时间内，需要完成像素的充电和栅极驱动信号的复位。对于具有较高分辨率的显示装置，其栅极驱动信号的复位时间较长，导致用于每行像素的充电时间较短。这对于像素的充电是不利的。
发明内容
本公开的实施例提供一种移位寄存器单元、栅极驱动电路及其驱动方法、以及显示装置。所提出的移位寄存器单元可以输出具有缩短的复位时间的栅极驱动信号。
根据本公开的第一方面，提供一种移位寄存器单元，具有包括输入阶段、输出阶段、复位阶段和保持阶段的工作周期，所述移位寄存器单元包括：输入模块，被配置成在所述输入阶段将输入信号传送至上拉节点以将所述上拉节点的电压拉高；输出模块，被配置成a)在所述输出阶段将时钟信号传送到输出端作为栅极开启电压并将所述上拉节点的电压进一步拉高一预定量，并且b)在所述复位阶段将所述时钟信号传送到所述输出端以将所述输出端的电压拉低至基准电压并将所述上拉节点的电压拉低所述预定量；第一复位模块，被配置成在所述复位阶段响应于第一复位信号将所述上拉节点的被拉低的电压进一步拉低至所述基准电压；以及第一下拉控制模块，被配置成响应于第一下拉控制信号而a)在所述复位阶段将所述输出端的被拉低的电压由所述基准电压改变至栅极关断电压，并且b)在所述保持阶段使所述上拉节点的电压保持在所述基准电压并使所述输出端的电压保持在所述栅 极关断电压，所述基准电压小于所述栅极关断电压。
根据本公开的第二方面，提供一种栅极驱动电路，包括多个级联的如第一方面中所述的移位寄存器单元。
根据本公开的第三方面，提供一种显示装置，包括如第二方面中任一项所述的栅极驱动电路。
根据本公开的第四方面，提供一种驱动包括多个移位寄存器单元的栅极驱动电路的方法，所述方法包括：对于所述多个移位寄存器单元中的每个：执行输入阶段，其中将输入信号传送至上拉节点以将所述上拉节点的电压拉高；执行输出阶段，其中将时钟信号传送到输出端作为栅极开启电压并将所述上拉节点的电压进一步拉高一预定量；执行复位阶段，其中将所述时钟信号传送到所述输出端以将所述输出端的电压拉低至基准电压并将所述上拉节点的电压拉低所述预定量，响应于第一复位信号将所述上拉节点的被拉低的电压进一步拉低至所述基准电压，并且响应于第一下拉控制信号将所述输出端的被拉低的电压由所述基准电压改变至栅极关断电压，所述基准电压小于所述栅极关断电压；以及执行保持阶段，其中响应于第一下拉控制信号使所述上拉节点的电压保持在所述基准电压并使所述输出端的电压保持在所述栅极关断电压。
根据在下文中所描述的实施例，本公开的这些和其它方面将是清楚明白的，并且将参考在下文中所描述的实施例而被阐明。
附图说明
图1示意性地示出了根据本公开实施例的移位寄存器单元的框图；
图2示意性地示出了图示说明栅极驱动信号的复位时间的降低的波形图；
图3示出了图1中所示的移位寄存器单元的示例电路图；
图4示出了图3中所示的移位寄存器单元的示例电路的工作时序图；
图5示意性地示出了根据本公开实施例的栅极驱动电路的框图；并且
图6示意性地示出了根据本公开实施例的显示装置的框图。
具体实施方式
现在，将参照其中表示本公开的示范性实施例的附图更完整地描述本公开。然而，本公开可以按很多不同的方式体现，不应解读为局限于这里所述的实施例。相反，提供这些实施例使得本公开是详尽和完整的，并且向本领域的技术人员完全传达本公开的范围。全文中，相同的参考数字指代相同的元素。
参阅图1和4，根据本公开实施例的移位寄存器单元包括输入模块1、输出模块2、第一复位模块3和第一下拉控制模块4。移位寄存器单元的一个工作周期包括输入阶段t1、输出阶段t2、复位阶段t3和保持阶段t4。
输入模块1被配置成在输入阶段t1将输入信号Input传送至上拉节点PU以将所述上拉节点PU的电压拉高。
输出模块2被配置成a)在所述输出阶段t2将时钟信号CLK传送到输出端作为栅极开启电压并将所述上拉节点PU的电压进一步拉高一预定量，并且b)在所述复位阶段t3将所述时钟信号CLK传送到所述输出端以将所述输出端的电压拉低至基准电压Vref1并将所述上拉节点PU的电压拉低所述预定量。时钟信号CLK的低电平为基准电压Vref1。
第一复位模块3被配置成在所述复位阶段t3响应于第一复位信号Rst1将所述上拉节点PU的被拉低的电压进一步拉低至所述基准电压Vref1。
第一下拉控制模块4被配置成响应于第一下拉控制信号VHD1而在所述复位阶段t3将所述输出端的被拉低的电压由所述基准电压Vref1改变至栅极关断电压Vref2。所述基准电压Vref1小于所述栅极关断电压Vref2，并且第一下拉控制信号VHD1与时钟信号CLK具有180度相位差。
第一下拉控制模块4还被配置成在所述保持阶段t4使所述上拉节点PU的电压保持在所述基准电压Vref1并使所述输出端的电压保持在所述栅极关断电压Vref2。移位寄存器单元的输出端在各个阶段输出的电压组合成栅极驱动信号“Output”。在保持阶段t4，栅极驱动信号“Output”被保持在栅极关断电压Vref2，使显示装置能够工作在稳定的状态。
参阅图2，栅极驱动信号从高电平VGH被首先拉低至小于栅极关断电压Vref2的基准电压Vref1，并且随后被改变为栅极关断电压Vref2。与被直接拉低至栅极关断电压Vref2相比，栅极驱动信号在更短的时间内下降到预定值(例如，10％(VGH-Vref2))，从而实现了快速复位。如图2所示，复位时间Δt2小于复位时间Δt1。栅极驱动信号的缩短的复位时间可以保证像素的充电时间。
返回参阅图1和4，在一些实施例中，移位寄存器单元还包括第二下拉控制模块5，其被配置成在所述保持阶段t4响应于第二下拉控制信号VHD2使所述上拉节点PU的电压保持在所述基准电压Vref1并使栅极驱动信号“Output”保持在所述栅极关断电压Vref2。所述第二下拉控制信号VHD2具有与所述第一下拉控制信号VHD1的相位相反的相位。
在保持阶段t4，第二下拉控制模块5与第一下拉控制模块4具有相同的功能，即在各自的下拉控制信号的控制下，使上拉节点PU的电压保持在基准电压Vref1，并且使栅极驱动信号“Output”保持在栅极关断电压Vref2。由于第一下拉控制信号VHD1与第二下拉控制信号VHD2的相位相反，所以第一下拉控制模块4和第二下拉控制模块5交替工作，使得在保持阶段t4中的任意时间点，上拉节点PU的电压总是保持在基准电压Vref1，并且栅极驱动信号“Output”总是保持在栅极关断电压Vref2。这避免了栅极驱动信号“Output”由于输出端的悬浮引起的不确定性。
将理解的是，在移位寄存器单元仅包括第一下拉控制模块4的实施例中，可以通过使第一下拉控制信号VHD1保持在高电平来避免栅极驱动信号“Output”的不确定性。
在一些实施例中，移位寄存器单元还包括进位模块6和进位下拉模块7。
进位模块6被配置成a)在所述输出阶段t2将所述时钟信号CLK传送到进位端作为进位信号“Carry Out”，并且b)在所述复位阶段t3将所述时钟信号CLK传送到所述进位端以将所述进位端的电压拉低至所述基准电压Vref1。
进位下拉模块7被配置成a)在所述复位阶段t3使所述进位端的被拉低的电压保持在所述基准电压Vref1，并且b)在所述保持阶段t4 使所述进位端的电压保持在所述基准电压Vref1。
栅极驱动信号“Output”和进位信号“Carry Out”分别被提供在分离的输出端和进位端处，使得它们不会相互影响。在后面将描述的栅极驱动电路中，当前移位寄存器单元的进位信号“Carry Out”被提供作为另一移位寄存器单元的输入信号Input，并且不会受到当前移位寄存器单元的栅极驱动信号“Output”的负载的影响。而且，可以通过选用具有低功耗的晶体管来驱动栅极驱动信号“Output”以及进位信号“Carry Out”的输出来降低移位寄存器单元的功耗。当然，在其中未引入进位模块6和进位下拉模块7的实施例中，栅极驱动信号“Output”也可以被用作进位信号“Carry Out”。这有利于减小显示装置的边框。
在一些实施例中，移位寄存器单元还包括第二复位模块8，其被配置成在所述复位阶段t3响应于第二复位信号Rst2将所述进位端的电压拉低至所述基准电压Vref1。第二复位模块8的存在使得能够将进位端的电压更快速地拉低至基准电压Vref1。
现在参阅图3，其中示出了图1中所示的移位寄存器单元的一个示例电路。
在该示例中，输入模块1包括第一晶体管T1。第一晶体管T1的控制端和第一端均接收输入信号Input，并且第一晶体管T1的第二端与上拉节点PU连接。在输入阶段t1，输入信号Input控制第一晶体管T1导通，并且将上拉节点PU的电压拉高。
在该示例中，输出模块2包括第二晶体管T2。第二晶体管T2的控制端与上拉节点PU连接，第二晶体管T2的第一端接收时钟信号CLK，并且第二晶体管T2的第二端(即，输出端)输出栅极驱动信号“Output”。
在输出阶段t2开始时，上拉节点PU的电压控制第二晶体管T2导通，并且时钟信号CLK的高电平被传送到输出端。由于第二晶体管T2中的寄生电容(例如，栅-漏寄生电容和栅-源寄生电容)的自举，上拉节点PU的电压被进一步拉高一预定量。
在复位阶段t3开始时，由于第二晶体管T2中的寄生电容的自举，时钟信号CLK从高电平到低电平的转变使得上拉节点PU的电压被拉低预定量，但是仍然为高电平并且能够使第二晶体管T2导通。第二晶体管T2的第二端的电压被拉低至时钟信号CLK的低电平，即基准电 压Vref1。
在实践中，第二晶体管T2中的寄生电容可能将例如由于时钟信号CLK的高电平引起的噪声信号耦合到上拉节点PU。为了减小这种由寄生电容造成的影响，移位寄存器单元还可以包括电容C1。电容C1的一端与第二晶体管T2的第二端连接，并且电容C1的另一端与上拉节点PU连接。也即，电容C1与寄生电容并联。从上拉节点PU的视角，上拉节点PU一侧的电容增大，从而降低了来自时钟信号CLK的噪声对上拉节点PU的电压的影响。这可以增强移位寄存器单元的抗干扰能力。
在该示例中，第一复位模块3包括第三晶体管T3。第三晶体管T3的控制端接收第一复位信号Rst1，第三晶体管T3的第一端与上拉节点PU连接，并且第三晶体管T3的第二端与用于提供基准电压Vref1的信号线连接。
在复位阶段t3内的某个时间，第一复位信号Rst1控制第三晶体管T3导通，使得上拉节点PU与提供基准电压Vref1的信号线连通，从而将上拉节点PU的电压拉低至基准电压Vref1。
在该示例中，第一下拉控制模块4包括第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8和第九晶体管T9。第四晶体管T4的控制端和第一端均接收第一下拉控制信号VHD1，并且第四晶体管T4的第二端连接第五晶体管T5的控制端和第六晶体管T6的第一端。第五晶体管T5的第一端接收第一下拉控制信号VHD1，并且第五晶体管T5的第二端与第一下拉节点PD1连接。第六晶体管T6的控制端与上拉节点PU连接，并且第六晶体管T6的第二端与用于提供基准电压Vref1的信号线连接。第七晶体管T7的控制端与上拉节点PU连接，第七晶体管T7的第一端与第一下拉节点PD1连接，并且第七晶体管T7的第二端与用于提供基准电压Vref1的信号线连接。第八晶体管T8的控制端与第一下拉节点PD1连接，第八晶体管T8的第一端与上拉节点PU连接，并且第八晶体管T8的第二端与用于提供基准电压Vref1的信号线连接。第九晶体管T9的控制端与第一下拉节点PD1连接，第九晶体管T9的第一端与第二晶体管T2的第二端连接，并且第九晶体管T9的第二端与用于提供栅极关断电压Vref2的信号线连接。
在复位阶段t3，第一下拉控制信号VHD1控制第四晶体管T4导通。在上拉节点PU的电压为高电平时，第六晶体管T6和第七晶体管T7导通。由于第四晶体管T4和第六晶体管T6的宽长比设计，第四晶体管T4的第二端的电压仍然处于低电平。在第一复位信号Rst1到来之后，上拉节点PU的电压被拉低至基准电压Vref1，使得第六晶体管T6和第七晶体管T7截止。导通的第四晶体管T4进而控制第五晶体管T5导通，使得第一下拉节点PD1的电压变为高电平。因此，第八晶体管T8导通将上拉节点PU的电压拉低至基准电压Vref1，并且第九晶体管T9导通将第二晶体管T2的第二端的电压由基准电压Vref1改变至栅极关断电压Vref2。
在保持阶段t4，在第一下拉控制信号VHD1为高电平时，第一下拉节点PD1的电压处于高电平。因此，第八晶体管T8导通使上拉节点PU的电压保持在基准电压Vref1，并且第九晶体管T9导通使第二晶体管T2的第二端电压保持在栅极关断电压Vref2。
第八晶体管T8和第三晶体管T3均起到将上拉节点PU的电压拉低至基准电压Vref1的作用，使得上拉节点PU的电压能够被更快速地拉低。
在该示例中，第一下拉控制模块4还可以包括第十晶体管T10和第十一晶体管T11。第十晶体管T10的控制端接收输入信号Input，第十晶体管T10的第一端与第四晶体管T4的第二端连接，并且第十晶体管T10的第二端与用于提供基准电压Vref1的信号线连接。第十一晶体管T11的控制端接收输入信号Input，第十一晶体管T11的第一端与第一下拉节点PD1连接，并且第十一晶体管T11的第二端与用于提供基准电压Vref1的信号线连接。
在输入阶段t1，在将上拉节点PU的电压拉高的同时，输入信号Input还会控制第十晶体管T10和第十一晶体管T11导通。由于第四晶体管T4和第十晶体管T10的宽长比设计，第四晶体管T4的第二端的电压仍然处于低电平并且使得第五晶体管T5截止。第十一晶体管T11导通会将第一下拉节点PD1的电压拉低至基准电压Vref1。这样，当拉高上拉节点PU的电压时，输入信号Input将第一下拉节点PD1的电压拉低，从而避免第八晶体管T8和第九晶体管T9导通而影响上拉节点PU和输出端的电压的情况。这提高了移位寄存器单元的可靠性。
在该示例中，第二下拉控制模块5包括第十二晶体管T12、第十三晶体管T13、第十四晶体管T14、第十五晶体管T15、第十六晶体管T16和第十七晶体管T17。第十二晶体管T12的控制端与第二下拉节点PD2连接，第十二晶体管T12的第一端与第二晶体管T2的第二端连接，并且第十二晶体管T12的第二端与用于提供栅极关断电压Vref2的信号线连接。第十三晶体管T13的控制端和第十三晶体管T13的第一端均接收第二下拉控制信号VHD2，并且第十三晶体管T13的第二端连接第十四晶体管T14的控制端和第十五晶体管T15的第一端。第十四晶体管T14的第一端接收第二下拉控制信号VHD2，并且第十四晶体管T14的第二端与第二下拉节点PD2连接。第十五晶体管T15的控制端与上拉节点PU连接，并且第十五晶体管T15的第二端与用于提供基准电压Vref1的信号线连接。第十六晶体管T16的控制端与上拉节点PU连接，第十六晶体管T16的第一端与第二下拉节点PD2连接，并且第十六晶体管T16的第二端与用于提供基准电压Vref1的信号线连接。第十七晶体管T17的控制端与第二下拉节点PD2连接，第十七晶体管T17的第一端与上拉节点PU连接，并且第十七晶体管T17的第二端与用于提供基准电压Vref1的信号线连接。
在输出阶段t2，上拉节点PU的高电平能够控制第十五晶体管T15和第十六晶体管T16均导通。由于第十三晶体管T13和第十五晶体管T15的宽长比设计，第十三晶体管T13的第二端的电压仍然处于低电平，使得第十四晶体管T14截止。导通的第十六晶体管T16将第二下拉节点PD2的电压拉低至基准电压Vref1。因此，在输出阶段t2，第二下拉节点PD2的电压不能够使第十二晶体管T12和第十七晶体管T17导通，避免了对上拉节点PU和输出端的电压的影响。
在保持阶段t4，在第二下拉控制信号VHD2为高电平时，第十三晶体管T13和第十四晶体管T14导通，使得第二下拉节点PD2的电压为高电平，并且第十二晶体管T12和第十七晶体管T17导通。第十二晶体管T12导通使第二晶体管T2的第二端的电压保持在栅极关断电压Vref2，并且第十七晶体管T17导通使上拉节点PU的电压保持在基准电压Vref1。
在该示例中，第二下拉控制模块5还可以包括第十八晶体管T18和第十九晶体管T19。第十八晶体管T18的控制端接收输入信号Input， 第十八晶体管T18的第一端与第十三晶体管T13的第二端连接，第十八晶体管T18的第二端与用于提供基准电压Vref1的信号线连接；第十九晶体管T19的控制端接收输入信号Input，第十九晶体管T19的第一端与第二下拉节点PD2连接，第十九晶体管T19的第二端与用于提供基准电压Vref1的信号线连接。
在输入阶段t1，在将上拉节点PU的电压拉高的同时，输入信号Input还会控制第十八晶体管T18和第十九晶体管T19导通。由于第十三晶体管T13和第十八晶体管T18的宽长比设计，第十三晶体管T13的第二端的电压仍然处于低电平并且使得第十四晶体管T14截止。第十九晶体管T19导通会将第二下拉节点PD2的电压拉低至基准电压Vref1。这样，当拉高上拉节点PU的电压时，输入信号Input将第二下拉加点的电压拉低，从而避免第十二晶体管T12和第十七晶体管T17导通而影响上拉节点PU和输出端的电压的情况。这提高了移位寄存器单元的可靠性。
在该示例中，进位模块6包括第二十晶体管T20。第二十晶体管T20的控制端与上拉节点PU连接，第二十晶体管T20的第一端接收时钟信号CLK，并且第二十晶体管T20的第二端(即，进位端)输出进位信号“Carry Out”。
在输出阶段t2，上拉节点PU的电压控制第二十晶体管T20导通，并且时钟信号CLK的高电平被输出到第二十晶体管T20的第二端作为进位信号。在刚进入到复位阶段t3时，上拉节点PU的电压继续控制第二十晶体管T20导通，并且时钟信号CLK的低电平(基准电压Vref1)被输出到第二十晶体管T20。
在该示例中，进位下拉模块7包括第二十一晶体管T21和第二十二晶体管T22。第二十一晶体管T21的控制端与第一下拉节点PD1连接，第二十一晶体管T21的第一端与第二十晶体管T20的第二端连接，并且第二十一晶体管T21的第二端与用于提供基准电压Vref1的信号线连接。第二十二晶体管T22的控制端与第二下拉节点PD2连接，第二十二晶体管T22的第一端与第二十晶体管T20的第二端连接，并且第二十二晶体管T22的第二端与用于提供基准电压Vref1的信号线连接。
在复位阶段t3，第一下拉节点PD1的高电平控制第二十一晶体管 T21导通，并且第二十晶体管T20的第二端的电压被保持在基准电压Vref1。
在保持阶段t4，第一下拉节点PD1的高电平控制第二十一晶体管T21导通，并且第二下拉节点PD2的高电平控制第二十二晶体管T22导通。第二十晶体管T20的第二端的电压被保持在基准电压Vref1。
在该示例中，第二复位模块8包括第二十三晶体管T23。第二十三晶体管T23的控制端接收第二复位信号Rst2，第二十三晶体管T23的第一端与第二十晶体管T20的第二端连接，并且第二十三晶体管T23的第二端与用于提供基准电压Vref1的信号线连接。
在复位阶段t3，第二复位信号Rst2控制第二十三晶体管T23导通，将进位端的电压拉低至基准电压Vref1。第二十三晶体管T23与第二十一晶体管T21的配合使得进位端的电压能够被更快速地拉低至基准电压Vref1。
在上面的实施例中，第一晶体管T1至第二十三晶体管T23被描述和图示为N型晶体管。然而，在适当的情况下，可以使用P型晶体管和对应的时序信号来实现相同的功能。用于开启P型晶体管的栅极电压为低电平电压，并且用于关断P型晶体管的栅极电压为高电平电压。
请参阅图5，其中示出了根据本公开实施例的一种栅极驱动电路，其包括若干级联的上述移位寄存器单元。移位寄存器单元的细节已经在上面详细地描述，此处不做赘述。
图5示出了多个移位寄存器单元的示例性级联。第n个移位寄存器单元输出的进位信号“Carry Out”被提供作为第n+k个移位寄存器单元的输入信号Input。第n个移位寄存器单元输出的进位信号“Carry Out”被提供作为第n-k个移位寄存器单元的第一复位信号Rst1。第n+1个移位寄存器单元输出的进位信号“Carry Out”被提供作为第n-k个移位寄存器单元的第二复位信号Rst2。第n+1个移位寄存器单元输出的进位信号“Carry Out”被提供作为第n+1-k级移位寄存器单元的第一复位信号Rst1。n为大于等于4的整数，并且k为小于n的整数且大于等于3。
在图5的示例中，移位寄存器单元GOA1至GOA6分别连接第一时钟信号线至第六时钟信号线，即分别接收第一时钟信号CLK1至第六时钟信号CLK6。GOA1至GOA6连接同一个第一下拉控制信号线， 即接收同一个第一下拉控制信号VHD1。GOA1至GOA6连接同一个第二下拉控制信号线，即接收同一个第二下拉控制信号VHD2。GOA1至GOA6连接同一个用于提供基准电压Vref1的信号线，即接收同一个基准电压Vref1。GOA1至GOA6连接同一个用于提供栅极关断电压Vref2的信号线，即接收同一个栅极关断电压Vref2。帧起始信号STV被提供作为GOA1至GOA3的输入信号Input。GOA1至GOA6的输出端为对应的栅线提供对应的栅极驱动信号“Output”。
GOA1输出的进位信号“Carry Out”被提供作为GOA4的输入信号Input。GOA4输出的进位信号“Carry Out”被提供作为GOA1的第一复位信号Rst1。GOA5输出的进位信号“Carry Out”被提供作为GOA1的第二复位信号Rst2。
GOA2输出的进位信号“Carry Out”被提供作为GOA5的输入信号Input。GOA5输出的进位信号“Carry Out”被提供作为GOA2的第一复位信号Rst1。GOA6输出的进位信号“Carry Out”被提供作为GOA2的第二复位信号Rst2。
GOA3输出的进位信号“Carry Out”被提供作为GOA6的输入信号Input。GOA6输出的进位信号“Carry Out”被提供作为GOA3的第一复位信号Rst1。GOA6的下一个移位寄存器单元(未示出)输出的进位信号被提供作为GOA3的第二复位信号Rst2。
GOA4至GOA6以及另外的移位寄存器单元(未示出)的连接是类似的，并且此处为了简单起见被省略。
本公开实施例还提供一种驱动包括多个移位寄存器单元的栅极驱动电路的方法。参阅图1和4，该方法包括针对每个移位寄存器单元执行以下步骤。
在输入阶段t1，输入模块1将输入信号Input传送至上拉节点PU以将上拉节点PU的电压拉高。
在输出阶段t2，输出模块2将时钟信号CLK传送到输出端作为栅极开启电压并将上拉节点PU的电压进一步拉高一预定量。
在复位阶段t3，输出模块2将时钟信号CLK传送到所述输出端以将输出端的电压拉低至基准电压Vref1并将上拉节点PU的电压拉低所述预定量。第一复位模块3响应于第一复位信号Rst1将上拉节点PU的被拉低的电压进一步拉低至基准电压Vref1。第一下拉控制模块4响 应于第一下拉控制信号VHD1将输出端的被拉低的电压由基准电压Vref1改变至栅极关断电压Vref2。
在保持阶段t4，第一下拉控制模块4响应于第一下拉控制信号VHD1使上拉节点PU的电压保持在基准电压Vref1并使输出端的电压保持在栅极关断电压Vref2。
该方法的各个阶段的细节在前面结合图1、3和4描述的实施例中被描述，并且在此为了简单起见被省略。
栅极驱动信号从高电平VGH被首先拉低至小于栅极关断电压Vref2的基准电压Vref1，并且随后被改变为栅极关断电压Vref2。与被直接拉低至栅极关断电压Vref2相比，栅极驱动信号在更短的时间内下降到预定值(例如，10％(VGH-Vref2))，从而实现了快速复位。
此外，在保持阶段t4，栅极驱动信号“Output”被保持在栅极关断电压Vref2，使显示装置能够工作在稳定的状态。
图6为根据本公开实施例的显示装置100的示意图。参照图6，显示装置100包括用于显示图像的显示面板110、用于向显示面板110输出数据电压的数据驱动电路120以及用于向显示面板110输出栅极电压的栅极驱动电路130。栅极驱动电路130可以是上面实施例中描述的栅极驱动电路，对其的详细描述在此被省略。
显示面板110的示例包括液晶显示面板和有机发光二极管显示面板。在一些实施例中，数据驱动电路120和栅极驱动电路130可以集成在显示面板110上。在一些实施例中，数据驱动电路120和栅极驱动电路130中的至少一个可以形成单独的芯片。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此。任何熟悉本技术领域的技术人员可轻易想到的变化或替换都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求为准。

Claims (26)

  1. 一种移位寄存器单元，具有包括输入阶段、输出阶段、复位阶段和保持阶段的工作周期，所述移位寄存器单元包括：
    输入模块，被配置成在所述输入阶段将输入信号传送至上拉节点以将所述上拉节点的电压拉高；
    输出模块，被配置成a)在所述输出阶段将时钟信号传送到输出端作为栅极开启电压并将所述上拉节点的电压进一步拉高一预定量，并且b)在所述复位阶段将所述时钟信号传送到所述输出端以将所述输出端的电压拉低至基准电压并将所述上拉节点的电压拉低所述预定量；
    第一复位模块，被配置成在所述复位阶段响应于第一复位信号将所述上拉节点的被拉低的电压进一步拉低至所述基准电压；以及
    第一下拉控制模块，被配置成响应于第一下拉控制信号而a)在所述复位阶段将所述输出端的被拉低的电压由所述基准电压改变至栅极关断电压，并且b)在所述保持阶段使所述上拉节点的电压保持在所述基准电压并使所述输出端的电压保持在所述栅极关断电压，所述基准电压小于所述栅极关断电压。
  2. 根据权利要求1所述的移位寄存器单元，其中所述输入模块包括第一晶体管，其具有均用于接收所述输入信号的控制端和第一端，以及与所述上拉节点连接的第二端。
  3. 根据权利要求1所述的移位寄存器单元，其中所述输出模块包括第二晶体管，其具有与所述上拉节点连接的控制端、用于接收所述时钟信号的第一端、以及与所述输出端连接的的第二端。
  4. 根据权利要求1所述的移位寄存器单元，其中所述第一复位模块包括第三晶体管，其具有用于接收所述第一复位信号的控制端、与所述上拉节点连接的第一端、以及用于接收所述基准电压的第二端。
  5. 根据权利要求1所述的移位寄存器单元，其中所述第一下拉控制模块包括：
    第四晶体管，具有均用于接收所述第一下拉控制信号的控制端和第一端、以及第二端；
    第五晶体管，具有与所述第四晶体管的第二端连接的控制端、用于接收所述第一下拉控制信号的第一端、以及与第一下拉节点连接的 第二端；
    第六晶体管，具有与所述上拉节点连接的控制端、与所述第四晶体管的第二端连接的第一端、以及用于接收所述基准电压的第二端；
    第七晶体管，具有与所述上拉节点连接的控制端、与所述第一下拉节点连接的第一端、以及用于接收所述基准电压的第二端；
    第八晶体管，具有与所述第一下拉节点连接的控制端、与所述上拉节点连接的第一端、以及用于接收所述基准电压的第二端；以及
    第九晶体管，具有与所述第一下拉节点连接的控制端、与所述输出端连接的第一端、以及用于接收所述栅极关断电压的第二端。
  6. 根据权利要求5所述的移位寄存器单元，其中所述第一下拉控制模块还包括：
    第十晶体管，具有用于接收所述输入信号的控制端、与所述第四晶体管的第二端连接的第一端、以及用于接收所述基准电压的第二端；以及
    第十一晶体管，具有用于接收所述输入信号的控制端、与所述第一下拉节点连接的第一端、以及用于接收所述基准电压的第二端。
  7. 根据权利要求1所述的移位寄存器单元，还包括第二下拉控制模块，其被配置成在所述保持阶段响应于第二下拉控制信号使所述上拉节点的电压保持在所述基准电压并使所述输出端的电压保持在所述栅极关断电压，所述第二下拉控制信号具有与所述第一下拉控制信号的相位相反的相位。
  8. 根据权利要求7所述的移位寄存器单元，其中所述第二下拉控制模块包括：
    第十二晶体管，具有与第二下拉节点连接的控制端、与所述输出端连接的第一端、以及用于接收所述栅极关断电压的第二端；
    第十三晶体管，具有均用于接收所述第二下拉控制信号的控制端和第一端、以及第二端；
    第十四晶体管，具有与所述第十三晶体管的第二端连接的控制端、用于接收所述第二下拉控制信号的第一端、以及与所述第二下拉节点连接的第二端；
    第十五晶体管，具有与所述上拉节点连接的控制端、与所述第十三晶体管的第二端连接的第一端、以及用于接收所述基准电压的第二 端；
    第十六晶体管，具有与所述上拉节点连接的控制端、与所述第二下拉节点连接的第一端、以及用于接收所述基准电压的第二端；以及
    第十七晶体管，具有与所述第二下拉节点连接的控制端、与所述上拉节点连接的第一端、以及用于接收所述基准电压的第二端。
  9. 根据权利要求8所述的移位寄存器单元，其中所述第二下拉控制模块还包括：
    第十八晶体管，具有用于接收所述输入信号的控制端、与所述第十三晶体管的第二端连接的第一端、以及用于接收所述基准电压的第二端；以及
    第十九晶体管，具有用于接收所述输入信号的控制端、与所述第二下拉节点连接的第一端、以及用于接收所述基准电压的第二端。
  10. 根据权利要求7所述的移位寄存器单元，还包括：
    进位模块，被配置成a)在所述输出阶段将所述时钟信号传送到进位端作为进位信号，并且b)在所述复位阶段将所述时钟信号传送到所述进位端以将所述进位端的电压拉低至所述基准电压；以及
    进位下拉模块，被配置成a)在所述复位阶段使所述进位端的被拉低的电压保持在所述基准电压，并且b)在所述保持阶段使所述进位端的电压保持在所述基准电压。
  11. 根据权利要求10所述的移位寄存器单元，其中所述进位模块包括第二十晶体管，其具有与所述上拉节点连接的控制端、用于接收所述时钟信号的第一端、以及与所述进位端连接的第二端。
  12. 根据权利要求10所述的移位寄存器单元，其中所述进位下拉模块包括：
    第二十一晶体管，具有与第一下拉节点连接的控制端、与所述进位端连接的第一端、以及用于接收所述基准电压的第二端；以及
    第二十二晶体管，具有与第二下拉节点连接的控制端、与所述进位端连接的第一端、以及用于接收所述基准电压的第二端。
  13. 根据权利要求10所述的移位寄存器单元，还包括第二复位模块，其被配置成在所述复位阶段响应于第二复位信号将所述进位端的电压拉低至所述基准电压。
  14. 根据权利要求13所述的移位寄存器单元，其中所述第二复位 模块包括第二十三晶体管，其具有用于接收所述第二复位信号的控制端、与所述进位端连接的第一端、以及用于接收所述基准电压的第二端。
  15. 根据权利要求1所述的移位寄存器单元，还包括电容，其具有与所述输出端连接的一端和与所述上拉节点连接的另一端。
  16. 一种栅极驱动电路，包括多个级联的如权利要求1-6中任一项所述的移位寄存器单元。
  17. 根据权利要求16所述的栅极驱动电路，其中所述多个移位寄存器单元中的每个还包括第二下拉控制模块，其被配置成在所述保持阶段响应于第二下拉控制信号使所述上拉节点的电压保持在所述基准电压并使所述输出端的电压保持在所述栅极关断电压，所述第二下拉控制信号具有与所述第一下拉控制信号的相位相反的相位。
  18. 根据权利要求17所述的栅极驱动电路，其中所述多个移位寄存器单元中的每个还包括：
    进位模块，被配置成a)在所述输出阶段将所述时钟信号传送到进位端作为进位信号，并且b)在所述复位阶段将所述时钟信号传送到所述进位端以将所述进位端的电压拉低至所述基准电压；以及
    进位下拉模块，被配置成a)在所述复位阶段使所述进位端的被拉低的电压保持在所述基准电压，并且b)在所述保持阶段使所述进位端的电压保持在所述基准电压。
  19. 根据权利要求18所述的栅极驱动电路，其中所述多个移位寄存器单元中的每个还包括第二复位模块，其被配置成在所述复位阶段响应于第二复位信号将所述进位端的电压拉低至所述基准电压。
  20. 根据权利要求19所述的栅极驱动电路，其中来自所述多个移位寄存器单元中的第n个的进位信号被提供作为所述多个移位寄存器单元中的第n+k个的输入信号和所述多个移位寄存器单元中的第n-k个的第一复位信号，并且来自所述多个移位寄存器单元输出中的第n+1个的进位信号被提供作为所述多个移位寄存器单元中的第n-k个的第二复位信号和所述多个移位寄存器单元中的第n+1-k个的第一复位信号，其中n为大于等于4的整数，并且k为小于n的整数且大于等于3。
  21. 根据权利要求16-20中任一项所述的栅极驱动电路，其中所述多个移位寄存器单元中的每个还包括电容，其具有与所述输出端连接 的一端和与所述上拉节点连接的另一端。
  22. 一种显示装置，包括如权利要求16-21中任一项所述的栅极驱动电路。
  23. 一种驱动包括多个移位寄存器单元的栅极驱动电路的方法，所述方法包括：
    对于所述多个移位寄存器单元中的每个：
    执行输入阶段，其中将输入信号传送至上拉节点以将所述上拉节点的电压拉高；
    执行输出阶段，其中将时钟信号传送到输出端作为栅极开启电压并将所述上拉节点的电压进一步拉高一预定量；
    执行复位阶段，其中将所述时钟信号传送到所述输出端以将所述输出端的电压拉低至基准电压并将所述上拉节点的电压拉低所述预定量，响应于第一复位信号将所述上拉节点的被拉低的电压进一步拉低至所述基准电压，并且响应于第一下拉控制信号将所述输出端的被拉低的电压由所述基准电压改变至栅极关断电压，所述基准电压小于所述栅极关断电压；以及
    执行保持阶段，其中响应于第一下拉控制信号使所述上拉节点的电压保持在所述基准电压并使所述输出端的电压保持在所述栅极关断电压。
  24. 根据权利要求23所述的方法，其中执行所述保持阶段还包括响应于第二下拉控制信号使所述上拉节点的电压保持在所述基准电压并使所述输出端的电压保持在所述栅极关断电压，所述第二下拉控制信号具有与所述第一下拉控制信号的相位相反的相位。
  25. 根据权利要求24所述的方法，其中执行所述输出阶段还包括将所述时钟信号传送到进位端作为进位信号，其中执行所述复位阶段还包括将所述时钟信号传送到所述进位端以将所述进位端的电压拉低至所述基准电压，并且使所述进位端的被拉低的电压保持在所述基准电压，并且其中执行所述保持阶段还包括使所述进位端的电压保持在所述基准电压。
  26. 根据权利要求25所述的方法，其中执行所述复位阶段还包括响应于第二复位信号将所述进位端的电压拉低至所述基准电压。
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