WO2017128565A1 - 低温多晶硅阵列基板的制作方法 - Google Patents
低温多晶硅阵列基板的制作方法 Download PDFInfo
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- WO2017128565A1 WO2017128565A1 PCT/CN2016/082717 CN2016082717W WO2017128565A1 WO 2017128565 A1 WO2017128565 A1 WO 2017128565A1 CN 2016082717 W CN2016082717 W CN 2016082717W WO 2017128565 A1 WO2017128565 A1 WO 2017128565A1
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- polysilicon
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 156
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 155
- 239000000758 substrate Substances 0.000 title claims abstract description 86
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- 238000000034 method Methods 0.000 claims abstract description 60
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- 230000008569 process Effects 0.000 claims abstract description 34
- 239000010410 layer Substances 0.000 claims description 417
- 229920002120 photoresistant polymer Polymers 0.000 claims description 117
- 229910052751 metal Inorganic materials 0.000 claims description 47
- 239000002184 metal Substances 0.000 claims description 47
- 238000000151 deposition Methods 0.000 claims description 41
- 239000011229 interlayer Substances 0.000 claims description 33
- 238000002161 passivation Methods 0.000 claims description 29
- 239000011241 protective layer Substances 0.000 claims description 27
- -1 aluminum tin oxide Chemical compound 0.000 claims description 20
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- 150000004706 metal oxides Chemical group 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 150000002500 ions Chemical class 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 8
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- 238000006356 dehydrogenation reaction Methods 0.000 claims description 5
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- 239000010936 titanium Substances 0.000 claims description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 230000003213 activating effect Effects 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
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- 229910052796 boron Inorganic materials 0.000 claims description 4
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- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 4
- JAONJTDQXUSBGG-UHFFFAOYSA-N dialuminum;dizinc;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Al+3].[Al+3].[Zn+2].[Zn+2] JAONJTDQXUSBGG-UHFFFAOYSA-N 0.000 claims description 4
- 229910052733 gallium Inorganic materials 0.000 claims description 4
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical group [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 4
- 229910052750 molybdenum Inorganic materials 0.000 claims description 4
- 239000011733 molybdenum Substances 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 239000011574 phosphorus Substances 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 claims description 4
- WHXAGNPBEKUGSK-UHFFFAOYSA-N zinc antimony(3+) indium(3+) oxygen(2-) Chemical compound [Sb+3].[Zn+2].[O-2].[In+3].[O-2].[O-2].[O-2] WHXAGNPBEKUGSK-UHFFFAOYSA-N 0.000 claims description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 15
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- SAZXSKLZZOUTCH-UHFFFAOYSA-N germanium indium Chemical compound [Ge].[In] SAZXSKLZZOUTCH-UHFFFAOYSA-N 0.000 description 1
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- 230000036632 reaction speed Effects 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
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- 239000011787 zinc oxide Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
Definitions
- LCDs liquid crystal displays
- Various consumer electronic products such as digital assistants, digital cameras, notebook computers, and desktop computers have become mainstream in display devices.
- the present invention provides a method for fabricating a low temperature polysilicon array substrate, comprising the following steps:
- the first photoresist layer and the second photoresist layer are ashed by using a dry etching device, so that the thin layer regions on both sides of the first photoresist layer are completely removed, and the first photoresist is simultaneously
- the thick layer region in the middle of the layer and the thickness of the second photoresist layer are thinned; the first polysilicon is masked by the thick layer region on the remaining first photoresist layer and the second photoresist layer as a mask N-type heavy doping is performed on both sides of the segment to obtain two N-type heavily doped regions.
- Step 6 depositing an interlayer insulating layer on the first gate, the second gate, and the gate insulating layer, and patterning the interlayer insulating layer and the gate insulating layer to obtain the N a first via above the heavily doped region and a second via above the P-type heavily doped region, and then dehydrogenating and activating the interlayer insulating layer;
- Step 10 depositing a passivation protective layer on the common electrode and the flat layer, the passivation protective layer coating a third via on the flat layer, and then patterning the passivation protective layer Obtaining a fourth via hole on the passivation protective layer at the bottom of the third via hole;
- the material of the first transparent conductive oxide layer and the second transparent conductive oxide layer is a metal oxide.
- the invention also provides a method for manufacturing a low temperature polysilicon array substrate, comprising the following steps:
- Step 5 P-type heavily doping the two sides of the second polysilicon segment with a photomask to obtain two P-type heavily doped regions, and the second polysilicon segments are located on two P-type heavily doped regions. a region between the regions forms a second channel region;
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- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Nonlinear Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Mathematical Physics (AREA)
- Optics & Photonics (AREA)
- Ceramic Engineering (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
Abstract
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Claims (17)
- 一种低温多晶硅阵列基板的制作方法,包括如下步骤:步骤1、提供一基板,在所述基板上定义出NMOS区与PMOS区,在所述基板上沉积第一金属层,对所述第一金属层进行图形化处理,得到位于NMOS区的第一遮光层及位于PMOS区的第二遮光层;步骤2、在所述第一遮光层、第二遮光层、及基板上形成缓冲层,在所述缓冲层上沉积非晶硅层,采用低温结晶工艺将所述非晶硅层转化为多晶硅层,利用光罩对NMOS区的多晶硅层进行沟道掺杂;步骤3、在所述多晶硅层上涂布光阻层,采用一道半色调光罩对所述光阻层进行曝光、显影后,得到位于NMOS区的第一光阻层与位于PMOS区的第二光阻层,所述第一光阻层包括中间的厚层区域以及位于厚层区域两侧的薄层区域,所述第二光阻层的厚度均匀,且所述第一光阻层的厚层区域与所述第二光阻层的厚度相同;以所述第一光阻层与第二光阻层为遮挡,对所述多晶硅层进行蚀刻,分别得到位于NMOS区的第一多晶硅段与位于PMOS区的第二多晶硅段;采用干蚀刻设备对所述第一光阻层与第二光阻层进行灰化处理,使得所述第一光阻层上位于两侧的薄层区域被完全去除,同时所述第一光阻层上位于中间的厚层区域以及第二光阻层的厚度减薄;以剩余的第一光阻层上的厚层区域与第二光阻层为掩模,对所述第一多晶硅段的两侧进行N型重掺杂,得到两N型重掺杂区。
- 如权利要求1所述的低温多晶硅阵列基板的制作方法,还包括如下步骤:步骤4、在所述第一多晶硅段、第二多晶硅段、及缓冲层上沉积栅极绝缘层,在所述栅极绝缘层上沉积第二金属层,对所述第二金属层进行图形化处理,得到分别对应于第一多晶硅段与第二多晶硅段上方的第一栅极与第二栅极;以所述第一栅极为光罩对所述第一多晶硅段进行N型轻掺杂,得到分别位于两N型重掺杂区内侧的两N型轻掺杂区,所述第一多晶硅段上位于两N型轻掺杂区之间的区域形成第一沟道区;步骤5、利用光罩对所述第二多晶硅段的两侧进行P型重掺杂,得到两P型重掺杂区,所述第二多晶硅段上位于两P型重掺杂区之间的区域形成第二沟道区;步骤6、在所述第一栅极、第二栅极、及栅极绝缘层上沉积层间绝缘层,对所述层间绝缘层及栅极绝缘层进行图形化处理,得到位于所述N型重掺杂区上方的第一过孔及位于所述P型重掺杂区上方的第二过孔,之后对所述层间绝缘层进行去氢和活化处理;步骤7、在所述层间绝缘层上沉积第三金属层,对所述第三金属层进行图形化处理,得到第一源极、第一漏极、第二源极、第二漏极,所述第一源极、第一漏极分别通过第一过孔与N型重掺杂区相接触,所述第二源极、第二漏极分别通过第二过孔与P型重掺杂区相接触;步骤8、在所述第一源极、第一漏极、第二源极、第二漏极、及层间绝缘层上形成平坦层,对所述平坦层进行图形化处理,得到位于所述第一漏极上方的第三过孔;步骤9、在所述平坦层上沉积第一透明导电氧化物层,对所述第一透明导电氧化物层进行图形化处理,得到公共电极;步骤10、在所述公共电极、及平坦层上沉积钝化保护层,所述钝化保护层包覆所述平坦层上的第三过孔,之后对所述钝化保护层进行图形化处理,得到位于所述第三过孔底部的钝化保护层上的第四过孔;步骤11、在所述钝化保护层上沉积第二透明导电氧化物层,对所述第二透明导电氧化物层进行图形化处理,得到像素电极,所述像素电极通过第四过孔与第一漏极相接触。
- 如权利要求1所述的低温多晶硅阵列基板的制作方法,其中,所述步骤2中,所述低温结晶工艺为准分子激光退火法或金属诱导横向晶化法。
- 如权利要求1所述的低温多晶硅阵列基板的制作方法,其中,所述步骤2中,所述沟道掺杂的具体操作为:在所述多晶硅层上涂布光阻层,利用光罩对光阻层进行曝光、显影,去除位于NMOS区的光阻层后,对整个NMOS区的多晶硅层进行P型轻掺杂。
- 如权利要求2所述的低温多晶硅阵列基板的制作方法,其中,所述步骤6中,采用快速热退火工艺对所述层间绝缘层进行去氢和活化处理。
- 如权利要求2所述的低温多晶硅阵列基板的制作方法,其中,所述基板为玻璃基板;所述第一金属层、第二金属层、第三金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合;所述缓冲层、栅极绝缘层、层间绝缘层、及钝化保护层为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层叠加构成的复合层;所述平坦层为有机光阻材料。
- 如权利要求2所述的低温多晶硅阵列基板的制作方法,其中,所述第一透明导电氧化物层、第二透明导电氧化物层的材料为金属氧化物。
- 如权利要求7所述的低温多晶硅阵列基板的制作方法,其中,所述金属氧化物为铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、或铟锗锌氧化物。
- 如权利要求2所述的低温多晶硅阵列基板的制作方法,其中,所述N型重掺杂、N型轻掺杂掺入的离子为磷离子或者砷离子。
- 如权利要求4所述的低温多晶硅阵列基板的制作方法,其中,所述P型重掺杂、P型轻掺杂掺入的离子为硼离子或者镓离子。
- 一种低温多晶硅阵列基板的制作方法,包括如下步骤:步骤1、提供一基板,在所述基板上定义出NMOS区与PMOS区,在所述基板上沉积第一金属层,对所述第一金属层进行图形化处理,得到位于NMOS区的第一遮光层及位于PMOS区的第二遮光层;步骤2、在所述第一遮光层、第二遮光层、及基板上形成缓冲层,在所述缓冲层上沉积非晶硅层,采用低温结晶工艺将所述非晶硅层转化为多晶硅层,利用光罩对NMOS区的多晶硅层进行沟道掺杂;步骤3、在所述多晶硅层上涂布光阻层,采用一道半色调光罩对所述光阻层进行曝光、显影后,得到位于NMOS区的第一光阻层与位于PMOS区的第二光阻层,所述第一光阻层包括中间的厚层区域以及位于厚层区域两侧的薄层区域,所述第二光阻层的厚度均匀,且所述第一光阻层的厚层区域与所述第二光阻层的厚度相同;以所述第一光阻层与第二光阻层为遮挡,对所述多晶硅层进行蚀刻,分别得到位于NMOS区的第一多晶硅段与位于PMOS区的第二多晶硅段;采用干蚀刻设备对所述第一光阻层与第二光阻层进行灰化处理,使得所述第一光阻层上位于两侧的薄层区域被完全去除,同时所述第一光阻层上位于中间的厚层区域以及第二光阻层的厚度减薄;以剩余的第一光阻层上的厚层区域与第二光阻层为掩模,对所述第一多晶硅段的两侧进行N型重掺杂,得到两N型重掺杂区;还包括如下步骤:步骤4、在所述第一多晶硅段、第二多晶硅段、及缓冲层上沉积栅极绝缘层,在所述栅极绝缘层上沉积第二金属层,对所述第二金属层进行图形化处理,得到分别对应于第一多晶硅段与第二多晶硅段上方的第一栅极与第二栅极;以所述第一栅极为光罩对所述第一多晶硅段进行N型轻掺杂,得到分别位于两N型重掺杂区内侧的两N型轻掺杂区,所述第一多晶硅段上位于两N型轻掺杂区之间的区域形成第一沟道区;步骤5、利用光罩对所述第二多晶硅段的两侧进行P型重掺杂,得到两P型重掺杂区,所述第二多晶硅段上位于两P型重掺杂区之间的区域形成第二沟道区;步骤6、在所述第一栅极、第二栅极、及栅极绝缘层上沉积层间绝缘层,对所述层间绝缘层及栅极绝缘层进行图形化处理,得到位于所述N型重掺杂区上方的第一过孔及位于所述P型重掺杂区上方的第二过孔,之后对所述层间绝缘层进行去氢和活化处理;步骤7、在所述层间绝缘层上沉积第三金属层,对所述第三金属层进行图形化处理,得到第一源极、第一漏极、第二源极、第二漏极,所述第一源极、第一漏极分别通过第一过孔与N型重掺杂区相接触,所述第二源极、第二漏极分别通过第二过孔与P型重掺杂区相接触;步骤8、在所述第一源极、第一漏极、第二源极、第二漏极、及层间绝缘层上形成平坦层,对所述平坦层进行图形化处理,得到位于所述第一漏极上方的第三过孔;步骤9、在所述平坦层上沉积第一透明导电氧化物层,对所述第一透明导电氧化物层进行图形化处理,得到公共电极;步骤10、在所述公共电极、及平坦层上沉积钝化保护层,所述钝化保护层包覆所述平坦层上的第三过孔,之后对所述钝化保护层进行图形化处理,得到位于所述第三过孔底部的钝化保护层上的第四过孔;步骤11、在所述钝化保护层上沉积第二透明导电氧化物层,对所述第二透明导电氧化物层进行图形化处理,得到像素电极,所述像素电极通过第四过孔与第一漏极相接触;其中,所述步骤2中,所述低温结晶工艺为准分子激光退火法或金属诱导横向晶化法;其中,所述步骤2中,所述沟道掺杂的具体操作为:在所述多晶硅层上涂布光阻层,利用光罩对光阻层进行曝光、显影,去除位于NMOS区的光阻层后,对整个NMOS区的多晶硅层进行P型轻掺杂。
- 如权利要求11所述的低温多晶硅阵列基板的制作方法,其中,所述步骤6中,采用快速热退火工艺对所述层间绝缘层进行去氢和活化处理。
- 如权利要求11所述的低温多晶硅阵列基板的制作方法,其中,所述基板为玻璃基板;所述第一金属层、第二金属层、第三金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合;所述缓冲层、栅极绝缘层、层间绝缘层、及钝化保护层为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层叠加构成的复合层;所述平坦层为有机光阻材料。
- 如权利要求11所述的低温多晶硅阵列基板的制作方法,其中,所述第一透明导电氧化物层、第二透明导电氧化物层的材料为金属氧化物。
- 如权利要求14所述的低温多晶硅阵列基板的制作方法,其中,所述金属氧化物为铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、或铟锗锌氧化物。
- 如权利要求11所述的低温多晶硅阵列基板的制作方法,其中,所述N型重掺杂、N型轻掺杂掺入的离子为磷离子或者砷离子。
- 如权利要求11所述的低温多晶硅阵列基板的制作方法,其中,所述P型重掺杂、P型轻掺杂掺入的离子为硼离子或者镓离子。
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2016
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CN104124206A (zh) * | 2013-04-23 | 2014-10-29 | 上海和辉光电有限公司 | Ltps阵列基板的制造方法 |
CN104617102A (zh) * | 2014-12-31 | 2015-05-13 | 深圳市华星光电技术有限公司 | 阵列基板及阵列基板制造方法 |
CN105097552A (zh) * | 2015-08-14 | 2015-11-25 | 京东方科技集团股份有限公司 | 薄膜晶体管及阵列基板的制备方法、阵列基板及显示装置 |
CN105161458A (zh) * | 2015-08-17 | 2015-12-16 | 武汉华星光电技术有限公司 | Tft基板的制作方法 |
CN105470197A (zh) * | 2016-01-28 | 2016-04-06 | 武汉华星光电技术有限公司 | 低温多晶硅阵列基板的制作方法 |
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US10101620B2 (en) | 2018-10-16 |
KR20180098621A (ko) | 2018-09-04 |
US20180067351A1 (en) | 2018-03-08 |
JP2019505999A (ja) | 2019-02-28 |
GB2560685B (en) | 2021-03-17 |
US20180373076A1 (en) | 2018-12-27 |
JP6646329B2 (ja) | 2020-02-14 |
KR102049685B1 (ko) | 2019-11-27 |
CN105470197A (zh) | 2016-04-06 |
CN105470197B (zh) | 2018-03-06 |
GB201812015D0 (en) | 2018-09-05 |
US10473990B2 (en) | 2019-11-12 |
GB2560685A (en) | 2018-09-19 |
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