TW578309B

TW578309B - Manufacturing method of low temperature poly-silicon thin-film transistor

Info

Publication number: TW578309B
Application number: TW92102797A
Authority: TW
Inventors: Kuen-Jr Lin; Kuen-Hung Chen
Original assignee: Au Optronics Corp
Priority date: 2003-02-11
Filing date: 2003-02-11
Publication date: 2004-03-01
Also published as: TW200415791A

Abstract

A kind of manufacturing method of low temperature poly-silicon (LTPS) CMOS process for thin-film transistor (TFT) is provided. The method comprises forming a poly island as an N-TFT and a P-TFT on an insulative substrate; sequentially depositing a gate insulation layer and a gate metal layer on the insulative substrate; patterning the gate metal layer to form a gate metal of the N-TFT and the gate metal mask of the P-TFT; using the gate metal of the N-TFT and the gate metal mask as a mask to perform N- ion implantation step onto the poly island to form the N- region of the N-TFT; forming a resist pattern on the gate metal of the N-TFT and the gate metal mask of the P-TFT, in which a portion of the resist pattern defines the gate metal of the P-TFT, and another portion of the resist pattern covers the gate metal of the N-TFT and the adjacent portion of the gate insulation layer surface to define the LDD structure of the N-TFT; performing an N+ ion implantation on the poly island to form the source/drain (S/D) region of the N-TFT; etching the portion of the gate metal mask not covered by the resist pattern to form the gate metal of the P-TFT; using the resist pattern and the gate metal of the P-TFT as a mask to perform p+ ion implantation on the poly island to form the S/D region of the P-TFT; stripping the resist pattern; and forming the S/D metal gates of the N-TFT and the P-TFT.

Description

578309 五、發明說明（l) 發明所屬之技術領域： m關於一種低溫多晶石夕（LTPS)薄膜電晶體技術，尤指一種低溫多晶矽薄膜電晶體的⑶⑽製程改良。乍先前技術：心著薄膜電晶體（thin-film transistors ;TFTs)製作技術的陕速進步，具備了輕薄、省電和無幅射線等優點之液晶顯示器（Hquid crystal display ;LCD)已大量應用於計算機、個人數位助理器（PD A )、手錶、筆記型電〜月句、數位相機、液晶顯示器和行動電話等各式電子產品。再加上業界積極的投入研發以及採用大型化的生產設備，使液晶顯示器的生產成本不斷下降，更令液晶顯示器的需求量大增。目前的TFT LCD分為非晶矽（a-Si)薄膜電晶體液晶顯示器與多晶矽（Poly-Si )薄膜電晶體液晶顯示器二種。低溫多晶矽（Low Temperature Poly-Silicon ;LTPS)是新一代的薄膜電晶體液晶顯示器製造流程，所謂低溫多晶矽 (LTPS)技術主要是藉由雷射退火製程（Laser Anneal)將 a-Si的薄膜轉變為多晶矽（Poly-Si )薄膜層。多晶矽的電晶體電子移動速度較非晶矽提高百倍，具有顯示畫面反映速度快、高亮度和高解析度等優點；此外，由於電子移578309 V. Description of the invention (l) The technical field to which the invention belongs: m About a low-temperature polycrystalline silicon (LTPS) thin-film transistor technology, especially a method for improving the manufacturing process of a low-temperature polycrystalline silicon thin-film transistor. At first glance: With the rapid advancement of thin-film transistors (TFTs) manufacturing technology, liquid crystal displays (LCDs) with the advantages of lightness, thinness, power saving, and frameless rays have been widely used. Used in various electronic products such as computers, personal digital assistants (PD A), watches, notebook computers, digital cameras, digital cameras, LCD monitors, and mobile phones. Coupled with the industry's active investment in research and development and the use of large-scale production equipment, the production cost of liquid crystal displays has continued to drop, and the demand for liquid crystal displays has increased significantly. Current TFT LCDs are divided into two types: amorphous silicon (a-Si) thin film transistor liquid crystal display and poly-Si (poly-Si) thin film transistor liquid crystal display. Low Temperature Poly-Silicon (LTPS) is a new generation of thin-film transistor liquid crystal display manufacturing process. The so-called low-temperature poly-silicon (LTPS) technology mainly uses a laser annealing process (Laser Anneal) to transform a-Si films into Poly-Si thin film layer. Polycrystalline silicon's electrons move 100 times faster than amorphous silicon, which has the advantages of fast display, high brightness and high resolution; in addition,

578309578309

動速度快，Poly —Si可作為驅動電路，因此可將週邊驅動電路製作在破璃基板上，以減輕其重量，達到輕薄化的要求。再者，由於LTPS TFT將驅動IC整合在LCD面板内，因此可降低1C成本，而且可減少IC後段加工所產生的率，因此亦可提升良率。匕’在低溫多晶石夕製程中’必須同時顧及晝素内部路的元件特性需求…同時可以提高驅以及降低畫素的漏電流有輕摻雜汲極是較佳的電路設言十，因其可降低熱傳導m牛或電路所造成的劣化現象，亦可在負偏㈣ ΐ?附二子和電洞的生成速率而進-步降低漏電/瓜，以維持驅動LCD所需的元件特性。請參見圖-A至圖一K，該等圖式係為習知技術 ::間極（t0p gate)LTPS簡製程（周邊驅動程示意圖。☆習知技術一中，總共使用了 /1先罩來製作出周邊驅動電路的CM0S N-TFT具有LDD結構。疋件其中如圖一A所示，首先在一絕緣基板丨（例如玻璃美 = ; = Γ和一非晶石夕膜層3 ’該緩衝二的作用出ΐ ίΪ ίίΪ1内的雜質因後續的高溫製程而擴散出來。接者，使用準分子雷射技術（Excimer ;el 578309With a fast moving speed, Poly-Si can be used as a driving circuit, so peripheral driving circuits can be fabricated on a broken glass substrate to reduce its weight and meet the requirements for lightness and thinness. In addition, because the LTPS TFT integrates the driver IC in the LCD panel, it can reduce the 1C cost and reduce the rate of IC post-processing, so the yield can be improved. In the low-temperature polycrystalline silicon process, we must also take into account the component characteristics of the internal circuit of the element ... At the same time, it can improve the drive and reduce the leakage current of the pixel. A lightly doped drain is a better circuit design. It can reduce the degradation caused by thermal conduction mN or circuit, and can further reduce the leakage / melon at the rate of negative bias and the generation rate of holes and holes to maintain the characteristics of the components required to drive the LCD. Please refer to Figure-A to Figure 1K. These diagrams are the conventional technology :: t0p gate LTPS simplified process (peripheral driver schematic. ☆ In the first conventional technology, a total of / 1 first mask is used. The CM0S N-TFT to make the peripheral driving circuit has an LDD structure. As shown in FIG. 1A, first, an insulating substrate (such as glass beauty =; = Γ and an amorphous stone film layer 3 ′ The effect of Buffer 2 is ΐ Ϊ ί Ϊ 的 1 Impurities in Ϊ1 are diffused due to subsequent high-temperature processes. In turn, excimer laser technology (Excimer; el 578309) is used.

τ = 4非晶♦膜層3，使該非晶矽結晶變成多晶矽而 /一夕:矽膜層3 ’ 。之後，進行微影蝕刻製程，如圖一猎由一第一光阻圖案4(使用第-道光罩），將在 / 基板1上之多晶矽膜層3，圖案化，以形成欲作為二FT和P-TFT的一多晶矽島狀物（poly island ) 5，並接者沉積一閘極絕緣層6，如圖所示。接=來:進行N-TFT的N+離子植入步驟，如圖一])所示，形成=一阻圖案7 (使用第二道光罩）於該閘極絕緣層6 ^ ’、其中该第二光阻圖案7將位於N —TFT之LDD結構和閘極區域，該多晶石夕島狀物5部份罩住以及將位於整個P-TFT區域的該多晶矽島狀物5部份罩住，並接著對該多晶矽島狀物5進行N+離子植入，形成N —TFT之S/D區域8。然後，剝除該第二光阻圖案7，並沉積一閘極金屬層9，如圖E所示’再進行微影|虫刻製程，藉由一第三光阻圖案 1 〇 (使用第三道光罩），將該閘極金屬層9圖案化，以形成N-TFT和P-TFT的閘極金屬9，，如圖一F所示。之後，直接以該閘極金屬9,作為罩幕，進行N-離子植入步驟，形成 N-TFT 之 LDD 結構 11。然後’如圖一 G所示，形成一第四光阻圖案丨3 (使用第四道光罩）以覆罩整個N-TFT區域，並對P-TFT區域進行P+離子植入步驟，以形成P-TFT的s/D區域14。進行至此，τ = 4 amorphous layer 3, which makes the amorphous silicon crystal become polycrystalline silicon and / overnight: silicon film layer 3 '. After that, a lithography etching process is performed, as shown in FIG. 1, a first photoresist pattern 4 (using a first channel mask) is used to pattern the polycrystalline silicon film layer 3 on the substrate 1 to form two FT and A poly island 5 of the P-TFT and a gate insulating layer 6 are deposited in parallel, as shown in the figure. Connect = come: N-TFT N + ion implantation steps are performed, as shown in Figure 1]), forming a resist pattern 7 (using a second mask) on the gate insulating layer 6 ^ ', where the second The photoresist pattern 7 will be located in the LDD structure and gate region of the N-TFT, the polycrystalline silicon island 5 is partially covered, and the polycrystalline silicon island 5 is partially covered in the entire P-TFT region. Then, N + ion implantation is performed on the polycrystalline silicon island 5 to form an N / TFT S / D region 8. Then, the second photoresist pattern 7 is peeled off, and a gate metal layer 9 is deposited. As shown in FIG. E ', the photolithography | worming process is performed again, and a third photoresist pattern 10 (using the third Mask), the gate metal layer 9 is patterned to form gate metal 9 of N-TFT and P-TFT, as shown in FIG. 1F. After that, the gate metal 9 is directly used as a mask to perform the N-ion implantation step to form the LDD structure 11 of the N-TFT. Then, as shown in FIG. 1G, a fourth photoresist pattern is formed (using a fourth photomask) to cover the entire N-TFT region, and a P + ion implantation step is performed on the P-TFT region to form P -S / D region 14 of the TFT. So far,

578309 五、發明說明（4) N-TFT和P-TFT之主亞^士士塞。1 , 丄〜王要結構已大致完成接下來玻璃基 1 2和該 (圖未一介層示。接該金屬示，使極5 1，素區域 ’剝除該第四光阻圖案1 3，並沉積一介電層1 2於該板1上’並覆蓋住該閘極金屬9，，然後對該介電層閑極絕緣層6進行微影蝕刻製程，藉由一光阻圖案顯不’使用第五道光罩），形成N-TFT和p —TFT的第，50 ’以裸露出N-TFT和P-TFT的S/D，如圖一Η所著、積一金屬層並填充該第一介層洞50，然後對層進二j影蝕刻製程，藉由一光阻圖案（圖未顯，第六=光罩），形成N-TFT和P-TFT的S/D金屬電 ^為貝料線（data Hne )，與該LCD面板上的像和^面板外部的電路作連接，如圖一 I所示。製程，藉由一光阻圖案（圖未層用52第進Λ微^;刻578309 V. Description of the invention (4) Asia Taxi, the master of N-TFT and P-TFT. 1, 丄 ~ Wang Yao's structure has been roughly completed. Next, the glass substrate 12 and the substrate are not shown in the figure. Then connect the metal, make the electrode 5 1, the prime region 'strip the fourth photoresist pattern 1 3, and A dielectric layer 12 is deposited on the plate 1 and covers the gate metal 9, and then a lithographic etching process is performed on the dielectric layer insulating layer 6, and a photoresist pattern is used. Fifth photomask), forming the N-TFT and p-TFT, 50 'to expose the S / D of the N-TFT and P-TFT, as shown in Figure 1, accumulate a metal layer and fill the first The interlayer hole 50 is then subjected to an etching process of the layer. A photoresist pattern (not shown, sixth = photomask) is used to form N-TFT and P-TFT S / D metal electrodes. The data line (data Hne) is connected to the image on the LCD panel and the circuit outside the panel, as shown in FIG. Process, by a photoresist pattern

金屬電極”。㈣，沉積銦二稞露出部份的S/D 第二介層洞53，然後對該氧化銦錫屉‘ 3〇 )並填充該藉由-光阻圖f (圖未顯示，使影姓刻製程， I TO連接電極54，可與該LCD面板外邻的=光罩），形成 - K所示。卜。P的電路作連接，如圖另外，請參見圖二A至圖二D，該笤闯# > 4圖式係為習知技術二有 578309 、發明說明（5) 自我對準的頂部閘極（top gate ) LTPS CMOS製程異於 ”知技術一之步驟流程示意圖。在習知技術二中，首先以相，於前述岡—A至圖一c的步驟形成欲作為N-TFT和P-TFT ^為夕晶矽島狀物（P〇 1 y i s 1 and ) 5 ;接著沉積閘極絕緣 ^後，如圖二A所示，沉積一閘極金屬層1 9於該閘極絕緣曰6上，再進行微影鍅刻製程，藉由一第二光阻圖案1 7、 (使用第二道光罩），將在該閘極金屬層1 9圖案化，以形成1^—TFT的閘極金屬19,和P-TFT的閘極金屬罩19” ，並剝‘ 該第二光阻圖案1 7，如圖二B所示，其中該閘極金屬罩i 9t 將在整個P-TFT區域之該多晶矽島狀物5的部份完全罩住。之後，直接以該閘極金屬1 9,和該閘極金屬罩丨9，，作為罩幕，進行N+離子植入步驟，形成N-TFT之S/D區域18。接著，進行P-TFT的P+離子植入步驟，如圖二c所示，形成一第二光阻圖案20 (使用第三道光罩）於該閘極金屬19，和該閘極金屬罩19”上，其中該第三光阻圖案2〇將在p —Tft 之閘極金屬1 9 ’區域之多晶矽島狀物5部份以及在整個 N - T F T區域之多晶石夕島狀物5部份罩住，並接著將未被第一光阻圖案20遮蓋住的該閘極金屬罩19”部份蝕刻掉，而带一成P-TFT之閘極金屬19，，然後對該多晶矽島狀物5進行^ 離子植入而形成P-TFT之S/D區域24。之後，剝除該第三光阻圖案2 0，如圖二D所示。此習知技術二在進行第三道光Metal electrode ". Alas, deposit the exposed S / D second interlayer hole 53 of the indium difluoride, and then fill the indium tin oxide drawer '30) and fill the pass-resistance pattern f (not shown in the figure, In the process of engraving the film name, the ITO connection electrode 54 can be connected to the outer edge of the LCD panel = photomask) to form -K. B. The circuit of P is connected as shown in the figure. Please refer to Figure 2A to Figure 2. Second, the 笤 ## diagram is a conventional technique. There are 578309, invention description (5) self-aligned top gate LTPS CMOS process is different from the "first technique" process flow diagram. . In the conventional technique two, first, the phase to be formed as the N-TFT and the P-TFT in the steps of Gang-A to FIG. 1c ^ is a Si-crystalline silicon island (P〇1 yis 1 and) 5; After depositing the gate insulation, as shown in FIG. 2A, a gate metal layer 19 is deposited on the gate insulation layer 6 and then a lithography process is performed to pass a second photoresist pattern 1 7 (Using a second mask), patterning the gate metal layer 19 to form a gate metal 19 of the 1-TFT, and a gate metal cover 19 "of the P-TFT, and peeling the first Two photoresist patterns 17, as shown in FIG. 2B, in which the gate metal cover i 9t will completely cover the part of the polycrystalline silicon island 5 in the entire P-TFT region. Then, the gate is directly used. The metal 19 and the gate metal cover 9 are used as a mask to perform the N + ion implantation step to form the S / D region 18 of the N-TFT. Next, the P + TFT P + ion implantation step is performed, such as As shown in FIG. 2c, a second photoresist pattern 20 (using a third photomask) is formed on the gate metal 19 and the gate metal cover 19 ", wherein the third photoresist pattern 20 will be at p —Tft gate metal The polycrystalline silicon island 5 part in the 19 'region and the polycrystalline silicon island part 5 in the entire N-TFT region are covered, and then the gate electrode not covered by the first photoresist pattern 20 is covered. The metal cover 19 "is partially etched away, and a gate metal 19 is formed into the P-TFT, and then the polycrystalline silicon island 5 is ion-implanted to form the S / D region 24 of the P-TFT. After that, The third photoresist pattern 20 is stripped, as shown in FIG. 2D. This conventional technique 2 is performing a third light

578309 五、發明說明（6) 〜罩後，即已完成N-TFT和P-TFT之主要結構。接下來，以相同於前述圖一 Η至圖一 κ的步驟，使用四道光罩來形成N-TFT和P-TFT的S/D金屬電極51和ΙΤ0連接電極 54 ° 在習知技術二中，雖然總共僅只使用七道光罩，來製作出 CMOS TFT元件，但所製作的N —TFT並不具有LDD結構。發明内容：本發明之主要目的，即是在提供一種低溫多晶矽薄膜電晶體的CMOS製程改良方法，可減少!^以CM〇s製程所需使用的光罩數目’並同時製作具有LDD結構的N —M〇s電路設計。本發明係揭示一種低溫多晶矽薄膜電晶體的“㈧製作方法。首先，在一絕緣基板上，形成欲作為一N — TFT和一 P-TFT的多晶矽島狀物（p〇ly island )，然後依序沉積一閘極絕緣層和一閘極金屬層於該絕緣基板上；之後，圖案化該閘極金屬層，以形成該N — TFT的閘極金屬和該p_TFT的閘極金屬罩，其中，該閘極金屬罩將在整個該區域之該多晶矽島狀物的部份完全罩住。接著，以該N — TFT的閘極金屬和該閘極金屬罩作為罩|，對該多晶矽島狀物進行N-離子植入步驟，形成該^71^之N—區域；然後形成一578309 V. Description of the invention (6) ~ After the mask, the main structures of N-TFT and P-TFT have been completed. Next, using the same steps as in the foregoing FIG. 1 to FIG. 1 κ, four photomasks are used to form the S / D metal electrodes 51 and ITO connection electrodes 54 of the N-TFT and P-TFT. In the conventional technology 2, Although only a total of seven photomasks are used to make a CMOS TFT element, the N-TFT produced does not have an LDD structure. Summary of the invention: The main purpose of the present invention is to provide a method for improving the CMOS process of a low-temperature polycrystalline silicon thin film transistor, which can reduce the number of photomasks used in the CMOS process and simultaneously produce N with an LDD structure. —Mos circuit design. The invention discloses a method for fabricating a low-temperature polycrystalline silicon thin film transistor. First, a polycrystalline silicon island (Nu-TFT and P-TFT) is formed on an insulating substrate. A gate insulating layer and a gate metal layer are sequentially deposited on the insulating substrate; thereafter, the gate metal layer is patterned to form the gate metal of the N-TFT and the gate metal cover of the p_TFT, wherein, The gate metal cover completely covers the portion of the polycrystalline silicon island in the entire area. Next, the gate metal of the N-TFT and the gate metal cover are used as the cover | A N-ion implantation step is performed to form the N-region of ^ 71 ^; and then a

第10頁 578309 五、發明說明（7) 光阻圖案於該N-TFT的閘極金屬和該P-TFT的閘極金屬罩上，其中一部份光阻圖案定義出該p-TFT之閘極金屬，而該光阻圖案之另一部份罩覆住該N — TFT之閘極金屬以及鄰接的部份閘極絕緣層表面，以定義出該之LDD結構；接著對該多晶矽島狀物進行N+離子植入，形成該n-TFT之 S/D區域，並蝕刻未被該光阻圖案遮蓋住的該閘極金屬罩部份’形成該P - T F T之閘極金屬。接下來，以該光阻圖案和該P-TFT之閘極金屬作為罩幕，對該多晶矽島狀物進行 P+離子植入，形成該Ρ-TFT之S/D區域，然後剝除該光阻圖案；之後形成該N-TFT和該P-TFT的S/D金屬電極。在上述的製作方法中，藉由在形成該光阻圖案於該N-tft 的閉極金屬和該P-TFT的閘極金屬罩上的步驟時，使形成在該N-TFT的閘極金屬上之光阻圖案的位置與該^71^的閘極金屬相對稱或不對稱，可形成對稱型或不對稱的n_tft 之S / D區域。Page 10 578309 V. Description of the invention (7) The photoresist pattern is on the gate metal of the N-TFT and the gate metal cover of the P-TFT, and a part of the photoresist pattern defines the gate of the p-TFT Metal, and another part of the photoresist pattern covers the gate metal of the N-TFT and the surface of the adjacent gate insulating layer to define the LDD structure; then the polycrystalline silicon island N + ion implantation is performed to form the S / D region of the n-TFT, and the gate metal cover portion that is not covered by the photoresist pattern is etched to form the gate metal of the P-TFT. Next, using the photoresist pattern and the gate metal of the P-TFT as a mask, P + ion implantation is performed on the polycrystalline silicon island to form the S / D region of the P-TFT, and then the photoresist is removed Pattern; S / D metal electrodes of the N-TFT and the P-TFT are then formed. In the above manufacturing method, the step of forming the photoresist pattern on the closed metal of the N-tft and the gate metal cover of the P-TFT is performed by forming the gate metal of the N-TFT. The position of the upper photoresist pattern is symmetrical or asymmetric with the gate metal of ^ 71 ^, which can form a symmetrical or asymmetrical n / tft S / D region.

再者，本發明另揭示一種藉由蝕刻方法來定義Ν — τρ 結構的LTPS CM0S製作方法。首先，形成欲作為_n —丁^ 一P —TFT的多晶石夕島狀物（p〇ly island)在一絕緣, 士 ’然後依序沉積一閘極絕緣層和一閘極金屬層於二_ 土板上。之後，圖案化該閘極金屬層、、、、Furthermore, the present invention further discloses a manufacturing method of an LTPS CMOS that defines an N-τρ structure by an etching method. First, polycrystalline islands (poly islands) to be used as _n —ding ^ a P —TFT are formed on an insulator, and then a gate insulating layer and a gate metal layer are sequentially deposited on Second _ soil. After that, the gate metal layer is patterned.

^ t.N-TFT , ：'TFT 金屬罩將在整個該"FT區域之該多晶石夕島狀：的；：^ t.N-TFT,: 'The TFT metal cover will be in the polycrystalline island state of the " FT region ::;

第11頁 578309Page 11 578309

全罩住；接著，以該P-TFT的閘極金屬知罩作為罩幕，對該多晶石夕島狀物進=離亥/ -閉極金屬Full mask; Next, the gate metal mask of the P-TFT is used as a curtain, and the polycrystalline stone island is charged into the polycrystalline silicon / closed metal.

的閉極金屬和該閉極金屬罩上1 =圖案於該P-TFT P-TFT區域以及該N —TFT之閘極金屬^ “阻圖案將整個該 ^ 1屬和結構區域罩你· 接者，蝕刻未被該光阻圖案遮蓋住， ^ ^N-TFT ^ ^ ^ Λ Λ" ^ ^ ^ ^ ^ #n+^ ^ ^^n；tf^t is;D^# v ^ ^ 1 ύ / U區域。之德，以古女光^圖案作為罩幕，對㈣二間極金屬罩的侧。〆 w，進行姓刻㈣，使該第二閑極金屬罩的二，：Λ成該N_m之閑極金屬，同時定義出該"FT的、，、〇構區域。然後剝除該光阻圖案，以該n_tft之閘極金屬作為罩I ’對該多晶碎島狀物進行N—離子植人，形成該 N TFT之LDD結構，再形成该N-TFT和該p-TFT的S/D金屬電極0 實施方式：請參見圖三A至圖三G，該等圖式係為本發明之低溫多晶石夕 (LTPS )薄膜電晶體的CMOS製作方法的第一實施態樣異於習知技術之步驟流程示意圖。首先，同樣地，以相同於前述圖一A至圖一◦的步驟，形成欲作為N-TFT和P-TFT的該多晶矽島狀物（p〇ly island) ^78309On the closed metal and the closed metal cover 1 = pattern on the P-TFT P-TFT area and the gate metal of the N-TFT ^ "The resistance pattern covers the entire ^ 1 generature and structure area. , The etching is not covered by the photoresist pattern, ^ ^ N-TFT ^ ^ ^ Λ Λ " ^ ^ ^ ^ # n + ^ ^ ^^ n; tf ^ t is; D ^ # v ^ ^ 1 ύ / U Area, virtue, with the ancient female light ^ pattern as the screen, facing the side of the metal shield of the two poles. 〆w, engraving the surname, so that the second idler metal shield of two: Λ into the N_m of Idle metal, at the same time define the ",", "0" structure region of the "FT." Then strip the photoresist pattern and use the n_tft gate metal as a cover I 'to perform N-ion on the polycrystalline island Planting, forming the LDD structure of the N TFT, and then forming the S / D metal electrode of the N-TFT and the p-TFT. Embodiments: Please refer to FIG. 3A to FIG. 3G, which are drawings of the present invention. The first embodiment of the CMOS fabrication method of a low temperature polycrystalline stone (LTPS) thin-film transistor is different from the schematic flowchart of the conventional technology. First, the steps are the same as those in FIG. 1A to FIG. 1 ,form Polycrystalline silicon island to be used as N-TFT and P-TFT ^ 78309

並接著沉積該閘極絕緣層6。芦6^圖三A所示’沉積一閉極金屬層29於該閘極絕緣 7使々再進行微影蝕刻製程，藉由一第二光阻圖案27 成Ν-τΐτ第二道光罩），將在該閘極金屬層29圖案化，以形 — T-的閘極金屬29，和p_TFT的閘極金屬罩29” ，並剝 Μ ” It第一光阻圖案2 7，如圖三B所示，其中該閘極金屬罩住：在整個P — TFT區域之該多晶矽島狀物5的部份完全罩 ^ ’圖二B’係為圖三β的平面圖。之後，直接以該閘極金 —9和該閘極金屬罩29”作為罩幕，對該多晶矽島狀物進離子植入步驟，形成N-TFT之Ν-區域21，如圖三c所不〇然f ’進行N-TFT的N+離子植入步驟，如圖三D所示，形成一第二光阻圖案30 (使用第三道光罩）於該閘極金屬29，Then, the gate insulating layer 6 is deposited. Lu 6 ^ shown in Figure 3A 'deposit a closed metal layer 29 on the gate insulation 7 to make a photolithographic etching process, and then use a second photoresist pattern 27 to form a second mask of N-τΐτ), The gate metal layer 29 is patterned to form a gate metal 29 of T-, and a gate metal cover 29 "of p_TFT, and the first photoresist pattern 27 of M" It is peeled off, as shown in Figure 3B. As shown in the figure, the gate metal covers: a part of the polycrystalline silicon island 5 in the entire P-TFT region is completely covered. ^ 'Figure 2B' is a plan view of Figure 3 β. After that, the gate gold-9 and the gate metal cover 29 ″ are directly used as a mask, and an ion implantation step is performed on the polycrystalline silicon island to form an N-region 21 of the N-TFT, as shown in FIG. 3c. 〇 ran f 'N-TFT N + ion implantation step, as shown in Figure 3D, forming a second photoresist pattern 30 (using a third mask) on the gate metal 29,

和该閘極金屬罩29π上，其中該第三光阻圖案3〇將在p-TFT 之閘極金屬2 9 ’區域的該多晶矽島狀物5部份以及在ν-TFΤ 之閘極金屬2 9 ’和LDD結構區域的該多晶矽島狀物5部份罩住（此時，就將該LDD結構的長度精確地定義出），並接著對該多晶矽島狀物5進行Ν +離子植入，而同時形成ν-TFT 之S/D區域28和LDD結構21，，如圖三E所示。然後，將未被該第三光阻圖案3 0遮蓋住的該閘極金屬罩 29π部份蝕刻掉，而形成P-TFT之閘極金屬29，，如圖三F所And the gate metal cover 29π, wherein the third photoresist pattern 30 will be in the polysilicon island 5 part of the gate metal 2 9 'region of the p-TFT and the gate metal 2 in the ν-TFΤ 9 'and the LDD structure region of the polycrystalline silicon island 5 is partially covered (at this time, the length of the LDD structure is precisely defined), and then the polycrystalline silicon island 5 is subjected to N + ion implantation, The S / D region 28 and the LDD structure 21 of the ν-TFT are formed at the same time, as shown in FIG. 3E. Then, the gate metal cover 29π which is not covered by the third photoresist pattern 30 is partially etched away to form a gate metal 29 of the P-TFT, as shown in FIG. 3F.

第13頁 578309 五、發明說明（ίο) 示，接著，直接以該第三光阻圖案30和該閘極金屬29，作為罩幕，對該多晶矽島狀物5進行P+離子植入，以形成 P-TFT之S/D區域34，之後，剝除該第三光阻圖案3〇，如圖三G所示，圖三G，係為圖三G的平面圖。值得注意的是，在進行P+離子植入時，對於N-TFT之S/D區域28 (即N+區域）而言，是反摻雜（counter-doping)，因此，所使用之N + 劑量和p+劑量必須先經過適當調配，以便使~—TFT之N+區域在經P+離子植入步驟後，仍保持“摻雜類型和低阻值特Page 13 578309 V. Description of the Invention (（), and then, using the third photoresist pattern 30 and the gate metal 29 as a mask, P + ion implantation is performed on the polycrystalline silicon island 5 to form The S / D region 34 of the P-TFT is then stripped of the third photoresist pattern 30, as shown in FIG. 3G, and FIG. 3G is a plan view of FIG. 3G. It is worth noting that when performing P + ion implantation, the S / D region 28 (ie, the N + region) of the N-TFT is counter-doping. Therefore, the N + dose and The p + dose must be properly adjusted so that the N + region of the ~ -TFT will still maintain the "doping type and low resistance value characteristics" after the P + ion implantation step.

本發明之LTPS CMOS製程進行至此（使用了三道光罩）， N-TFT和P-TFT之主要結構亦已大致完成，接下來，就以4 同於前述圖一 Η至圖一 K的步驟，使用四道光罩來形成 N-TFT和P-TFT的S/D金屬電極51和ΙΤ0連接電極54。型的N-TFT之S/D區:L，T: :^/明転之第還二可實製施作態\不對稱So far, the LTPS CMOS process of the present invention has been carried out (three masks are used), and the main structures of the N-TFT and P-TFT have also been roughly completed. Next, the steps are the same as the steps in FIG. 1 to FIG. 1K. Four photomasks are used to form the S / D metal electrodes 51 and ITO connection electrodes 54 of the N-TFT and P-TFT. S / D area of N-TFT: L, T:: ^ / Mingji's second and second implementation state can be implemented asymmetrically

在第二實施態樣中，製作LTPS CM〇S的方法，大部份係如同前述本發明之第一實施態樣的步驟流程，但在進行 N - TFT的N+離子植入步驟時（即第三道光罩），使形成在 N TFT的閘極金屬29,上之一第三光阻圖案4〇的位置不對稱 =该閘極金屬2 9，，如圖四a所示，如此所定義形成之汲極區的LDD結構31較之於源極區的LDD結構31，的長度要來得In the second embodiment, most of the methods for manufacturing the LTPS CMOS are the same as the steps of the first embodiment of the present invention, but when the N + TFT N + ion implantation step is performed (ie, the first Three photomasks) to make the position of the third photoresist pattern 40 on the gate metal 29 of the N TFT asymmetric = the gate metal 29, as shown in FIG. The LDD structure 31 in the drain region is longer than the LDD structure 31 in the source region.

第14頁 578309 五、發明說明（π) " 長；換言之，N-TFT之S/D區域38就呈現出不對稱，如圖四 B所示，圖四B’係為圖四B的平面圖。此外，請參見圖五A至圖五G，其等係為本發明之低溫多晶矽（LTPS )薄膜電晶體的CMOS製作方法的第三實施態樣= 於習知技術之步驟流程示意圖。 ^ 同樣地，以相同於前述圖一A至圖一C的步驟，來形成欲作為N-TFT和P-TFT的該多晶矽島狀物（p〇ly isiand ) 5，並接著沉積該閘極絕緣層6。然後，如圖五A所示，沉積一閘極金屬層39於該閘極絕緣層6上’再進行微影姓刻製程，藉由一第二光阻圖案3 7 (使用第二道光罩），將在該閘極金屬層39圖案化，以形成P-TFT的閘極金屬39,和N-TFT的第一閘極金屬罩39”，並剝除该第一光阻圖案3 7，如圖五B所示，其中該閘極金屬罩39π將在整個N-TFT區域之該多晶矽島狀物5的部份完全罩住。之後，直接以該閘極金屬39，和該第一閘極金屬罩 3 9作為罩幕’對該多晶石夕島狀物進行ρ +離子植入步驟，形成P-TFT之S/D區域44，如圖五C所示。然後，如圖五D所示，形成一第三光阻圖案4 5 (使用第三道光罩）於該閘極金屬3 9，和該第一閘極金屬罩3 9π上，其中ό亥第二光阻圖案45將在整個p-TFT區域的該多晶石夕島狀Page 14 578309 5. Description of the invention (π) "Long; In other words, the S / D region 38 of the N-TFT appears asymmetry, as shown in Figure 4B, and Figure 4B 'is a plan view of Figure 4B . In addition, please refer to FIG. 5A to FIG. 5G, which are the third embodiment of the CMOS manufacturing method of the low temperature polycrystalline silicon (LTPS) thin film transistor according to the present invention. ^ Similarly, the same polysilicon islands 5 (P0ly isiand) 5 to be used as N-TFT and P-TFT are formed by the same steps as in FIG. 1A to FIG. 1C, and the gate insulation is then deposited. Layer 6. Then, as shown in FIG. 5A, a gate metal layer 39 is deposited on the gate insulating layer 6 ', and then a photolithography process is performed, and a second photoresist pattern 37 is used (a second photomask is used). , Patterning the gate metal layer 39 to form the gate metal 39 of the P-TFT, and the first gate metal cover 39 ″ of the N-TFT, and stripping the first photoresist pattern 37, such as As shown in FIG. 5B, the gate metal cover 39π will completely cover the part of the polycrystalline silicon island 5 in the entire N-TFT region. Then, the gate metal 39 and the first gate are directly The metal cover 39 is used as a cover screen to perform a p + ion implantation step on the polycrystalline stone island to form the S / D region 44 of the P-TFT, as shown in FIG. 5C. Then, as shown in FIG. 5D As shown, a third photoresist pattern 4 5 (using a third mask) is formed on the gate metal 39 and the first gate metal mask 3 9π, wherein the second photoresist pattern 45 will be The polycrystalline island in the p-TFT region

第15頁 578309 五、發明說明（12) 物5部份以及在N_TFT之閘極金屬39，和LDD結構區域的該多晶f島狀物5部份罩住；然後，將未被該第三光阻圖案45 遮盍住的該第一閘極金屬罩39"部份蝕刻掉，而形成n_tft 之第二閘極金屬罩39，，，，其中該第二閘極金屬罩39，，，將 N-TFT之LDD結構區域罩住，並接著對該多晶矽島狀物5進行N+離子植入，而形成N_TFTiS/D區域48，如圖五£所示〇接下來，以該第三光阻圖案45作為罩幕，使用乾敍刻或濕蝕刻技術，對該第二閘極金屬罩39，，，的側壁（side waU )進行蝕刻程序，使該第二閘極金屬罩的該侧壁產生回縮，而形成N-TFT之閘極金屬39，，同時亦定義出在該多晶石夕島狀物5之N-TFT的LDD結構區域，如圖五ρ所示。之後，剝除S亥第二光阻圖案45，以N-TFT和P-TFT之閘極金屬39，為罩幕’對該多晶矽島狀物5進行N-離子植入，以形成 N-TFT之LDD結構41，如圖五G所示。本發明之第三實施態樣的LTPS CMOS製程進行至此（亦僅使用了三道光罩）’N-TFT和P-TFT之主要結構已大致完成。同樣地，以相同於前述圖一Η至圖一κ的步驟，使用四道光罩來形成N-TFT和P-TFT的S/D金屬電極51和ΙΤ〇連接電極5 4 〇與習知技術一和二相互比較可知，利用本發明之製作方 578309 五、發明說明（13) 法’可減少習知技術一之LTPS CM〇s製程數目，並製作出習知技術二所缺乏之具有光罩 N-TFT。因此，本發明之LTps CM〇s製作方法可^ ,丨、、使用數目而使成本降低並提高產能，而作、 Ϊ = : &可同時提高驅動電路的可靠度以及降低畫素的漏電&，而使良率提昇。一 =亡所述僅係藉由較佳實施例詳細說明本發明，而非限制作此au 耗㈤’而且熟知此類技藝人士皆能明瞭，適當而 =微的改變及調整，仍將不失本發明之要義所在，亦不脫離本發明之精神和範圍。Page 15 578309 V. Description of the invention (12) Part 5 and the gate metal 39 in the N_TFT, and the polycrystalline f island 5 part in the LDD structure area; then, it will not be covered by the third The first gate metal cover 39 covered by the photoresist pattern 45 is partially etched away to form an n_tft second gate metal cover 39 ′, where the second gate metal cover 39 ′ is The LDD structure area of the N-TFT is covered, and then N + ion implantation is performed on the polycrystalline silicon island 5 to form an N_TFTiS / D area 48, as shown in FIG. 5. Next, the third photoresist pattern is used. 45 is used as a cover screen, and an etching process is performed on the side wall (side waU) of the second gate metal cover 39, using dry engraving or wet etching technology to make the side wall of the second gate metal cover 39,. Shrink to form the gate metal 39 of the N-TFT, and also define the LDD structure region of the N-TFT in the polycrystalline stone island 5 as shown in FIG. After that, the second photoresist pattern 45 is peeled off, and N-ion implantation is performed on the polycrystalline silicon island 5 with the gate metal 39 of the N-TFT and P-TFT as a mask to form an N-TFT. The LDD structure 41 is shown in Fig. 5G. The third embodiment of the LTPS CMOS process of the present invention has been carried out (only three photomasks are used). The main structures of the N-TFT and P-TFT have been substantially completed. Similarly, in the same steps as in the foregoing FIG. 1 to FIG. 1 κ, four photomasks are used to form the S / D metal electrodes 51 and ITO connection electrodes 5 4 〇 of the N-TFT and P-TFT, and the conventional technique 1. Compared with the two, it can be seen that using the producer 578309 of the present invention 5. The invention description (13) method can reduce the number of LTPS CM0s processes of the conventional technology 1, and make a mask N- TFT. Therefore, the manufacturing method of the LTps CM0s of the present invention can reduce the cost and increase the production capacity by using the number of operations, and the operation of 提高 =: & can simultaneously improve the reliability of the driving circuit and reduce the leakage of pixels & While improving yield. One = the description is only a detailed description of the present invention through a preferred embodiment, and is not limited to the consumption of this au ', and those skilled in the art will understand, appropriate and = slight changes and adjustments will still be made The gist of the present invention does not depart from the spirit and scope of the present invention.

第17頁 578309Page 17 578309

圖式簡單說明藉由以不詳細之描述結合所附圖式，當可明瞭上述内容及本發明之諸多優點，其中：孜術圖一 A至圖一K，係為習知技術一有關自我對準的頂 (top gate ) LTPS CMOS製程（周邊驅動電路）之步驟^宁程不意圖，圖二A至圖二D，係為習知技術二有關自我對準的頂部問極 LTPS CMOS製程異於習知技術一之步驟流程示意圖；甲The drawings are simply explained. By combining the drawings with non-descriptive descriptions, the above-mentioned content and many advantages of the present invention can be understood, among which: Figures A through K are the conventional techniques-related self-alignment. The steps of the quasi-top gate LTPS CMOS process (peripheral driving circuit) are not intended. Figures 2A to 2D are the conventional self-aligned top interrogation LTPS CMOS process. Schematic diagram of the steps of the conventional technology one;

圖三A至圖三G，係為本發明之低温多晶矽（ltps )薄膜電晶體的CMOS製作方法的第一實施態樣異於習知技術之步驟流程示意圖；圖三B’ ，係為圖三B的平面圖；圖三G’ ，係為圖三G的平面圖；圖四A至圖四B ’係為本發明之低溫多晶矽（LTps )薄膜電晶體的CMOS製作方法的第二實施態樣異於第一實施態樣之步驟流程示意圖；圖四B係為圖四B的平面圖；以及圖五A至圖五G，係為本發明之低溫多晶矽（[TPS )薄膜電FIG. 3A to FIG. 3G are schematic diagrams of steps in a first embodiment of a CMOS manufacturing method of a low-temperature polycrystalline silicon (ltps) thin film transistor according to the present invention, which is different from the conventional technique; FIG. 3B ′ is FIG. 3 A plan view of B; FIG. 3G ′ is a plan view of FIG. 3G; FIGS. 4A to 4B ′ are a second embodiment of the CMOS manufacturing method of the low temperature polycrystalline silicon (LTps) thin film transistor of the present invention, which is different from the second embodiment Schematic diagram of the steps of the first embodiment; Figure 4B is a plan view of Figure 4B; and Figures 5A to 5G are the low temperature polycrystalline silicon ([TPS) thin film electrodes of the present invention.

晶體的CMOS製作方法的第三實施態樣異於習知技術之步驟流程示意圖。元件圖號說明：The third embodiment of the CMOS fabrication method of the crystal is different from the steps in the conventional technology. Component drawing number description:

第18頁 578309 圖式簡單說明非晶矽膜層3 第一光阻圖案4 閘極絕緣層6 S/D 區域8, 14, 18，閘極金屬層9， 1 9，第三光阻圖案10, 20, 閘極金屬9’， 19’， LDD 結構 11，21’，41 介電層1 2 S/D金屬電極51 第二介層洞5 3 閘極金屬罩19”， 29 >及極區的L D D結構3 1 第一閘極金屬罩39π 多晶石夕膜層3 ’ 多晶矽島狀物5 第二光阻圖案7， 17, 34, 44, 48 第四光阻圖案1 3 第一介層洞5 0 保護層5 2 ΙΤΟ連接電極54 Ν -區域2 1 源極區的LDD結構31’ 第二閘極金屬罩3 9 ’ ’ 27, 37 24， 28， 29，39 30, 40, 45 29，， 39，Page 578309 The diagram briefly explains the amorphous silicon film layer 3 first photoresist pattern 4 gate insulation layer 6 S / D region 8, 14, 18, gate metal layer 9, 1 9, third photoresist pattern 10 , 20, Gate metal 9 ', 19', LDD structure 11, 21 ', 41 Dielectric layer 1 2 S / D metal electrode 51 Second interlayer hole 5 3 Gate metal cover 19 ”, 29 > Area LDD structure 3 1 first gate metal cover 39π polycrystalline silicon film layer 3 'polycrystalline silicon island 5 second photoresist pattern 7, 17, 34, 44, 48 fourth photoresist pattern 1 3 first introduction Layer hole 5 0 Protective layer 5 2 ΙΤ Connection electrode 54 Ν-region 2 1 LDD structure of source region 31 ′ Second gate metal cover 3 9 ′ 27, 37 24, 28, 29, 39 30, 40, 45 29, 39,

第19頁Page 19

Claims

578309 六、申請專利範圍 1· 一種低溫多晶石夕（LTPS)薄膜電晶體的CM〇s製作方法，包括：形成欲作為一N-TFT和一P-TFT的多晶矽島狀物（p〇ly island)在一絕緣基板上；依序沉積一閘極絕緣層和一閘極金屬層於該絕緣基板上；圖案化該間極金屬層，以形成該N_TFT的閘極金屬和該 P/TFT的閑極金屬罩，其中，該閘極金屬罩係將位於整個该P-TFT區域之該多晶矽島狀物的部份完全罩住；以，N-TFT的閘極金屬和該卜^了的閘極金屬罩作為罩幕，對β多曰a0 ；^島狀物進行N—離子植入步驟，形成該\一川之 N-區域；形成一光阻圖案於該N-TFT的閘極金屬和該p —τί?Τ的閘極金屬罩上’其中該光阻圖案之一部份定義出該p-TFT之閘極金屬’而該光阻圖案之另一部份罩覆住該N-TFT之閘極金屬以及鄰接的部份閘極絕緣層表面，以定義出該N — τ J? τ之 LDD結構；對該多晶矽島狀物進行N+離子植入，形成該n —TFT之S/D區域；578309 6. Scope of patent application 1. A method for manufacturing CMOS of a low temperature polycrystalline silicon (LTPS) thin film transistor, including: forming a polycrystalline silicon island (poli) to be used as an N-TFT and a P-TFT island) on an insulating substrate; sequentially depositing a gate insulating layer and a gate metal layer on the insulating substrate; patterning the intermediate metal layer to form the gate metal of the N_TFT and the P / TFT The idler metal cover, wherein the gate metal cover completely covers the part of the polycrystalline silicon island located in the entire P-TFT region; the gate metal of the N-TFT and the gate An electrode metal cover is used as a cover, and an N-ion implantation step is performed on β islands to form the N-region of the I-gawa; a photoresist pattern is formed on the gate metal of the N-TFT and The p-τί? Τ gate metal cover 'wherein a part of the photoresist pattern defines the gate metal of the p-TFT' and another part of the photoresist pattern covers the N-TFT Gate metal and adjacent gate insulation layer surfaces to define the LDD structure of the N — τ J? Τ; the polycrystalline silicon N + ion implantation was performed to form the n -TFT the S / D regions;

第20頁六、申請專利範圍形成該以該光阻圖案和該P-TFT之閘極金矽島狀物進行P+離子植入，# 、 -、罩幕，對該多晶伹八，形成该P —TFT之S/D區域；剝除該光阻圖案；以及形成該N_TFT和該Ρ-TFT的S/D金屬電極。 2.如申請專利範圍第丨項所述之 N+劑量和P+劑量係先經過方法，其中所使用之區域在經卿子植入步；；=，以便使該N-TFT之N + 值特性。仍保持N +摻雜類型和低阻 3·如申請專利範圍第1項所光阻圖案於該N-TFT的閘極金属作法，其中在形成該時，使形成在該Ν-m的閑間極金屬罩上的步驟與該N-m的閑極金屬相;;金屬上之該光阻圖案的位置 S/D區域。鸯相對稱’以便形成對稱型的N-TFT之 578309 六、申請專利範圍時，使形成在該N-TFT的開極金屬上之該光阻圖案的位置不對稱於該N-TFT的閘極金屬以便形成不對稱型的N-TFT 之S/D區域。 5·如申請專利範圍第1頊所述之製作方法，在形成該N-TFT 和該P-TFT的S/D金屬電極之後’另包括形成ΙΤ0連接電極步驟。 6·如申請專利範圍第1項所述之製作方法，其中一緩衝層形成在該多晶矽島狀物與該絕緣基板之間。 7· —種低溫多晶矽（LTPS )薄膜電晶體的CMOS製作方法，包括：形成欲作為一N-TFT和一P-TFT的多晶矽島狀物（p〇ly island )在一絕緣基板上；依序沉積一閘極絕緣層和，閘極金屬層於該絕緣基板上；圖案化該閘極金屬層，以形成該P —TFT的閘極金屬和該 N-TFT的第一閘極金屬罩，其中5亥第一閘極金屬罩將位於整個該N-TFT區域之該多晶矽島狀物的部份完全罩住；以該P-TFT的閘極金屬和該第一閘極金屬罩作為罩幕，對Page 20 6. The scope of the patent application is to form the P + ion implantation using the photoresist pattern and the gate silicon island of the P-TFT, #,-, the screen, and the polycrystalline silicon to form the polycrystalline silicon. P —TFT's S / D region; stripping the photoresist pattern; and forming S / D metal electrodes of the N_TFT and the P-TFT. 2. The N + dose and P + dose as described in item 丨 of the patent application range are first passed through the method, where the area used is at the implantation step; and =, in order to make the N + TFT's N + value characteristics. N + doping type and low resistance are maintained 3. The photoresist pattern is applied to the gate metal of the N-TFT as described in item 1 of the scope of patent application. The step on the electrode metal cover is in phase with the Nm free-electrode metal; the position S / D area of the photoresist pattern on the metal.鸯 Symmetric 'so as to form a symmetrical N-TFT 578309 6. When applying for a patent, the position of the photoresist pattern formed on the open metal of the N-TFT is asymmetric to the gate of the N-TFT Metal in order to form the S / D region of the asymmetric N-TFT. 5. According to the manufacturing method described in claim 1 of the patent application scope, after forming the S / D metal electrodes of the N-TFT and the P-TFT, a step of forming an ITO connection electrode is further included. 6. The manufacturing method as described in item 1 of the scope of patent application, wherein a buffer layer is formed between the polycrystalline silicon island and the insulating substrate. 7. · A CMOS fabrication method for a low temperature polycrystalline silicon (LTPS) thin film transistor, including: forming a polycrystalline silicon island (Polily island) to be an N-TFT and a P-TFT on an insulating substrate; sequentially Depositing a gate insulating layer and a gate metal layer on the insulating substrate; patterning the gate metal layer to form a gate metal of the P-TFT and a first gate metal cover of the N-TFT, wherein The first gate metal cover completely covers the portion of the polycrystalline silicon island located in the entire N-TFT region; and the gate metal of the P-TFT and the first gate metal cover are used as the screen. Correct

第22頁 578309 六、申請專利範圍該多晶矽島狀物進行P+離子植入步驟，形成該P-TFT之S/D 區域；形成一光阻圖案於該P — T F T的閘極金屬和該N - T F T的閘極金屬罩上，其中該光阻圖案將整個該P-TFT區域以及該N-TFT 之閘極金屬和L D D結構區域罩住；蝕刻未被該光阻圖案遮蓋住的該第一閘極金屬罩部份，形成該N-TFT之第二閘極金屬罩；對該多晶矽島狀物進行N+離子植入，形成該N-TFT之S/D區域；以該光阻圖案作為罩幕，對該第二閘極金屬罩的側壁 (s i de wa 11 )進行蝕刻程序，使該第二閘極金屬罩的該側壁產生回縮，而形成該N-TFT之閘極金屬，同時定義出該N-TFT的LDD結構區域；剝除該光阻圖案；以該N-TFT之閘極金屬作為罩幕，對該多晶矽島狀物進行 N-離子植入，形成該N-TFT之LDD結構；以及形成該N-TFT和該P-TFT的S/D金屬電極。Page 22 578309 6. Application scope The polycrystalline silicon island is subjected to a P + ion implantation step to form the S / D region of the P-TFT; a photoresist pattern is formed on the gate metal of the P-TFT and the N- On the gate metal cover of the TFT, wherein the photoresist pattern covers the entire P-TFT region and the gate metal and LDD structure region of the N-TFT; etching the first gate not covered by the photoresist pattern The metal gate part forms the second gate metal cap of the N-TFT; N + ion implantation is performed on the polycrystalline silicon island to form the S / D region of the N-TFT; and the photoresist pattern is used as a mask , Performing an etching process on the side wall (si de wa 11) of the second gate metal cover, causing the side wall of the second gate metal cover to retract, thereby forming the gate metal of the N-TFT, and simultaneously defining The LDD structure region of the N-TFT; stripping the photoresist pattern; using the gate metal of the N-TFT as a mask, performing N-ion implantation on the polycrystalline silicon island to form the LDD structure of the N-TFT And forming an S / D metal electrode of the N-TFT and the P-TFT.

第23頁 578309Page 23 578309

六、申請專利範圍乾颠進行 8列n月專f範圍第7項所述之製作方法，其中使用二f ’對5亥第二閘極金屬罩的側壁（s i de wa 1 1 ) 餘刻程序。 9.如申請專利範圍第7項所述之製作方法，其中使用濕钱刻技術，對該第二閘極金屬罩的側壁（side wal 1 )進行蝕刻程序。 10·如申請專利範圍第7項所述之製作方法，在形成該 N-TFT和該P-TFT的S/D金屬電極之後，另包括形成IT〇連接電極步驟。6. The scope of the patent application is to carry out the manufacturing method described in item 7 of the 8-month n-f special range, in which two f's are used on the side wall of the second gate metal cover (si de wa 1 1). . 9. The manufacturing method according to item 7 of the scope of the patent application, wherein the side gate (side wal 1) of the second gate metal cover is etched by using a wet engraving technique. 10. According to the manufacturing method described in item 7 of the scope of patent application, after forming the S / D metal electrodes of the N-TFT and the P-TFT, a step of forming an IT0 connection electrode is further included.