WO2017113760A1 - 积分电路及电容感测电路 - Google Patents

积分电路及电容感测电路 Download PDF

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WO2017113760A1
WO2017113760A1 PCT/CN2016/090472 CN2016090472W WO2017113760A1 WO 2017113760 A1 WO2017113760 A1 WO 2017113760A1 CN 2016090472 W CN2016090472 W CN 2016090472W WO 2017113760 A1 WO2017113760 A1 WO 2017113760A1
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Prior art keywords
switch
coupled
input
capacitor
amplifier
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PCT/CN2016/090472
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English (en)
French (fr)
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文亚南
杨富强
梁颖思
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深圳市汇顶科技股份有限公司
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Publication of WO2017113760A1 publication Critical patent/WO2017113760A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/0418—Control or interface arrangements specially adapted for digitisers for error correction or compensation, e.g. based on parallax, calibration or alignment
    • G06F3/04182—Filtering of noise external to the device and not generated by digitiser components
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/005—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements using switched capacitors, e.g. dynamic amplifiers; using switched capacitors as resistors in differential amplifiers

Definitions

  • the present patent application is applicable to the field of touch technology, and particularly relates to an integrating circuit and a capacitance sensing circuit capable of effectively sensing a change in capacitance.
  • the operational interfaces of various electronic products have gradually become more humanized in recent years.
  • the user can directly operate on the screen with a finger or a stylus, input information/text/pattern, and save the trouble of using an input device such as a keyboard or a button.
  • the touch panel usually consists of an inductive panel and a display disposed behind the inductive panel. The electronic device judges the meaning of the touch according to the position touched by the user on the sensing panel and the picture presented by the display at the time, and performs the corresponding operation result.
  • Capacitive touch technology utilizes the amount of capacitance change of the capacitor to be tested in the circuit under test to interpret the touch event.
  • the existing capacitive touch technology can be divided into self-capacitance and mutual capacitance (Mutual).
  • -Capacitance the capacitive sensing circuit in the self-capacitive touch panel or the mutual capacitive touch panel converts the capacitance of the capacitor to be tested into an analog output signal, and converts the analog output signal into an analog to digital converter. The digital signal is interpreted by the back end capacitance judging circuit.
  • the capacitance change of the capacitance to be measured is relatively small, and the amount of signal change caused by the change of the capacitance of the analog output signal is correspondingly small.
  • the analog output signal may include a fixed signal and a variable signal, wherein the fluctuation signal is a signal variation caused by the capacitance change of the analog output signal, and the capacitance sensing circuit changes according to the analog output signal. The size of the signal is used to determine the amount of capacitance change of the capacitor to be tested. In other words, the varying signal has a critical impact on capacitive sensing.
  • FIG. 1 is a schematic diagram of a capacitance sensing circuit according to Embodiment 1 of the present invention.
  • FIG. 3 is a schematic diagram of the integration circuit of FIG. 1 according to Embodiment 1 of the present invention.
  • FIG. 4 is a schematic diagram of a capacitance sensing circuit according to Embodiment 2 of the present invention.
  • a technical problem to be solved by some embodiments of the present invention is to provide an integrating circuit for effectively sensing a change in capacitance.
  • an integration circuit including:
  • the amplifier contains:
  • An integrating capacitor coupled between the first input end and the output end
  • the discharge capacitor contains:
  • a first switch coupled between the first input end of the amplifier and the second end of the discharge capacitor
  • the second switch is coupled between the first end and the second end of the discharge capacitor.
  • the present invention further provides a capacitance sensing circuit for sensing a capacitance to be tested of the circuit to be tested, including:
  • a first analog signal converter for generating a first digital signal
  • a capacitance determining circuit coupled to the first analog signal converter, for determining a capacitance change of the capacitor to be tested according to the first digital signal
  • the first amplifier includes:
  • a first integrating capacitor coupled between the first input end and the output end of the first amplifier
  • the first discharge capacitor includes:
  • a first switch coupled between the first input end of the first amplifier and the second end of the discharge capacitor
  • the second switch is coupled between the first end and the second end of the first discharge capacitor.
  • the integrating circuit provided by some embodiments of the present invention uses a discharge capacitor and a switch connected to the discharge capacitor to limit the output signal between the maximum voltage and the minimum voltage, so that even after the integration circuit is performed for a long time, the total integrated voltage can be It is much larger than the dynamic range of the analog signal converter without causing the analog signal converter to enter saturation. Therefore, the integrating circuit of the present invention can reduce the dynamic range requirement of the analog signal converter, thereby reducing circuit complexity and production cost, and can effectively sense the change of the capacitance. For an analog signal converter with certain precision, some embodiments of the present invention can also improve the accuracy of the capacitance sensing circuit, thereby improving the signal to noise ratio (SNR) of the system. In addition, since the discharge capacitor can effectively reduce the maximum voltage of the integration, the integral capacitor in the integration circuit can use a relatively small capacitance, thereby reducing the circuit area.
  • SNR signal to noise ratio
  • FIG. 1 is a schematic diagram of a capacitance sensing circuit 10 according to an embodiment of the present invention.
  • the capacitance sensing circuit 10 applies a signal TX to the circuit under test 100 and receives a signal RX from the circuit under test 100.
  • the capacitance sensing circuit 10 senses the capacitance C UT to be tested of the circuit under test 100 according to the signal TX and the signal RX.
  • the capacitive sensing circuit 10 includes an integrating circuit 104, an analog signal converter 108, a capacitance determining circuit 102, and a mixer 106.
  • the mixer 106 is coupled between the circuit under test 100 and the integrating circuit 104, and includes a multiplier MP and a waveform generator 160.
  • the mixer 106 inputs an input signal V IN to the integrating circuit 104.
  • the integrating circuit 104 is based on the input signal.
  • V IN generates an output signal V OUT ;
  • the analog signal converter 108 is coupled to the integrating circuit 104 , and the analog signal converter 108 is used to convert the output signal V OUT into a digital signal V D ;
  • the capacitance determining circuit 102 is coupled to the analog signal converter 108, used to determine the capacitance change of the capacitor C UT to be tested according to the digital signal V D .
  • the integrating circuit 104 includes an amplifier Amp, an integrating capacitor C I , a discharge capacitor C F , a resistor R, a control signal generator 140, and switches SW1 and SW2.
  • the amplifier Amp includes a negative input terminal (ie, a first input terminal, marked with a "-" sign), a positive input terminal (ie, a second input terminal, marked with a "+” sign), and an output terminal.
  • the positive input of the amplifier Amp receives the reference voltage V REF and the output is used to output the output signal V OUT .
  • the resistor R is coupled to the negative input terminal of the amplifier Amp, and the other end receives the input signal V IN , and the resistor R is used to adjust the ratio between the input signal V IN and the output signal V OUT .
  • the integrating capacitor C I is coupled between the negative input terminal and the output terminal of the amplifier Amp.
  • the first end of the discharging capacitor C F is used to receive the voltage V S , and the second end is coupled to the switch SW1 , wherein the voltage V S is less than the reference. Voltage V REF .
  • the switch SW1 is coupled between the negative input terminal of the amplifier Amp and the second end of the discharge capacitor C F , and the switch SW2 is coupled between the first end and the second end of the discharge capacitor C F .
  • the switches SW1, SW2 are controlled by the control signal generator 140, that is, the control signal generator 140 generates control signals CTL1, CTL2 to control the conduction states of the switches SW1, SW2, respectively.
  • a first phase T 1 the control signal generator 140 generates control signal CTL1 the switch SW1 is turned off, the integrating circuit 104 at this time for continuously integrating the input signal V IN, i.e. the integrating capacitor C I is continuously accumulated charges, the output The signal V OUT also continuously drops. Further, in the first phase period T 1, the control signal generator 140 generates a control signal CTL2 switch SW2 is turned on, the discharge capacity C F influence by switch SW2 is turned on and is no stored charge. In the second phase T 2 , the control signal generator 140 generates the control signals CTL1, CTL2 to turn on the switch SW1 and the switch SW2 to open.
  • the charge accumulated in the integrating capacitor C I is discharged to the discharge capacitor C F , that is, the discharge capacitor C F is charged, and after the discharge capacitor C F is charged to saturation, the pair can continue to be The input signal V IN is integrated.
  • the output signal V OUT is instantaneously pulled up until the discharge capacitor C F Charging to saturation, wherein the output signal V OUT is momentarily pulled up by After the discharge capacitor C F is charged to saturation, the output signal V OUT continues to decrease continuously due to integration of the input signal V IN by the integrating circuit 104.
  • FIG. 2 is a waveform diagram of the output signal V OUT and the control signals CTL1 and CTL2 changing with time.
  • the switches SW1 and SW2 are turned on.
  • the switches SW1 and SW2 are turned off.
  • the integrating circuit 104 starts operating at time t 0 when the voltage of the output signal V OUT is the voltage V REF .
  • the control signal generator 140 controls the switches SW1, SW2 such that the integration circuit 104 enters the first phase T 1 for the first time.
  • the integration circuit 104 charges the discharge capacitor C F Clear, and continuously integrating circuit 104 for integrating the input signal V IN, continuously integrating capacitor C I to the accumulated charges, the output signal V OUT decreases continuously.
  • the control signal generator 140 controls the switches SW1, SW2 so that the integrating circuit 104 first enters the second phase T 2, in a second phase T 2, due to the charge accumulated in the integrating capacitor C I is released into the discharge
  • the capacitor C F causes the output signal V OUT to be pulled high until the discharge capacitor C F is charged to saturation (corresponding to time t 2 ).
  • control signal generator 140 can control switch SW1 to cause integration circuit 104 to enter first phase T1 a second time, during which integration circuit 104 continues to integrate input signal V IN and output signal V OUT continues to drop, In the process in which the integration circuit 104 integrates the input signal V IN , the control signal generator 140 can control the switch SW2 to clear the charge of the discharge capacitor C F .
  • the control signal generator 140 repeatedly controls the switch SW1 such that the integrating circuit 104 operates back and forth between the first phase T 1 and the second phase T 2 , and in each of the first phases T1, the control signal generator 140 controls the switch SW2
  • the signal value of the output signal V OUT is the voltage V t and within the operation time interval T OP (the operation time interval T OP is from time t 0 to time t The time interval between 3 )
  • the number of times the integration circuit 104 enters the second phase T 2 is N times, that is, the integration circuit 104 has a total of N times into the second phase T 2 in the operation time interval T OP .
  • the control signal generator 140 can periodically operate the integration circuit 104 back and forth between the first phase T 1 and the second phase T 2 according to the frequency signal.
  • the voltage V ini represents the amount of change in which the output signal V OUT falls due to integration by the integration circuit 104 from the start of operation to the first time into the second phase T 2 .
  • the variation range of the output signal V OUT falls between the maximum voltage Vmax and the minimum voltage Vmin, and the voltage amplitude difference between the maximum voltage Vmax and the minimum voltage Vmin for
  • the total integrated voltage V O of the integrating circuit 104 from time t 0 to time t 3 is (ie, the total integrated charge accumulated by the integrating capacitor C I from time t 0 to time t 3 is C I (V O - V REF )).
  • the capacitance sensing circuit 10 can perform the foregoing operation through the integrating circuit 104 at the first time to obtain the first total integrated voltage V O1 .
  • the capacitor sensing circuit 10 can additionally perform the foregoing operation through the integrating circuit 104 at the second time to obtain the second total integrated voltage V O2 .
  • the voltage V t1 and the voltage V t2 are respectively the voltage values of the output signal V OUT after the integration operation of the operation time interval T OP by the integration circuit 104 at the first time and the second time, and the number of times N 1 and the number of times N 2 are respectively an integration circuit.
  • 104 performs the number of times the integration circuit 104 enters the second phase T 2 after the integration operation of the operation time interval T OP at the first time and the second time.
  • the capacitance change of the capacitor C UT to be tested is related to the voltage difference V DIFF between the first total integrated voltage V O1 and the second total integrated voltage V O2 , and the voltage difference V DIFF is In other words, the change in capacitance of the capacitor C UT to be tested is only related to the number of times N 1 , the number of times N 2 , the voltage V t1 , and the voltage V t2 .
  • the voltage difference V DIFF It is only related to the voltage V t1 and the voltage V t2 , that is, the capacitance change of the capacitance C UT to be tested is only related to the voltage V t1 and the voltage V t2 .
  • the range of the voltage V t1 and the voltage V t2 falls between the maximum voltage Vmax and the minimum voltage Vmin.
  • the dynamic range of the analog signal converter 108 only needs to be at the maximum voltage Vmax and the minimum voltage Vmin. The requirement for the dynamic range of the analog signal converter 108 is reduced.
  • the present embodiment uses the integration circuit 104 to limit the output signal V OUT between the maximum voltage Vmax and the minimum voltage Vmin. Even after the integration circuit 104 performs the integration operation time interval T OP , the total integration voltage V O can be large.
  • the dynamic range of the analog signal converter 108 is not caused to cause the analog signal converter 108 to enter a saturated state.
  • this embodiment reduces the dynamic range requirements of the analog signal converter 108, thereby reducing circuit complexity and production costs.
  • this embodiment can also improve the accuracy of the capacitance sensing circuit and the signal-to-noise ratio of the system.
  • the integral capacitor C I in the integrating circuit 104 can use a relatively small capacitance, thereby reducing the circuit area.
  • control signal generator 140 is not limited to periodically operating the integration circuit 104 back and forth between the first phase T 1 and the second phase T 2 according to the frequency signal, and the control signal generator 140 may be based on the output signal V OUT .
  • the control signal generator 140 may be based on the output signal V OUT .
  • the control signal generator 140 generates a control signal CTL1, CTL2 the integrating circuit 104 enters the second phase T 2, in order to charge and discharge the capacitor C F pulled output signal V OUT .
  • FIG. 3 is a schematic diagram of an integration circuit 304 according to an embodiment of the present invention.
  • the integrating circuit 304 is similar to the integrating circuit 104, so the same components follow the same symbols.
  • the integration circuit 304 includes a switched capacitor module 302. One end of the switched capacitor module 302 is coupled to the negative input terminal of the amplifier Amp, and the other end is configured to receive the input signal V IN .
  • the switched capacitor module 302 includes a capacitor C S and a switch S1, S2, S3, and S4.
  • the switch S1 is coupled to the first end of the capacitor C S for receiving the input signal V IN
  • the switch S2 is coupled to the capacitor C S .
  • the switch S3 is coupled between the second end of the capacitor C S and the negative input of the amplifier Amp
  • the switch S4 is coupled between the second end of the capacitor C S and the ground.
  • the switches S1, S2, S3, S4 can be controlled by the frequency control signals ph1, ph2, wherein the frequency control signals ph1, ph2 are mutually orthogonal frequency control signals (ie, the times when the frequency control signals ph1, ph2 are high) do not overlap each other. ).
  • the frequency control signal ph1 can be used to control the on state of the switches S1, S3, and the frequency control signal ph2 can be used to control the on state of the switches S2, S4; in another embodiment, The frequency control signal ph1 can be used to control the conduction state of the switches S1, S4, and the frequency control signal ph2 can be used to control the conduction state of the switches S2, S3.
  • the switching capacitor module 302 is used to adjust the ratio between the input signal V IN and the output signal V OUT , and the conduction states of the switches S1, S2, S3, and S4 are controlled by the mutually orthogonal frequency control signals ph1 and ph2. It belongs to the scope of the invention.
  • FIG. 4 is a schematic diagram of a capacitance sensing circuit 40 according to an embodiment of the present invention.
  • the capacitive sensing circuit 40 is similar to the capacitive sensing circuit 10, so the same components follow the same symbols.
  • the capacitive sensing circuit 40 integrates the in-phase component of the signal RX using the integrating circuit 404_a; unlike the capacitive sensing circuit 10, the capacitive sensing circuit 40 utilizes the included in the mixer.
  • the phase rotator 462 and the multiplier MP2 of 406 extract the orthogonal component of the signal RX and integrate the orthogonal component of the signal RX by the integrating circuit 404_b.
  • the integrating circuits 404_a, 404_b are respectively coupled to the analog signal converters 408_a, 408_b, and the analog signal converters 408_a, 408_b are used to convert the output signals V OUT1 , V OUT2 generated by the integrating circuits 404_a, 404_b into digital signals V D1 , respectively V D2 , the capacitance judging circuit 102 can judge the capacitance change of the capacitor C UT to be tested according to the digital signals V D1 and V D2 , so that the capacitance interpretation is more accurate.
  • control signal generator 440 generates control signals CTL1, CTL2, CTL3, and CTL4 to respectively control the conduction states of the switches SW1, SW2, SW3, and SW4, and the control switch conduction mechanism can refer to the aforementioned related paragraphs, and is no longer Narration.
  • the integrating circuits 404_a, 404_b and the integrating circuit 104 have the same circuit architecture, and are not limited thereto. It is also within the scope of the present invention that the integrating circuit of the present embodiment can have the same circuit architecture as the integrating circuit 304 (i.e., replace the resistors R1, R2 in the integrating circuits 404_a, 404_b with the switched capacitor module 302).
  • the integrating circuit and the capacitive sensing circuit of some embodiments of the present invention use a discharge capacitor and a switch coupled to the discharge capacitor to limit the output signal between the maximum voltage and the minimum voltage, so that even if the integration circuit is After a long time integration, the total integrated voltage can be much larger than the dynamic range of the analog signal converter without causing the analog signal converter to enter saturation. Therefore, the integrating circuit and the capacitive sensing circuit of some embodiments of the present invention can reduce the dynamic range requirements of the analog signal converter, thereby reducing circuit complexity and production cost. For an analog signal converter with a certain precision, some embodiments of the present invention can also improve the accuracy of the capacitance sensing circuit and the signal to noise ratio of the system. In addition, since the discharge capacitor can effectively reduce the maximum voltage of the integration, the integral capacitor in the integration circuit can use a relatively small capacitance, thereby reducing the circuit area.

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Abstract

一种积分电路及电容感测电路，适用于触控技术领域，包含有放大器(Amp)、积分电容(C I)、放电电容(C F)、第一开关(SW1)和第二开关(SW2)；放大器(Amp)包含有第一输入端、第二输入端，以及输出端，用来输出一输出信号(V OUT)；积分电容(C I)耦接于第一输入端与输出端之间；放电电容(C F)包含有第一端和第二端，第一端用来接收第一电压(V S)；第一开关(SW1)，耦接于放大器(Amp)的第一输入端与放电电容(C F)的第二端之间；以及第二开关(SW2)，耦接于放电电容(C F)的第一端与该第二端之间，该积分电路能有效感测电容的变化。

Description

积分电路及电容感测电路 技术领域
本专利申请适用于触控技术领域，尤其涉及一种能有效感测电容变化的积分电路及电容感测电路。
背景技术
随着科技日益进步，近年来各种电子产品的操作接口逐渐人性化。举例而言，透过触控面板，使用者可直接以手指或触控笔在屏幕上操作、输入信息/文字/图样，省去使用键盘或按键等输入装置的麻烦。实际上，触控面板通常是由感应面板和设置于感应面板后方的显示器组成。电子装置是根据使用者在感应面板上所触碰的位置，以及当时显示器所呈现的画面，来判断该次触碰的意涵，并执行相对应的操作结果。
电容式触控技术利用感测待测电路中待测电容的电容变化量来判读触碰事件，现有的电容式触控技术可分为自容式(Self-Capacitance)和互容式(Mutual-Capacitance)两种，自容式触控面板或互容式触控面板中的电容感测电路可将待测电容的电容转换成模拟输出信号，并利用模拟数字转换器将模拟输出信号转换成数字信号，以供后端电容判断电路进行判读。然而，无论是自容式触控面板或是互容式触控面板，其待测电容的电容变化量都相当微小，而使得该模拟输出信号受到电容变化而产生的信号变化量也相应地微小。从另一角度来说，该模拟输出信号可包含有固定信号和变动信号，其中该变动信号为该模拟输出信号受到电容变化而产生的信号变化量，电容感测电路根据该模拟输出信号中变动信号的大小来判断待测电容的电容变化量。换句话说，变动信号对电容感测具有关键性影响。为了正确地解析待测电容的电容变化，现有 技术利用具有大动态范围(Dynamic Range)以及高分辨率的模拟数字转换器来解析该模拟输出信号，造成电路复杂度以及生产成本增加；另一方面，模拟数字转换器的大动态范围及高分辨率大多耗费在解析该模拟输出信号的固定信号部份，而对于对电容感测产生关键影响的变动信号反而无法有效地解析。因此，现有技术实有改善的必要。
附图说明
图1为本发明实施例一提供的电容感测电路的示意图；
图2为本发明实施例提供的多个波形图；
图3为本发明实施例一提供的图1中的积分电路的示意图；
图4为本发明实施例二提供的电容感测电路的示意图。
发明内容
本发明部分实施例所要解决的技术问题在于提供一种积分电路，以有效感测电容的变化。
为了解决上述技术问题，本发明一个实施例提供了一种积分电路，包括：
放大器，包含有：
第一输入端；
第二输入端；以及
输出端，用来输出一输出信号；
积分电容，耦接于所述第一输入端与所述输出端之间；
放电电容，包含有：
第一端，用来接收第一电压；以及
第二端；
第一开关，耦接于所述放大器的第一输入端与所述放电电容的第二端之间；以及
第二开关，耦接于所述放电电容的第一端与第二端之间。
为了解决上述技术问题，本发明还提供了电容感测电路，用来感测待测电路的待测电容，包括：
第一模拟信号转换器，用来产生第一数字信号；
电容判断电路，耦接于所述第一模拟信号转换器，用来根据所述第一数字信号，判断所述待测电容的电容变化；以及
第一积分电路，耦接于所述待测电路与所述第一模拟信号转换器之间，所述第一积分电路包括：
第一放大器，包含有：
第一输入端；
第二输入端；以及
输出端，用来输出第一输出信号至所述第一模拟信号转换器；
第一积分电容，耦接于所述第一放大器的第一输入端与输出端之间；
第一放电电容，包括：
第一端，用来接收第一电压；以及
第二端；
第一开关，耦接于所述第一放大器的第一输入端与所述放电电容的第二端之间；以及
第二开关，耦接于所述第一放电电容的第一端与第二端之间。
本发明部分实施例提供的积分电路利用放电电容及连接于放电电容的开关，将输出信号限制在最大电压与最小电压之间，如此一来，即使积分电路在进行长时间之后，总积分电压可远大于模拟信号转换器之动态范围，而不会造成模拟信号转换器进入饱和状态。因此，本发明的积分电路可降低对模拟信号转换器之动态范围的要求，进而降低电路复杂度及生产成本，且可以有效感测电容的变化。对于具有一定精度的模拟信号转换器，本发明部分实施例也能提高电容感测电路的精度，从而提高***的信噪比(Signal to Noise Ratio，SNR)。 另外，由于放电电容能有效减小积分的最大电压，因此积分电路中的积分电容可用相对较小的电容，从而减小电路面积。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明部分实施例进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以理解本发明，并不用于限定本发明。
请参考图1，图1为本发明一个实施例电容感测电路10的示意图。电容感测电路10将信号TX施加于待测电路100，并从待测电路100接收信号RX，电容感测电路10根据信号TX和信号RX感测待测电路100的待测电容CUT。
电容感测电路10包含有一积分电路104、模拟信号转换器108、电容判断电路102和混波器106。混波器106耦接于待测电路100与积分电路104之间，包含乘法器MP和波形产生器160，混波器106将一输入信号VIN输入至积分电路104；积分电路104根据输入信号VIN产生输出信号VOUT；模拟信号转换器108耦接于积分电路104，模拟信号转换器108用来将输出信号VOUT转换成数字信号VD；电容判断电路102耦接于模拟信号转换器108，用来根据数字信号VD判断待测电容CUT的电容变化。
积分电路104包含有：放大器Amp、积分电容CI、放电电容CF、电阻R、控制信号产生器140和开关SW1、SW2。放大器Amp包含有负输入端(即第一输入端，标示有「－」号)、正输入端(即第二输入端，标示有「+」号)和输出端。放大器Amp的正输入端接收参考电压VREF，输出端用来输出输出信号VOUT。电阻R的一端耦接于放大器Amp的负输入端，另一端接收输入信号VIN，电阻R用来调整输入信号VIN与输出信号VOUT之间的比例。积分电容CI耦接于放大器Amp的负输入端与输出端之间，放电电容CF的第一端用来接收电压VS，第二端耦接于开关SW1，其中，电压VS小于参考电压VREF。开关SW1耦接于放大器Amp的负输入端与放电电容CF的第二端之间，而开关SW2耦接于放电电容CF的第一端与第 二端之间。开关SW1、SW2受控于控制信号产生器140，即控制信号产生器140产生控制信号CTL1、CTL2，以分别控制开关SW1、SW2的导通状态。
电容感测电路10与积分电路104的操作原理叙述如下。在第一阶段T1中，控制信号产生器140产生控制信号CTL1使开关SW1为断开，此时积分电路104持续地对输入信号VIN进行积分，即积分电容CI持续地累积电荷，输出信号VOUT也持续地下降。另外，在第一阶段T1的一段时间中，控制信号产生器140产生控制信号CTL2使开关SW2为导通，放电电容CF受到开关SW2为导通的影响而没有储存电荷。在第二阶段T2中，控制信号产生器140产生控制信号CTL1、CTL2使开关SW1导通而开关SW2为断开。此时因电压VS小于参考电压VREF，累积于积分电容CI的电荷会释放到放电电容CF，即对放电电容CF充电，待放电电容CF充电至饱和后，即可继续对输入信号VIN进行积分。其中，因积分电容CI耦接至放大器Amp的负输入端，当累积于积分电容CI的电荷释放到放电电容CF时，会造成输出信号VOUT瞬间被拉高，直到放电电容CF充电至饱和，其中，输出信号VOUT瞬间被拉高的幅度为
Figure PCTCN2016090472-appb-000001
在放电电容CF充电至饱和后，输出信号VOUT才会继续因积分电路104对输入信号VIN进行积分而持续地下降。
具体来说，请参考图2，图2为输出信号VOUT和控制信号CTL1、CTL2随时间变化的波形图，其中当控制信号CTL1、CTL2为高电位时，开关SW1、SW2为导通，当控制信号CTL1、CTL2为低电位时，开关SW1、SW2为断开。积分电路104在时间t0时开始运作，此时输出信号VOUT的电压为电压VREF。积分电路104开始运作后，控制信号产生器140控制开关SW1、SW2使得积分电路104第一次进入第一阶段T1。在第一阶段T1中，积分电路104清除放电电容CF的电荷，且积分电路104持续地对输入信号VIN进行积分，积分电容CI持续地累积电荷，输出信号VOUT持续地下降。在时间t1时，控制信号产生器140控制开关SW1、SW2使得积分电路104第一次进入第二阶段T2，在第二阶段T2中，因累积于积分电容CI的电荷释放到放电电容CF，使得输出信号VOUT被拉高，直到放电电容CF充电至饱和(对应至时间t2)。在时间t2后，控制信号产生器140可控制开关SW1 使积分电路104第二次进入第一阶段T1，期间积分电路104继续地对输入信号VIN进行积分，而输出信号VOUT继续下降，在积分电路104对输入信号VIN进行积分的过程中，控制信号产生器140可控制开关SW2以清除放电电容CF的电荷。控制信号产生器140周而复始地控制开关SW1使得积分电路104来回操作于第一阶段T1与第二阶段T2之间，而于每一次的第一阶段T1中，控制信号产生器140控制开关SW2以清除放电电容CF的电荷，直到时间t3时，输出信号VOUT的信号值为电压Vt，且在操作时间区间TOP之内(操作时间区间TOP为从时间t0到时间t3之间的时间区间)，积分电路104进入第二阶段T2的次数为N次，即在操作时间区间TOP内积分电路104总共计有N次进入第二阶段T2。其中，控制信号产生器140可根据频率信号周期性地使积分电路104来回操作于第一阶段T1与第二阶段T2之间。另外，电压Vini代表积分电路104从开始运作到第一次进入第二阶段T2之间输出信号VOUT因进行积分而下降的变化量。
由图2可知，自第一次进入第二阶段T2后，输出信号VOUT的变化范围落在最大电压Vmax与最小电压Vmin之间，且最大电压Vmax与最小电压Vmin之间的电压幅度差为
Figure PCTCN2016090472-appb-000002
而积分电路104从时间t0到时间t3之间的总积分电压VO为
Figure PCTCN2016090472-appb-000003
(即从时间t0到时间t3之间积分电容CI所累积的总积分电荷量为CI(VO－VREF))。
为了感测待测电容CUT的电容变化，电容感测电路10可于第一时间通过积分电路104进行前述操作，而得到第一总积分电压VO1为
Figure PCTCN2016090472-appb-000004
电容感测电路10可另外于第二时间再一次通过积分电路104进行前述操作，而得到第二总积分电压VO2为
Figure PCTCN2016090472-appb-000005
其中电压Vt1和电压Vt2分别为积分电路104在第一时间和第二时间进行操作时间区间TOP的积分操作后输出信号VOUT的电压 值，次数N1与次数N2分别为积分电路104在第一时间和第二时间进行操作时间区间TOP的积分操作后积分电路104进入第二阶段T2的次数。
需注意的是，待测电容CUT的电容变化相关于第一总积分电压VO1与第二总积分电压VO2的电压差值VDIFF，而电压差值VDIFF为
Figure PCTCN2016090472-appb-000006
换句话说，待测电容CUT的电容变化仅与次数N1、次数N2、电压Vt1和电压Vt2相关，若适当设计使得次数N1与次数N2相等，则电压差值VDIFF仅与电压Vt1和电压Vt2相关，即待测电容CUT的电容变化仅与电压Vt1和电压Vt2相关。另外，电压Vt1和电压Vt2的范围落在最大电压Vmax与最小电压Vmin之间，换句话说，模拟信号转换器108的动态范围(Dynamic Range)仅需要在最大电压Vmax与最小电压Vmin之间，即降低了对模拟信号转换器108的动态范围的要求。
由上述可知，本实施例利用积分电路104，将输出信号VOUT限制在最大电压Vmax与最小电压Vmin之间，即使积分电路104在进行积分操作时间区间TOP之后，总积分电压VO可远大于模拟信号转换器108的动态范围，而不会造成模拟信号转换器108进入饱和状态。相较于现有技术，本实施例降低对模拟信号转换器108的动态范围的要求，进而降低电路复杂度和生产成本。对于具有一定精度的模拟信号转换器，本实施例也能提高电容感测电路的精度和***的信噪比。另外，由于放电电容能有效减小积分的最大电压，因此积分电路104中的积分电容CI可用相对较小的电容，从而减小电路面积。
需注意的是，前述实施例是用以说明本发明部分实施例的概念，本领域技术人员当可据以做不同的修饰，而不限于此。举例来说，控制信号产生器140不限于根据频率信号周期性地使积分电路104来回操作于第一阶段T1与第二阶段T2之间，控制信号产生器140可根据输出信号VOUT来作为产生控制信号CTL1、CTL2的判断依据。例如，当输出信号VOUT低于最小电压Vmin时，控制信号产生器140产生控制信号CTL1、CTL2使积分电路104进入第二阶段T2，以对放电电容CF充电及拉高输出信号VOUT。
另外，在积分电路104中利用电阻R来调整输入信号VIN与输出信号VOUT之间的比例，而不限于此，另可利用切换式电容模组来调整输入信号VIN与输出信号VOUT之间的比例，即可利用切换式电容模组取代积分电路104中的电阻R。举例来说，请参考图3，图3为本发明实施例提供的积分电路304的示意图。积分电路304与积分电路104类似，故相同组件沿用相同符号。与积分电路104不同的是，积分电路304包含切换式电容模组302，切换式电容模组302的一端耦接于放大器Amp的负输入端，另一端用来接收输入信号VIN。
切换式电容模组302包含电容CS和开关S1、S2、S3、S4，开关S1耦接于电容CS的第一端，用来接收输入信号VIN，开关S2耦接于电容CS的第一端与接地端之间，开关S3耦接于电容CS的第二端与放大器Amp的负输入端之间，开关S4耦接于电容CS的第二端与接地端之间。开关S1、S2、S3、S4可受控于频率控制信号ph1、ph2，其中频率控制信号ph1、ph2为相互正交的频率控制信号(即频率控制信号ph1、ph2为高电位的时间不相互重叠)。具体来说，在一实施例中，频率控制信号ph1可用来控制开关S1、S3的导通状态，而频率控制信号ph2可用来控制开关S2、S4的导通状态；于另一实施例中，频率控制信号ph1可用来控制开关S1、S4的导通状态，而频率控制信号ph2可用来控制开关S2、S3的导通状态。只要利用切换式电容模组302调整输入信号VIN与输出信号VOUT之间的比例，并利用相互正交的频率控制信号ph1、ph2控制开关S1、S2、S3、S4的导通状态，皆属于本发明的范畴。
另外，在电容感测电路10中，仅针对信号RX的同相分量(In Phase Component)进行积分，而不限于此，亦可针对信号RX的同相分量以及正交分量(Quadrature Component)同时进行积分，以对待测电容CUT达到更精准的判读。举例来说，请参考图4，图4为本发明一个实施例提供的电容感测电路40的示意图。电容感测电路40与电容感测电路10类似，故相同组件沿用相同符号。与电容感测电路10相同的是，电容感测电路40利用积分电路404_a对信号RX的同相分量进行积分；而与电容感测电路10不同的是，电容感测电路40 利用包含于混波器406的相位旋转器462和乘法器MP2撷取出信号RX的正交分量，并利用积分电路404_b对信号RX的正交分量进行积分。积分电路404_a、404_b分别耦接于模拟信号转换器408_a、408_b，模拟信号转换器408_a、408_b用来将积分电路404_a、404_b所产生的输出信号VOUT1、VOUT2分别转换成数字信号VD1、VD2，电容判断电路102即可根据数字信号VD1、VD2判断待测电容CUT的电容变化，使得电容判读更为准确。
另外，控制信号产生器440产生控制信号CTL1、CTL2、CTL3、CTL4，以分别控制开关SW1、SW2、SW3、SW4的导通状态，其控制开关导通机制可参考前述相关段落，在此不再赘述。需注意的是，在图4中，积分电路404_a、404_b与积分电路104之间具有相同的电路架构，而不限于此。本实施例的积分电路可与积分电路304之间具有相同的电路架构(即以切换式电容模组302取代积分电路404_a、404_b中的电阻R1、R2)，亦属于本发明的范畴。
由上述可知，本发明部分实施例的积分电路及电容感测电路利用放电电容及耦接于放电电容的开关，将输出信号限制在最大电压与最小电压之间，如此一来，即使积分电路在进行长时间积分之后，总积分电压可远大于模拟信号转换器的动态范围，而不会造成模拟信号转换器进入饱和状态。因此，本发明部分实施例的积分电路及电容感测电路可降低对模拟信号转换器的动态范围的要求，进而降低电路复杂度和生产成本。对于具有一定精度的模拟信号转换器，本发明部分实施例也能提高电容感测电路的精度和***的信噪比。另外，由于放电电容能有效减小积分的最大电压，因此积分电路中的积分电容可用相对较小的电容，从而减小电路面积。
以上所述仅为本发明的部分较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (23)

  1. 一种积分电路，包括：
    放大器，包含有：
    第一输入端；
    第二输入端；以及
    输出端，用来输出一输出信号；
    积分电容，耦接于所述第一输入端与所述输出端之间；
    放电电容，包含有：
    第一端，用来接收第一电压；以及
    第二端；
    第一开关，耦接于所述放大器的第一输入端与所述放电电容的第二端之间；以及
    第二开关，耦接于所述放电电容的第一端与第二端之间。
  2. 如权利要求1所述的积分电路，其中，还包括：控制信号产生器，用来产生第一控制信号和第二控制信号，以分别控制所述第一开关和所述第二开关的导通状态。
  3. 如权利要求2所述的积分电路，其中，所述控制信号产生器根据频率信号或所述输出信号，产生所述第一控制信号和所述第二控制信号。
  4. 如权利要求1，2或3所述的积分电路，其中，所述放大器的第二输入端接收参考电压，所述第一电压小于所述参考电压。
  5. 如权利要求1到4任一项所述的积分电路，其中，还包括电阻，所述电阻的一端耦接于所述放大器的第一输入端，电阻的另一端用来接收输入信号。
  6. 如权利要求1到5任一项所述的积分电路，其中，还包括切换式电容模组，切换式电容模组的一端耦接于所述放大器的第一输入端，切换式电容模组的另一端用来接收输入信号。
  7. 如权利要求6所述的积分电路，其中，所述切换式电容模组包括：第一切换电容、第三开关、第四开关、第五开关和第六开关；
    所述第三开关和所述第四开关耦接于所述第一切换电容的第一端，所述第五开关和所述第六开关耦接于所述第一切换电容的第二端，所述第三开关接收所述输入信号，所述第五开关耦接于所述放大器的第一输入端，所述第四开关和所述第六开关耦接于接地端。
  8. 一种电容感测电路，用来感测待测电路的待测电容，包括：
    第一模拟信号转换器，用来产生第一数字信号；
    电容判断电路，耦接于所述第一模拟信号转换器，用来根据所述第一数字信号，判断所述待测电容的电容变化；以及
    第一积分电路，耦接于所述待测电路与所述第一模拟信号转换器之间，所述第一积分电路包括：
    第一放大器，包含有：
    第一输入端；
    第二输入端；以及
    输出端，用来输出第一输出信号至所述第一模拟信号转换器；
    第一积分电容，耦接于所述第一放大器的第一输入端与输出端之间；
    第一放电电容，包括：
    第一端，用来接收第一电压；以及
    第二端；
    第一开关，耦接于所述第一放大器的第一输入端与所述放电电容的第二端之间；以及
    第二开关，耦接于所述第一放电电容的第一端与第二端之间。
  9. 如权利要求8所述的电容感测电路，其中，所述第一积分电路还包括：控制信号产生器，用来产生第一控制信号和第二控制信号，以分别控制所述第一开关和所述第二开关的导通状态。
  10. 如权利要求9所述的电容感测电路，其中，所述控制信号产生器根据频率信号或所述第一输出信号，产生所述第一控制信号和所述第二控制信号。
  11. 如权利要求8，9或10所述的电容感测电路，其中，还包括混波器，耦接于所述待测电路与所述第一积分电路之间。
  12. 如权利要求11所述的电容感测电路，其中，还包括第一电阻，所述第一电阻的一端耦接于所述第一放大器的第一输入端，所述第一电阻的另一端耦接于所述混波器。
  13. 如权利要求11或12所述的电容感测电路，其中，还包括第一切换式电容模组，所述第一切换式电容模组的一端耦接于所述第一放大器的第一输入端，所述第一切换式电容模组的另一端耦接于所述混波器。
  14. 如权利要求13所述的电容感测电路，其中，所述第一切换式电容模组包括：
    第一切换电容、第三开关、第四开关、第五开关和第六开关；
    所述第三开关和所述第四开关耦接于所述第一切换电容的第一端，所述第五开关和所述第六开关耦接于所述第一切换电容的第二端，所述第三开关接收输入信号，所述第五开关耦接于所述放大器的第一输入端，所述第四开关和所述第六开关耦接于接地端。
  15. 如权利要求11到14任一项所述的电容感测电路，其中，所述混波器包括第一乘法器和波形产生器；所述第一乘法器耦接于所述待测电路与所述第一积分电路之间，所述波形产生器耦接于所述第一乘法器。
  16. 如权利要求15所述的电容感测电路，其中，所述混波器还包括相位旋转器和第二乘法器；所述相位旋转器耦接于所述波形产生器与所述第二乘法器之间。
  17. 如权利要求16所述的电容感测电路，其中，还包括：
    第二模拟信号转换器，耦接于所述电容判断电路，用来产生第二数字信号；以及
    第二积分电路，耦接于所述混波器的第二乘法器与所述第二模拟信号转换器之间，所述第二积分电路包括：
    第二放大器，包含有：
    第一输入端；
    第二输入端；以及
    输出端，用来输出第二输出信号至所述第二模拟信号转换器；
    第二积分电容，耦接于所述第二放大器的第一输入端与输出端之间；
    第二放电电容，包括：
    第一端，用来接收所述第一电压；以及
    第二端；
    第七开关，耦接于所述第二放大器的第一输入端与所述第二放电电容的第二端之间；以及
    第八开关，耦接于所述第二放电电容的第一端与第二端之间；
    其中，所述电容判断电路根据所述第一数字信号和所述第二数字信号，判断所述待测电容的电容变化。
  18. 如权利要求17所述的电容感测电路，其中，所述控制信号产生器产生第三控制信号和第四控制信号，以分别控制所述第七开关和所述第八开关的导通状态。
  19. 如权利要求18所述的电容感测电路，其中，所述控制信号产生器根据所述频率信号或所述第二输出信号，产生所述第三控制信号和所述第四控制信号。
  20. 如权利要求17，18或19所述的电容感测电路，其中，还包括第二电阻，所述第二电阻的一端耦接于所述第二放大器的第一输入端，所述第二电阻的另一端耦接于所述混波器的第二乘法器。
  21. 如权利要求17到20任一项所述的电容感测电路，其中，还包括第二切换式电容模组，第二切换式电容模组的一端耦接于所述第二放大器的第一输入端，第二切换式电容模组的另一端耦接于所述第二乘法器。
  22. 如权利要求21所述的电容感测电路，其中，所述第二切换式电容模组包括：
    第二切换电容、第九开关、第十开关、第十一开关和第十二开关；
    所述第九开关和所述第十开关耦接于所述第二切换电容的第一端，所述第十一开关和所述第十二开关耦接于所述第二切换电容的第二端，所述第九开关 接收输入信号，所述第十一开关耦接于所述放大器的第一输入端，所述第十开关和所述第十二开关耦接于接地端。
  23. 如权利要求17到22任一项所述的电容感测电路，其中，所述第一放大器的第二输入端和所述第二放大器的第二输入端接收参考电压，所述第一电压小于所述参考电压。
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