WO2017067376A1 - 移位寄存器单元、栅极驱动装置、显示装置、控制方法 - Google Patents

移位寄存器单元、栅极驱动装置、显示装置、控制方法 Download PDF

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Publication number
WO2017067376A1
WO2017067376A1 PCT/CN2016/100657 CN2016100657W WO2017067376A1 WO 2017067376 A1 WO2017067376 A1 WO 2017067376A1 CN 2016100657 W CN2016100657 W CN 2016100657W WO 2017067376 A1 WO2017067376 A1 WO 2017067376A1
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Prior art keywords
pull
signal
control node
down control
thin film
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PCT/CN2016/100657
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English (en)
French (fr)
Inventor
崔贤植
韩承佑
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京东方科技集团股份有限公司
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Priority to EP16856809.5A priority Critical patent/EP3367376A4/en
Priority to US15/532,605 priority patent/US10043585B2/en
Publication of WO2017067376A1 publication Critical patent/WO2017067376A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/188—Organisation of a multiplicity of shift registers, e.g. regeneration, timing or input-output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G11C19/186—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET using only one transistor per capacitor, e.g. bucket brigade shift register
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation

Definitions

  • the present disclosure relates to a shift register unit and a control method thereof, a gate driving device including the shift register unit, and a display device including the gate driving device.
  • a gate driving signal is supplied to a gate of each thin film transistor of a pixel region by a gate driving device.
  • a gate driving device is formed on an array substrate of a liquid crystal display by an array process, thereby reducing cost and simplifying processes.
  • a gate driving device formed using GOA technology includes a plurality of shift register units each connected to a gate line of a thin film transistor of a pixel region. Specifically, each of the shift register units is respectively connected to a gate line of a thin film transistor of a pixel region formed in a row, and a driving output signal output from each shift register unit is used to perform on/off control of a thin film transistor of a corresponding row. . For example, when a shift register unit outputs a high-level drive output signal, the thin film transistor of the row connected thereto is turned on. Then, the thin film transistor of the turned-on row performs brightness control based on the signal output from the data driving device.
  • the display device when the shift register unit cannot operate normally, the display device cannot perform normal display. Therefore, the stability requirements of the shift register unit become high.
  • the present disclosure provides a shift register unit and a control method thereof, a gate driving device including the shift register unit, and a display device including the same, which can improve stability of a gate driving circuit, thereby reliably Display.
  • a shift register unit includes: an input module, connected to the driving input signal input end, the clock signal input end, and the pull-up control node, configured to control the pull-up control node according to the driving input signal and the clock signal Potential; pull-up module, with high-level DC signal input, the pull-up control node, drive output letter The output terminal is connected to be configured to pull up the driving output signal according to the potential of the pull-up control node; the first pull-down control signal generating module, the input end of the first signal, and the input of the driving input signal The terminal, the pull-up control node, and the first pull-down control node are connected, configured to control the power according to the driving input signal and the potential of the pull-up control node during the first signal being high level a potential of the first pull-down control node; a second pull-down control signal generating module, connected to the input end of the second signal, the driving input signal input end, the pull-up control node
  • a gate driving device includes: N shift register units as described above. Where N is a natural number greater than one.
  • the input of the drive input signal of the first mobile register module is connected to the output of the start signal.
  • a display device includes a display panel, and a gate driving device configured as described above to output a driving output signal to the display panel.
  • a control method applied to the aforementioned shift register unit includes: controlling a potential of the pull-up control node according to the driving input signal and the clock signal; pulling up the driving output signal according to the potential of the pull-up control node; and during the first signal being the high level, according to Driving the input signal, the potential of the pull-up control node to control the potential of the first pull-down control node; and during the second signal being the high level, according to the driving input signal, the potential of the pull-up control node Controlling a potential of the second pull-down control node, wherein the first signal alternates with the second signal to a high level; according to a potential of the first pull-down control node and a potential pair of the second pull-down control node The drive output signal is pulled down.
  • a shift register unit and a control method thereof according to the present disclosure a gate driving device including the shift register unit, and a display device including the gate driving device alternately pass the first according to the first signal and the second signal
  • the pull-down control signal generating module and the second pull-down control signal generating module generate a pull-down control signal for controlling the pull-down module. Therefore, the first pull-down control section can be effectively avoided
  • the aging of the pull-down module caused by the excessive duty cycle of the point and the second pull-down control node Thereby, the stability of the shift register unit, the gate driving device, and the display device can be improved.
  • FIG. 1 is a circuit diagram of a direct current (DC) driving type shift register unit applied in the present disclosure.
  • FIG. 2 is a waveform diagram of respective nodes in the circuit of the shift register unit shown in FIG. 1.
  • FIG. 3 is a functional block diagram of a shift register unit of an embodiment of the present disclosure.
  • FIG. 4 is a detailed circuit diagram of a shift register unit of an embodiment of the present disclosure.
  • Fig. 5 is a waveform diagram of nodes in the circuit of the shift register unit shown in Fig. 4.
  • Fig. 6 is a waveform diagram of a node in the circuit of the shift register unit shown in Fig. 4.
  • FIG. 7 is a functional block diagram of a gate driving device including a shift register unit of an embodiment of the present disclosure.
  • FIG. 8 is a functional block diagram of a display device including a gate driving device of an embodiment of the present disclosure.
  • FIG. 9 is a flowchart showing a method of controlling a shift register unit according to an embodiment of the present disclosure.
  • the source and drain of the thin film transistor employed in the embodiment of the present disclosure are symmetrical, so that the source and the drain are interchangeably named.
  • the thin film transistor can be classified into an N-type transistor or a P-type transistor in accordance with the characteristics of the thin film transistor.
  • an N-type transistor will be described as an example, but a P-type transistor may be used.
  • a P-type transistor when a P-type transistor is employed, those skilled in the art can adjust the input signals of the respective input terminals according to the type of transistors used.
  • Fig. 1 is a circuit diagram of a shift register unit 1 of a DC drive method applied to the invention.
  • Figure 2 is a diagram A waveform diagram of each node in the circuit of the shift register unit 1 shown in FIG.
  • the shift register unit 1 shown in FIG. 1 includes an input module 11, a pull-up module 12, a pull-down control signal generating module 13, and a pull-down module 14.
  • the input module 11 is connected to the drive input signal input terminal INPUT, the clock signal input terminal CLK, and the pull-up control node PU, and is configured to control the potential of the pull-up control node PU according to the drive input signal INPUT and the clock signal CLK.
  • the input module 11 may include: a first thin film transistor T1 having a drain and a gate connected to the input signal input terminal INPUT, a source stage connected to the pull-up control node PU, and a second thin film transistor T2.
  • the drain and the gate are connected to the clock signal input terminal CLK;
  • the capacitor C1 has one end connected to the source of the second thin film transistor T2 and the other end connected to the pull-up control node PU.
  • the first thin film transistor T1 When the signal for driving the input signal input terminal INPUT is at a high level, the first thin film transistor T1 is turned on. Therefore, the signal driving the input signal input terminal INPUT is transmitted to the pull-up control node PU. On the other hand, when the signal for driving the input signal input terminal INPUT is at a low level, the first thin film transistor T1 is turned off, so that the signal for driving the input signal input terminal INPUT cannot be transmitted to the control node PU.
  • the second thin film transistor T2 is turned on. Therefore, the signal of the clock signal input terminal CLK is transmitted to the pull-up control node PU. On the contrary, when the signal of the clock signal input terminal CLK is at a low level, the second thin film transistor T2 is turned off, so that the signal of the clock signal input terminal CLK cannot be transmitted to the control node PU.
  • the potential of the pull-up control node PU can be controlled to the potential of the signal of the input signal terminal INPUT plus the signal of the clock signal input terminal CLK.
  • the second thin film transistor T2 is turned off, so the potential of the pull-up control node PU and the input signal of the driving input are input.
  • the signal of the terminal INPUT is the same.
  • the third cycle since the signal of the clock signal input terminal CLK is at a high level, the second thin film transistor T2 is turned on, so the potential of the pull-up control node PU is controlled by the capacitor C1 to drive the input signal terminal INPUT.
  • the signal is added to the potential after the signal of the clock signal input terminal CLK.
  • the potential of the pull-up control node PU in the third cycle is twice the potential of the pull-up control node PU in the second cycle.
  • the pull-up module 12 is connected to the high-level DC signal input terminal DCH, the pull-up control node PU, and the drive output signal output terminal OUTPUT, and is configured according to the pull-up control node PU.
  • the potential pulls up the drive output signal.
  • the pull-up module 12 may include a third thin film transistor T3 having a drain connected to the high-level DC signal input terminal DCH, a gate connected to the pull-up control node PU, and a source stage and a driving output signal output. End OUTPUT connection.
  • the third thin film transistor T3 is configured to be turned on when the potential of the pull-up control node PU is greater than the on-voltage. As shown in FIG. 2, since the potential of the pull-up control node PU in the first period is smaller than the on-voltage of the third thin film transistor T3, the third thin film transistor T3 is turned off. Therefore, the signal driving the output signal output terminal OUTPUT is at a low level. Further, in the second period and the third period, since the potential of the pull-up control node PU is equal to or higher than the on-voltage of the third thin film transistor T3, the third thin film transistor T3 is turned on.
  • the potential of the output signal output terminal OUTPUT is the potential of the pull-up control node PU. half.
  • the pull-down control signal generating module 13 is connected to the high-level DC signal input terminal DCH, the driving input signal input terminal INPUT, the pull-up control node PU, and the pull-down control node PD, and is configured to be based on the driving input signal and the potential of the pull-up control node PU. Controls the potential of the pull-down control node PD.
  • the pull-down control signal generating module 13 may include a fourteenth thin film transistor T14, a fifteenth thin film transistor T15, and a sixteenth thin film transistor 16.
  • the drain and the gate of the fourteenth thin film transistor T14 are connected to the high level DC signal input terminal DCH, and the source level thereof is connected to the pull-down control node PD.
  • the fifteenth thin film transistor T15 or the sixteenth thin film transistor T16 is not turned on, the pull-down control node PD is maintained at a high level.
  • the drain of the fifteenth thin film transistor T15 is connected to the pull-down control node PD, the gate is connected to the drive input signal input terminal INPUT, and the source stage is connected to the low-level signal input terminal VSS. Thereby, when the signal for driving the input signal input terminal INPUT is at the high level, the fifteenth thin film transistor T15 is turned on, whereby the pull-down control node PD can be controlled to the low level.
  • the 16th thin film transistor drain is connected to the pull-down control node PD, the gate is connected to the pull-up control node PU, and the source stage is connected to the low-level signal input terminal VSS. Thereby, when the pull-up control node PU is at the high level, the sixteenth thin film transistor T16 is turned on, whereby the pull-down control node PD can be controlled to the low level.
  • the signal for driving the input signal input terminal INPUT becomes a high level and/or the signal of the pull-up control node PD becomes a high level, and thus the first period to the third period During the cycle, the pull-down control node PD is controlled at a low level.
  • the signal for driving the input signal input terminal INPUT and the signal of the pull-up control node PD are both low, and the fifteenth thin film transistor T15 and the sixteenth thin film transistor T16 are turned off, so the pull-down control node PD is high.
  • the level DC signal is held at a high level.
  • the pull-down control node PD is kept at a low level for a long time, that is, a pull-down control
  • the duty cycle of the node PD is very large (about 99.7%).
  • the value of the duty ratio is merely an example, and is actually related to the number of shift register units included in the gate driving device, the connection manner of the gate driving device to the display panel, and the like.
  • the pull-down module 14 is connected to the pull-down control node PD and configured to pull down the drive output signal according to the potential of the pull-down control node PD.
  • the pull-down module 14 includes a seventeenth thin film transistor T17 and an eighteenth thin film transistor T18.
  • the drain of the seventeenth thin film transistor T17 is connected to the drive output signal output terminal OUTPUT
  • the source stage is connected to the low level signal input terminal VSS
  • the gate is connected to the pull-down control node PD.
  • the drain of the eighteenth thin film transistor T18 is connected to the pull-up control node PU, the source stage is connected to the low-level signal input terminal VSS, and the gate is connected to the pull-down control node PD.
  • the pull-down control node PD is at the high level, the eighteenth thin film transistor T18 is turned on, and therefore the potential of the pull-up control node PU can be effectively maintained at the low level.
  • the pull-up control node PU is at a low level, since the potential of the pull-up control node PU is smaller than the turn-on voltage of the third thin film transistor T3, the signal from the drive output signal output terminal OUTPUT is effectively kept low. level.
  • the signal for driving the output signal output terminal OUTPUT is effectively maintained at the low level by the pull-down module 14.
  • the pull-down module 14 simultaneously pulls down the pull-up control node PU and the drive output signal output terminal OUTPUT as an example, but the present disclosure is not limited thereto, and may only be pulled up as needed.
  • the control node PU or the drive output signal output terminal OUTPUT is pulled down.
  • the pull-down module 14 may also include only the seventeenth thin film transistor T17 or the eighteenth thin film transistor T18.
  • Memory unit. 3 is a functional block diagram of a shift register unit of an embodiment of the present disclosure.
  • 4 is a circuit diagram of a shift register unit of an exemplary embodiment of the present disclosure.
  • the shift register unit 2 includes an input module 21, a pull-up module 22, a first pull-down control signal generating module 23, a second pull-down control signal generating module 24, and a pull-down. Module 25.
  • a gate driving device in a display device can be configured.
  • the input module 21 is connected to the drive input signal input terminal INPUT, the clock signal input terminal CLK, and the pull-up control node PU, and is configured to control the potential of the pull-up control node PU according to the drive input signal INPUT and the clock signal CLK.
  • the input module 21 may include a first thin film transistor T1, a second thin film transistor T2, and a capacitor C1.
  • the connection structure of the first thin film transistor T1, the second thin film transistor T2, and the capacitor C1 is the same as that of FIG. 2, and the description thereof will not be repeated here.
  • the drive input signal and the clock signal can be transmitted to the pull-up control node PU through the first thin film transistor T1 and the second thin film transistor T2. Further, by the capacitor C1, the potential of the pull-up control node PU can be controlled to be equal to the potential of the signal input to the input signal input terminal INPUT plus the signal of the clock signal input terminal CLK.
  • the potential of the pull-up control node PU in the third cycle is twice the potential of the pull-up control node PU in the second cycle.
  • the initial period in which the drive input signal becomes a high level is referred to as a first period.
  • the input module 21 of the embodiment of the present disclosure is not limited to the configuration shown in FIG. 4, and other configurations may be employed.
  • the input module 21 may be configured by other components (for example, diodes) or the like, and the input module 21 may be configured by other connection methods as long as the input module 21 can drive the signal input to the input signal INPUT and the signal of the clock signal input terminal CLK. Pass to the pull-up control node.
  • the drive input signal becomes a high level, and then in the third period, the slave clock signal input terminal CLK The input signal goes high. That is, the period in which the clock signal is at the high level is set to a period immediately following the drive input signal. Thereby, the drive output signal after shifting the drive input signal can be easily generated by the pull-up module 22 described below.
  • the pull-up module 22 is connected to the high-level DC signal input terminal DCH, the pull-up control node PU, and the drive output signal output terminal OUTPUT, and is configured to pull up the drive output signal according to the potential of the pull-up control node PU.
  • the pull-up module 22 includes, for example, a third thin film transistor T3.
  • the connection structure of the third thin film transistor T3 is the same as that of FIG. 2, and the description thereof will not be repeated here.
  • the drive output signal shifted by the drive input signal is output from the drive output signal output terminal OUTPUT according to the potential of the pull-up control node PU through the third thin film transistor T3.
  • the third thin film transistor T3 may be configured to be turned on when the potential of the pull-up control node PU is greater than the on-voltage. As shown in FIG. 5, since the potential of the pull-up control node PU in the first period is smaller than the on-voltage of the third thin film transistor T3, the third thin film transistor T3 is turned off. Therefore, the signal driving the output signal output terminal OUTPUT is at a low level.
  • the third thin film transistor T3 is turned on. Further, under the action of a signal connected to the high-level DC signal input terminal DCH of the drain of the third transistor T3, as shown in FIG. 5, the potential output from the drive output signal output terminal OUTPUT is the pull-up control node PU. Half of the potential.
  • the pull-up module 22 of the embodiment of the present disclosure is not limited to the configuration shown in FIG. 4, and other configurations may be employed.
  • the pull-up module may be configured by other components (for example, a diode) or the like, and the pull-up module 22 may be configured by other connection methods as long as the pull-up module 22 can output the output signal from the drive according to the potential of the pull-up control node PU.
  • the terminal OUTPUT output can output the drive output signal after the drive input signal is shifted.
  • the turn-on voltage of the third thin film transistor T3 is set to be larger than the potential of the pull-up control node PU in the first period, thereby shifting the drive output signal.
  • an appropriate drive output signal may be generated based on the potential of the pull-up control node PU by another means or circuit.
  • the pull-up module shown in FIG. 4 by connecting the pull-up control node PU to the drive output signal output terminal OUTPUT, it is possible to obtain the potential of the pull-up control node PU in the second period and the third period. Drive output letter of half of the potential number.
  • the duty ratio of the pull-down control node PD is very large, and is at a high level for a long time.
  • the thin film transistor (for example, the seventeenth thin film transistor T17) constituting the pull-down module 16 is in an on state for a long period of time, so that the thin film transistor constituting the pull-down module 16 is easily deteriorated.
  • the stability of the shift register unit 1 cannot be ensured, which adversely affects the operational stability of the gate driving device and the display device.
  • the first pull-down control signal generating module 23 and the second pull-down control signal generating module 24 are respectively used to generate a pull-down control signal, and the pull-down module 25 is in the The pull-down control signal generation module 23 and the second pull-down control signal generation module 24 respectively pull down the drive output signal under the control of the pull-down control signal. Therefore, it is possible to effectively prevent the duty ratio of the potential of the pull-down control node from being excessively large, and it is possible to prevent the thin film transistor constituting the pull-down module 25 from being in a long-term conduction state. Thereby, it is possible to avoid rapid deterioration of the thin film transistor constituting the pull-down module 25 and increase the stability of the shift register unit 2.
  • the first pull-down control signal generating module 23 is connected to the first signal input terminal DC1, the driving input signal input terminal INPUT, the pull-up control node PU, and the first pull-down control node PD1, and is configured to be in the first While the signal DC1 is at the high level, the potential of the first pull-down control node PD1 is controlled in accordance with the drive input signal and the potential of the pull-up control node.
  • the first pull-down control signal generating module 23 may include a fourth thin film transistor T4, a fifth thin film transistor T5, and a sixth thin film transistor T6.
  • the drain and the gate of the fourth thin film transistor T4 are connected to the first signal input terminal DC1
  • the source stage is connected to the first pull-down control node PD1
  • the drain of the fifth thin film transistor T5 is connected to the first pull-down control node PD1.
  • the gate is connected to the input terminal INPUT of the drive input signal
  • the source stage is connected to the low level signal input terminal VSS
  • the drain of the sixth thin film transistor T6 is connected to the first pull-down control node PD1, the gate and the pull-up control The node PU is connected, and the source stage is connected to the low level signal input terminal VSS.
  • the fourth thin film transistor T4 when the first signal DC1 is at a high level, the fourth thin film transistor T4 is turned on, so that in the case where the fifth thin film transistor T5 and the sixth thin film transistor T6 are turned off, the first The pull-down control node PD1 is kept at a high level. While the first signal DC1 is at a high level, in a case where the signal for driving the input signal input terminal INPUT is at a high level, the fifth thin film transistor T5 Turning on, thereby enabling the first pull-down control node PD1 to be controlled at a low level.
  • the sixth thin film transistor T6 is turned on, whereby the first pull-down control node PD1 can be controlled at a low level.
  • the waveform of each node is shown as an example in which the first signal DC1 is at a high level.
  • the signal for driving the input signal input terminal INPUT becomes a high level and/or the signal of the pull-up control node PD becomes a high level, and thus in the first to third periods
  • the first pull-down control node PD1 is controlled at a low level.
  • the signal for driving the input signal input terminal INPUT and the signal for the pull-up control node PD are both low, and the fifth thin film transistor T5 and the sixth thin film transistor T6 are turned off, so A pull-down control node PD1 is held at a high level by the high-level DC signal.
  • the first pull-down control signal generating module 23 of the embodiment of the present disclosure is not limited to the configuration shown in FIG. 4, and other configurations may be employed.
  • the first pull-down control signal generating module 23 is configured by another component (for example, a diode) or the like, and the first pull-down control signal generating module 23 may be configured by other connection methods as long as the first pull-down control signal generating module 23 While the first signal DC1 is at a high level, the potential of the first pull-down control node PD1 may be controlled according to the drive input signal and the potential of the pull-up control node.
  • the second pull-down control signal generating module 24 is connected to the second signal input terminal DC2, the driving input signal input terminal INPUT, the pull-up control node PU, and the second pull-down control node PD2, and is configured to be in a period in which the second signal DC2 is at a high level.
  • the potential of the second pull-down control node is controlled according to the drive input signal and the potential of the pull-up control node.
  • the second pull-down control signal generating module 24 includes a seventh thin film transistor T7, an eighth thin film transistor T8, and a ninth thin film transistor T9.
  • the drain and the gate of the seventh thin film transistor T7 are connected to the second signal input terminal DC2, the source stage is connected to the second pull-down control node PD2, and the drain of the eighth thin film transistor T8 is connected to the second pull-down control node PD2.
  • the gate is connected to the input signal input terminal INPUT, and the source is connected to the low level signal input terminal VSS; the drain of the ninth thin film transistor T9 is connected to the second pull-down control node PD2, and the gate is connected to the pull-up control node PU.
  • the source level is connected to the low level signal input terminal VSS.
  • the seventh thin film transistor T7 is turned on, so that in the case where the eighth thin film transistor T8 and the ninth thin film transistor T9 are turned off, the second The pull-down control node PD2 is kept at a high level.
  • the eighth thin film transistor T8 is turned on, whereby the second pull-down control node PD2 can be controlled to a low level.
  • the ninth thin film transistor T9 is turned on, whereby the second pull-down control node PD2 can be controlled at the low level.
  • the waveform of each node is shown as an example in which the first signal DC1 is at a high level and the second signal DC2 is at a low level.
  • the seventh thin film transistor T7 is turned off, so the second pull-down control node PD2 is maintained at a low level.
  • the second pull-down control node PD2 becomes a low level in the first period to the third period, in the same manner as the first pull-down control node PD1, in other periods (for example, Stay high in four cycles).
  • the second pull-down control signal generating module 24 of the embodiment of the present disclosure is not limited to the configuration shown in FIG. 4, and other configurations may be employed.
  • the second pull-down control signal generating module 24 is configured by another component (for example, a diode) or the like, and the second pull-down control signal generating module 24 may be configured by other connection methods as long as the second pull-down control signal generating module 24 is in the second While the signal DC2 is at the high level, the potential of the second pull-down control node PD2 may be controlled according to the drive input signal and the potential of the pull-up control node.
  • the first signal DC1 and the second signal DC2 alternately become a high level.
  • the second signal DC2 is at a low level at a timing when the first signal DC1 is at a high level.
  • the second signal DC2 is at a high level.
  • the waveforms of the first signal DC1 and the second signal DC2 are illustrated by taking the duty ratios of the first signal DC1 and the second signal DC2 as 50%, respectively.
  • the duty ratios of the first signal DC1 and the second signal DC2 may be adjusted as long as the first signal DC1 and the second signal DC2 are alternately brought to a high level.
  • the first pull-down control signal generation module 23 operates while the first signal is at the high level
  • the second pull-down control signal generation module 24 operates while the second signal is at the high level.
  • the first pull-down control signal generating module 23 and the second pull-down control signal generating module 24 alternately operate.
  • the first pull-down control signal generating module 23 includes a tenth thin film transistor.
  • the second pull-down control signal generating module 24 includes the eleventh thin Membrane transistor T11.
  • the drain of the tenth thin film transistor T10 is connected to the first pull-down control node PD1, the gate is connected to the second pull-down control node PD2, and the source stage is connected to the low-level signal input terminal VSS.
  • the drain of the eleventh thin film transistor T11 is connected to the second pull-down control node PD2, the gate is connected to the first pull-down control node PD1, and the source is connected to the low-level signal input terminal VSS.
  • the tenth thin film transistor T10 is turned on, and the second pull-down control signal generating module 24 operates.
  • the first pull-down control node PD1 can be effectively kept at a low level, thereby ensuring that the first pull-down control signal generating module 23 does not operate.
  • the eleventh thin film transistor T11 is turned on, and the first pull-down control signal generating module 23 operates.
  • the second pull-down control node PD2 can be effectively kept at a low level, thereby ensuring that the second pull-down control signal generating module 24 does not operate.
  • the first pull-down control signal generating module 23 includes the tenth thin film transistor T10
  • the second pull-down control signal generating module 24 includes the eleventh thin film transistor T11 so that the first signal DC1 and the second signal DC2 can alternately become When the level is high, it is reliably ensured that the first pull-down control signal generating module 23 and the second pull-down control signal generating module 24 operate alternately.
  • the pull-down module 25 is connected to the first pull-down control node PD1 and the second pull-down control node PD2, and is configured to pull down the drive output signal according to the potential of the first pull-down control node and the potential of the second pull-down control node.
  • the pull-down module 25 includes a twelfth thin film transistor T12.
  • the drain of the twelfth thin film transistor T12 is connected to the output terminal OUTPUT of the driving output signal, the source stage is connected to the low level signal input terminal VSS, the first gate is connected to the first pull-down control node PD1, and the second gate is connected The second pull-down control node PD2 is connected.
  • the twelfth thin film transistor T12 is a double gate type thin film transistor. Therefore, when a high level is applied to the first gate or the second gate, the twelfth thin film transistor T12 is turned on.
  • the twelfth thin film transistor T12 is turned on, thereby driving The output OUTPUT of the output signal can be effectively held low.
  • the first pull-down control node PD1 is at a high level, and therefore, under the action of the pull-down module 25, the signal for driving the output signal output terminal OUTPUT is effectively maintained at a low level.
  • the pull-down module 25 can simultaneously simultaneously control the potential of the first pull-down control node PD1 and the second pull-down control node.
  • the potential pulls down the drive output signal, so the drive output signal can be effectively pulled down.
  • the pull-down module 25 pulls down the drive output signal, so that the first signal DC1 is at the high level.
  • the pull-down operation is performed in accordance with the first pull-down control node PD1, and the pull-down operation is performed in accordance with the second pull-down control node PD2 while the second signal DC2 is at the high level.
  • the pull-down module 25 of the embodiment of the present disclosure is not limited to the structure shown in FIG. 4, and other structures may be adopted as long as the pull-down module 25 can according to the potential of the first pull-down control node and the potential of the second pull-down control node. Pull down the drive output signal.
  • the pull-down module 25 of the embodiment of the present disclosure further includes a thirteenth thin film transistor T13.
  • the drain of the thirteenth thin film transistor T13 is connected to the pull-up control node PU, the source stage is connected to the low-level signal input terminal VSS, and the first gate is connected to the first pull-down control node PD1, and the second gate is connected.
  • the pole is connected to the second pull-down control node PD2.
  • the thirteenth thin film transistor T13 is turned on, so that the potential of the pull-up control node PU can be effectively kept low.
  • Level As described above, when the pull-up control node PU is at a low level, since the potential of the pull-up control node PU is smaller than the turn-on voltage of the third thin film transistor T3, the signal from the output terminal OUTPUT of the drive output signal is effectively kept low. Level.
  • the first pull-down control signal generating module 23 and the second pull-down control signal The generation module alternately controls the first pulldown control node PD1 and the second pulldown control node PD2.
  • the pull-down module 25 can pull down the drive output signal according to the first pull-down control node PD1 and the second pull-down control node PD2. That is, during the period when the first signal is at the high level, the pull-down module 25 can pull down the drive output signal according to the potential of the first pull-down control node PD1, and can follow the second pull-down control node while the second signal is at the high level.
  • the potential of PD2 pulls down the drive output signal.
  • the first pull-down control node PD1 is at a low level during the second signal DC2 becoming a high level, so the PD1 duty ratio of the first pull-down control node can be controlled not to Especially large.
  • the duty ratio of the first pull-down control node PD1 is slightly smaller than the duty ratio of the first signal DC1, which is approximately equal to 50% in the case shown, for example, in FIG.
  • the second pull-down control node PD2 is at a low level during the period when the first signal DC1 is at a high level, so the duty ratio of the second pull-down control node PD2 can be controlled so as not to be particularly large.
  • the duty ratio of the second pull-down control node PD2 is slightly smaller than the duty ratio of the second signal DC1, which is approximately equal to 50% in the case shown in FIG. Therefore, it is possible to avoid that a certain PN junction of the bipolar thin film transistor constituting the pull-down module 25 configured as shown in FIG. 4 is in an on state for a long period of time, and it is possible to avoid rapid deterioration of the thin film transistor. Thereby, the stability of the shift register unit, the gate driving device, and the display device can be improved.
  • FIG. 7 shows a functional block diagram of a gate driving device including a shift register unit of an embodiment of the present disclosure.
  • the gate driving device of the embodiment of the present disclosure includes N shift register units. Where N is a natural number greater than one. Also, each of the shift register units included in the gate driving device may adopt the configuration as described above.
  • the input terminal of the driving input signal of the nth shift register unit is connected to the output terminal of the driving output signal of the n-1th shift register unit.
  • the input end of the drive input signal of the first mobile register module is connected to the output end of the start signal.
  • the drive output signals output from the first to Nth shift register units are sequentially driven output signals that are periodically shifted from the start signal.
  • the first signal, the second signal, and the high-level DC signal are respectively received, thereby outputting the pair of driving inputs according to the received signal.
  • the drive output signal after the signal is shifted.
  • FIG. 8 is a functional block diagram of a display device including a gate driving device of an embodiment of the present disclosure.
  • the display device includes a display panel and a gate driving device. Further, in the display device shown in FIG. 8, other devices may be provided as needed. For example, as shown in Figure 8, the display is loaded The reset can include a data drive.
  • the gate driving device included in the display device of FIG. 8 can adopt the structure shown in FIG.
  • Each of the shift register units included in the gate driving device is configured to turn on/off a thin film transistor of a corresponding row of a pixel region of the display panel. Specifically, when the driving output signal outputted by the shift register unit becomes a high level, the thin film transistors of the corresponding rows are turned on. Since the shift register units sequentially output the shifted drive output signals, the thin film transistors of the respective rows in the display panel are sequentially turned on, so that the turned-on thin film transistors can perform luminance according to signals output from the data driving device. control.
  • FIG. 9 is a flowchart showing a method of controlling a shift register unit according to an embodiment of the present disclosure. Next, a control method applied to a shift register unit of an embodiment of the present disclosure will be described with reference to FIG.
  • step S1 the potential of the pull-up control node is controlled in accordance with the drive input signal and the clock signal.
  • the input module 21 is connected to the drive input signal input terminal INPUT, the clock signal input terminal CLK, and the pull-up control node PU, and is configured to be based on the drive input signal.
  • the INPUT and clock signals CLK control the potential of the pull-up control node PU.
  • the input module 21 may include a first thin film transistor T1, a second thin film transistor T2, and a capacitor C1.
  • the drive input signal and the clock signal can be transmitted to the pull-up control node PU through the first thin film transistor T1 and the second thin film transistor T2. Further, by the capacitor C1, the potential of the pull-up control node PU can be controlled to the potential of the signal of the drive signal terminal INPUT plus the signal of the clock signal CLK.
  • step S2 the drive output signal is pulled up according to the potential of the pull-up control node.
  • the pull-up module 22 is connected to the high-level DC signal input terminal DCH, the pull-up control node PU, and the drive output signal output terminal OUTPUT, and is configured.
  • the drive output signal is pulled up according to the potential of the pull-up control node PU.
  • the pull-up module 22 includes a third thin film transistor T3.
  • the drive output signal shifted by the drive input signal is output from the drive output signal output terminal OUTPUT by the third thin film transistor T3 according to the potential of the pull-up control node PU.
  • the third thin film transistor T3 is configured to be turned on when the potential of the pull-up control node PU is greater than the on-voltage. As shown in FIG. 5, since the potential of the pull-up control node PU in the first period is smaller than the on-voltage of the third thin film transistor T3, the third thin film transistor T3 is turned off. Therefore, the output letter from the driver The signal output from the OUTPUT output is low.
  • the third thin film transistor T3 is turned on. Further, under the action of the signal of the input terminal DCH of the high-level DC signal connected to the drain of the third transistor T3, as shown in FIG. 5, the potential of the output signal output terminal OUTPUT is the potential of the pull-up control node PU. Half of it.
  • step S3 during the period when the first signal is at the high level, the potential of the first pull-down control node is controlled according to the drive input signal and the potential of the pull-up control node.
  • the first pull-down control signal generating module 23 and the input terminal DC1 of the first signal, the drive input signal input terminal INPUT, and the pull-up control node PU The first pull-down control node PD1 is connected, and is configured to control the potential of the first pull-down control node PD1 according to the driving input signal and the potential of the pull-up control node while the first signal DC1 is at a high level.
  • the first pull-down control signal generating module 23 includes a fourth thin film transistor T4, a fifth thin film transistor T5, and a sixth thin film transistor T6.
  • the fourth thin film transistor T4 is turned on, thereby maintaining the first pull-down control node PD1 at a high level in a case where the fifth thin film transistor T5 and the sixth thin film transistor T6 are turned off.
  • the first signal is at a high level, in a case where the signal of the input terminal INPUT of the drive input signal is at a high level, the fifth thin film transistor T5 is turned on, whereby the first pull-down control node PD1 can be controlled to be low. Level.
  • the sixth thin film transistor T6 is turned on, whereby the first pull-down control node PD1 can be controlled at a low level.
  • step S4 during the period when the second signal is at the high level, the potential of the second pull-down control node is controlled according to the drive input signal and the potential of the pull-up control node.
  • the second pull-down control node PD2 is connected, and is configured to control the potential of the second pull-down control node according to the driving input signal and the potential of the pull-up control node while the second signal DC2 is at a high level.
  • the second pull-down control signal generating module 24 includes a seventh thin film transistor T7, an eighth thin film transistor T8, and a ninth thin film transistor T9.
  • the seventh thin film transistor T7 is turned on, so that when the eighth thin film transistor T8 and the ninth thin film transistor T9 are turned off, the second pull-down is performed.
  • Control node PD2 remains at a high level. While the second signal is at a high level, in a case where the signal for driving the input signal input terminal INPUT is at a high level, the eighth thin film transistor T8 is turned on, whereby the second pull-down control node PD2 can be controlled at a low level. .
  • the ninth thin film transistor T9 is turned on, whereby the second pull-down control node PD2 can be controlled at the low level.
  • the first signal and the second signal alternately become a high level.
  • the second signal DC2 is at a low level at a timing when the first signal DC1 is at a high level.
  • the second signal DC2 is at a high level.
  • the first pull-down control signal generating module 23 operates while the first signal is at a high level, and the second pull-down control signal generating module 24 at a second signal is
  • the high level period is high
  • the first pull-down control signal generating module 23 and the second pull-down control signal generating module 24 alternately operate when the first signal DC1 and the second signal DC2 alternately become the high level.
  • step S5 the drive output signal is pulled down according to the potential of the first pull-down control node and the potential of the second pull-down control node.
  • the pull-down module 25 is connected to the first pull-down control node PD1 and the second pull-down control node PD2, and is configured to be based on the first pull-down control node.
  • the potential and the potential of the second pull-down control node pull down the drive output signal.
  • the pull-down module 25 includes a twelfth thin film transistor T12. In a case where the first pull-down control node PD1 becomes a high level or the second pull-down control node PD2 becomes a high level, the twelfth thin film transistor T12 is turned on, so that the driving output signal output terminal OUTPUT can be effectively kept low. Level.
  • the first pull-down control node PD1 is at a high level, and thus in the pull-down module 25 The signal of the output terminal OUTPUT of the drive output signal is effectively maintained at a low level.
  • the pull-down module 25 can simultaneously pull down the drive output signal according to the potential of the first pull-down control node PD1 and the potential of the second pull-down control node, so that the drive output signal can be effectively pulled down.
  • the pull-down module 25 pulls down the drive output signal, so that the first signal is at the high level.
  • the first pull-down control node PD1 performs a pull-down operation, and performs a pull-down operation according to the second pull-down control node PD2 while the second signal is at a high level.
  • the pull-down module 25 may further include a thirteenth thin film transistor T13.
  • the thirteenth thin film transistor T13 is turned on, and thus the potential of the pull-up control node PU can be effectively maintained at a low level.
  • the pull-up control node PU is at a low level, since the potential of the pull-up control node PU is smaller than the on-voltage of the third thin film transistor T3, the signal from the output terminal OUTPUT of the drive output signal is effectively maintained at a low level.
  • the first pull-down control node and the second pull-down control node can be alternately controlled. Then, the driving output signal is pulled down according to the first pull-down control node and the second pull-down control node. That is, during the period when the first signal is at the high level, the drive output signal can be pulled down according to the potential of the first pull-down control node, and during the second signal being at the high level, the drive can be driven according to the potential of the second pull-down control node. The output signal is pulled down.
  • the first pull-down control node is at a low level during the period when the second signal becomes the high level, and thus the duty ratio of the first pull-down control node can be controlled not to be particularly large.
  • the second pull-down control node PD2 is at a low level during the period when the first signal DC1 is at a high level, so the duty ratio of the second pull-down control node can be controlled so as not to be particularly large. Therefore, it is possible to avoid that a certain PN junction of the bipolar thin film transistor constituting the pull-down module 25 configured as shown in FIG. 4 is in an on state for a long period of time, and it is possible to avoid rapid deterioration of the thin film transistor. Thereby, the stability of the shift register unit, the gate driving device, and the display device can be improved.

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Abstract

一种移位寄存器单元及其控制方法、包括该移位寄存器单元的栅极驱动装置、以及包括该栅极驱动装置的显示装置。所述移位寄存器单元包括：输入模块(21)；上拉模块(22)；第一下拉控制信号生成模块(23)，在第一信号为高电平期间，根据驱动输入信号、上拉控制节点的电位来控制第一下拉控制节点的电位；第二下拉控制信号生成模块(24)，在第二信号为高电平期间，根据驱动输入信号、上拉控制节点的电位来控制第二下拉控制节点的电位，其中第一信号与第二信号交替成为高电平；下拉模块(25)，根据第一下拉控制节点的电位和第二下拉控制节点的电位对驱动输出信号进行下拉，能够提高栅极驱动电路的稳定性，从而可靠地进行显示。

Description

移位寄存器单元、栅极驱动装置、显示装置、控制方法 技术领域
本公开涉及移位寄存器单元及其控制方法、包括该移位寄存器单元的栅极驱动装置、以及包括该栅极驱动装置的显示装置。
背景技术
目前，显示装置得到了广泛的应用。在薄膜晶体管液晶显示器TFT-LCD(Thin Film Transistor-liquid crystal Display)中，通过栅极驱动装置对像素区域的各个薄膜晶体管的栅极提供栅极驱动信号。在GOA技术(Gate Driver on Array或者Gate On Array，阵列基板行驱动)中，在液晶显示器的阵列基板上通过阵列工艺形成栅极驱动装置，从而能够降低成本、简化工序。
采用GOA技术形成的栅极驱动装置包括多个移位寄存器单元，每个移位寄存器单元与像素区域的薄膜晶体管的栅线连接。具体地，各个移位寄存器单元分别与按行形成的像素区域的薄膜晶体管的栅线连接，通过各个移位寄存器单元输出的驱动输出信号，对相应的行的薄膜晶体管进行导通/截止等控制。例如，在某个移位寄存器单元输出高电平的驱动输出信号时，与其连接的行的薄膜晶体管被导通。然后，被导通的行的薄膜晶体管根据数据驱动装置输出的信号而进行亮度控制。
如上，在显示装置中，在移位寄存器单元无法正常工作时，显示装置无法进行正常的显示。因此，移位寄存器单元的稳定性要求变高。
发明内容
本公开提供一种移位寄存器单元及其控制方法、包括该移位寄存器单元的栅极驱动装置、以及包括该栅极驱动装置的显示装置，能够提高栅极驱动电路的稳定性，从而可靠地进行显示。
根据本公开的第一方面，提供一种移位寄存器单元。所述移位寄存器单元包括：输入模块，与驱动输入信号输入端、时钟信号输入端、上拉控制节点连接，配置来根据所述驱动输入信号和所述时钟信号来控制所述上拉控制节点的电位；上拉模块，与高电平直流信号输入端、所述上拉控制节点、驱动输出信 号输出端连接，配置来根据所述上拉控制节点的电位对所述驱动输出信号进行上拉；第一下拉控制信号生成模块，与第一信号的输入端、所述驱动输入信号的输入端、所述上拉控制节点、第一下拉控制节点连接，配置来在所述第一信号为高电平期间，根据所述驱动输入信号、所述上拉控制节点的电位来控制所述第一下拉控制节点的电位；第二下拉控制信号生成模块，与第二信号的输入端、所述驱动输入信号输入端、所述上拉控制节点、第二下拉控制节点连接，配置来在第二信号为高电平期间，根据所述驱动输入信号、所述上拉控制节点的电位来控制所述第二下拉控制节点的电位，其中所述第一信号与所述第二信号交替成为高电平；下拉模块，与所述第一下拉控制节点、所述第二下拉控制节点连接，配置来根据所述第一下拉控制节点的电位和所述第二下拉控制节点的电位对所述驱动输出信号进行下拉。
根据本公开的第二方面，提供一种栅极驱动装置。所述栅极驱动装置包括：N个如上所述的移位寄存器单元。其中，N为大于1的自然数。第n个移位寄存器单元的驱动输入信号的输入端与第n-1个移位寄存器单元的驱动输出信号的输出端连接，其中，1<n<＝N。第1个移动寄存器模块的驱动输入信号的输入端与起始信号的输出端连接。
根据本公开的第三方面，提供一种显示装置。所述显示装置包括：显示面板；配置来对显示面板输出驱动输出信号的如上所述的栅极驱动装置。
根据本公开的第四方面，提供一种应用于前述移位寄存器单元的控制方法。所述控制方法包括：根据驱动输入信号和时钟信号来控制上拉控制节点的电位；根据所述上拉控制节点的电位对驱动输出信号进行上拉；在第一信号为高电平期间，根据所述驱动输入信号、所述上拉控制节点的电位来控制第一下拉控制节点的电位；在第二信号为高电平期间，根据所述驱动输入信号、所述上拉控制节点的电位来控制第二下拉控制节点的电位，其中所述第一信号与所述第二信号交替成为高电平；根据所述第一下拉控制节点的电位和所述第二下拉控制节点的电位对所述驱动输出信号进行下拉。
根据本公开的移位寄存器单元及其控制方法、包括该移位寄存器单元的栅极驱动装置、以及包括该栅极驱动装置的显示装置，根据第一信号和第二信号，交替地通过第一下拉控制信号生成模块和第二下拉控制信号生成模块生成用于控制所述下拉模块的下拉控制信号。因此，能够有效地避免第一下拉控制节 点和第二下拉控制节点的占空比过高而导致的下拉模块的老化。由此，能够提高移位寄存器单元、栅极驱动装置和显示装置的稳定性。
附图说明
图1是在本公开中应用的直流(DC)驱动方式的移位寄存器单元的电路图。
图2是图1所示的移位寄存器单元的电路中的各个节点的波形图。
图3是本公开的实施方式的移位寄存器单元的功能框图。
图4是本公开的实施例的移位寄存器单元的具体电路图。
图5是图4所示的移位寄存器单元的电路中的节点的波形图。
图6是图4所示的移位寄存器单元的电路中的节点的波形图。
图7是本公开的实施方式的包括移位寄存器单元的栅极驱动装置的功能框图。
图8是本公开的实施方式的包括栅极驱动装置的显示装置的功能框图。
图9是表示本公开的实施方式的移位寄存器单元的控制方法的流程图。
具体实施方式
下面，参照附图来具体说明本公开的实施方式。提供以下参照附图的描述，以帮助对由权利要求及其等价物所限定的本公开的示例实施方式的理解。其包括帮助理解的各种具体细节，但它们只能被看作是示例性的。因此，本领域技术人员将认识到，可对这里描述的实施方式进行各种改变和修改，而不脱离本公开的范围和精神。而且，为了使说明书更加清楚简洁，将省略对本领域熟知功能和构造的详细描述。
在本公开的实施方式中采用的薄膜晶体管的源极和漏极是对称的，所以其源极和漏极在名称上可以互换。此外，按照薄膜晶体管的特性区分可以将薄膜晶体管分为N型晶体管或P型晶体管。在以下的说明中，以N型晶体管为例展开说明，但是也可以采用P型晶体管。此外，在采用P型晶体管时，本领域技术人员能够根据所采用的晶体管的类型，对各个输入端的输入信号进行相应的调整。
首先，参照图1和图2来说明直流驱动(DC)驱动方式的移位寄存器单元。图1是在发明中应用的直流驱动方式的移位寄存器单元1的电路图。图2是图 1所示的移位寄存器单元1的电路中的各个节点的波形图。
图1所示的移位寄存器单元1包括输入模块11、上拉模块12、下拉控制信号生成模块13和下拉模块14。
输入模块11与驱动输入信号输入端INPUT、时钟信号输入端CLK、上拉控制节点PU连接，配置来根据驱动输入信号INPUT和时钟信号CLK来控制上拉控制节点PU的电位。
具体地，例如，输入模块11可以包括：第一薄膜晶体管T1，其漏极和栅极与驱动输入信号输入端INPUT连接，其源级与上拉控制节点PU连接；第二薄膜晶体管T2，其漏极和栅极与时钟信号输入端CLK连接；电容C1，其一端与第二薄膜晶体管T2的源级连接，其另一端与上拉控制节点PU连接。
在驱动输入信号输入端INPUT的信号为高电平时，第一薄膜晶体管T1被导通。因此，驱动输入信号输入端INPUT的信号传递到上拉控制节点PU。反之，在驱动输入信号输入端INPUT的信号为低电平时，第一薄膜晶体管T1被截止，因此无法向上拉控制节点PU传递驱动输入信号输入端INPUT的信号。
同样，在时钟信号输入端CLK的信号为高电平时，第二薄膜晶体管T2被导通。因此，时钟信号输入端CLK的信号传递到上拉控制节点PU。反之，在时钟信号输入端CLK的信号为低电平时，第二薄膜晶体管T2被截止，因此无法向上拉控制节点PU传递时钟信号输入端CLK的信号。
此外，通过电容C1，在上拉控制节点PU的电位能够被控制为驱动输入信号端INPUT的信号加上时钟信号输入端CLK的信号后的电位。
如图2所示，在第一周期～第二周期中，由于时钟信号输入端CLK的信号为低电平，第二薄膜晶体管T2被截止，因此上拉控制节点PU的电位与驱动输入信号输入端INPUT的信号相同。在第三周期中，由于时钟信号输入端CLK的信号为高电平，第二薄膜晶体管T2被导通，因此上拉控制节点PU的电位在电容C1的作用下被控制为驱动输入信号端INPUT信号加上时钟信号输入端CLK的信号后的电位。根据图2可知，第三周期中的上拉控制节点PU的电位为第二周期中的上拉控制节点PU的电位的两倍。
返回参见图1，上拉模块12与高电平直流信号输入端DCH、上拉控制节点PU、驱动输出信号输出端OUTPUT连接，配置来根据上拉控制节点PU的 电位对驱动输出信号进行上拉。
具体地，例如，上拉模块12可以包括第三薄膜晶体管T3，其漏极与高电平直流信号输入端DCH连接，其栅极与上拉控制节点PU连接，其源级与驱动输出信号输出端OUTPUT连接。
可选择地，第三薄膜晶体管T3构成为，在上拉控制节点PU的电位大于导通电压的情况下被导通。如图2所示，由于第一周期中的上拉控制节点PU的电位小于第三薄膜晶体管T3的导通电压，因此第三薄膜晶体管T3被截止。因此，驱动输出信号输出端OUTPUT的信号为低电平。此外，在第二周期和第三周期中，由于上拉控制节点PU的电位大于等于第三薄膜晶体管T3的导通电压，因此第三薄膜晶体管T3被导通。进而，在连接到第三晶体管T3的漏极的高电平直流信号输入端DCH的信号的作用下，如图2所示，驱动输出信号输出端OUTPUT的电位为上拉控制节点PU的电位的一半。
下拉控制信号生成模块13与高电平直流信号输入端DCH、驱动输入信号输入端INPUT、上拉控制节点PU、下拉控制节点PD连接，配置来根据驱动输入信号、上拉控制节点PU的电位来控制下拉控制节点PD的电位。
具体地，例如，下拉控制信号生成模块13可以包括第十四薄膜晶体管T14、第十五薄膜晶体管T15、第十六薄膜晶体管16。其中，第十四薄膜晶体管T14的漏极和栅极与高电平直流信号输入端DCH连接，其源级与下拉控制节点PD连接。由此，若第十五薄膜晶体管T15或第十六薄膜晶体管T16没有被导通，则下拉控制节点PD保持在高电平。
第十五薄膜晶体管T15的漏极与下拉控制节点PD连接，栅极与驱动输入信号输入端INPUT连接，源级与低电平信号输入端VSS连接。由此，在驱动输入信号输入端INPUT的信号为高电平的情况下，第十五薄膜晶体管T15被导通，由此能够将下拉控制节点PD控制在低电平。此外，第十六薄膜晶体管漏极与下拉控制节点PD连接，栅极与上拉控制节点PU连接，源级与低电平信号输入端VSS连接。由此，在上拉控制节点PU为高电平的情况下，第十六薄膜晶体管T16被导通，由此能够将下拉控制节点PD控制在低电平。
如图2所示，在第一周期～第三周期中，驱动输入信号输入端INPUT的信号成为高电平和/或上拉控制节点PD的信号成为高电平，因此在第一周期～第三周期中，下拉控制节点PD控制在低电平。此外，在其他周期(例如第四周 期)中，驱动输入信号输入端INPUT的信号和上拉控制节点PD的信号都是低电平，第十五薄膜晶体管T15和第十六薄膜晶体管T16的被截止，因此下拉控制节点PD在高电平直流信号的作用下保持在高电平。
此外，在移位寄存器单元1工作期间，由于驱动输入信号输入端INPUT的信号和上拉控制节点PD的信号通常保持在低电平，导致下拉控制节点PD长期保持在低电平，即下拉控制节点PD的占空比非常大(大约99.7％)。当然，该占空比的数值仅仅是举例说明，实际与在栅极驱动装置中包含的移位寄存器单元的数目、栅极驱动装置与显示面板的连接方式等相关。
返回参见图1，下拉模块14与下拉控制节点PD连接，配置来根据下拉控制节点PD的电位对驱动输出信号进行下拉。
具体地，下拉模块14包括第十七薄膜晶体管T17和第十八薄膜晶体管T18。在该实施例中，第十七薄膜晶体管T17的漏极与驱动输出信号输出端OUTPUT连接，源级与低电平信号输入端VSS连接，栅极与下拉控制节点PD连接。由此，在下拉控制节点PD为高电平时，第十七薄膜晶体管T17被导通，因此驱动输出信号输出端OUTPUT能够有效地保持在低电平。
此外，在该实施例中，第十八薄膜晶体管T18的漏极与上拉控制节点PU连接，源级与低电平信号输入端VSS连接，栅极与下拉控制节点PD连接。由此，在下拉控制节点PD为高电平时，第十八薄膜晶体管T18被导通，因此上拉控制节点PU的电位能够有效地保持在低电平。如上所述，在上拉控制节点PU为低电平时，由于上拉控制节点PU的电位小于第三薄膜晶体管T3的导通电压，使得从驱动输出信号输出端OUTPUT的信号有效地保持在低电平。
如图2所示，在除了第一周期～第三周期的其他周期(例如第四周期)中，在下拉模块14的作用下，驱动输出信号输出端OUTPUT的信号有效地保持在低电平。
此外，在该实施例中以下拉模块14同时对上拉控制节点PU和驱动输出信号输出端OUTPUT进行下拉的情况为例进行了说明，但是本公开不限定于此，可以根据需要仅对上拉控制节点PU或驱动输出信号输出端OUTPUT进行下拉。此时，下拉模块14也可以仅包括第十七薄膜晶体管T17或第十八薄膜晶体管T18。
下面，参照图3至图6来说明按照本公开的一些可替换实施方式的移位寄 存器单元。图3是本公开的实施方式的移位寄存器单元的功能框图。图4是本公开的一种示例性实施例的移位寄存器单元的电路图。
如图3所示，按照本公开的一种实施方式的移位寄存器单元2包括输入模块21、上拉模块22、第一下拉控制信号生成模块23、第二下拉控制信号生成模块24和下拉模块25。其中，通过配置多个本公开的实施方式的移位寄存器单元2，可以构成显示装置中的栅极驱动装置。
在图3中，输入模块21与驱动输入信号输入端INPUT、时钟信号输入端CLK、上拉控制节点PU连接，配置来根据驱动输入信号INPUT和时钟信号CLK来控制上拉控制节点PU的电位。
参照图4，输入模块21可以包括第一薄膜晶体管T1、第二薄膜晶体管T2、电容C1。其中，第一薄膜晶体管T1、第二薄膜晶体管T2、电容C1的连接结构与图2相同，在此不进行重复的说明。
通过第一薄膜晶体管T1、第二薄膜晶体管T2，能够将驱动输入信号和时钟信号传递到上拉控制节点PU。此外，通过电容C1，在上拉控制节点PU的电位能够被控制为等于驱动输入信号输入端INPUT的信号加上时钟信号输入端CLK的信号后的电位。
下面参照图5的波形图来描述图4所示的移位寄存器单元的电路的工作过程。在第一周期～第二周期中，由于时钟信号输入端CLK的信号为低电平，第二薄膜晶体管T2被截止，因此上拉控制节点PU的电位与驱动输入信号输入端INPUT的信号相同。在第三周期中，由于时钟信号输入端CLK的信号为高电平，第二薄膜晶体管T2被导通，因此上拉控制节点T4的电位在电容C1的作用下被控制为等于驱动输入信号输入端INPUT的信号加上时钟信号输入端CLK的信号后的电位。根据图5可知，第三周期中的上拉控制节点PU的电位为第二周期中的上拉控制节点PU的电位的两倍。在本公开的实施方式的描述中，为了方便说明，以驱动输入信号成为高电平的起始周期称为第一周期。
在这里，本公开的实施方式的输入模块21不限定于图4所示的结构，也可以采用其他的结构。例如，通过其他的元件(例如二极管)等构成输入模块21，也可以以其他的连接方式构成输入模块21，只要输入模块21能够将驱动输入信号输入端INPUT的信号和时钟信号输入端CLK的信号传递到上拉控制节点即可。
此外，如图4所示构成输入模块21的情况下，可选择地，在第一周期～第二周期中，驱动输入信号成为高电平，然后在第三周期中，从时钟信号输入端CLK输入的信号成为高电平。即，时钟信号成为高电平的期间被设置为紧随驱动输入信号成为高电平的期间。由此，能够通过下述的上拉模块22，方便地生成对驱动输入信号进行移位后的驱动输出信号。
上拉模块22与高电平直流信号输入端DCH、上拉控制节点PU、驱动输出信号输出端OUTPUT连接，配置来根据上拉控制节点PU的电位对驱动输出信号进行上拉。参照图4，上拉模块22例如包括第三薄膜晶体管T3。其中，第三薄膜晶体管T3的连接结构与图2相同，在此不进行重复的说明。
通过第三薄膜晶体管T3，根据上拉控制节点PU的电位而从驱动输出信号输出端OUTPUT输出对驱动输入信号移位后的驱动输出信号。例如，第三薄膜晶体管T3可以构成为，在上拉控制节点PU的电位大于导通电压的情况下导通。如图5所示，由于第一周期中的上拉控制节点PU的电位小于第三薄膜晶体管T3的导通电压，因此第三薄膜晶体管T3截止。因此，驱动输出信号输出端OUTPUT的信号为低电平。此外，在第二周期和第三周期中，由于上拉控制节点PU的电位大于等于第三薄膜晶体管T3的导通电压，因此第三薄膜晶体管T3导通。进而，在连接到第三晶体管T3的漏极的高电平直流信号输入端DCH的信号的作用下，如图5所示，从驱动输出信号输出端OUTPUT输出的电位为上拉控制节点PU的电位的一半。
在这里，本公开的实施方式的上拉模块22不限定于图4所示的结构，也可以采用其他的结构。例如，通过其他的元件(例如二极管)等构成上拉模块，也可以以其他的连接方式构成上拉模块22，只要上拉模块22能够根据上拉控制节点PU的电位而从驱动输出信号的输出端OUTPUT输出对驱动输入信号移位后的驱动输出信号即可。
例如，在图4所示的上拉模块22中，第三薄膜晶体管T3的导通电压被设置为大于第一周期中的上拉控制节点PU的电位，从而实现了对驱动输出信号进行移位的功能。但是，也可以通过其他的方式或电路，根据上拉控制节点PU的电位而生成适当的驱动输出信号。再如，在图4所示的上拉模块中，通过将上拉控制节点PU连接到驱动输出信号输出端OUTPUT，从而能够在第二周期和第三周期中得到其电位为上拉控制节点PU的电位的一半的驱动输出信 号。当然，也可以在上拉控制节点PU与驱动输出信号的输出端OUTPUT之间设置电容，从而根据上拉控制节点PU的电位而生成适当的驱动输出信号。
此外，在结合图1和图2说明的移位寄存器单元1中，下拉控制节点PD的占空比非常大，长期处于高电平。由此，构成下拉模块16的薄膜晶体管(例如，第十七薄膜晶体管T17)长期处于导通的状态，从而导致构成下拉模块16的薄膜晶体管容易产生老化。在构成下拉模块16的薄膜晶体管老化时，移位寄存器单元1的稳定性无法得到保障，进而对栅极驱动装置、以及显示装置的工作稳定性也带来不良影响。
相对于此，在本公开的图3所示的实施方式中，采用第一下拉控制信号生成模块23、第二下拉控制信号生成模块24来分别生成下拉控制信号，并且下拉模块25在由第一下拉控制信号生成模块23、第二下拉控制信号生成模块24分别生成的下拉控制信号的控制下对驱动输出信号进行下拉。从而，能够有效地避免下拉控制节点的电位的占空比过大，从而能够避免构成下拉模块25的薄膜晶体管处于长期导通的状态。由此，能够避免构成下拉模块25的薄膜晶体管快速老化，增加了移位寄存器单元2的稳定性。
如图3所示，第一下拉控制信号生成模块23与第一信号输入端DC1、驱动输入信号输入端INPUT、上拉控制节点PU、第一下拉控制节点PD1连接，配置来在第一信号DC1为高电平期间，根据驱动输入信号、上拉控制节点的电位来控制第一下拉控制节点PD1的电位。
例如，参考图4，第一下拉控制信号生成模块23可以包括第四薄膜晶体管T4、第五薄膜晶体管T5和第六薄膜晶体管T6。其中，第四薄膜晶体管T4的漏极和栅极与第一信号输入端DC1连接，源级与第一下拉控制节点PD1连接；第五薄膜晶体管T5的漏极与第一下拉控制节点PD1连接，栅极与驱动输入信号的输入端INPUT连接，源级与低电平信号输入端VSS连接；第六薄膜晶体管T6的漏极与第一下拉控制节点PD1连接，栅极与上拉控制节点PU连接，源级与低电平信号输入端VSS连接。
由此，在本公开的实施方式中，在第一信号DC1为高电平时，第四薄膜晶体管T4导通，从而在第五薄膜晶体管T5和第六薄膜晶体管T6截止的情况下，将第一下拉控制节点PD1保持在高电平。在第一信号DC1为高电平期间，在驱动输入信号输入端INPUT的信号为高电平的情况下，第五薄膜晶体管T5 导通，由此能够将第一下拉控制节点PD1控制在低电平。同样，在第一信号为高电平期间，在上拉控制节点PU为高电平的情况下，第六薄膜晶体管T6导通，由此能够将第一下拉控制节点PD1控制在低电平。
在图5中，以第一信号DC1为高电平的情形为例表示了各个节点的波形。参考图5，在第一周期～第三周期中，驱动输入信号输入端INPUT的信号成为高电平和/或上拉控制节点PD的信号成为高电平，因此在第一周期～第三周期中，第一下拉控制节点PD1控制在低电平。此外，在其他周期(例如第四周期)中，驱动输入信号输入端INPUT的信号和上拉控制节点PD的信号都是低电平，第五薄膜晶体管T5和第六薄膜晶体管T6截止，因此第一下拉控制节点PD1在高电平直流信号的作用下保持在高电平。
在这里，本公开的实施方式的第一下拉控制信号生成模块23不限定于图4所示的结构，也可以采用其他的结构。例如，通过其他的元件(例如二极管)等构成第一下拉控制信号生成模块23，也可以以其他的连接方式构成第一下拉控制信号生成模块23，只要第一下拉控制信号生成模块23在第一信号DC1为高电平期间，根据驱动输入信号、上拉控制节点的电位来控制第一下拉控制节点PD1的电位即可。
第二下拉控制信号生成模块24与第二信号输入端DC2、驱动输入信号输入端INPUT、上拉控制节点PU、第二下拉控制节点PD2连接，配置来在第二信号DC2为高电平期间，根据驱动输入信号、上拉控制节点的电位来控制第二下拉控制节点的电位。
例如，参考图4，第二下拉控制信号生成模块24包括第七薄膜晶体管T7、第八薄膜晶体管T8、第九薄膜晶体管T9。其中，第七薄膜晶体管T7的漏极和栅极与第二信号输入端DC2连接，源级与第二下拉控制节点PD2连接；第八薄膜晶体管T8的漏极与第二下拉控制节点PD2连接，栅极与驱动输入信号输入端INPUT连接，其源级与低电平信号输入端VSS连接；第九薄膜晶体管T9的漏极与第二下拉控制节点PD2连接，栅极与上拉控制节点PU连接，源级与低电平信号输入端VSS连接。
由此，在本公开的实施方式中，在第二信号DC2为高电平时，第七薄膜晶体管T7导通，从而在第八薄膜晶体管T8和第九薄膜晶体管T9截止的情况下，将第二下拉控制节点PD2保持在高电平。在第二信号DC2为高电平期间， 在驱动输入信号输入端INPUT的信号为高电平的情况下，第八薄膜晶体管T8导通，由此能够将第二下拉控制节点PD2控制在低电平。同样，在第二电平为高电平期间，在上拉控制节点PU为高电平的情况下，第九薄膜晶体管T9导通，由此能够将第二下拉控制节点PD2控制在低电平。
在图5所示的波形图中，以第一信号DC1为高电平且第二信号DC2为低电平的情形为例，表示了各个节点的波形。参考图5，由于第二信号DC2为低电平，第七薄膜晶体管T7截止，因此第二下拉控制节点PD2保持在低电平。假设第二信号DC2为高电平的情况下，第二下拉控制节点PD2与第一下拉控制节点PD1相同地，在第一周期～第三周期中成为低电平，在其他周期(例如第四周期)中保持在高电平。
在这里，本公开的实施方式的第二下拉控制信号生成模块24不限定于图4所示的结构，也可以采用其他的结构。例如，通过其他的元件(例如二极管)等构成第二下拉控制信号生成模块24，也可以以其他的连接方式构成第二下拉控制信号生成模块24，只要第二下拉控制信号生成模块24在第二信号DC2为高电平期间，根据驱动输入信号、上拉控制节点的电位来控制第二下拉控制节点PD2的电位即可。
在本公开的实施方式中，第一信号DC1与第二信号DC2交替成为高电平。具体地，如图6所示，在第一信号DC1处于高电平的时刻，第二信号DC2处于低电平。相反，在第一信号DC1处于低电平的时刻，第二信号DC2处于高电平。在图6中，以第一信号DC1和第二信号DC2的占空比分别为50％为例，图示了第一信号DC1和第二信号DC2的波形。但是，在本公开的实施方式中，也可以对第一信号DC1和第二信号DC2的占空比进行调整，只要能够保证第一信号DC1与第二信号DC2交替成为高电平。
如上所述，第一下拉控制信号生成模块23在第一信号为高电平的期间进行动作，第二下拉控制信号生成模块24在第二信号为高电平的期间进行动作，因此在第一信号DC1与第二信号DC2交替成为高电平的情况下，第一下拉控制信号生成模块23和第二下拉控制信号生成模块24交替地进行动作。
为了确保第一下拉控制信号生成模块23和第二下拉控制信号生成模块24交替地进行动作，在本公开的实施方式中可选择地，第一下拉控制信号生成模块23包括第十薄膜晶体管T10，第二下拉控制信号生成模块24包括第十一薄 膜晶体管T11。
参考图4，第十薄膜晶体管T10漏极与第一下拉控制节点PD1连接，栅极与第二下拉控制节点PD2连接，源级与低电平信号输入端VSS连接。第十一薄膜晶体管T11的漏极与第二下拉控制节点PD2连接，栅极与第一下拉控制节点PD1连接，源级与低电平信号输入端VSS连接。
由此，在第二信号成为高电平而第二下拉控制节点PD2成为高电平时，第十薄膜晶体管T10导通，同时第二下拉控制信号生成模块24进行工作。在第十薄膜晶体管T10导通时，能够有效地将第一下拉控制节点PD1保持在低电平，从而保证第一下拉控制信号生成模块23不进行工作。同样，在第一信号成为高电平而第一下拉控制节点PD1成为高电平时，第十一薄膜晶体管T11导通，同时第一下拉控制信号生成模块23进行工作。在第十薄膜晶体管T11导通时，能够有效地将第二下拉控制节点PD2保持在低电平，从而保证第二下拉控制信号生成模块24不进行工作。
如上所述，第一下拉控制信号生成模块23包括第十薄膜晶体管T10，第二下拉控制信号生成模块24包括第十一薄膜晶体管T11，从而能够在第一信号DC1和第二信号DC2交替成为高电平时，可靠地保证第一下拉控制信号生成模块23和第二下拉控制信号生成模块24交替地进行工作。
下拉模块25与第一下拉控制节点PD1、第二下拉控制节点PD2连接，配置来根据第一下拉控制节点的电位和第二下拉控制节点的电位对驱动输出信号进行下拉。
参考图4，下拉模块25包括第十二薄膜晶体管T12。第十二薄膜晶体管T12的漏极与驱动输出信号的输出端OUTPUT连接，源级与低电平信号输入端VSS连接，第一栅极与第一下拉控制节点PD1连接，第二栅极与第二下拉控制节点PD2连接。其中，第十二薄膜晶体管T12为双栅极型的薄膜晶体管，因此在第一栅极或第二栅极施加了高电平的情况下，第十二薄膜晶体管T12导通。
具体地，在图4所示的结构中，在第一下拉控制节点PD1成为高电平或者第二下拉控制节点PD2成为高电平的情况下，第十二薄膜晶体管T12导通，从而驱动输出信号的输出端OUTPUT能够有效地保持在低电平。
例如，如图5所示的波形图所示，在除了第一周期～第三周期的其他周期 (例如第四周期)中，第一下拉控制节点PD1为高电平，因此在下拉模块25的作用下，驱动输出信号输出端OUTPUT的信号有效地保持在低电平。
如上所述，虽然第一下拉控制信号生成模块23和第二下拉控制信号生成模块24交替地进行工作，但是下拉模块25能够同时根据第一下拉控制节点PD1的电位和第二下拉控制节点的电位对驱动输出信号进行下拉，因此能够有效地对驱动输出信号进行下拉。即，下拉模块25在第一下拉控制节点PD1成为高电平或者第二下拉控制节点PD2成为高电平的情况下，对驱动输出信号进行下拉，因此在第一信号DC1为高电平期间按照第一下拉控制节点PD1进行下拉动作，在第二信号DC2为高电平期间按照第二下拉控制节点PD2进行下拉动作。
此外，本公开的实施方式的下拉模块25不限定于图4所示的结构，也可以采用其他的结构，只要下拉模块25能够根据第一下拉控制节点的电位和第二下拉控制节点的电位对驱动输出信号进行下拉即可。
可选择地，本公开的实施方式的下拉模块25还包括第十三薄膜晶体管T13。参考图4，第十三薄膜晶体管T13的漏极与上拉控制节点PU连接，源级与低电平信号输入端VSS连接，第一栅极与第一下拉控制节点PD1连接，第二栅极与第二下拉控制节点PD2连接。
具体地，在第一下拉控制节点PD1为高电平或者第二下拉控制节点PD2为高电平时，第十三薄膜晶体管T13导通，因此上拉控制节点PU的电位能够有效地保持在低电平。如上所述，在上拉控制节点PU为低电平时，由于上拉控制节点PU的电位小于第三薄膜晶体管T3的导通电压，使得从驱动输出信号的输出端OUTPUT的信号有效地保持在低电平。
如上所述，根据本公开的实施方式的移位寄存器单元2，由于第一信号DC1与第二信号DC2交替地成为高电平，从而第一下拉控制信号生成模块23和第二下拉控制信号生成模块交替地对第一下拉控制节点PD1和第二下拉控制节点PD2进行控制。然后，下拉模块25能够根据第一下拉控制节点PD1和第二下拉控制节点PD2，对驱动输出信号进行下拉。即，在第一信号为高电平期间，下拉模块25能够按照第一下拉控制节点PD1的电位对驱动输出信号进行下拉，在第二信号为高电平期间，能够按照第二下拉控制节点PD2的电位对驱动输出信号进行下拉。
由此，在本公开的实施方式中，第一下拉控制节点PD1在第二信号DC2成为高电平期间处于低电平，因此第一下拉控制节点的PD1占空比能够控制成不会特别大。例如，第一下拉控制节点PD1的占空比略小于第一信号DC1的占空比，在例如图6所示的情况下为约等于50％。同样第二下拉控制节点PD2在第一信号DC1为高电平期间处于低电平，因此第二下拉控制节点PD2的占空比能够控制成不会特别大。例如，第二下拉控制节点PD2的占空比略小于第二信号DC1的占空比，在图6所示的情况下为约等于50％。从而，能够避免构成如图4构成的下拉模块25的双极型薄膜晶体管的某个PN结长期处于导通状态，能够避免薄膜晶体管快速老化。由此，能够提高移位寄存器单元、栅极驱动装置和显示装置的稳定性。
下面，参照图7来说明本公开的实施方式的栅极驱动装置。图7示出了本公开的实施方式的包括移位寄存器单元的栅极驱动装置的功能框图。
如图7所示，本公开的实施方式的栅极驱动装置包括N个移位寄存器单元。其中，N为大于1的自然数。并且，栅极驱动装置所包括的每个移位寄存器单元可以采用如上所述的结构。
在图7所示的栅极驱动装置的结构中，第n个移位寄存器单元的驱动输入信号的输入端与第n-1个移位寄存器单元的驱动输出信号的输出端连接。其中，1<n<＝N。即，第n-1个移位寄存器单元的驱动输出信号作为驱动输入信号输入到第n个移位寄存器单元。此外，第1个移动寄存器模块的驱动输入信号的输入端与起始信号的输出端连接。
由此，从第1个～第N个移位寄存器单元输出的驱动输出信号依次成为，从起始信号按周期移位后的驱动输出信号。
此外，在图7所示的栅极驱动装置所包括的各个移位寄存器单元中，分别接收第一信号、第二信号以及高电平直流信号，从而根据所接收的上述信号而输出对驱动输入信号移位后的驱动输出信号。
下面，参照图8来说明本公开的实施方式的包括栅极驱动装置的显示装置的功能框图。图8是本公开的实施方式的包括栅极驱动装置的显示装置的功能框图。
如图8所示，显示装置包括显示面板、栅极驱动装置。此外，在图8所示的显示装置中，可以根据需要而设置其他的装置。例如，如图8所示，显示装 置还可以包括数据驱动装置。
图8的显示装置所包括的栅极驱动装置可以采用图7所示的结构。栅极驱动装置所包括的各个移位寄存器单元配置来对显示面板的像素区域的对应的行的薄膜晶体管进行导通/截止。具体地，当移位寄存器单元所输出的驱动输出信号成为高电平时，对所对应的行的薄膜晶体管进行导通。由于各个移位寄存器单元依次输出移位后的驱动输出信号，因此在显示面板中各个行的薄膜晶体管依次被导通，从而被导通的薄膜晶体管能够按照数据驱动装置输出的信号而进行亮度等的控制。
图9是表示本公开的实施方式的移位寄存器单元的控制方法的流程图。下面，参照图9来说明本公开的实施方式的应用于移位寄存器单元的控制方法。
在步骤S1中，根据驱动输入信号和时钟信号来控制上拉控制节点的电位。
具体地，在应用于图2所示的移位寄存器单元2的情况下，输入模块21与驱动输入信号输入端INPUT、时钟信号输入端CLK、上拉控制节点PU连接，配置来根据驱动输入信号INPUT和时钟信号CLK来控制上拉控制节点PU的电位。例如，输入模块21可以包括第一薄膜晶体管T1、第二薄膜晶体管T2、电容C1。
通过第一薄膜晶体管T1、第二薄膜晶体管T2，能够将驱动输入信号和时钟信号传递到上拉控制节点PU。此外，通过电容C1，在上拉控制节点PU的电位能够被控制为驱动输入信号端INPUT的信号加上时钟信号CLK的信号后的电位。
在步骤S2中，根据上拉控制节点的电位对驱动输出信号进行上拉。
具体地，在应用于图2所示的移位寄存器单元2的情况下，上拉模块22与高电平直流信号输入端DCH、上拉控制节点PU、驱动输出信号输出端OUTPUT连接，配置来根据上拉控制节点PU的电位对驱动输出信号进行上拉。例如，上拉模块22包括第三薄膜晶体管T3。
通过第三薄膜晶体管T3，根据上拉控制节点PU的电位，从驱动输出信号输出端OUTPUT输出对驱动输入信号移位后的驱动输出信号。例如，将第三薄膜晶体管T3构成为，在上拉控制节点PU的电位大于导通电压的情况下导通。如图5所示，由于第一周期中的上拉控制节点PU的电位小于第三薄膜晶体管T3的导通电压，因此第三薄膜晶体管T3截止。因此，从驱动输出信 号输出端OUTPUT输出的信号为低电平。此外，在第二周期和第三周期中，由于上拉控制节点PU的电位大于等于第三薄膜晶体管T3的导通电压，因此第三薄膜晶体管T3导通。进而，在连接到第三晶体管T3的漏极的高电平直流信号的输入端DCH的信号的作用下，如图5所示，驱动输出信号输出端OUTPUT的电位为上拉控制节点PU的电位的一半。
在步骤S3中，在第一信号为高电平期间，根据所述驱动输入信号、所述上拉控制节点的电位来控制第一下拉控制节点的电位。
具体地，在应用于图2所示的移位寄存器单元2的情况下，第一下拉控制信号生成模块23与第一信号的输入端DC1、驱动输入信号输入端INPUT、上拉控制节点PU、第一下拉控制节点PD1连接，配置来在第一信号DC1为高电平期间，根据驱动输入信号、上拉控制节点的电位来控制第一下拉控制节点PD1的电位。
例如，第一下拉控制信号生成模块23包括第四薄膜晶体管T4、第五薄膜晶体管T5和第六薄膜晶体管T6。在第一信号为高电平时，第四薄膜晶体管T4导通，从而在第五薄膜晶体管T5和第六薄膜晶体管T6截止的情况下，将第一下拉控制节点PD1保持在高电平。在第一信号为高电平期间，在驱动输入信号的输入端INPUT的信号为高电平的情况下，第五薄膜晶体管T5导通，由此能够将第一下拉控制节点PD1控制在低电平。同样，在第一信号为高电平期间，在上拉控制节点PU为高电平的情况下，第六薄膜晶体管T6导通，由此能够将第一下拉控制节点PD1控制在低电平。
在步骤S4中，在第二信号为高电平期间，根据所述驱动输入信号、所述上拉控制节点的电位来控制第二下拉控制节点的电位。
具体地，在应用于图2所示的移位寄存器单元2的情况下，第二下拉控制信号生成模块24与第二信号的输入端DC2、驱动输入信号输入端INPUT、上拉控制节点PU、第二下拉控制节点PD2连接，配置来在第二信号DC2为高电平期间，根据驱动输入信号、上拉控制节点的电位来控制第二下拉控制节点的电位。
第二下拉控制信号生成模块24包括第七薄膜晶体管T7、第八薄膜晶体管T8、第九薄膜晶体管T9。在第二信号为高电平时，第七薄膜晶体管T7导通，从而在第八薄膜晶体管T8和第九薄膜晶体管T9截止的情况下，将第二下拉 控制节点PD2保持在高电平。在第二信号为高电平期间，在驱动输入信号输入端INPUT的信号为高电平的情况下，第八薄膜晶体管T8导通，由此能够将第二下拉控制节点PD2控制在低电平。同样，在第二电平为高电平期间，在上拉控制节点PU为高电平的情况下，第九薄膜晶体管T9导通，由此能够将第二下拉控制节点PD2控制在低电平。
在本公开的实施方式中，第一信号与第二信号交替成为高电平。具体地，如图6所示，在第一信号DC1处于高电平的时刻，第二信号DC2处于低电平。相反，在第一信号DC1处于低电平的时刻，第二信号DC2处于高电平。在图2所示的移位寄存器单元2的情况下，第一下拉控制信号生成模块23在第一信号为高电平的期间进行动作，第二下拉控制信号生成模块24在第二信号为高电平的期间进行动作，因此在第一信号DC1与第二信号DC2交替成为高电平的情况下，第一下拉控制信号生成模块23和第二下拉控制信号生成模块24交替地进行动作。
在步骤S5中，根据第一下拉控制节点的电位和第二下拉控制节点的电位对所述驱动输出信号进行下拉。
具体地，在应用于图2所示的移位寄存器单元2的情况下，下拉模块25与第一下拉控制节点PD1、第二下拉控制节点PD2连接，配置来根据第一下拉控制节点的电位和第二下拉控制节点的电位对驱动输出信号进行下拉。例如，下拉模块25包括第十二薄膜晶体管T12。在第一下拉控制节点PD1成为高电平或者第二下拉控制节点PD2成为高电平的情况下，第十二薄膜晶体管T12被导通，从而驱动输出信号输出端OUTPUT能够有效地保持在低电平。例如，如图5所示的波形图所示，在除了第一周期～第三周期的其他周期(例如第四周期)中，第一下拉控制节点PD1为高电平，因此在下拉模块25的作用下，驱动输出信号的输出端OUTPUT的信号有效地保持在低电平。
由此，下拉模块25能够同时根据第一下拉控制节点PD1的电位和第二下拉控制节点的电位对驱动输出信号进行下拉，因此能够有效地对驱动输出信号进行下拉。即，下拉模块25在第一下拉控制节点PD1成为高电平或者第二下拉控制节点PD2成为高电平的情况下，对驱动输出信号进行下拉，因此在第一信号为高电平期间按照第一下拉控制节点PD1进行下拉动作，在第二信号为高电平期间按照第二下拉控制节点PD2进行下拉动作。
此外，下拉模块25还可以包括第十三薄膜晶体管T13。在第一下拉控制节点PD1为高电平或者第二下拉控制节点PD2为高电平时，第十三薄膜晶体管T13导通，因此上拉控制节点PU的电位能够有效地保持在低电平。在上拉控制节点PU为低电平时，由于上拉控制节点PU的电位小于第三薄膜晶体管T3的导通电压，使得从驱动输出信号的输出端OUTPUT的信号有效地保持在低电平。
根据本公开的实施方式的控制方法，由于第一信号与第二信号交替地成为高电平，从而能够交替地对第一下拉控制节点和第二下拉控制节点进行控制。然后，根据第一下拉控制节点和第二下拉控制节点，对驱动输出信号进行下拉。即，在第一信号为高电平期间，能够按照第一下拉控制节点的电位对驱动输出信号进行下拉，在第二信号为高电平期间，能够按照第二下拉控制节点的电位对驱动输出信号进行下拉。
由此，在本公开的实施方式中，第一下拉控制节点在第二信号成为高电平期间处于低电平，因此第一下拉控制节点的占空比能够控制成不会特别大。同样第二下拉控制节点PD2在第一信号DC1为高电平期间处于低电平，因此第二下拉控制节点的占空比能够控制成不会特别大。从而，能够避免构成如图4构成的下拉模块25的双极型薄膜晶体管的某个PN结长期处于导通状态，能够避免薄膜晶体管快速老化。由此，能够提高移位寄存器单元、栅极驱动装置和显示装置的稳定性。
在上面详细描述了本公开的各个实施方式。然而，本领域技术人员应该理解，在不脱离本公开的原理和精神的情况下，可对这些实施方式进行各种修改，组合或子组合，并且这样的修改应落入本公开的范围内。
本申请要求于2015年10月20日递交的中国专利申请第201510684372.5号的优先权，在此全文引用该中国专利申请公开的内容作为本申请的一部分。

Claims (12)

  1. 一种移位寄存器单元，包括：
    输入模块，与驱动输入信号输入端、时钟信号输入端、上拉控制节点连接，配置来根据所述驱动输入信号和所述时钟信号来控制所述上拉控制节点的电位；
    上拉模块，与高电平直流信号输入端、所述上拉控制节点、驱动输出信号输出端连接，配置来根据所述上拉控制节点的电位对所述驱动输出信号进行上拉；
    第一下拉控制信号生成模块，与第一信号输入端、所述驱动输入信号输入端、所述上拉控制节点、第一下拉控制节点连接，配置来在所述第一信号为高电平期间，根据所述驱动输入信号、所述上拉控制节点的电位来控制所述第一下拉控制节点的电位；
    第二下拉控制信号生成模块，与第二信号输入端、所述驱动输入信号输入端、所述上拉控制节点、第二下拉控制节点连接，配置来在第二信号为高电平期间，根据所述驱动输入信号、所述上拉控制节点的电位来控制所述第二下拉控制节点的电位，其中所述第一信号与所述第二信号交替成为高电平；
    下拉模块，与所述第一下拉控制节点、所述第二下拉控制节点连接，配置来根据所述第一下拉控制节点的电位和所述第二下拉控制节点的电位对所述驱动输出信号进行下拉。
  2. 如权利要求1所述的移位寄存器单元，其中，
    所述输入模块包括：
    第一薄膜晶体管，其漏极和栅极与所述驱动输入信号的输入端连接，其源级与所述上拉控制节点连接；
    第二薄膜晶体管，其漏极和栅极与所述时钟信号的输入端连接；
    电容，其一端与所述第二薄膜晶体管的源级连接，其另一端与所述上拉控制节点连接。
  3. 如权利要求1所述的移位寄存器单元，其中，
    所述上拉模块包括：
    第三薄膜晶体管，其漏极与所述高电平直流信号的输入端连接，其栅极与所述上拉控制节点连接，其源级与所述驱动输出信号的输出端连接。
  4. 如权利要求1所述的移位寄存器单元，其中，
    第一下拉控制信号生成模块包括：
    第四薄膜晶体管，其漏极和栅极与所述第一信号的输入端连接，其源级与所述第一下拉控制节点连接；
    第五薄膜晶体管，其漏极与所述第一下拉控制节点连接，其栅极与驱动输入信号的输入端连接，其源级与低电平信号输入端连接；
    第六薄膜晶体管，其漏极与所述第一下拉控制节点连接，其栅极与所述上拉控制节点连接，其源级与低电平信号输入端连接。
  5. 如权利要求1-4之一所述的移位寄存器单元，其中，
    第二下拉控制信号生成模块包括：
    第七薄膜晶体管，其漏极和栅极与第二信号的输入端连接，其源级与所述第二下拉控制节点连接；
    第八薄膜晶体管，其漏极与所述第二下拉控制节点连接，其栅极与驱动输入信号的输入端连接，其源级与低电平信号输入端连接；
    第九薄膜晶体管，其漏极与所述第二下拉控制节点连接，其栅极与所述上拉控制节点连接，其源级与低电平信号输入端连接。
  6. 如权利要求4所述的移位寄存器单元，其中，
    第一下拉控制信号生成模块还包括：
    第十薄膜晶体管，其漏极与所述第一下拉控制节点连接，其栅极与所述第二下拉控制节点连接，其源级与低电平信号输入端连接。
  7. 如权利要求5所述的移位寄存器单元，其中，
    第二下拉控制信号生成模块还包括：
    第十一薄膜晶体管，其漏极与所述第二下拉控制节点连接，其栅极与所述第一下拉控制节点连接，其源级与低电平信号输入端连接。
  8. 如权利要求1所述的移位寄存器单元，其中，
    所述下拉模块包括：
    第十二薄膜晶体管，其漏极与驱动输出信号的输出端连接，其源级与低电平信号输入端连接，其第一栅极与所述第一下拉控制节点连接，其第二栅极与 所述第二下拉控制节点连接。
  9. 如权利要求8所述的移位寄存器单元，其中，
    所述下拉模块包括：
    第十三薄膜晶体管，其漏极与所述上拉控制节点连接，其源级与低电平信号输入端连接，其第一栅极与所述第一下拉控制节点连接，其第二栅极与所述第二下拉控制节点连接。
  10. 一种栅极驱动装置，其中，
    所述栅极驱动装置包括：
    N个如权利要求1至9的任一项所述的移位寄存器单元，
    其中，N为大于1的自然数，
    第n个移位寄存器单元的驱动输入信号的输入端与第n-1个移位寄存器单元的驱动输出信号的输出端连接，其中，1<n<＝N，
    第1个移动寄存器模块的驱动输入信号的输入端与起始信号的输出端连接。
  11. 一种显示装置，包括：
    显示面板；
    如权利要求9所述的栅极驱动装置，配置来对显示面板输出驱动输出信号。
  12. 一种控制方法，应用于如权利要求1-9之一所述的移位寄存器单元，所述控制方法包括：
    根据驱动输入信号和时钟信号来控制上拉控制节点的电位；
    根据所述上拉控制节点的电位对驱动输出信号进行上拉；
    在第一信号为高电平期间，根据所述驱动输入信号、所述上拉控制节点的电位来控制第一下拉控制节点的电位；
    在第二信号为高电平期间，根据所述驱动输入信号、所述上拉控制节点的电位来控制第二下拉控制节点的电位，其中所述第一信号与所述第二信号交替成为高电平；
    根据所述第一下拉控制节点的电位和所述第二下拉控制节点的电位对所述驱动输出信号进行下拉。
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