WO2018196291A1 - 移位寄存器单元及其驱动方法、移位寄存器以及显示装置 - Google Patents
移位寄存器单元及其驱动方法、移位寄存器以及显示装置 Download PDFInfo
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
Definitions
- the present disclosure relates to the field of display technologies, and in particular, to a shift register unit and a driving method thereof, a shift register, and a display device.
- OLED organic light emitting diode
- One common shift register circuit is the gate drive circuit.
- the gate driving circuit sequentially outputs a gate scan signal to a gate line connected to each row of pixels.
- the gate scan signal controls the pixel drive circuit to drive the OLED to emit light. Since the threshold voltage of the driving transistor in the pixel driving circuit may drift with time, the pixel driving circuit usually compensates the threshold voltage in the light-emitting preparation stage of the OLED so that the current flowing through the OLED is independent of the threshold voltage.
- Another shift register circuit can be used to control the illumination time and timing of the OLED during the control of the pixel drive circuit.
- the embodiments described herein provide a shift register unit whose output signal has a duty ratio adjustable and a simple circuit structure, a driving method thereof, a shift register, and a display device.
- a shift register unit includes an input circuit, a first control circuit, a second control circuit, a first hold circuit, a second hold circuit, and an output circuit.
- the input circuit is configured to be based on input signals from the input
- the voltage of the first node is controlled from the first clock signal of the first clock signal terminal.
- the first control circuit is configured to control the voltage of the second node based on the first voltage from the first voltage terminal, the first clock signal, and the voltage of the first node.
- the second control circuit is configured to control the voltage of the third node based on the voltage of the second node and the second clock signal from the second clock signal terminal.
- the first hold circuit is configured to maintain the voltage of the first node based on the second voltage from the second voltage terminal and the voltage of the third node.
- the second hold circuit is configured to maintain the voltages of the second node and the third node.
- the output circuit is configured to output the first voltage or the second voltage from the output under the control of the voltages of the first node and the third node.
- the input circuit includes a first transistor.
- the first transistor of the first transistor is coupled to the input terminal, and the second electrode of the first transistor is coupled to the first node.
- the first control circuit includes a second transistor and a third transistor.
- the control electrode of the second transistor is coupled to the first clock signal terminal, the first electrode of the second transistor is coupled to the first voltage terminal, and the second electrode of the second transistor is coupled to the second node.
- the control electrode of the third transistor is coupled to the first node, the first electrode of the third transistor is coupled to the first clock signal terminal, and the second electrode of the third transistor is coupled to the second node.
- the second control circuit includes a fourth transistor.
- the control electrode of the fourth transistor is coupled to the second node, the first electrode of the fourth transistor is coupled to the second clock signal terminal, and the second electrode of the fourth transistor is coupled to the third node.
- the first holding circuit includes a first capacitor and a fifth transistor.
- the first end of the first capacitor is coupled to the second voltage end, and the second end of the first capacitor is coupled to the first node.
- the control electrode of the fifth transistor is coupled to the third node, the first electrode of the fifth transistor is coupled to the second voltage terminal, and the second electrode of the fifth transistor is coupled to the first node.
- the second holding circuit includes a second capacitor.
- the first end of the second capacitor is coupled to the second node, and the second end of the second capacitor is coupled to the third node.
- the second holding circuit further includes a third capacitor.
- the first end of the third capacitor is coupled to the third node, and the second end of the third capacitor is coupled to the second voltage end.
- the output circuit includes a sixth transistor and a seventh transistor.
- Sixth The control electrode of the transistor is coupled to the first node, the first electrode of the sixth transistor is coupled to the first voltage terminal, and the second electrode of the sixth transistor is coupled to the output terminal.
- the control electrode of the seventh transistor is coupled to the third node, the first electrode of the seventh transistor is coupled to the second voltage terminal, and the second electrode of the seventh transistor is coupled to the output terminal.
- all of the transistors in the shift register unit are P-type transistors, the first voltage terminal provides a low voltage signal and the second voltage terminal provides a high voltage signal.
- all of the transistors in the shift register unit are N-type transistors, the first voltage terminal provides a high voltage signal and the second voltage terminal provides a low voltage signal.
- the first clock signal and the second clock signal have the same clock period and amplitude and opposite phases, and the duty ratios of the first clock signal and the second clock signal are both 1/2.
- a shift register unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first capacitor, a second capacitor, and a third capacitor.
- the first transistor of the first transistor is coupled to the input terminal, and the second electrode of the first transistor is coupled to the first node.
- the control electrode of the second transistor is coupled to the first clock signal terminal, the first electrode of the second transistor is coupled to the first voltage terminal, and the second electrode of the second transistor is coupled to the second node.
- the control electrode of the third transistor is coupled to the first node, the first electrode of the third transistor is coupled to the first clock signal terminal, and the second electrode of the third transistor is coupled to the second node.
- the control electrode of the fourth transistor is coupled to the second node, the first electrode of the fourth transistor is coupled to the second clock signal terminal, and the second electrode of the fourth transistor is coupled to the third node.
- the first end of the first capacitor is coupled to the second voltage end, and the second end of the first capacitor is coupled to the first node.
- the control electrode of the fifth transistor is coupled to the third node, the first electrode of the fifth transistor is coupled to the second voltage terminal, and the second electrode of the fifth transistor is coupled to the first node.
- the first end of the second capacitor is coupled to the second node, and the second end of the second capacitor is coupled to the third node.
- the first end of the third capacitor is coupled to the third node, and the second end of the third capacitor is coupled to the second voltage end.
- the control electrode of the sixth transistor is coupled to the first node, the first electrode of the sixth transistor is coupled to the first voltage terminal, and the second electrode of the sixth transistor is coupled to the output terminal.
- the control electrode of the seventh transistor is coupled to the third node, the first electrode of the seventh transistor is coupled to the second voltage terminal, and the second electrode of the seventh transistor is coupled to the output terminal.
- the shift register unit further includes a third capacitor.
- Third capacitor The first end of the third capacitor is coupled to the second end, and the second end of the third capacitor is coupled to the second voltage end.
- a driving method of driving a shift register unit as described above.
- the input signal of the shift register unit has a first voltage and a second voltage.
- the duration during which the input signal is at the second voltage is N times the pulse width of the first clock signal. N is an odd number.
- the driving method includes the following stages. In the first phase, the second voltage is input to the input terminal, the first voltage is input to the first clock signal terminal, and the second voltage is input to the second clock signal terminal to provide the second voltage to the first node to provide the second node.
- the first voltage provides a second clock signal to the third node and a first voltage from the output terminal.
- the voltage of the second node is maintained such that the voltage of the third node changes with the voltage of the second clock signal terminal, and the second voltage is output from the output terminal.
- the first voltage is input to the input terminal, the voltages of the first node and the second node are maintained, and the second clock signal is supplied to the third node, and the second voltage is outputted from the output terminal.
- the N+2th stage an input signal is supplied to the first node, the voltage of the second node is maintained, and a second clock signal is supplied to the third node, and the first voltage is output from the output terminal.
- the N+3th stage the voltages of the first node and the third node are maintained, and the first clock signal is supplied to the second node, and the first voltage is continuously outputted from the output terminal.
- N is set to 3
- the driving method includes the following stages.
- the second voltage is input to the input terminal
- the first voltage is input to the first clock signal terminal
- the second voltage is input to the second clock signal terminal to provide the second voltage to the first node to provide the second node.
- the first voltage provides a second clock signal to the third node and a first voltage from the output terminal.
- the second phase the voltages of the first node and the second node are maintained, and a second clock signal is provided to the third node, and a second voltage is output from the output terminal.
- the voltages of the first node and the second node are maintained, and a second clock signal is provided to the third node, and the second voltage is continuously outputted from the output terminal.
- a first voltage is input to the input terminal, the voltages of the first node and the second node are maintained, and a second clock signal is supplied to the third node, and the second voltage is continuously outputted from the output terminal.
- an input signal is provided to the first node, the voltage of the second node is maintained, and a second clock signal is provided to the third node, and the first voltage is output from the output terminal.
- the voltages of the first node and the third node are maintained, and a first clock signal is provided to the second node, and the first voltage is continuously outputted from the output terminal.
- a shift register comprising a plurality of cascaded shift register units as described above.
- the input end of the shift register unit of any stage is coupled to the output end of the shift register unit of the first stage, and the first clock signal and the first clock signal of the shift register unit of the previous stage are mutually inverted signals.
- the start signal is input to the input of the first stage shift register unit.
- an array substrate comprising the shift register as described above.
- a display panel comprising the array substrate as described above.
- the display panel is an LCD display panel or an OLED display panel.
- a display device comprising the display panel as described above.
- Embodiments of the present disclosure provide a shift register unit of a simple structure.
- the shift register unit uses a small number of transistors, which can reduce the layout area of the array substrate, and is advantageous for realizing high resolution products.
- the shift register unit according to an embodiment of the present disclosure may implement an output signal whose duty ratio is adjustable.
- FIG. 1 is a schematic block diagram of a shift register unit in accordance with an embodiment of the present disclosure
- FIG. 2 is an exemplary circuit diagram of a shift register unit in accordance with an embodiment of the present disclosure
- FIG. 3 is a timing diagram of signals of the shift register unit shown in Figure 2;
- FIG. 4 is an exemplary equivalent circuit diagram of a shift register unit in a first phase and a third phase, in accordance with an embodiment of the present disclosure
- FIG. 5 is an exemplary equivalent circuit diagram of a shift register unit in a second phase and a fourth phase, in accordance with an embodiment of the present disclosure
- FIG. 6 is an exemplary equivalent circuit diagram of a shift register unit in a fifth stage, in accordance with an embodiment of the present disclosure
- FIG. 7 is an exemplary equivalent circuit diagram of a shift register unit in a sixth stage, in accordance with an embodiment of the present disclosure.
- FIG. 8 is an exemplary circuit diagram of a shift register unit in accordance with another embodiment of the present disclosure.
- FIG. 9 is a schematic flowchart of a driving method of driving a shift register unit as shown in FIG. 1 according to an embodiment of the present disclosure
- FIG. 10 is a schematic flowchart of one example of a driving method of driving a shift register unit as shown in FIG. 1 according to an embodiment of the present disclosure
- FIG. 11 is an exemplary circuit diagram of a shift register in accordance with an embodiment of the present disclosure.
- FIG. 12 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.
- the source and drain (emitter and collector) of the transistor are symmetrical, and the source and drain (emitter and collector) of the N-type transistor and the P-type transistor
- the conduction current is opposite in direction, so in the embodiment of the present disclosure, the crystal is unified
- the controlled intermediate end of the tube is called the control pole, the signal input is called the first pole, and the signal output is called the second pole.
- the transistors employed in the embodiments of the present disclosure are primarily switching transistors.
- terms such as "first" and "second” are used to distinguish one component (or a portion of the component) from another component (or another portion of the component).
- FIG. 1 shows a schematic block diagram of a shift register unit 100 in accordance with an embodiment of the present disclosure.
- the shift register unit 100 includes an input circuit 110, a first control circuit 120, a second control circuit 130, a first hold circuit 140, a second hold circuit 150, and an output circuit 160.
- the input circuit 110 is connected to the first control circuit 120, the first hold circuit 140, and the output circuit 160, and is configured to control the first according to an input signal from the input terminal STV and a first clock signal from the first clock signal terminal CLK1.
- the first control circuit 120 is connected to the input circuit 110, the second control circuit 130, the first holding circuit 140, the second holding circuit 150, and the output circuit 160, and is configured to be based on the first voltage from the first voltage terminal V1, A clock signal and a voltage of the first node N1 control the voltage of the second node N2.
- the second control circuit 130 is connected to the first control circuit 120, the first hold circuit 140, the second hold circuit 150, and the output circuit 160, and is configured to be based on the voltage of the second node N2 and the second signal signal terminal CLK2
- the second clock signal controls the voltage of the third node N3.
- the first hold circuit 140 is connected to the input circuit 110, the first control circuit 120, the second control circuit 130, the second hold circuit 150, and the output circuit 160, and is configured to be based on the second voltage and the second voltage terminal V2.
- the voltage of the three nodes N3 maintains the voltage of the first node N1.
- the second hold circuit 150 is connected to the first control circuit 120, the second control circuit 130, the first hold circuit 140, and the output circuit 160, and is configured to maintain the voltages of the second node N2 and the third node N3.
- the output circuit 160 is connected to the input circuit 110, the first control circuit 120, the second control circuit 130, the first hold circuit 140, and the second hold circuit 150, and is configured to be at the voltages of the first node N1 and the third node N3.
- the first voltage or the second voltage is output from the output terminal OUT under control.
- the shift register unit according to the present embodiment is capable of outputting an output signal identical to the duty ratio of the input signal, and using the output signal as an input signal of the shift register unit of the next stage, thereby A shift register circuit with adjustable duty cycle is implemented.
- FIG. 2 shows an example circuit diagram of a shift register unit 100 in accordance with an embodiment of the present disclosure.
- the input circuit 110 includes a first transistor T1.
- the control electrode of the first transistor T1 is coupled to the first clock signal terminal CLK1
- the first electrode of the first transistor T1 is coupled to the input terminal STV
- the second electrode of the first transistor T1 is coupled to the first node N1.
- the first control circuit 120 includes a second transistor T2 and a third transistor T3.
- the control electrode of the second transistor T2 is coupled to the first clock signal terminal CLK1, the first electrode of the second transistor T2 is coupled to the first voltage terminal V1, and the second electrode of the second transistor T2 is coupled to the second node N2.
- the control electrode of the third transistor T3 is coupled to the first node N1, the first electrode of the third transistor T3 is coupled to the first clock signal terminal CLK1, and the second electrode of the third transistor T3 is coupled to the second node N2.
- the second control circuit 130 includes a fourth transistor T4.
- the control electrode of the fourth transistor T4 is coupled to the second node N2, the first electrode of the fourth transistor T4 is coupled to the second clock signal terminal CLK2, and the second electrode of the fourth transistor T4 is coupled to the third node N3.
- the first holding circuit 140 includes a first capacitor C1 and a fifth transistor T5.
- the first end of the first capacitor C1 is coupled to the second voltage terminal V2, and the second end of the first capacitor C1 is coupled to the first node N1.
- the control electrode of the fifth transistor T5 is coupled to the third node N3, the first electrode of the fifth transistor T5 is coupled to the second voltage terminal V2, and the second electrode of the fifth transistor T5 is coupled to the first node N1.
- the second hold circuit 150 includes a second capacitor C2.
- the first end of the second capacitor C2 is coupled to the second node N2, and the second end of the second capacitor C2 is coupled to the third node N3.
- the output circuit 160 includes a sixth transistor T6 and a seventh transistor T7.
- the control electrode of the sixth transistor T6 is coupled to the first node N1, the first electrode of the sixth transistor T6 is coupled to the first voltage terminal V1, and the second electrode of the sixth transistor T6 is coupled to the output terminal OUT.
- the control electrode of the seventh transistor T7 is coupled to the third node N3, the first electrode of the seventh transistor T7 is coupled to the second voltage terminal V2, and the second electrode of the seventh transistor T7 is coupled to the output terminal OUT.
- the shift register unit according to the embodiment has a simple structure, uses a small number of transistors, can reduce the layout area of the array substrate, and is advantageous for realizing a high-resolution product. And the shift register unit can realize an output signal with adjustable duty ratio.
- FIG. 3 shows a timing chart of respective signals of the shift register unit 100 shown in FIG. 2.
- the first voltage signal terminal V1 outputs a low voltage signal VGL
- the second voltage signal terminal V2 outputs a high voltage signal VGH.
- the first clock signal CK is input to the first clock signal terminal CLK1.
- the second clock signal CKB is input to the second clock signal terminal CLK2.
- the first clock signal CK and the second clock signal CKB have the same clock period and amplitude and opposite phases, and the duty ratios of the first clock signal CK and the second clock signal CKB are both 1/2.
- the duration of the high voltage signal VGH of the input signal is three times the pulse width of the first clock signal.
- "0" represents a low voltage
- "1" represents a high voltage.
- a high voltage signal VGH is input to the input terminal STV.
- the low voltage signal VGL is input to the first clock signal terminal CLK1, and the first transistor T1 is turned on, so that the voltage of the first node N1 is a high voltage. Since the first node N1 is at a high voltage, both the third transistor T3 and the sixth transistor T6 are turned off.
- the low voltage signal VGL of the first clock signal terminal CLK1 turns on the second transistor T2, so that the voltage of the second node N2 is a low voltage.
- the low voltage of the second node N2 turns on the fourth transistor T4, thereby inputting the high voltage from the second clock signal terminal CLK2 to the third node N3.
- both the fifth transistor T5 and the seventh transistor T7 are turned off. Since the sixth transistor T6 and the seventh transistor T7 are both turned off, the output terminal OUT maintains the voltage of the previous stage, that is, the low voltage.
- a high voltage signal VGH is input to the input terminal STV.
- the high voltage signal VGH is input to the first clock signal terminal CLK1, and the first transistor T1 is turned off.
- the voltage of the first node N1 is maintained at a high voltage by the first capacitor C1. Since the first node N1 is at a high voltage, both the third transistor T3 and the sixth transistor T6 are turned off.
- the high voltage signal VGH from the first clock signal terminal CLK1 turns off the second transistor T2.
- the voltage of the second node N2 is maintained by the second capacitor C2 low voltage.
- the low voltage of the second node N2 causes the fourth transistor T4 to continue to be turned on, thereby inputting the low voltage signal VGL from the second clock signal terminal CLK2 to the third node N3.
- both the fifth transistor T5 and the seventh transistor T7 are turned on, and the voltage of the second node N2 is pulled down twice due to the second capacitor C2, thereby opening the fourth transistor more fully. T4.
- the high voltage signal VGH from the second voltage terminal V2 charges the first capacitor C1, thereby helping to maintain the high voltage of the first node N1.
- the sixth transistor T6 is turned off and the seventh transistor T7 is turned on, the output terminal OUT outputs the high voltage VGH from the second voltage terminal V2.
- a high voltage signal VGH is input to the input terminal STV.
- the low voltage signal VGL is input to the first clock signal terminal CLK1, and the first transistor T1 is turned on, so that the voltage of the first node N1 is a high voltage. Since the first node N1 is at a high voltage, both the third transistor T3 and the sixth transistor T6 are turned off.
- the low voltage signal VGL of the first clock signal terminal CLK1 turns on the second transistor T2, so that the voltage of the second node N2 is a low voltage.
- the low voltage of the second node N2 turns on the fourth transistor T4, thereby inputting the high voltage from the second clock signal terminal CLK2 to the third node N3.
- both the fifth transistor T5 and the seventh transistor T7 are turned off. Since the sixth transistor T6 and the seventh transistor T7 are both turned off, the output terminal OUT maintains the voltage of the previous stage, that is, the high voltage VGH.
- a low voltage signal VGL is input to the input terminal STV.
- the high voltage signal VGH is input to the first clock signal terminal CLK1, and the first transistor T1 is turned off.
- the voltage of the first node N1 is maintained at a high voltage by the first capacitor C1. Since the first node N1 is at a high voltage, both the third transistor T3 and the sixth transistor T6 are turned off.
- the high voltage signal VGH of the first clock signal terminal CLK1 turns off the second transistor T2.
- the voltage of the second node N2 is held at a low voltage by the second capacitor C2.
- the low voltage of the second node N2 causes the fourth transistor T4 to continue to be turned on, thereby inputting the low voltage from the second clock signal terminal CLK2 to the third node N3.
- the third node N3 becomes low
- the voltage is applied, so that the fifth transistor T5 and the seventh transistor T7 are both turned on, and the voltage of the second node N2 is pulled down twice due to the second capacitor C2, thereby opening the fourth transistor T4 more fully.
- the fifth transistor T5 turned on
- the high voltage from the second voltage terminal V2 charges the first capacitor C1, thereby helping to maintain the high voltage of the first node N1.
- the sixth transistor T6 is turned off and the seventh transistor T7 is turned on, the output terminal OUT outputs a high voltage from the second voltage terminal V2.
- a low voltage signal VGL is input to the input terminal STV.
- the low voltage signal VGL is input to the first clock signal terminal CLK1, and the first transistor T1 is turned on, so that the voltage of the first node N1 is a low voltage. Since the first node N1 is at a low voltage, both the third transistor T3 and the sixth transistor T6 are turned on.
- the low voltage signal VGL of the first clock signal terminal CLK1 turns on the second transistor T2, so that the voltage of the second node N2 is a low voltage.
- the low voltage of the second node N2 turns on the fourth transistor T4, thereby inputting the high voltage from the second clock signal terminal CLK2 to the third node N3.
- both the fifth transistor T5 and the seventh transistor T7 are turned off. Since the sixth transistor T6 is turned on and the seventh transistor T7 is turned off, the output terminal OUT outputs a low voltage from the first voltage terminal V1.
- a low voltage signal VGL is input to the input terminal STV.
- the high voltage signal VGH is input to the first clock signal terminal CLK1, and the first transistor T1 is turned off.
- the voltage of the first node N1 is maintained at a low voltage by the first capacitor C1. Since the first node N1 is at a low voltage, both the third transistor T3 and the sixth transistor T6 are turned on.
- the high voltage signal VGH of the first clock signal terminal CLK1 turns off the second transistor T2.
- the high voltage from the first clock signal terminal CLK1 is input to the second node N2 via the third transistor T3, causing its voltage to become a high voltage.
- the high voltage of the second node N2 turns off the fourth transistor T4.
- the third node N3 is held at a high voltage by the second capacitor C2. Since the third node N3 is at a high voltage, both the fifth transistor T5 and the seventh transistor T7 are turned off. Since the sixth transistor T6 is turned on and the seventh transistor T7 is turned off, the output terminal OUT is output. Low voltage from the first voltage terminal V1.
- the shift register unit according to the present embodiment is capable of outputting an output signal identical to the duty ratio of the input signal, and uses the output signal as an input signal of the shift register unit of the next stage, thereby achieving duty Than adjustable shift register circuit. For example, if the duration of the high voltage signal of the input signal is N times the pulse width of the first clock signal, the duration of the high voltage signal of the output signal is also N times the pulse width of the first clock signal. Further, the shift register unit according to the present embodiment can also be applied to shift registers of different functions in accordance with the duty ratio of the input signal.
- the shift register unit can be applied to a shift register that controls the gate scan signal. If the duration of the high voltage signal setting the input signal is a multiple of the pulse width of the clock signal, the shift register unit can be applied to a shift register that controls the illumination time and timing of the OLED.
- the transistors in shift register cell 100 as shown in FIG. 2 may also be N-type transistors.
- the first voltage signal terminal V1 outputs a high voltage signal VGH
- the second voltage signal terminal V2 outputs a low voltage signal VGL.
- the first clock signal CK and the second clock signal CKB have the same clock period and amplitude and opposite phases, and the duty ratios of the first clock signal CK and the second clock signal CKB are both 1/2.
- the voltages of the various signals at various stages are opposite to the voltages of the various signals shown in Figure 3 at various stages.
- a partial transistor may be an N-type transistor, and a part of the transistor is a P-type transistor. Any variations and modifications based on the embodiments of the present disclosure should fall within the protection scope of the present disclosure.
- FIG. 8 is an exemplary circuit diagram of a shift register unit 100 in accordance with another embodiment of the present disclosure.
- the shift register unit 100 in FIG. 8 differs from the shift register unit 100 in FIG. 2 in that a third capacitor C3 is added to the second hold circuit 150.
- the first end of the third capacitor C3 is coupled to the third node N3, and the second end of the third capacitor C3 is coupled to the second voltage terminal V2. Since the second end of the third capacitor C3 is a fixed voltage, the third node N3 can be better maintained. The voltage is better to maintain the stability of the shift register unit.
- the structure of the shift register unit according to an embodiment of the present disclosure is simple, and can be implemented with a smaller number of transistors, so that the layout area can be reduced.
- the shift register unit according to an embodiment of the present disclosure may implement an output signal whose duty ratio is adjustable.
- FIG. 9 illustrates a schematic flowchart of a driving method of driving the shift register unit 100 illustrated in FIG. 1 according to an embodiment of the present disclosure.
- the input signal of the shift register unit 100 has a first voltage and a second voltage.
- the duration during which the input signal is at the second voltage is N times the pulse width of the first clock signal.
- N is an odd number.
- the driving method includes the following stages.
- step S902 in the first phase, the second voltage is input to the input terminal, the first voltage is input to the first clock signal terminal, and the second voltage is input to the second clock signal terminal to provide the second voltage to the first node.
- the second node provides a first voltage, provides a second clock signal to the third node, and outputs a first voltage from the output.
- step S904 in the second to N stages, the second voltage is input to the input terminal, and the voltage of the second node is maintained such that the voltage of the third node changes with the voltage of the second clock signal terminal, and the second voltage is output from the output terminal.
- step S906 in the (N+1)th stage, the first voltage is input to the input terminal, the second voltage is input to the first clock signal terminal, and the first voltage is input to the second clock signal terminal to maintain the first node and the second node. And a second clock signal is supplied to the third node to output a second voltage from the output.
- step S908 in the N+2 phase, the first voltage is input to the input terminal, the first voltage is input to the first clock signal terminal, and the second voltage is input to the second clock signal terminal to provide an input signal to the first node.
- the voltage of the second node is maintained, and a second clock signal is provided to the third node, and the first voltage is output from the output terminal.
- step S910 in the N+3 phase, the first voltage is input to the input terminal, the second voltage is input to the first clock signal terminal, and the first voltage is input to the second clock signal terminal to maintain the first node and the third node.
- the voltage is supplied to the second node and the first voltage is continuously output from the output.
- FIG. 10 is a schematic flow chart of one example of the driving method shown in FIG. In this example, N is set to 3.
- step S1002 in the first stage, the second voltage is input to the input terminal, the first voltage is input to the first clock signal terminal, and the second voltage is input to the second clock signal terminal to provide the second voltage to the first node.
- the second node provides a first voltage, provides a second clock signal to the third node, and outputs a first voltage from the output.
- step S1004 in the second phase, the second voltage is input to the input terminal, the second voltage is input to the first clock signal terminal, and the first voltage is input to the second clock signal terminal to maintain the voltages of the first node and the second node. And providing a second clock signal to the third node and outputting the second voltage from the output terminal.
- step S1006 in the third stage, the second voltage is input to the input terminal, the first voltage is input to the first clock signal terminal, and the second voltage is input to the second clock signal terminal to maintain the voltages of the first node and the second node. And providing a second clock signal to the third node, and continuing to output the second voltage from the output end.
- step S1008 in the fourth stage, the first voltage is input to the input terminal, the second voltage is input to the first clock signal terminal, and the first voltage is input to the second clock signal terminal to maintain the voltages of the first node and the second node. And providing a second clock signal to the third node, and continuing to output the second voltage from the output end.
- step S1010 in the fifth stage, the first voltage is input to the input terminal, the first voltage is input to the first clock signal terminal, and the second voltage is input to the second clock signal terminal to provide an input signal to the first node, keeping the first The voltage of the two nodes, and provides a second clock signal to the third node, and outputs the first voltage from the output terminal.
- step S1012 in the sixth stage, the first voltage is input to the input terminal, the second voltage is input to the first clock signal terminal, and the first voltage is input to the second clock signal terminal to maintain the voltages of the first node and the third node. And providing a first clock signal to the second node, and continuing to output the first voltage from the output.
- the transistors in shift register unit 100 are all P-type transistors, and the first voltage is a low voltage and the second voltage is a high voltage.
- the transistors in shift register unit 100 are all N-type transistors, and the first voltage is a high voltage and the second voltage is a low voltage.
- FIG. 11 is an exemplary circuit diagram of a shift register 1100 in accordance with an embodiment of the present disclosure.
- the shift register 1100 may include a plurality of cascaded shift register units R1, R2, ..., Rn, .
- n denotes a certain stage of the shift register unit in the plurality of cascaded shift register units 100 in the shift register 1100, and does not represent the total number of shift register units included in the shift register 1100.
- the nth stage shift register unit Rn is any one of the shift register units 100 as shown in FIG. 1, FIG. 2 or FIG.
- the input terminal STV of the n-th shift register unit Rn is coupled to the output terminal OUT of the shift register unit of the first stage, and the first clock signal terminal CLK1 is coupled to the second clock signal terminal CLK2 of the shift register unit of the first stage.
- the second clock signal terminal CLK2 is coupled to the first clock signal terminal CLK1 of the upper stage shift register unit.
- the input terminal STV of the first stage shift register unit R1 is input with a start signal.
- a start signal is input to the input terminal STV of the first stage shift register unit R1, and the output end OUT of the first stage shift register unit R1 is coupled to the input end of the second stage shift register unit.
- STV a start signal
- the first clock signal CK is input to the first clock signal terminal CLK1 of the first stage shift register unit R1.
- the second clock signal CKB is input to the second clock signal terminal CLK2 of the first stage shift register unit R1.
- the input terminal STV of the second-stage shift register unit R2 is coupled to the output terminal OUT of the first-stage shift register unit R1, and the output terminal OUT of the second-stage shift register unit R2 is coupled to the third-stage.
- the second clock signal CKB is input to the first clock signal terminal CLK1 of the second stage shift register unit R2.
- the first clock signal CK is input to the second clock signal terminal CLK2 of the second stage shift register unit R2.
- the first clock signal and the second clock signal input by the shift register units of each stage have the same clock period and amplitude and opposite phases.
- the duty ratio of the first clock signal and the second clock signal are both 1/2.
- a shift register according to an embodiment of the present disclosure may be used as a shift providing a gate scan signal Register for use in liquid crystal display panels or OLED display panels.
- the shift register according to an embodiment of the present disclosure can also be used as a shift register for controlling the light emission time and timing of the OLED for use in an OLED display panel.
- FIG. 12 shows a schematic structural view of a display device 1200 according to an embodiment of the present disclosure.
- Display device 1200 can include shift register 1100 as shown in FIG.
- the display device according to an embodiment of the present disclosure can be applied to any product having a display function, such as an electronic paper, a mobile phone, a tablet, a television, a notebook computer, a digital photo frame, a navigator, or the like.
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Abstract
Description
Claims (17)
- 一种移位寄存器单元,包括输入电路、第一控制电路、第二控制电路、第一保持电路、第二保持电路和输出电路,其中,所述输入电路被配置为根据来自输入端的输入信号和来自第一时钟信号端的第一时钟信号来控制第一节点的电压;所述第一控制电路被配置为根据来自第一电压端的第一电压、所述第一时钟信号和所述第一节点的电压来控制第二节点的电压;所述第二控制电路被配置为根据所述第二节点的电压和来自第二时钟信号端的第二时钟信号来控制第三节点的电压;所述第一保持电路被配置为根据来自第二电压端的第二电压和所述第三节点的电压来保持所述第一节点的电压;所述第二保持电路被配置为保持所述第二节点和第三节点的电压;所述输出电路被配置为在所述第一节点和第三节点的电压的控制下从输出端输出所述第一电压或所述第二电压。
- 根据权利要求1所述的移位寄存器单元,其中,输入电路包括第一晶体管,其中,所述第一晶体管的控制极耦接所述第一时钟信号端,所述第一晶体管的第一极耦接所述输入端,所述第一晶体管的第二极耦接所述第一节点。
- 根据权利要求1或2所述的移位寄存器单元,其中,第一控制电路包括第二晶体管和第三晶体管,其中,所述第二晶体管的控制极耦接所述第一时钟信号端,所述第二晶体管的第一极耦接第一电压端,所述第二晶体管的第二极耦接所述第二节点;所述第三晶体管的控制极耦接所述第一节点,所述第三晶体管的第一极耦接所述第一时钟信号端,所述第三晶体管的第二极耦接所述第二节点。
- 根据权利要求1至3中任一项所述的移位寄存器单元,其中,第二控制电路包括第四晶体管,其中,所述第四晶体管的控制极耦接所述第二节点,所述第四晶体管的第一极耦接所述第二时钟信号端,所述第四晶体管的第二极耦接所述第三节点。
- 根据权利要求1至4中任一项所述的移位寄存器单元,其中,第一保持电路包括第一电容器和第五晶体管,其中,所述第一电容器的第一端耦接所述第二电压端,所述第一电容器的第二端耦接所述第一节点;所述第五晶体管的控制极耦接所述第三节点,所述第五晶体管的第一极耦接所述第二电压端,所述第五晶体管的第二极耦接所述第一节点。
- 根据权利要求1至5中任一项所述的移位寄存器单元,其中,第二保持电路包括第二电容器,其中,所述第二电容器的第一端耦接所述第二节点,所述第二电容器的第二端耦接所述第三节点。
- 根据权利要求6所述的移位寄存器单元,其中,第二保持电路还包括第三电容器,其中,所述第三电容器的第一端耦接所述第三节点,所述第三电容器的第二端耦接所述第二电压端。
- 根据权利要求1至7中任一项所述的移位寄存器单元,其中,输出电路包括第六晶体管和第七晶体管,其中,所述第六晶体管的控制极耦接所述第一节点,所述第六晶体管的第一极耦接所述第一电压端,所述第六晶体管的第二极耦接所述输出端;所述第七晶体管的控制极耦接所述第三节点,所述第七晶体管的第一极耦接所述第二电压端,所述第七晶体管的第二极耦接所述输出端。
- 根据权利要求1至8中任一项所述的移位寄存器单元,其中,移位寄存器单元中的所有晶体管都为P型晶体管,所述第一电压端提供低电压信号,所述第二电压端提供高电压信号。
- 根据权利要求1至9中任一项所述的移位寄存器单元,其中,移位寄存器单元中的所有晶体管都为N型晶体管,所述第一电压端提供高电 压信号,所述第二电压端提供低电压信号。
- 根据权利要求1至10中任一项所述的移位寄存器单元,其中,所述第一时钟信号和所述第二时钟信号具有相同的时钟周期和振幅以及相反的相位,并且所述第一时钟信号与所述第二时钟信号的占空比均为1/2。
- 一种移位寄存器单元,包括:第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第一电容器、第二电容器和第三电容器,其中,所述第一晶体管的控制极耦接第一时钟信号端,所述第一晶体管的第一极耦接输入端,所述第一晶体管的第二极耦接第一节点;所述第二晶体管的控制极耦接所述第一时钟信号端,所述第二晶体管的第一极耦接第一电压端,所述第二晶体管的第二极耦接第二节点;所述第三晶体管的控制极耦接所述第一节点,所述第三晶体管的第一极耦接所述第一时钟信号端,所述第三晶体管的第二极耦接所述第二节点;所述第四晶体管的控制极耦接所述第二节点,所述第四晶体管的第一极耦接第二时钟信号端,所述第四晶体管的第二极耦接第三节点;所述第一电容器的第一端耦接第二电压端,所述第一电容器的第二端耦接所述第一节点;所述第五晶体管的控制极耦接所述第三节点,所述第五晶体管的第一极耦接所述第二电压端,所述第五晶体管的第二极耦接所述第一节点;所述第二电容器的第一端耦接所述第二节点,所述第二电容器的第二端耦接所述第三节点;所述第三电容器的第一端耦接所述第三节点,所述第三电容器的第二端耦接所述第二电压端;所述第六晶体管的控制极耦接所述第一节点,所述第六晶体管的第一极耦接所述第一电压端,所述第六晶体管的第二极耦接输出端;所述第七晶体管的控制极耦接所述第三节点,所述第七晶体管的第一极耦接所述第二电压端,所述第七晶体管的第二极耦接所述输出端。
- 根据权利要求12所述的移位寄存器单元,还包括第三电容器,其中,所述第三电容器的第一端耦接所述第三节点,所述第三电容器的第二端耦接所述第二电压端。
- 一种驱动如权利要求1-13中任一项所述的移位寄存器单元的驱动方法,其中,所述移位寄存器单元的输入信号具有第一电压和第二电压,其中所述输入信号处于所述第二电压的持续时间是第一时钟信号的脉宽的N倍,其中N为奇数,所述驱动方法包括:在第一阶段,向输入端输入第二电压,向第一时钟信号端输入第一电压,向第二时钟信号端输入第二电压,以向第一节点提供第二电压,向第二节点提供第一电压,向第三节点提供第二时钟信号,从输出端输出第一电压;在第二至N阶段,保持第二节点的电压以使第三节点的电压随着第二时钟信号端的电压变化,从输出端输出第二电压;在第N+1阶段,向输入端输入第一电压,保持第一节点和第二节点的电压,并向第三节点提供第二时钟信号,从输出端输出第二电压;在第N+2阶段,向第一节点提供输入信号,保持第二节点的电压,并向第三节点提供第二时钟信号,从输出端输出第一电压;在第N+3阶段,保持第一节点和第三节点的电压,并向第二节点提供第一时钟信号,从输出端继续输出第一电压。
- 根据权利要求14所述的驱动方法,其中,N被设置为3,所述驱动方法包括:在第一阶段,向输入端输入第二电压,向第一时钟信号端输入第一电压,向第二时钟信号端输入第二电压,以向第一节点提供第二电压,向第二节点提供第一电压,向第三节点提供第二时钟信号,从输出端输出第一电压;在第二阶段,保持第一节点和第二节点的电压,并向第三节点提供第二时钟信号,从输出端输出第二电压;在第三阶段,保持第一节点和第二节点的电压,并向第三节点提供第 二时钟信号,从输出端继续输出第二电压;在第四阶段,向输入端输入第一电压,保持第一节点和第二节点的电压,并向第三节点提供第二时钟信号,从输出端继续输出第二电压;在第五阶段,向第一节点提供输入信号,保持第二节点的电压,并向第三节点提供第二时钟信号,从输出端输出第一电压;在第六阶段,保持第一节点和第三节点的电压,并向第二节点提供第一时钟信号,从输出端继续输出第一电压。
- 一种移位寄存器,包括多个级联的如权利要求1至13中任一项所述的移位寄存器单元,其中,任一级移位寄存器单元的输入端耦接上一级移位寄存器单元的输出端,且第一时钟信号与上一级移位寄存器单元的第一时钟信号互为反相信号;第一级移位寄存器单元的输入端被输入起始信号。
- 一种显示装置,包括如权利要求16所述的移位寄存器。
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CN106887209B (zh) * | 2017-04-28 | 2019-04-16 | 京东方科技集团股份有限公司 | 移位寄存器单元及其驱动方法、移位寄存器以及显示装置 |
CN109147635B (zh) * | 2017-06-27 | 2021-04-16 | 上海天马有机发光显示技术有限公司 | 一种移位寄存器、其驱动方法及显示装置 |
CN107657918B (zh) | 2017-09-29 | 2019-10-01 | 上海天马微电子有限公司 | 发光控制信号生成电路、其驱动方法及装置 |
CN108735151B (zh) * | 2018-05-07 | 2020-04-21 | 上海天马微电子有限公司 | 发光控制信号生成电路、显示面板和显示装置 |
CN110176217B (zh) * | 2018-07-16 | 2020-06-23 | 京东方科技集团股份有限公司 | 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置 |
EP4145433A4 (en) * | 2020-04-30 | 2023-05-24 | BOE Technology Group Co., Ltd. | SHIFT REGISTER, GATE ELECTRODE DRIVE CIRCUIT, AND GATE ELECTRODE DRIVE METHOD |
CN111508433B (zh) * | 2020-05-28 | 2021-08-31 | 京东方科技集团股份有限公司 | 信号生成电路、信号生成方法、信号生成模组和显示装置 |
WO2022226765A1 (zh) | 2021-04-27 | 2022-11-03 | 京东方科技集团股份有限公司 | 驱动电路、驱动方法、移位寄存器和显示装置 |
US20240221608A1 (en) * | 2021-11-29 | 2024-07-04 | Boe Technology Group Co., Ltd. | Shift register and driving method thereof, light emission control driver and display apparatus |
CN114999397A (zh) * | 2022-04-27 | 2022-09-02 | 湖北长江新型显示产业创新中心有限公司 | 一种发光控制电路、显示面板及显示装置 |
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US20190073933A1 (en) | 2019-03-07 |
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