WO2018196291A1 - 移位寄存器单元及其驱动方法、移位寄存器以及显示装置 - Google Patents

移位寄存器单元及其驱动方法、移位寄存器以及显示装置 Download PDF

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Publication number
WO2018196291A1
WO2018196291A1 PCT/CN2017/106088 CN2017106088W WO2018196291A1 WO 2018196291 A1 WO2018196291 A1 WO 2018196291A1 CN 2017106088 W CN2017106088 W CN 2017106088W WO 2018196291 A1 WO2018196291 A1 WO 2018196291A1
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Prior art keywords
node
voltage
transistor
coupled
clock signal
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PCT/CN2017/106088
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English (en)
French (fr)
Inventor
玄明花
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京东方科技集团股份有限公司
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Priority to US15/773,873 priority Critical patent/US10629108B2/en
Publication of WO2018196291A1 publication Critical patent/WO2018196291A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a shift register unit and a driving method thereof, a shift register, and a display device.
  • OLED organic light emitting diode
  • One common shift register circuit is the gate drive circuit.
  • the gate driving circuit sequentially outputs a gate scan signal to a gate line connected to each row of pixels.
  • the gate scan signal controls the pixel drive circuit to drive the OLED to emit light. Since the threshold voltage of the driving transistor in the pixel driving circuit may drift with time, the pixel driving circuit usually compensates the threshold voltage in the light-emitting preparation stage of the OLED so that the current flowing through the OLED is independent of the threshold voltage.
  • Another shift register circuit can be used to control the illumination time and timing of the OLED during the control of the pixel drive circuit.
  • the embodiments described herein provide a shift register unit whose output signal has a duty ratio adjustable and a simple circuit structure, a driving method thereof, a shift register, and a display device.
  • a shift register unit includes an input circuit, a first control circuit, a second control circuit, a first hold circuit, a second hold circuit, and an output circuit.
  • the input circuit is configured to be based on input signals from the input
  • the voltage of the first node is controlled from the first clock signal of the first clock signal terminal.
  • the first control circuit is configured to control the voltage of the second node based on the first voltage from the first voltage terminal, the first clock signal, and the voltage of the first node.
  • the second control circuit is configured to control the voltage of the third node based on the voltage of the second node and the second clock signal from the second clock signal terminal.
  • the first hold circuit is configured to maintain the voltage of the first node based on the second voltage from the second voltage terminal and the voltage of the third node.
  • the second hold circuit is configured to maintain the voltages of the second node and the third node.
  • the output circuit is configured to output the first voltage or the second voltage from the output under the control of the voltages of the first node and the third node.
  • the input circuit includes a first transistor.
  • the first transistor of the first transistor is coupled to the input terminal, and the second electrode of the first transistor is coupled to the first node.
  • the first control circuit includes a second transistor and a third transistor.
  • the control electrode of the second transistor is coupled to the first clock signal terminal, the first electrode of the second transistor is coupled to the first voltage terminal, and the second electrode of the second transistor is coupled to the second node.
  • the control electrode of the third transistor is coupled to the first node, the first electrode of the third transistor is coupled to the first clock signal terminal, and the second electrode of the third transistor is coupled to the second node.
  • the second control circuit includes a fourth transistor.
  • the control electrode of the fourth transistor is coupled to the second node, the first electrode of the fourth transistor is coupled to the second clock signal terminal, and the second electrode of the fourth transistor is coupled to the third node.
  • the first holding circuit includes a first capacitor and a fifth transistor.
  • the first end of the first capacitor is coupled to the second voltage end, and the second end of the first capacitor is coupled to the first node.
  • the control electrode of the fifth transistor is coupled to the third node, the first electrode of the fifth transistor is coupled to the second voltage terminal, and the second electrode of the fifth transistor is coupled to the first node.
  • the second holding circuit includes a second capacitor.
  • the first end of the second capacitor is coupled to the second node, and the second end of the second capacitor is coupled to the third node.
  • the second holding circuit further includes a third capacitor.
  • the first end of the third capacitor is coupled to the third node, and the second end of the third capacitor is coupled to the second voltage end.
  • the output circuit includes a sixth transistor and a seventh transistor.
  • Sixth The control electrode of the transistor is coupled to the first node, the first electrode of the sixth transistor is coupled to the first voltage terminal, and the second electrode of the sixth transistor is coupled to the output terminal.
  • the control electrode of the seventh transistor is coupled to the third node, the first electrode of the seventh transistor is coupled to the second voltage terminal, and the second electrode of the seventh transistor is coupled to the output terminal.
  • all of the transistors in the shift register unit are P-type transistors, the first voltage terminal provides a low voltage signal and the second voltage terminal provides a high voltage signal.
  • all of the transistors in the shift register unit are N-type transistors, the first voltage terminal provides a high voltage signal and the second voltage terminal provides a low voltage signal.
  • the first clock signal and the second clock signal have the same clock period and amplitude and opposite phases, and the duty ratios of the first clock signal and the second clock signal are both 1/2.
  • a shift register unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first capacitor, a second capacitor, and a third capacitor.
  • the first transistor of the first transistor is coupled to the input terminal, and the second electrode of the first transistor is coupled to the first node.
  • the control electrode of the second transistor is coupled to the first clock signal terminal, the first electrode of the second transistor is coupled to the first voltage terminal, and the second electrode of the second transistor is coupled to the second node.
  • the control electrode of the third transistor is coupled to the first node, the first electrode of the third transistor is coupled to the first clock signal terminal, and the second electrode of the third transistor is coupled to the second node.
  • the control electrode of the fourth transistor is coupled to the second node, the first electrode of the fourth transistor is coupled to the second clock signal terminal, and the second electrode of the fourth transistor is coupled to the third node.
  • the first end of the first capacitor is coupled to the second voltage end, and the second end of the first capacitor is coupled to the first node.
  • the control electrode of the fifth transistor is coupled to the third node, the first electrode of the fifth transistor is coupled to the second voltage terminal, and the second electrode of the fifth transistor is coupled to the first node.
  • the first end of the second capacitor is coupled to the second node, and the second end of the second capacitor is coupled to the third node.
  • the first end of the third capacitor is coupled to the third node, and the second end of the third capacitor is coupled to the second voltage end.
  • the control electrode of the sixth transistor is coupled to the first node, the first electrode of the sixth transistor is coupled to the first voltage terminal, and the second electrode of the sixth transistor is coupled to the output terminal.
  • the control electrode of the seventh transistor is coupled to the third node, the first electrode of the seventh transistor is coupled to the second voltage terminal, and the second electrode of the seventh transistor is coupled to the output terminal.
  • the shift register unit further includes a third capacitor.
  • Third capacitor The first end of the third capacitor is coupled to the second end, and the second end of the third capacitor is coupled to the second voltage end.
  • a driving method of driving a shift register unit as described above.
  • the input signal of the shift register unit has a first voltage and a second voltage.
  • the duration during which the input signal is at the second voltage is N times the pulse width of the first clock signal. N is an odd number.
  • the driving method includes the following stages. In the first phase, the second voltage is input to the input terminal, the first voltage is input to the first clock signal terminal, and the second voltage is input to the second clock signal terminal to provide the second voltage to the first node to provide the second node.
  • the first voltage provides a second clock signal to the third node and a first voltage from the output terminal.
  • the voltage of the second node is maintained such that the voltage of the third node changes with the voltage of the second clock signal terminal, and the second voltage is output from the output terminal.
  • the first voltage is input to the input terminal, the voltages of the first node and the second node are maintained, and the second clock signal is supplied to the third node, and the second voltage is outputted from the output terminal.
  • the N+2th stage an input signal is supplied to the first node, the voltage of the second node is maintained, and a second clock signal is supplied to the third node, and the first voltage is output from the output terminal.
  • the N+3th stage the voltages of the first node and the third node are maintained, and the first clock signal is supplied to the second node, and the first voltage is continuously outputted from the output terminal.
  • N is set to 3
  • the driving method includes the following stages.
  • the second voltage is input to the input terminal
  • the first voltage is input to the first clock signal terminal
  • the second voltage is input to the second clock signal terminal to provide the second voltage to the first node to provide the second node.
  • the first voltage provides a second clock signal to the third node and a first voltage from the output terminal.
  • the second phase the voltages of the first node and the second node are maintained, and a second clock signal is provided to the third node, and a second voltage is output from the output terminal.
  • the voltages of the first node and the second node are maintained, and a second clock signal is provided to the third node, and the second voltage is continuously outputted from the output terminal.
  • a first voltage is input to the input terminal, the voltages of the first node and the second node are maintained, and a second clock signal is supplied to the third node, and the second voltage is continuously outputted from the output terminal.
  • an input signal is provided to the first node, the voltage of the second node is maintained, and a second clock signal is provided to the third node, and the first voltage is output from the output terminal.
  • the voltages of the first node and the third node are maintained, and a first clock signal is provided to the second node, and the first voltage is continuously outputted from the output terminal.
  • a shift register comprising a plurality of cascaded shift register units as described above.
  • the input end of the shift register unit of any stage is coupled to the output end of the shift register unit of the first stage, and the first clock signal and the first clock signal of the shift register unit of the previous stage are mutually inverted signals.
  • the start signal is input to the input of the first stage shift register unit.
  • an array substrate comprising the shift register as described above.
  • a display panel comprising the array substrate as described above.
  • the display panel is an LCD display panel or an OLED display panel.
  • a display device comprising the display panel as described above.
  • Embodiments of the present disclosure provide a shift register unit of a simple structure.
  • the shift register unit uses a small number of transistors, which can reduce the layout area of the array substrate, and is advantageous for realizing high resolution products.
  • the shift register unit according to an embodiment of the present disclosure may implement an output signal whose duty ratio is adjustable.
  • FIG. 1 is a schematic block diagram of a shift register unit in accordance with an embodiment of the present disclosure
  • FIG. 2 is an exemplary circuit diagram of a shift register unit in accordance with an embodiment of the present disclosure
  • FIG. 3 is a timing diagram of signals of the shift register unit shown in Figure 2;
  • FIG. 4 is an exemplary equivalent circuit diagram of a shift register unit in a first phase and a third phase, in accordance with an embodiment of the present disclosure
  • FIG. 5 is an exemplary equivalent circuit diagram of a shift register unit in a second phase and a fourth phase, in accordance with an embodiment of the present disclosure
  • FIG. 6 is an exemplary equivalent circuit diagram of a shift register unit in a fifth stage, in accordance with an embodiment of the present disclosure
  • FIG. 7 is an exemplary equivalent circuit diagram of a shift register unit in a sixth stage, in accordance with an embodiment of the present disclosure.
  • FIG. 8 is an exemplary circuit diagram of a shift register unit in accordance with another embodiment of the present disclosure.
  • FIG. 9 is a schematic flowchart of a driving method of driving a shift register unit as shown in FIG. 1 according to an embodiment of the present disclosure
  • FIG. 10 is a schematic flowchart of one example of a driving method of driving a shift register unit as shown in FIG. 1 according to an embodiment of the present disclosure
  • FIG. 11 is an exemplary circuit diagram of a shift register in accordance with an embodiment of the present disclosure.
  • FIG. 12 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.
  • the source and drain (emitter and collector) of the transistor are symmetrical, and the source and drain (emitter and collector) of the N-type transistor and the P-type transistor
  • the conduction current is opposite in direction, so in the embodiment of the present disclosure, the crystal is unified
  • the controlled intermediate end of the tube is called the control pole, the signal input is called the first pole, and the signal output is called the second pole.
  • the transistors employed in the embodiments of the present disclosure are primarily switching transistors.
  • terms such as "first" and "second” are used to distinguish one component (or a portion of the component) from another component (or another portion of the component).
  • FIG. 1 shows a schematic block diagram of a shift register unit 100 in accordance with an embodiment of the present disclosure.
  • the shift register unit 100 includes an input circuit 110, a first control circuit 120, a second control circuit 130, a first hold circuit 140, a second hold circuit 150, and an output circuit 160.
  • the input circuit 110 is connected to the first control circuit 120, the first hold circuit 140, and the output circuit 160, and is configured to control the first according to an input signal from the input terminal STV and a first clock signal from the first clock signal terminal CLK1.
  • the first control circuit 120 is connected to the input circuit 110, the second control circuit 130, the first holding circuit 140, the second holding circuit 150, and the output circuit 160, and is configured to be based on the first voltage from the first voltage terminal V1, A clock signal and a voltage of the first node N1 control the voltage of the second node N2.
  • the second control circuit 130 is connected to the first control circuit 120, the first hold circuit 140, the second hold circuit 150, and the output circuit 160, and is configured to be based on the voltage of the second node N2 and the second signal signal terminal CLK2
  • the second clock signal controls the voltage of the third node N3.
  • the first hold circuit 140 is connected to the input circuit 110, the first control circuit 120, the second control circuit 130, the second hold circuit 150, and the output circuit 160, and is configured to be based on the second voltage and the second voltage terminal V2.
  • the voltage of the three nodes N3 maintains the voltage of the first node N1.
  • the second hold circuit 150 is connected to the first control circuit 120, the second control circuit 130, the first hold circuit 140, and the output circuit 160, and is configured to maintain the voltages of the second node N2 and the third node N3.
  • the output circuit 160 is connected to the input circuit 110, the first control circuit 120, the second control circuit 130, the first hold circuit 140, and the second hold circuit 150, and is configured to be at the voltages of the first node N1 and the third node N3.
  • the first voltage or the second voltage is output from the output terminal OUT under control.
  • the shift register unit according to the present embodiment is capable of outputting an output signal identical to the duty ratio of the input signal, and using the output signal as an input signal of the shift register unit of the next stage, thereby A shift register circuit with adjustable duty cycle is implemented.
  • FIG. 2 shows an example circuit diagram of a shift register unit 100 in accordance with an embodiment of the present disclosure.
  • the input circuit 110 includes a first transistor T1.
  • the control electrode of the first transistor T1 is coupled to the first clock signal terminal CLK1
  • the first electrode of the first transistor T1 is coupled to the input terminal STV
  • the second electrode of the first transistor T1 is coupled to the first node N1.
  • the first control circuit 120 includes a second transistor T2 and a third transistor T3.
  • the control electrode of the second transistor T2 is coupled to the first clock signal terminal CLK1, the first electrode of the second transistor T2 is coupled to the first voltage terminal V1, and the second electrode of the second transistor T2 is coupled to the second node N2.
  • the control electrode of the third transistor T3 is coupled to the first node N1, the first electrode of the third transistor T3 is coupled to the first clock signal terminal CLK1, and the second electrode of the third transistor T3 is coupled to the second node N2.
  • the second control circuit 130 includes a fourth transistor T4.
  • the control electrode of the fourth transistor T4 is coupled to the second node N2, the first electrode of the fourth transistor T4 is coupled to the second clock signal terminal CLK2, and the second electrode of the fourth transistor T4 is coupled to the third node N3.
  • the first holding circuit 140 includes a first capacitor C1 and a fifth transistor T5.
  • the first end of the first capacitor C1 is coupled to the second voltage terminal V2, and the second end of the first capacitor C1 is coupled to the first node N1.
  • the control electrode of the fifth transistor T5 is coupled to the third node N3, the first electrode of the fifth transistor T5 is coupled to the second voltage terminal V2, and the second electrode of the fifth transistor T5 is coupled to the first node N1.
  • the second hold circuit 150 includes a second capacitor C2.
  • the first end of the second capacitor C2 is coupled to the second node N2, and the second end of the second capacitor C2 is coupled to the third node N3.
  • the output circuit 160 includes a sixth transistor T6 and a seventh transistor T7.
  • the control electrode of the sixth transistor T6 is coupled to the first node N1, the first electrode of the sixth transistor T6 is coupled to the first voltage terminal V1, and the second electrode of the sixth transistor T6 is coupled to the output terminal OUT.
  • the control electrode of the seventh transistor T7 is coupled to the third node N3, the first electrode of the seventh transistor T7 is coupled to the second voltage terminal V2, and the second electrode of the seventh transistor T7 is coupled to the output terminal OUT.
  • the shift register unit according to the embodiment has a simple structure, uses a small number of transistors, can reduce the layout area of the array substrate, and is advantageous for realizing a high-resolution product. And the shift register unit can realize an output signal with adjustable duty ratio.
  • FIG. 3 shows a timing chart of respective signals of the shift register unit 100 shown in FIG. 2.
  • the first voltage signal terminal V1 outputs a low voltage signal VGL
  • the second voltage signal terminal V2 outputs a high voltage signal VGH.
  • the first clock signal CK is input to the first clock signal terminal CLK1.
  • the second clock signal CKB is input to the second clock signal terminal CLK2.
  • the first clock signal CK and the second clock signal CKB have the same clock period and amplitude and opposite phases, and the duty ratios of the first clock signal CK and the second clock signal CKB are both 1/2.
  • the duration of the high voltage signal VGH of the input signal is three times the pulse width of the first clock signal.
  • "0" represents a low voltage
  • "1" represents a high voltage.
  • a high voltage signal VGH is input to the input terminal STV.
  • the low voltage signal VGL is input to the first clock signal terminal CLK1, and the first transistor T1 is turned on, so that the voltage of the first node N1 is a high voltage. Since the first node N1 is at a high voltage, both the third transistor T3 and the sixth transistor T6 are turned off.
  • the low voltage signal VGL of the first clock signal terminal CLK1 turns on the second transistor T2, so that the voltage of the second node N2 is a low voltage.
  • the low voltage of the second node N2 turns on the fourth transistor T4, thereby inputting the high voltage from the second clock signal terminal CLK2 to the third node N3.
  • both the fifth transistor T5 and the seventh transistor T7 are turned off. Since the sixth transistor T6 and the seventh transistor T7 are both turned off, the output terminal OUT maintains the voltage of the previous stage, that is, the low voltage.
  • a high voltage signal VGH is input to the input terminal STV.
  • the high voltage signal VGH is input to the first clock signal terminal CLK1, and the first transistor T1 is turned off.
  • the voltage of the first node N1 is maintained at a high voltage by the first capacitor C1. Since the first node N1 is at a high voltage, both the third transistor T3 and the sixth transistor T6 are turned off.
  • the high voltage signal VGH from the first clock signal terminal CLK1 turns off the second transistor T2.
  • the voltage of the second node N2 is maintained by the second capacitor C2 low voltage.
  • the low voltage of the second node N2 causes the fourth transistor T4 to continue to be turned on, thereby inputting the low voltage signal VGL from the second clock signal terminal CLK2 to the third node N3.
  • both the fifth transistor T5 and the seventh transistor T7 are turned on, and the voltage of the second node N2 is pulled down twice due to the second capacitor C2, thereby opening the fourth transistor more fully. T4.
  • the high voltage signal VGH from the second voltage terminal V2 charges the first capacitor C1, thereby helping to maintain the high voltage of the first node N1.
  • the sixth transistor T6 is turned off and the seventh transistor T7 is turned on, the output terminal OUT outputs the high voltage VGH from the second voltage terminal V2.
  • a high voltage signal VGH is input to the input terminal STV.
  • the low voltage signal VGL is input to the first clock signal terminal CLK1, and the first transistor T1 is turned on, so that the voltage of the first node N1 is a high voltage. Since the first node N1 is at a high voltage, both the third transistor T3 and the sixth transistor T6 are turned off.
  • the low voltage signal VGL of the first clock signal terminal CLK1 turns on the second transistor T2, so that the voltage of the second node N2 is a low voltage.
  • the low voltage of the second node N2 turns on the fourth transistor T4, thereby inputting the high voltage from the second clock signal terminal CLK2 to the third node N3.
  • both the fifth transistor T5 and the seventh transistor T7 are turned off. Since the sixth transistor T6 and the seventh transistor T7 are both turned off, the output terminal OUT maintains the voltage of the previous stage, that is, the high voltage VGH.
  • a low voltage signal VGL is input to the input terminal STV.
  • the high voltage signal VGH is input to the first clock signal terminal CLK1, and the first transistor T1 is turned off.
  • the voltage of the first node N1 is maintained at a high voltage by the first capacitor C1. Since the first node N1 is at a high voltage, both the third transistor T3 and the sixth transistor T6 are turned off.
  • the high voltage signal VGH of the first clock signal terminal CLK1 turns off the second transistor T2.
  • the voltage of the second node N2 is held at a low voltage by the second capacitor C2.
  • the low voltage of the second node N2 causes the fourth transistor T4 to continue to be turned on, thereby inputting the low voltage from the second clock signal terminal CLK2 to the third node N3.
  • the third node N3 becomes low
  • the voltage is applied, so that the fifth transistor T5 and the seventh transistor T7 are both turned on, and the voltage of the second node N2 is pulled down twice due to the second capacitor C2, thereby opening the fourth transistor T4 more fully.
  • the fifth transistor T5 turned on
  • the high voltage from the second voltage terminal V2 charges the first capacitor C1, thereby helping to maintain the high voltage of the first node N1.
  • the sixth transistor T6 is turned off and the seventh transistor T7 is turned on, the output terminal OUT outputs a high voltage from the second voltage terminal V2.
  • a low voltage signal VGL is input to the input terminal STV.
  • the low voltage signal VGL is input to the first clock signal terminal CLK1, and the first transistor T1 is turned on, so that the voltage of the first node N1 is a low voltage. Since the first node N1 is at a low voltage, both the third transistor T3 and the sixth transistor T6 are turned on.
  • the low voltage signal VGL of the first clock signal terminal CLK1 turns on the second transistor T2, so that the voltage of the second node N2 is a low voltage.
  • the low voltage of the second node N2 turns on the fourth transistor T4, thereby inputting the high voltage from the second clock signal terminal CLK2 to the third node N3.
  • both the fifth transistor T5 and the seventh transistor T7 are turned off. Since the sixth transistor T6 is turned on and the seventh transistor T7 is turned off, the output terminal OUT outputs a low voltage from the first voltage terminal V1.
  • a low voltage signal VGL is input to the input terminal STV.
  • the high voltage signal VGH is input to the first clock signal terminal CLK1, and the first transistor T1 is turned off.
  • the voltage of the first node N1 is maintained at a low voltage by the first capacitor C1. Since the first node N1 is at a low voltage, both the third transistor T3 and the sixth transistor T6 are turned on.
  • the high voltage signal VGH of the first clock signal terminal CLK1 turns off the second transistor T2.
  • the high voltage from the first clock signal terminal CLK1 is input to the second node N2 via the third transistor T3, causing its voltage to become a high voltage.
  • the high voltage of the second node N2 turns off the fourth transistor T4.
  • the third node N3 is held at a high voltage by the second capacitor C2. Since the third node N3 is at a high voltage, both the fifth transistor T5 and the seventh transistor T7 are turned off. Since the sixth transistor T6 is turned on and the seventh transistor T7 is turned off, the output terminal OUT is output. Low voltage from the first voltage terminal V1.
  • the shift register unit according to the present embodiment is capable of outputting an output signal identical to the duty ratio of the input signal, and uses the output signal as an input signal of the shift register unit of the next stage, thereby achieving duty Than adjustable shift register circuit. For example, if the duration of the high voltage signal of the input signal is N times the pulse width of the first clock signal, the duration of the high voltage signal of the output signal is also N times the pulse width of the first clock signal. Further, the shift register unit according to the present embodiment can also be applied to shift registers of different functions in accordance with the duty ratio of the input signal.
  • the shift register unit can be applied to a shift register that controls the gate scan signal. If the duration of the high voltage signal setting the input signal is a multiple of the pulse width of the clock signal, the shift register unit can be applied to a shift register that controls the illumination time and timing of the OLED.
  • the transistors in shift register cell 100 as shown in FIG. 2 may also be N-type transistors.
  • the first voltage signal terminal V1 outputs a high voltage signal VGH
  • the second voltage signal terminal V2 outputs a low voltage signal VGL.
  • the first clock signal CK and the second clock signal CKB have the same clock period and amplitude and opposite phases, and the duty ratios of the first clock signal CK and the second clock signal CKB are both 1/2.
  • the voltages of the various signals at various stages are opposite to the voltages of the various signals shown in Figure 3 at various stages.
  • a partial transistor may be an N-type transistor, and a part of the transistor is a P-type transistor. Any variations and modifications based on the embodiments of the present disclosure should fall within the protection scope of the present disclosure.
  • FIG. 8 is an exemplary circuit diagram of a shift register unit 100 in accordance with another embodiment of the present disclosure.
  • the shift register unit 100 in FIG. 8 differs from the shift register unit 100 in FIG. 2 in that a third capacitor C3 is added to the second hold circuit 150.
  • the first end of the third capacitor C3 is coupled to the third node N3, and the second end of the third capacitor C3 is coupled to the second voltage terminal V2. Since the second end of the third capacitor C3 is a fixed voltage, the third node N3 can be better maintained. The voltage is better to maintain the stability of the shift register unit.
  • the structure of the shift register unit according to an embodiment of the present disclosure is simple, and can be implemented with a smaller number of transistors, so that the layout area can be reduced.
  • the shift register unit according to an embodiment of the present disclosure may implement an output signal whose duty ratio is adjustable.
  • FIG. 9 illustrates a schematic flowchart of a driving method of driving the shift register unit 100 illustrated in FIG. 1 according to an embodiment of the present disclosure.
  • the input signal of the shift register unit 100 has a first voltage and a second voltage.
  • the duration during which the input signal is at the second voltage is N times the pulse width of the first clock signal.
  • N is an odd number.
  • the driving method includes the following stages.
  • step S902 in the first phase, the second voltage is input to the input terminal, the first voltage is input to the first clock signal terminal, and the second voltage is input to the second clock signal terminal to provide the second voltage to the first node.
  • the second node provides a first voltage, provides a second clock signal to the third node, and outputs a first voltage from the output.
  • step S904 in the second to N stages, the second voltage is input to the input terminal, and the voltage of the second node is maintained such that the voltage of the third node changes with the voltage of the second clock signal terminal, and the second voltage is output from the output terminal.
  • step S906 in the (N+1)th stage, the first voltage is input to the input terminal, the second voltage is input to the first clock signal terminal, and the first voltage is input to the second clock signal terminal to maintain the first node and the second node. And a second clock signal is supplied to the third node to output a second voltage from the output.
  • step S908 in the N+2 phase, the first voltage is input to the input terminal, the first voltage is input to the first clock signal terminal, and the second voltage is input to the second clock signal terminal to provide an input signal to the first node.
  • the voltage of the second node is maintained, and a second clock signal is provided to the third node, and the first voltage is output from the output terminal.
  • step S910 in the N+3 phase, the first voltage is input to the input terminal, the second voltage is input to the first clock signal terminal, and the first voltage is input to the second clock signal terminal to maintain the first node and the third node.
  • the voltage is supplied to the second node and the first voltage is continuously output from the output.
  • FIG. 10 is a schematic flow chart of one example of the driving method shown in FIG. In this example, N is set to 3.
  • step S1002 in the first stage, the second voltage is input to the input terminal, the first voltage is input to the first clock signal terminal, and the second voltage is input to the second clock signal terminal to provide the second voltage to the first node.
  • the second node provides a first voltage, provides a second clock signal to the third node, and outputs a first voltage from the output.
  • step S1004 in the second phase, the second voltage is input to the input terminal, the second voltage is input to the first clock signal terminal, and the first voltage is input to the second clock signal terminal to maintain the voltages of the first node and the second node. And providing a second clock signal to the third node and outputting the second voltage from the output terminal.
  • step S1006 in the third stage, the second voltage is input to the input terminal, the first voltage is input to the first clock signal terminal, and the second voltage is input to the second clock signal terminal to maintain the voltages of the first node and the second node. And providing a second clock signal to the third node, and continuing to output the second voltage from the output end.
  • step S1008 in the fourth stage, the first voltage is input to the input terminal, the second voltage is input to the first clock signal terminal, and the first voltage is input to the second clock signal terminal to maintain the voltages of the first node and the second node. And providing a second clock signal to the third node, and continuing to output the second voltage from the output end.
  • step S1010 in the fifth stage, the first voltage is input to the input terminal, the first voltage is input to the first clock signal terminal, and the second voltage is input to the second clock signal terminal to provide an input signal to the first node, keeping the first The voltage of the two nodes, and provides a second clock signal to the third node, and outputs the first voltage from the output terminal.
  • step S1012 in the sixth stage, the first voltage is input to the input terminal, the second voltage is input to the first clock signal terminal, and the first voltage is input to the second clock signal terminal to maintain the voltages of the first node and the third node. And providing a first clock signal to the second node, and continuing to output the first voltage from the output.
  • the transistors in shift register unit 100 are all P-type transistors, and the first voltage is a low voltage and the second voltage is a high voltage.
  • the transistors in shift register unit 100 are all N-type transistors, and the first voltage is a high voltage and the second voltage is a low voltage.
  • FIG. 11 is an exemplary circuit diagram of a shift register 1100 in accordance with an embodiment of the present disclosure.
  • the shift register 1100 may include a plurality of cascaded shift register units R1, R2, ..., Rn, .
  • n denotes a certain stage of the shift register unit in the plurality of cascaded shift register units 100 in the shift register 1100, and does not represent the total number of shift register units included in the shift register 1100.
  • the nth stage shift register unit Rn is any one of the shift register units 100 as shown in FIG. 1, FIG. 2 or FIG.
  • the input terminal STV of the n-th shift register unit Rn is coupled to the output terminal OUT of the shift register unit of the first stage, and the first clock signal terminal CLK1 is coupled to the second clock signal terminal CLK2 of the shift register unit of the first stage.
  • the second clock signal terminal CLK2 is coupled to the first clock signal terminal CLK1 of the upper stage shift register unit.
  • the input terminal STV of the first stage shift register unit R1 is input with a start signal.
  • a start signal is input to the input terminal STV of the first stage shift register unit R1, and the output end OUT of the first stage shift register unit R1 is coupled to the input end of the second stage shift register unit.
  • STV a start signal
  • the first clock signal CK is input to the first clock signal terminal CLK1 of the first stage shift register unit R1.
  • the second clock signal CKB is input to the second clock signal terminal CLK2 of the first stage shift register unit R1.
  • the input terminal STV of the second-stage shift register unit R2 is coupled to the output terminal OUT of the first-stage shift register unit R1, and the output terminal OUT of the second-stage shift register unit R2 is coupled to the third-stage.
  • the second clock signal CKB is input to the first clock signal terminal CLK1 of the second stage shift register unit R2.
  • the first clock signal CK is input to the second clock signal terminal CLK2 of the second stage shift register unit R2.
  • the first clock signal and the second clock signal input by the shift register units of each stage have the same clock period and amplitude and opposite phases.
  • the duty ratio of the first clock signal and the second clock signal are both 1/2.
  • a shift register according to an embodiment of the present disclosure may be used as a shift providing a gate scan signal Register for use in liquid crystal display panels or OLED display panels.
  • the shift register according to an embodiment of the present disclosure can also be used as a shift register for controlling the light emission time and timing of the OLED for use in an OLED display panel.
  • FIG. 12 shows a schematic structural view of a display device 1200 according to an embodiment of the present disclosure.
  • Display device 1200 can include shift register 1100 as shown in FIG.
  • the display device according to an embodiment of the present disclosure can be applied to any product having a display function, such as an electronic paper, a mobile phone, a tablet, a television, a notebook computer, a digital photo frame, a navigator, or the like.

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Abstract

一种移位寄存器单元，其包括输入电路（110）、第一控制电路（120）、第二控制电路（130）、第一保持电路（140）、第二保持电路（150）和输出电路（160）。输入电路（110）被配置为根据输入信号（STV）和第一时钟信号（CLK1）来控制第一节点（N1）的电压。第一控制电路（120）被配置为根据第一电压（V1）、第一时钟信号（CLK1）和第一节点（N1）的电压来控制第二节点（N2）的电压。第二控制电路（130）被配置为根据第二节点（N2）的电压和第二时钟信号（CLK2）来控制第三节点（N3）的电压。第一保持电路（140）被配置为根据第二电压（V2）和第三节点（N3）的电压来保持第一节点（N1）的电压。第二保持电路（150）被配置为保持第二节点（N2）和第三节点（N3）的电压。输出电路（160）被配置为在第一节点（N1）和第三节点（N3）的电压的控制下从输出端（OUT）输出第一电压（V1）或第二电压（V2）。

Description

移位寄存器单元及其驱动方法、移位寄存器以及显示装置
相关申请的交叉引用
本申请要求于2017年04月28日递交的中国专利申请第201710295732.1号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及显示技术领域，具体地，涉及移位寄存器单元及其驱动方法、移位寄存器以及显示装置。
背景技术
目前，在显示面板的技术领域，有机发光二极管(Organic Light Emitting Diode，简称OLED)显示面板发展迅速，同时阵列基板上的移位寄存器技术也随之有了很大的进步。一种常见的移位寄存器电路是栅极驱动电路。栅极驱动电路向与每一行像素连接的栅线依次输出栅极扫描信号。栅极扫描信号控制像素驱动电路来驱动OLED发光。由于像素驱动电路中的驱动晶体管的阈值电压会随着时间漂移，因此像素驱动电路通常都会在OLED的发光准备阶段补偿该阈值电压，以使流过OLED的电流与阈值电压无关。而在控制像素驱动电路的过程中可以使用另一个移位寄存器电路来控制OLED的发光时间和时序。
发明内容
本文中描述的实施例提供了一种输出信号的占空比可调并且电路结构简单的移位寄存器单元及其驱动方法、移位寄存器以及显示装置。
根据本公开的第一方面，提供了一种移位寄存器单元。该移位寄存器单元包括输入电路、第一控制电路、第二控制电路、第一保持电路、第二保持电路和输出电路。输入电路被配置为根据来自输入端的输入信号和来 自第一时钟信号端的第一时钟信号来控制第一节点的电压。第一控制电路被配置为根据来自第一电压端的第一电压、第一时钟信号和第一节点的电压来控制第二节点的电压。第二控制电路被配置为根据第二节点的电压和来自第二时钟信号端的第二时钟信号来控制第三节点的电压。第一保持电路被配置为根据来自第二电压端的第二电压和第三节点的电压来保持第一节点的电压。第二保持电路被配置为保持第二节点和第三节点的电压。输出电路被配置为在第一节点和第三节点的电压的控制下从输出端输出第一电压或第二电压。
在本公开的实施例中，输入电路包括第一晶体管。第一晶体管的控制极耦接第一时钟信号端，第一晶体管的第一极耦接输入端，第一晶体管的第二极耦接第一节点。
在本公开的实施例中，第一控制电路包括第二晶体管和第三晶体管。第二晶体管的控制极耦接第一时钟信号端，第二晶体管的第一极耦接第一电压端，第二晶体管的第二极耦接第二节点。第三晶体管的控制极耦接第一节点，第三晶体管的第一极耦接第一时钟信号端，第三晶体管的第二极耦接第二节点。
在本公开的实施例中，第二控制电路包括第四晶体管。第四晶体管的控制极耦接第二节点，第四晶体管的第一极耦接第二时钟信号端，第四晶体管的第二极耦接第三节点。
在本公开的实施例中，第一保持电路包括第一电容器和第五晶体管。第一电容器的第一端耦接第二电压端，第一电容器的第二端耦接第一节点。第五晶体管的控制极耦接第三节点，第五晶体管的第一极耦接第二电压端，第五晶体管的第二极耦接第一节点。
在本公开的实施例中，第二保持电路包括第二电容器。第二电容器的第一端耦接第二节点，第二电容器的第二端耦接第三节点。
在本公开的进一步的实施例中，第二保持电路还包括第三电容器。第三电容器的第一端耦接第三节点，第三电容器的第二端耦接第二电压端。
在本公开的实施例中，输出电路包括第六晶体管和第七晶体管。第六 晶体管的控制极耦接第一节点，第六晶体管的第一极耦接第一电压端，第六晶体管的第二极耦接输出端。第七晶体管的控制极耦接第三节点，第七晶体管的第一极耦接第二电压端，第七晶体管的第二极耦接输出端。
在本公开的实施例中，移位寄存器单元中的所有晶体管都为P型晶体管，第一电压端提供低电压信号，第二电压端提供高电压信号。
在本公开的实施例中，移位寄存器单元中的所有晶体管都为N型晶体管，第一电压端提供高电压信号，第二电压端提供低电压信号。
在本公开的实施例中，第一时钟信号和第二时钟信号具有相同的时钟周期和振幅以及相反的相位，并且第一时钟信号与第二时钟信号的占空比均为1/2。
根据本公开的第二方面，提供了一种移位寄存器单元。该移位寄存器单元包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第一电容器、第二电容器和第三电容器。第一晶体管的控制极耦接第一时钟信号端，第一晶体管的第一极耦接输入端，第一晶体管的第二极耦接第一节点。第二晶体管的控制极耦接第一时钟信号端，第二晶体管的第一极耦接第一电压端，第二晶体管的第二极耦接第二节点。第三晶体管的控制极耦接第一节点，第三晶体管的第一极耦接第一时钟信号端，第三晶体管的第二极耦接第二节点。第四晶体管的控制极耦接第二节点，第四晶体管的第一极耦接第二时钟信号端，第四晶体管的第二极耦接第三节点。第一电容器的第一端耦接第二电压端，第一电容器的第二端耦接第一节点。第五晶体管的控制极耦接第三节点，第五晶体管的第一极耦接第二电压端，第五晶体管的第二极耦接第一节点。第二电容器的第一端耦接第二节点，第二电容器的第二端耦接第三节点。第三电容器的第一端耦接第三节点，第三电容器的第二端耦接第二电压端。第六晶体管的控制极耦接第一节点，第六晶体管的第一极耦接第一电压端，第六晶体管的第二极耦接输出端。第七晶体管的控制极耦接第三节点，第七晶体管的第一极耦接第二电压端，第七晶体管的第二极耦接输出端。
在本公开的实施例中，移位寄存器单元还包括第三电容器。第三电容 器的第一端耦接第三节点，第三电容器的第二端耦接第二电压端。
根据本公开的第三方面，提供了一种驱动如上所述的移位寄存器单元的驱动方法。移位寄存器单元的输入信号具有第一电压和第二电压。输入信号处于第二电压的持续时间是第一时钟信号的脉宽的N倍。N为奇数。该驱动方法包括下列阶段。在第一阶段，向输入端输入第二电压，向第一时钟信号端输入第一电压，向第二时钟信号端输入第二电压，以向第一节点提供第二电压，向第二节点提供第一电压，向第三节点提供第二时钟信号，从输出端输出第一电压。在第二至N阶段，保持第二节点的电压以使第三节点的电压随着第二时钟信号端的电压变化，从输出端输出第二电压。在第N+1阶段，向输入端输入第一电压，保持第一节点和第二节点的电压，并向第三节点提供第二时钟信号，从输出端输出第二电压。在第N+2阶段，向第一节点提供输入信号，保持第二节点的电压，并向第三节点提供第二时钟信号，从输出端输出第一电压。在第N+3阶段，保持第一节点和第三节点的电压，并向第二节点提供第一时钟信号，从输出端继续输出第一电压。
在本公开的进一步的实施例中，N被设置为3，驱动方法包括下列阶段。在第一阶段，向输入端输入第二电压，向第一时钟信号端输入第一电压，向第二时钟信号端输入第二电压，以向第一节点提供第二电压，向第二节点提供第一电压，向第三节点提供第二时钟信号，从输出端输出第一电压。在第二阶段，保持第一节点和第二节点的电压，并向第三节点提供第二时钟信号，从输出端输出第二电压。在第三阶段，保持第一节点和第二节点的电压，并向第三节点提供第二时钟信号，从输出端继续输出第二电压。在第四阶段，向输入端输入第一电压，保持第一节点和第二节点的电压，并向第三节点提供第二时钟信号，从输出端继续输出第二电压。在第五阶段，向第一节点提供输入信号，保持第二节点的电压，并向第三节点提供第二时钟信号，从输出端输出第一电压。在第六阶段，保持第一节点和第三节点的电压，并向第二节点提供第一时钟信号，从输出端继续输出第一电压。
根据本公开的第四方面，提供了一种移位寄存器，其包括多个级联的如上所述的移位寄存器单元。任一级移位寄存器单元的输入端耦接上一级移位寄存器单元的输出端，且第一时钟信号与上一级移位寄存器单元的第一时钟信号互为反相信号。第一级移位寄存器单元的输入端被输入起始信号。
根据本公开的第五方面，提供了一种阵列基板，其包括如上所述的移位寄存器。
根据本公开的第六方面，提供了一种显示面板，其包括如上所述的阵列基板。
在本公开的实施例中，显示面板是LCD显示面板或OLED显示面板。
根据本公开的第七方面，提供了一种显示装置，其包括如上所述的显示面板。
本公开的实施例提供了一种结构简单的移位寄存器单元。该移位寄存器单元采用的晶体管数量少，可以减少阵列基板的版图面积，有利于实现高分辨率的产品。另外，根据本公开的实施例移位寄存器单元可以实现占空比可调的输出信号。
附图说明
为了更清楚地说明本公开的实施例的技术方案，下面将对实施例的附图进行简要说明，应当知道，以下描述的附图仅仅涉及本公开的一些实施例，而非对本公开的限制，其中：
图1是根据本公开的实施例的移位寄存器单元的示意性框图；
图2是根据本公开的实施例的移位寄存器单元的示例性电路图；
图3是如图2所示的移位寄存器单元的各信号的时序图；
图4是根据本公开的实施例的移位寄存器单元在第一阶段和第三阶段的示例性等效电路图；
图5是根据本公开的实施例的移位寄存器单元在第二阶段和第四阶段的示例性等效电路图；
图6是根据本公开的实施例的移位寄存器单元在第五阶段的示例性等效电路图；
图7是根据本公开的实施例的移位寄存器单元在第六阶段的示例性等效电路图；
图8是根据本公开的另一实施例的移位寄存器单元的示例性电路图；
图9是根据本公开的实施例的驱动如图1所示的移位寄存器单元的驱动方法的示意性流程图；
图10是根据本公开的实施例的驱动如图1所示的移位寄存器单元的驱动方法的一个示例的示意性流程图；
图11是根据本公开的实施例的移位寄存器的示例性电路图；
图12是根据本公开的实施例的显示装置的结构示意图。
具体实施方式
为了使本公开的实施例的目的、技术方案和优点更加清楚，下面将结合附图，对本公开的实施例的技术方案进行清楚、完整的描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域技术人员在无需创造性劳动的前提下所获得的所有其它实施例，也都属于本公开保护的范围。
除非另外定义，否则在此使用的所有术语(包括技术和科学术语)具有与本公开主题所属领域的技术人员所通常理解的相同含义。进一步将理解的是，诸如在通常使用的词典中定义的那些的术语应解释为具有与说明书上下文和相关技术中它们的含义一致的含义，并且将不以理想化或过于正式的形式来解释，除非在此另外明确定义。如在此所使用的，将两个或更多部分“连接”或“耦接”到一起的陈述应指这些部分直接结合到一起或通过一个或多个中间部件结合。
在本公开的所有实施例中，由于晶体管的源极和漏极(发射极和集电极)是对称的，并且N型晶体管和P型晶体管的源极和漏极(发射极和集电极)之间的导通电流方向相反，因此在本公开的实施例中，统一将晶体 管的受控中间端称为控制极，信号输入端称为第一极，信号输出端称为第二极。本公开的实施例中所采用的晶体管主要是开关晶体管。另外，诸如“第一”和“第二”的术语仅用于将一个部件(或部件的一部分)与另一个部件(或部件的另一部分)区分开。
图1示出根据本公开的实施例的移位寄存器单元100的示意性框图。如图1所示，移位寄存器单元100包括输入电路110、第一控制电路120、第二控制电路130、第一保持电路140、第二保持电路150和输出电路160。
输入电路110连接到第一控制电路120、第一保持电路140和输出电路160，并被配置为根据来自输入端STV的输入信号和来自第一时钟信号端CLK1的第一时钟信号来控制第一节点N1的电压。
第一控制电路120连接到输入电路110、第二控制电路130、第一保持电路140、第二保持电路150和输出电路160，并被配置为根据来自第一电压端V1的第一电压、第一时钟信号和第一节点N1的电压来控制第二节点N2的电压。
第二控制电路130连接到第一控制电路120、第一保持电路140、第二保持电路150和输出电路160，并被配置为根据第二节点N2的电压和来自第二时钟信号端CLK2的第二时钟信号来控制第三节点N3的电压。
第一保持电路140连接到输入电路110、第一控制电路120、第二控制电路130、第二保持电路150和输出电路160，并被配置为根据来自第二电压端V2的第二电压和第三节点N3的电压来保持第一节点N1的电压。
第二保持电路150连接到第一控制电路120、第二控制电路130、第一保持电路140和输出电路160，并被配置为保持第二节点N2和第三节点N3的电压。
输出电路160连接到输入电路110、第一控制电路120、第二控制电路130、第一保持电路140和第二保持电路150，并被配置为在第一节点N1和第三节点N3的电压的控制下从输出端OUT输出第一电压或第二电压。
根据本实施例的移位寄存器单元能够输出与输入信号的占空比相同的输出信号，并将该输出信号作为下一级移位寄存器单元的输入信号，从而 实现占空比可调的移位寄存器电路。
图2示出根据本公开的实施例的移位寄存器单元100的示例电路图。如图2所示，输入电路110包括第一晶体管T1。第一晶体管T1的控制极耦接第一时钟信号端CLK1，第一晶体管T1的第一极耦接输入端STV，第一晶体管T1的第二极耦接第一节点N1。
第一控制电路120包括第二晶体管T2和第三晶体管T3。第二晶体管T2的控制极耦接第一时钟信号端CLK1，第二晶体管T2的第一极耦接第一电压端V1，第二晶体管T2的第二极耦接第二节点N2。第三晶体管T3的控制极耦接第一节点N1，第三晶体管T3的第一极耦接第一时钟信号端CLK1，第三晶体管T3的第二极耦接第二节点N2。
第二控制电路130包括第四晶体管T4。第四晶体管T4的控制极耦接第二节点N2，第四晶体管T4的第一极耦接第二时钟信号端CLK2，第四晶体管T4的第二极耦接第三节点N3。
第一保持电路140包括第一电容器C1和第五晶体管T5。第一电容器C1的第一端耦接第二电压端V2，第一电容器C1的第二端耦接第一节点N1。第五晶体管T5的控制极耦接第三节点N3，第五晶体管T5的第一极耦接第二电压端V2，第五晶体管T5的第二极耦接第一节点N1。
第二保持电路150包括第二电容器C2。第二电容器C2的第一端耦接第二节点N2，第二电容器C2的第二端耦接第三节点N3。
输出电路160包括第六晶体管T6和第七晶体管T7。第六晶体管T6的控制极耦接第一节点N1，第六晶体管T6的第一极耦接第一电压端V1，第六晶体管T6的第二极耦接输出端OUT。第七晶体管T7的控制极耦接第三节点N3，第七晶体管T7的第一极耦接第二电压端V2，第七晶体管T7的第二极耦接输出端OUT。
根据本实施例的移位寄存器单元结构简单，采用的晶体管数量少，可以减少阵列基板的版图面积，有利于实现高分辨率的产品。并且该移位寄存器单元可以实现占空比可调的输出信号。
图3示出如图2所示的移位寄存器单元100的各信号的时序图。下面 结合图3所示的时序图，对如图2所示的移位寄存器单元100的工作过程进行详细描述。在以下的描述中，假定所有晶体管都是P型晶体管，第一电压信号端V1输出低电压信号VGL，第二电压信号端V2输出高电压信号VGH。向第一时钟信号端CLK1输入第一时钟信号CK。向第二时钟信号端CLK2输入第二时钟信号CKB。第一时钟信号CK和第二时钟信号CKB具有相同的时钟周期和振幅以及相反的相位，并且第一时钟信号CK与第二时钟信号CKB的占空比均为1/2。输入信号的高电压信号VGH的持续时间是第一时钟信号的脉宽的三倍。在下面的实施例中，“0”表示低电压；“1”表示高电压。
在第一阶段t1，STV＝1，CK＝0，CKB＝1。本阶段的移位寄存器单元100的等效电路图如图4所示，其中晶体管上的斜线表示该晶体管处于关闭状态。
向输入端STV输入高电压信号VGH。向第一时钟信号端CLK1输入低电压信号VGL，第一晶体管T1打开，从而使得第一节点N1的电压为高电压。由于第一节点N1为高电压，所以第三晶体管T3和第六晶体管T6都关闭。另外，第一时钟信号端CLK1的低电压信号VGL将第二晶体管T2打开，从而使得第二节点N2的电压为低电压。第二节点N2的低电压将第四晶体管T4打开，从而将来自第二时钟信号端CLK2的高电压输入到第三节点N3。由于第三节点N3为高电压，所以第五晶体管T5和第七晶体管T7都关闭。因为第六晶体管T6和第七晶体管T7都关闭，所以输出端OUT保持上一阶段的电压，即为低电压。
在第二阶段t2，STV＝1，CK＝1，CKB＝0。本阶段的移位寄存器单元100的等效电路图如图5所示。
向输入端STV输入高电压信号VGH。向第一时钟信号端CLK1输入高电压信号VGH，第一晶体管T1关闭。第一节点N1的电压由第一电容器C1保持为高电压。由于第一节点N1为高电压，所以第三晶体管T3和第六晶体管T6都关闭。另外，来自第一时钟信号端CLK1的高电压信号VGH将第二晶体管T2关闭。第二节点N2的电压由第二电容器C2保持为 低电压。第二节点N2的低电压使第四晶体管T4继续打开，从而将来自第二时钟信号端CLK2的低电压信号VGL输入到第三节点N3。由于第三节点N3变为低电压，所以第五晶体管T5和第七晶体管T7都打开，并且第二节点N2的电压由于第二电容器C2而被二次拉低，从而更充分地打开第四晶体管T4。在第五晶体管T5打开的情况下，来自第二电压端V2的高电压信号VGH对第一电容器C1充电，从而帮助保持第一节点N1的高电压。因为第六晶体管T6关闭而第七晶体管T7打开，所以输出端OUT输出来自第二电压端V2的高电压VGH。
在第三阶段t3，STV＝1，CK＝0，CKB＝1。本阶段的移位寄存器单元100的等效电路图如图4所示。
向输入端STV输入高电压信号VGH。向第一时钟信号端CLK1输入低电压信号VGL，第一晶体管T1打开，从而使得第一节点N1的电压为高电压。由于第一节点N1为高电压，所以第三晶体管T3和第六晶体管T6都关闭。另外，第一时钟信号端CLK1的低电压信号VGL将第二晶体管T2打开，从而使得第二节点N2的电压为低电压。第二节点N2的低电压将第四晶体管T4打开，从而将来自第二时钟信号端CLK2的高电压输入到第三节点N3。由于第三节点N3为高电压，所以第五晶体管T5和第七晶体管T7都关闭。因为第六晶体管T6和第七晶体管T7都关闭，所以输出端OUT保持上一阶段的电压，即为高电压VGH。
在第四阶段t4，STV＝0，CK＝1，CKB＝0。本阶段的移位寄存器单元100的等效电路图如图5所示。
向输入端STV输入低电压信号VGL。向第一时钟信号端CLK1输入高电压信号VGH，第一晶体管T1关闭。第一节点N1的电压由第一电容器C1保持为高电压。由于第一节点N1为高电压，所以第三晶体管T3和第六晶体管T6都关闭。另外，第一时钟信号端CLK1的高电压信号VGH将第二晶体管T2关闭。第二节点N2的电压由第二电容器C2保持为低电压。第二节点N2的低电压使第四晶体管T4继续打开，从而将来自第二时钟信号端CLK2的低电压输入到第三节点N3。由于第三节点N3变为低电 压，所以第五晶体管T5和第七晶体管T7都打开，并且第二节点N2的电压由于第二电容器C2而被二次拉低，从而更充分地打开第四晶体管T4。在第五晶体管T5打开的情况下，来自第二电压端V2的高电压对第一电容器C1充电，从而帮助保持第一节点N1的高电压。因为第六晶体管T6关闭而第七晶体管T7打开，所以输出端OUT输出来自第二电压端V2的高电压。
在第五阶段t5，STV＝0，CK＝0，CKB＝1。本阶段的移位寄存器单元100的等效电路图如图6所示。
向输入端STV输入低电压信号VGL。向第一时钟信号端CLK1输入低电压信号VGL，第一晶体管T1打开，从而使得第一节点N1的电压为低电压。由于第一节点N1为低电压，所以第三晶体管T3和第六晶体管T6都打开。另外，第一时钟信号端CLK1的低电压信号VGL将第二晶体管T2打开，从而使得第二节点N2的电压为低电压。第二节点N2的低电压将第四晶体管T4打开，从而将来自第二时钟信号端CLK2的高电压输入到第三节点N3。由于第三节点N3为高电压，所以第五晶体管T5和第七晶体管T7都关闭。因为第六晶体管T6打开而第七晶体管T7关闭，所以输出端OUT输出来自第一电压端V1的低电压。
在第六阶段t6，STV＝0，CK＝1，CKB＝0。本阶段的移位寄存器单元100的等效电路图如图7所示。
向输入端STV输入低电压信号VGL。向第一时钟信号端CLK1输入高电压信号VGH，第一晶体管T1关闭。第一节点N1的电压由第一电容器C1保持为低电压。由于第一节点N1为低电压，所以第三晶体管T3和第六晶体管T6都打开。另外，第一时钟信号端CLK1的高电压信号VGH将第二晶体管T2关闭。来自第一时钟信号端CLK1的高电压经由第三晶体管T3输入到第二节点N2，使其电压变为高电压。第二节点N2的高电压使第四晶体管T4关闭。第三节点N3由第二电容器C2保持为高电压。由于第三节点N3为高电压，所以第五晶体管T5和第七晶体管T7都关闭。因为第六晶体管T6打开而第七晶体管T7关闭，所以输出端OUT输出来 自第一电压端V1的低电压。
从图3中可见，根据本实施例的移位寄存器单元能够输出与输入信号的占空比相同的输出信号，并将该输出信号作为下一级移位寄存器单元的输入信号，从而实现占空比可调的移位寄存器电路。例如，如果输入信号的高电压信号的持续时间是第一时钟信号的脉宽的N倍，则输出信号的高电压信号的持续时间也是第一时钟信号的脉宽的N倍。此外，还可以根据输入信号的占空比来将根据本实施例的移位寄存器单元应用于不同功能的移位寄存器中。例如，如果设置输入信号的高电压信号的持续时间仅为时钟信号的脉宽的一倍，则可将该移位寄存器单元应用于控制栅极扫描信号的移位寄存器中。如果设置输入信号的高电压信号的持续时间为时钟信号的脉宽的多倍，则可将该移位寄存器单元应用于控制OLED的发光时间和时序的移位寄存器中。
本领域的技术人员应当理解，在本实施例的一个替代实施例中，如图2所示的移位寄存器单元100中的晶体管也可以都是N型晶体管。在这种情况下，第一电压信号端V1输出高电压信号VGH，第二电压信号端V2输出低电压信号VGL。第一时钟信号CK和第二时钟信号CKB具有相同的时钟周期和振幅以及相反的相位，并且第一时钟信号CK与第二时钟信号CKB的占空比均为1/2。在该替代实施例中，各信号在各个阶段的电压(未示出)与图3中示出的各信号在各个阶段的电压相反。
此外，本领域的技术人员还应当理解，在本实施例的其它替代实施例中，还可以不仅仅使用单一类型的晶体管，即，可以设置部分晶体管为N型晶体管，部分晶体管为P型晶体管。基于本公开实施例的任何变型和修改都应该落入本公开的保护范围内。
图8是根据本公开的另一实施例的移位寄存器单元100的示例性电路图。在图8中的移位寄存器单元100与图2中的移位寄存器单元100的区别在于，在第二保持电路150中增加了第三电容器C3。第三电容器C3的第一端耦接第三节点N3，第三电容器C3的第二端耦接第二电压端V2。由于第三电容器C3的第二端为固定电压，因此能够更好地保持第三节点N3 的电压，以更好地维持移位寄存器单元的工作稳定。
通过以上描述可以看出，根据本公开的实施例的移位寄存器单元的结构简单，可采用较少数量的晶体管实现，从而能够减少版图面积。另外，根据本公开的实施例的移位寄存器单元可以实现占空比可调的输出信号。
图9示出根据本公开的实施例的驱动如图1所示的移位寄存器单元100的驱动方法的示意性流程图。在本实施例中，移位寄存器单元100的输入信号具有第一电压和第二电压。输入信号处于第二电压的持续时间是第一时钟信号的脉宽的N倍。在这里，N为奇数。该驱动方法包括下列阶段。
在步骤S902，在第一阶段，向输入端输入第二电压，向第一时钟信号端输入第一电压，向第二时钟信号端输入第二电压，以向第一节点提供第二电压，向第二节点提供第一电压，向第三节点提供第二时钟信号，从输出端输出第一电压。
在步骤S904，在第二至N阶段，向输入端输入第二电压，保持第二节点的电压以使第三节点的电压随着第二时钟信号端的电压变化，从输出端输出第二电压。
在步骤S906，在第N+1阶段，向输入端输入第一电压，向第一时钟信号端输入第二电压，向第二时钟信号端输入第一电压，以保持第一节点和第二节点的电压，并向第三节点提供第二时钟信号，从输出端输出第二电压。
在步骤S908，在第N+2阶段，向输入端输入第一电压，向第一时钟信号端输入第一电压，向第二时钟信号端输入第二电压，以向第一节点提供输入信号，保持第二节点的电压，并向第三节点提供第二时钟信号，从输出端输出第一电压。
在步骤S910，在第N+3阶段，向输入端输入第一电压，向第一时钟信号端输入第二电压，向第二时钟信号端输入第一电压，以保持第一节点和第三节点的电压，并向第二节点提供第一时钟信号，从输出端继续输出第一电压。
图10是图9所示的驱动方法的一个示例的示意性流程图。在本示例中，N被设置为3。
在步骤S1002，在第一阶段，向输入端输入第二电压，向第一时钟信号端输入第一电压，向第二时钟信号端输入第二电压，以向第一节点提供第二电压，向第二节点提供第一电压，向第三节点提供第二时钟信号，从输出端输出第一电压。
在步骤S1004，在第二阶段，向输入端输入第二电压，向第一时钟信号端输入第二电压，向第二时钟信号端输入第一电压，以保持第一节点和第二节点的电压，并向第三节点提供第二时钟信号，从输出端输出第二电压。
在步骤S1006，在第三阶段，向输入端输入第二电压，向第一时钟信号端输入第一电压，向第二时钟信号端输入第二电压，以保持第一节点和第二节点的电压，并向第三节点提供第二时钟信号，从输出端继续输出第二电压。
在步骤S1008，在第四阶段，向输入端输入第一电压，向第一时钟信号端输入第二电压，向第二时钟信号端输入第一电压，以保持第一节点和第二节点的电压，并向第三节点提供第二时钟信号，从输出端继续输出第二电压。
在步骤S1010，在第五阶段，向输入端输入第一电压，向第一时钟信号端输入第一电压，向第二时钟信号端输入第二电压，以向第一节点提供输入信号，保持第二节点的电压，并向第三节点提供第二时钟信号，从输出端输出第一电压。
在步骤S1012，在第六阶段，向输入端输入第一电压，向第一时钟信号端输入第二电压，向第二时钟信号端输入第一电压，以保持第一节点和第三节点的电压，并向第二节点提供第一时钟信号，从输出端继续输出第一电压。
在本实施例的一个示例中，移位寄存器单元100中的晶体管都为P型晶体管，并且第一电压为低电压，第二电压为高电压。
在本实施例的另一个示例中，移位寄存器单元100中的晶体管都为N型晶体管，并且第一电压为高电压，第二电压为低电压。
图11是根据本公开的实施例的移位寄存器1100的示例性电路图。如图11所示，移位寄存器1100可包括多个级联的移位寄存器单元R1、R2、……、Rn、……。在此，n表示移位寄存器1100中的多个级联的移位寄存器单元100中的某一级移位寄存器单元，并不表示移位寄存器1100所包括的移位寄存器单元的总数。
在该实施例中，第n级移位寄存器单元Rn是如图1、图2或图8所示的移位寄存器单元100中的任一种。第n级移位寄存器单元Rn的输入端STV耦接上一级移位寄存器单元的输出端OUT，第一时钟信号端CLK1耦接上一级移位寄存器单元的第二时钟信号端CLK2，第二时钟信号端CLK2耦接上一级移位寄存器单元的第一时钟信号端CLK1。第一级移位寄存器单元R1的输入端STV被输入起始信号。
例如，当n＝1时，向第一级移位寄存器单元R1的输入端STV输入起始信号，第一级移位寄存器单元R1的输出端OUT耦接第二级移位寄存器单元的输入端STV。向第一级移位寄存器单元R1的第一时钟信号端CLK1输入第一时钟信号CK。向第一级移位寄存器单元R1的第二时钟信号端CLK2输入第二时钟信号CKB。
当n＝2时，第二级移位寄存器单元R2的输入端STV耦接第一级移位寄存器单元R1的输出端OUT，第二级移位寄存器单元R2的输出端OUT耦接第三级移位寄存器单元的输入端STV。向第二级移位寄存器单元R2的第一时钟信号端CLK1输入第二时钟信号CKB。向第二级移位寄存器单元R2的第二时钟信号端CLK2输入第一时钟信号CK。
随后的移位寄存器的连接方式以此类推，不再赘述。
各级移位寄存器单元输入的第一时钟信号和第二时钟信号具有相同的时钟周期和振幅以及相反的相位。在一个示例中，第一时钟信号与第二时钟信号的占空比均为1/2。
根据本公开的实施例的移位寄存器可以用作提供栅极扫描信号的移位 寄存器，以用于液晶显示面板或者OLED显示面板。
另外，根据本公开的实施例的移位寄存器也可以用作控制OLED的发光时间和时序的移位寄存器，以用于OLED显示面板。
图12示出根据本公开的实施例的显示装置1200的结构示意图。显示装置1200可包括如图11所示的移位寄存器1100。根据本公开实施例的显示装置可以应用于任何具有显示功能的产品，例如，电子纸、手机、平板电脑、电视机、笔记本电脑、数码相框或导航仪等。
除非上下文中另外明确地指出，否则在本文和所附权利要求中所使用的词语的单数形式包括复数，反之亦然。因而，当提及单数时，通常包括相应术语的复数。相似地，措辞“包含”和“包括”将解释为包含在内而不是独占性地。同样地，术语“包括”和“或”应当解释为包括在内的，除非本文中明确禁止这样的解释。在本文中使用术语“示例”之处，特别是当其位于一组术语之后时，所述“示例”仅仅是示例性的和阐述性的，且不应当被认为是独占性的或广泛性的。
适应性的进一步的方面和范围从本文中提供的描述变得明显。应当理解，本申请的各个方面可以单独或者与一个或多个其它方面组合实施。还应当理解，本文中的描述和特定实施例旨在仅说明的目的并不旨在限制本申请的范围。
以上对本公开的若干实施例进行了详细描述，但显然，本领域技术人员可以在不脱离本公开的精神和范围的情况下对本公开的实施例进行各种修改和变型。本公开的保护范围由所附的权利要求限定。

Claims (17)

  1. 一种移位寄存器单元，包括输入电路、第一控制电路、第二控制电路、第一保持电路、第二保持电路和输出电路，
    其中，所述输入电路被配置为根据来自输入端的输入信号和来自第一时钟信号端的第一时钟信号来控制第一节点的电压；
    所述第一控制电路被配置为根据来自第一电压端的第一电压、所述第一时钟信号和所述第一节点的电压来控制第二节点的电压；
    所述第二控制电路被配置为根据所述第二节点的电压和来自第二时钟信号端的第二时钟信号来控制第三节点的电压；
    所述第一保持电路被配置为根据来自第二电压端的第二电压和所述第三节点的电压来保持所述第一节点的电压；
    所述第二保持电路被配置为保持所述第二节点和第三节点的电压；
    所述输出电路被配置为在所述第一节点和第三节点的电压的控制下从输出端输出所述第一电压或所述第二电压。
  2. 根据权利要求1所述的移位寄存器单元，其中，输入电路包括第一晶体管，
    其中，所述第一晶体管的控制极耦接所述第一时钟信号端，所述第一晶体管的第一极耦接所述输入端，所述第一晶体管的第二极耦接所述第一节点。
  3. 根据权利要求1或2所述的移位寄存器单元，其中，第一控制电路包括第二晶体管和第三晶体管，
    其中，所述第二晶体管的控制极耦接所述第一时钟信号端，所述第二晶体管的第一极耦接第一电压端，所述第二晶体管的第二极耦接所述第二节点；
    所述第三晶体管的控制极耦接所述第一节点，所述第三晶体管的第一极耦接所述第一时钟信号端，所述第三晶体管的第二极耦接所述第二节点。
  4. 根据权利要求1至3中任一项所述的移位寄存器单元，其中，第二控制电路包括第四晶体管，
    其中，所述第四晶体管的控制极耦接所述第二节点，所述第四晶体管的第一极耦接所述第二时钟信号端，所述第四晶体管的第二极耦接所述第三节点。
  5. 根据权利要求1至4中任一项所述的移位寄存器单元，其中，第一保持电路包括第一电容器和第五晶体管，
    其中，所述第一电容器的第一端耦接所述第二电压端，所述第一电容器的第二端耦接所述第一节点；
    所述第五晶体管的控制极耦接所述第三节点，所述第五晶体管的第一极耦接所述第二电压端，所述第五晶体管的第二极耦接所述第一节点。
  6. 根据权利要求1至5中任一项所述的移位寄存器单元，其中，第二保持电路包括第二电容器，
    其中，所述第二电容器的第一端耦接所述第二节点，所述第二电容器的第二端耦接所述第三节点。
  7. 根据权利要求6所述的移位寄存器单元，其中，第二保持电路还包括第三电容器，
    其中，所述第三电容器的第一端耦接所述第三节点，所述第三电容器的第二端耦接所述第二电压端。
  8. 根据权利要求1至7中任一项所述的移位寄存器单元，其中，输出电路包括第六晶体管和第七晶体管，
    其中，所述第六晶体管的控制极耦接所述第一节点，所述第六晶体管的第一极耦接所述第一电压端，所述第六晶体管的第二极耦接所述输出端；
    所述第七晶体管的控制极耦接所述第三节点，所述第七晶体管的第一极耦接所述第二电压端，所述第七晶体管的第二极耦接所述输出端。
  9. 根据权利要求1至8中任一项所述的移位寄存器单元，其中，移位寄存器单元中的所有晶体管都为P型晶体管，所述第一电压端提供低电压信号，所述第二电压端提供高电压信号。
  10. 根据权利要求1至9中任一项所述的移位寄存器单元，其中，移位寄存器单元中的所有晶体管都为N型晶体管，所述第一电压端提供高电 压信号，所述第二电压端提供低电压信号。
  11. 根据权利要求1至10中任一项所述的移位寄存器单元，其中，所述第一时钟信号和所述第二时钟信号具有相同的时钟周期和振幅以及相反的相位，并且所述第一时钟信号与所述第二时钟信号的占空比均为1/2。
  12. 一种移位寄存器单元，包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第一电容器、第二电容器和第三电容器，
    其中，所述第一晶体管的控制极耦接第一时钟信号端，所述第一晶体管的第一极耦接输入端，所述第一晶体管的第二极耦接第一节点；
    所述第二晶体管的控制极耦接所述第一时钟信号端，所述第二晶体管的第一极耦接第一电压端，所述第二晶体管的第二极耦接第二节点；
    所述第三晶体管的控制极耦接所述第一节点，所述第三晶体管的第一极耦接所述第一时钟信号端，所述第三晶体管的第二极耦接所述第二节点；
    所述第四晶体管的控制极耦接所述第二节点，所述第四晶体管的第一极耦接第二时钟信号端，所述第四晶体管的第二极耦接第三节点；
    所述第一电容器的第一端耦接第二电压端，所述第一电容器的第二端耦接所述第一节点；
    所述第五晶体管的控制极耦接所述第三节点，所述第五晶体管的第一极耦接所述第二电压端，所述第五晶体管的第二极耦接所述第一节点；
    所述第二电容器的第一端耦接所述第二节点，所述第二电容器的第二端耦接所述第三节点；
    所述第三电容器的第一端耦接所述第三节点，所述第三电容器的第二端耦接所述第二电压端；
    所述第六晶体管的控制极耦接所述第一节点，所述第六晶体管的第一极耦接所述第一电压端，所述第六晶体管的第二极耦接输出端；
    所述第七晶体管的控制极耦接所述第三节点，所述第七晶体管的第一极耦接所述第二电压端，所述第七晶体管的第二极耦接所述输出端。
  13. 根据权利要求12所述的移位寄存器单元，还包括第三电容器，
    其中，所述第三电容器的第一端耦接所述第三节点，所述第三电容器的第二端耦接所述第二电压端。
  14. 一种驱动如权利要求1-13中任一项所述的移位寄存器单元的驱动方法，其中，所述移位寄存器单元的输入信号具有第一电压和第二电压，其中所述输入信号处于所述第二电压的持续时间是第一时钟信号的脉宽的N倍，其中N为奇数，
    所述驱动方法包括：
    在第一阶段，向输入端输入第二电压，向第一时钟信号端输入第一电压，向第二时钟信号端输入第二电压，以向第一节点提供第二电压，向第二节点提供第一电压，向第三节点提供第二时钟信号，从输出端输出第一电压；
    在第二至N阶段，保持第二节点的电压以使第三节点的电压随着第二时钟信号端的电压变化，从输出端输出第二电压；
    在第N+1阶段，向输入端输入第一电压，保持第一节点和第二节点的电压，并向第三节点提供第二时钟信号，从输出端输出第二电压；
    在第N+2阶段，向第一节点提供输入信号，保持第二节点的电压，并向第三节点提供第二时钟信号，从输出端输出第一电压；
    在第N+3阶段，保持第一节点和第三节点的电压，并向第二节点提供第一时钟信号，从输出端继续输出第一电压。
  15. 根据权利要求14所述的驱动方法，其中，N被设置为3，所述驱动方法包括：
    在第一阶段，向输入端输入第二电压，向第一时钟信号端输入第一电压，向第二时钟信号端输入第二电压，以向第一节点提供第二电压，向第二节点提供第一电压，向第三节点提供第二时钟信号，从输出端输出第一电压；
    在第二阶段，保持第一节点和第二节点的电压，并向第三节点提供第二时钟信号，从输出端输出第二电压；
    在第三阶段，保持第一节点和第二节点的电压，并向第三节点提供第 二时钟信号，从输出端继续输出第二电压；
    在第四阶段，向输入端输入第一电压，保持第一节点和第二节点的电压，并向第三节点提供第二时钟信号，从输出端继续输出第二电压；
    在第五阶段，向第一节点提供输入信号，保持第二节点的电压，并向第三节点提供第二时钟信号，从输出端输出第一电压；
    在第六阶段，保持第一节点和第三节点的电压，并向第二节点提供第一时钟信号，从输出端继续输出第一电压。
  16. 一种移位寄存器，包括多个级联的如权利要求1至13中任一项所述的移位寄存器单元，
    其中，任一级移位寄存器单元的输入端耦接上一级移位寄存器单元的输出端，且第一时钟信号与上一级移位寄存器单元的第一时钟信号互为反相信号；
    第一级移位寄存器单元的输入端被输入起始信号。
  17. 一种显示装置，包括如权利要求16所述的移位寄存器。
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Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106887209B (zh) * 2017-04-28 2019-04-16 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、移位寄存器以及显示装置
CN109147635B (zh) * 2017-06-27 2021-04-16 上海天马有机发光显示技术有限公司 一种移位寄存器、其驱动方法及显示装置
CN107657918B (zh) 2017-09-29 2019-10-01 上海天马微电子有限公司 发光控制信号生成电路、其驱动方法及装置
CN108735151B (zh) * 2018-05-07 2020-04-21 上海天马微电子有限公司 发光控制信号生成电路、显示面板和显示装置
CN110176217B (zh) * 2018-07-16 2020-06-23 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
EP4145433A4 (en) * 2020-04-30 2023-05-24 BOE Technology Group Co., Ltd. SHIFT REGISTER, GATE ELECTRODE DRIVE CIRCUIT, AND GATE ELECTRODE DRIVE METHOD
CN111508433B (zh) * 2020-05-28 2021-08-31 京东方科技集团股份有限公司 信号生成电路、信号生成方法、信号生成模组和显示装置
WO2022226765A1 (zh) 2021-04-27 2022-11-03 京东方科技集团股份有限公司 驱动电路、驱动方法、移位寄存器和显示装置
US20240221608A1 (en) * 2021-11-29 2024-07-04 Boe Technology Group Co., Ltd. Shift register and driving method thereof, light emission control driver and display apparatus
CN114999397A (zh) * 2022-04-27 2022-09-02 湖北长江新型显示产业创新中心有限公司 一种发光控制电路、显示面板及显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050201508A1 (en) * 2004-03-12 2005-09-15 Kyong-Ju Shin Shift register and display device including the same
CN104900268A (zh) * 2015-06-30 2015-09-09 上海天马有机发光显示技术有限公司 移位寄存器及其驱动方法、栅极驱动电路、显示装置
CN105185287A (zh) * 2015-08-27 2015-12-23 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路和相关显示装置
CN106486065A (zh) * 2016-12-29 2017-03-08 上海天马有机发光显示技术有限公司 移位寄存单元、寄存器、有机发光显示面板和驱动方法
CN106601177A (zh) * 2017-02-08 2017-04-26 上海天马有机发光显示技术有限公司 移位寄存器及其驱动方法、驱动电路和显示装置
CN106887209A (zh) * 2017-04-28 2017-06-23 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、移位寄存器以及显示装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014054516A1 (ja) * 2012-10-05 2014-04-10 シャープ株式会社 シフトレジスタ、それを備える表示装置、およびシフトレジスタの駆動方法
WO2014054517A1 (ja) * 2012-10-05 2014-04-10 シャープ株式会社 シフトレジスタ、それを備える表示装置、およびシフトレジスタの駆動方法
KR102425574B1 (ko) * 2015-06-29 2022-07-27 삼성디스플레이 주식회사 발광 제어 구동 장치 및 이를 포함하는 유기 발광 표시 장치
CN105609041B (zh) * 2016-03-23 2018-08-07 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN106531052A (zh) * 2017-01-03 2017-03-22 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路及显示装置
CN106782284B (zh) * 2017-03-02 2018-02-27 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动装置以及显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050201508A1 (en) * 2004-03-12 2005-09-15 Kyong-Ju Shin Shift register and display device including the same
CN104900268A (zh) * 2015-06-30 2015-09-09 上海天马有机发光显示技术有限公司 移位寄存器及其驱动方法、栅极驱动电路、显示装置
CN105185287A (zh) * 2015-08-27 2015-12-23 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路和相关显示装置
CN106486065A (zh) * 2016-12-29 2017-03-08 上海天马有机发光显示技术有限公司 移位寄存单元、寄存器、有机发光显示面板和驱动方法
CN106601177A (zh) * 2017-02-08 2017-04-26 上海天马有机发光显示技术有限公司 移位寄存器及其驱动方法、驱动电路和显示装置
CN106887209A (zh) * 2017-04-28 2017-06-23 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、移位寄存器以及显示装置

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