WO2016161768A1 - 移位寄存器单元、驱动电路和方法、阵列基板和显示装置 - Google Patents

移位寄存器单元、驱动电路和方法、阵列基板和显示装置 Download PDF

Info

Publication number
WO2016161768A1
WO2016161768A1 PCT/CN2015/089720 CN2015089720W WO2016161768A1 WO 2016161768 A1 WO2016161768 A1 WO 2016161768A1 CN 2015089720 W CN2015089720 W CN 2015089720W WO 2016161768 A1 WO2016161768 A1 WO 2016161768A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
pull
shift register
register unit
output
Prior art date
Application number
PCT/CN2015/089720
Other languages
English (en)
French (fr)
Inventor
王峥
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/906,744 priority Critical patent/US10068658B2/en
Publication of WO2016161768A1 publication Critical patent/WO2016161768A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present disclosure relates to the field of display technologies, and more particularly to a shift register unit, a gate drive circuit, an array substrate, a display device, and a driving method for the shift register unit.
  • Liquid crystal displays have the advantages of low radiation, small size, and low power consumption, and are widely used in electronic products such as notebook computers, flat-panel televisions, and mobile phones.
  • Liquid crystal displays typically include a pixel array, a data drive circuit, and a gate drive circuit.
  • the data driving circuit can input the input display data to the data line of the liquid crystal panel
  • the gate driving circuit converts the input clock signal into a shift register to control the pixel on/off in the pixel array.
  • the voltage is applied to the gate line of the liquid crystal panel line by line.
  • the existing gate driving circuit often adopts a Gate Driver on Array (GOA) design, in which a thin film transistor (TFT, Thin Film Transistor) gate switching circuit is integrated.
  • TFT Thin Film Transistor
  • the array substrate of the display panel is formed to form a scan drive for the display panel. This not only reduces the cost of the product in terms of material cost and manufacturing process, but also makes the display panel aesthetically pleasing.
  • clock signals are usually present in pairs, for example, including a clock signal CLK and a reverse clock signal CLKB.
  • the specific logarithm may be a pair, two pairs, three pairs, etc., that is, a structure of two clock signals, a structure of four clock signals, a structure of six clock signals, and the like.
  • a pull-down control unit for controlling the pull-down of the shift register is usually separately set in the shift register. After the pull-up unit of the shift register pulls up its output signal level according to the potential of the pull-up control node, the pull-down control unit controls to perform a pull-down operation.
  • the pull-down control unit typically includes a plurality of TFTs, and multiple TFTs are required in order to pull up and pull down the output signal level of the shift register.
  • the number of TFTs causes the wiring in the shift register to become complicated. Therefore, it is desirable to be able to reduce the number of components (particularly TFTs) in the shift register and to simplify the wiring design of the shift register.
  • the present disclosure provides a shift register unit, a gate drive circuit, an array substrate, and a display device. And a driving method for the shift register unit, which can reduce the number of TFTs required for the shift register unit, reduce power consumption in the shift register unit, and reduce wiring in the shift register unit.
  • a shift register unit in a first aspect, can include an input module, a pull-up module, a pull-down module, and a reset module.
  • the input module is coupled to the first signal input terminal and the pull-up control node for controlling the potential of the pull-up control node according to the signal of the first signal input terminal.
  • a pull-up module is connected to the pull-up control node, the second clock signal end, and the output end of the current stage, and is configured to output, according to the signal of the second clock signal end and the potential of the pull-up control node, from the output end of the current stage Output the output signal of this stage.
  • a pull-down module is connected to the third clock signal end, the pull-up control node, the current-stage output end, and the power supply end, and configured to, according to the signal of the third clock signal end, the potential of the pull-up control node and the The signal at the output of this stage is pulled low.
  • a reset module connected to the second signal input end, the pull-up control node, the current stage output end and the power supply end, for resetting the potential of the pull-up control node according to the signal of the second signal input end, and Pull down the signal at the output of the stage to a low level.
  • the shift register unit can further include an isolation module.
  • the isolation module is coupled to the second clock signal terminal and the pull-up control node for reducing signal fluctuations in a shift register unit caused by a signal of the second clock signal terminal.
  • the isolation module is further connected to the first clock signal end, and may include: a second capacitor having a connection to the first clock signal a first end of the end and a second end connected to the pull-up control node; a fourth capacitor having a first end coupled to the second clock signal end and a second end coupled to the pull-up control node.
  • the isolation module is further connected to the third clock signal end, and may include: a third capacitor having a connection to the a first end of the third clock signal end and a second end connected to the pull-up control node; a fourth capacitor having a first end connected to the second clock signal end and a first connection to the pull-up control node Two ends.
  • the signal in the first clock signal end, the signal in the second clock signal end, and the signal in the third clock signal end Can be a square wave signal, and respectively correspond to the upper level output signal, the local level input Out signal and next level output signal.
  • the upper stage output signal is an output signal of a previous stage shift register unit adjacent to the shift register unit.
  • the next stage output signal is an output signal of a next stage shift register unit adjacent to the shift register unit.
  • the power terminal may be connected to the second clock signal end, so as to provide a signal in the second clock signal end to The power terminal pulls down the potential of the pull-up control node and the signal of the output of the current stage.
  • the input module may include: a first transistor having a first pole and a gate connected to the first signal input, Its second pole is connected to the pull up control node.
  • the pull-up module may include: a first capacitor, a first end of which is connected to the pull-up control node; a second transistor, A first pole is coupled to the second clock signal terminal, a gate terminal is coupled to the second terminal of the first capacitor, and a second pole is coupled to the current stage output terminal.
  • the pull-down module may include: a third transistor, a first pole connected to the pull-up control node, and a gate pole connected to a third clock signal terminal, the second pole is connected to the power terminal; the fourth transistor has a first pole connected to the output end of the current stage, a gate pole connected to the third clock signal end, and a second The pole is connected to the power terminal.
  • the reset module may include: a fifth transistor having a first pole connected to the pull-up control node The second signal input end, the second pole is connected to the power terminal; the sixth transistor has a first pole connected to the output end of the current stage, a gate pole connected to the second signal input end, and a second The pole is connected to the power terminal.
  • a gate drive circuit comprising N shift register units.
  • the N shift register units are a first shift register unit to an Nth shift register unit.
  • Each shift register unit is a shift register unit as described above, where N is a natural number.
  • a first signal input of each of the second shift register unit to the Nth shift register unit is coupled to an output of a higher order shift register unit adjacent thereto.
  • a second signal input of each of the first shift register unit to the N-1th shift register unit is coupled to an output of a next stage shift register unit adjacent thereto.
  • an array substrate including a gate drive circuit as described above.
  • a display device comprising the array substrate as described above.
  • a driving method for a shift register unit includes an input module, a pull-up module, a pull-down module, and a reset module.
  • the input module is coupled to the first signal input and to the pull up control node.
  • the pull-up module is connected to the pull-up control node, the second clock signal end, and the current stage output end.
  • the pull-down module is connected to the third clock signal end, the pull-up control node, the current stage output end, and the power supply end.
  • the reset module is coupled to the second signal input terminal, the pull-up control node, the current stage output terminal, and the power supply terminal.
  • the driving method may include: in a first stage, the input module pulls up a potential of the pull-up control node to a high level of the first signal input end by using a signal of the first signal input end, where the pull-up module stores a high level of the first signal input terminal; the second stage, the pull-up control node controls the pull-up module to provide a high level of the second clock signal terminal to the output terminal of the current stage to output the local a third stage, the pull-down module pulls down the potential of the pull-up control node and the signal of the output of the current stage to a low level of the power supply end according to the signal of the third clock signal end; In the stage, the reset module resets the potential of the pull-up control node to the low level according to the signal of the second signal input end, and pulls down the signal of the output of the current stage to a low level.
  • the shift register unit further includes an isolation module, where the isolation module is connected to the first clock signal end, the second clock signal end, and the third
  • the clock signal terminal and the pull-up control node are used to reduce signal fluctuations in the shift register unit caused by signals of the respective clock signal terminals.
  • the signal in the first clock signal end, the signal in the second clock signal end, and the signal in the third clock signal end are square wave signals, and respectively correspond to the upper stage output signal and the current stage output signal.
  • an output signal of the next stage is an output signal of a shift register unit of the upper stage adjacent to the shift register unit, and the output signal of the next stage is the shift register unit The output signal of the adjacent next stage shift register unit.
  • a shift register can be implemented using a clock signal and a TFT, that is, A simple way to implement the pull-down operation of the shift register unit reduces the number of TFTs required for the shift register unit, reduces power consumption in the shift register unit, and reduces wiring in the shift register unit.
  • FIG. 1 is a block diagram schematically illustrating a module structure of a shift register unit according to an embodiment of the present disclosure
  • FIG. 2 is an equivalent circuit diagram schematically illustrating a specific implementation of the shift register unit of FIG. 1;
  • FIG. 3 is a block diagram schematically illustrating a module structure of another shift register unit according to an embodiment of the present disclosure
  • FIG. 4 is an equivalent circuit diagram schematically illustrating a specific implementation of another shift register unit of FIG. 3;
  • FIG. 5 is a waveform diagram schematically illustrating an operation timing of a shift register unit of an embodiment of the present disclosure
  • FIG. 6 is a block diagram schematically illustrating a structure of a gate driving circuit according to an embodiment of the present disclosure
  • FIG. 7 is a block diagram schematically illustrating a structure of an array substrate according to an embodiment of the present disclosure.
  • FIG. 8 is a block diagram schematically illustrating a structure of a display device according to an embodiment of the present disclosure.
  • FIG. 9 is a flow chart schematically illustrating a driving method for a shift register unit according to an embodiment of the present disclosure.
  • the thin film transistors employed in all of the embodiments of the present disclosure are source and drain symmetrical, and all of their sources and drains are interchangeably named.
  • the thin film transistor can be divided into an N-type transistor or a P-type transistor according to the characteristics of the thin film transistor.
  • the first pole can be the source
  • the second pole can be Is the strobe pole
  • the third pole can be Drain.
  • the thin film transistor used in the embodiment of the present disclosure may be an N-type transistor or a P-type transistor.
  • the thin film transistors are all N-type transistors as an example. When the signal of the gate is high, the thin film transistor is turned on. Further, in the case where the thin film transistor is a P-type transistor, when the signal of the gate electrode is a low level, the thin film transistor is turned on, and the timing of the driving signal needs to be adjusted accordingly.
  • FIG. 1 is a block diagram schematically illustrating a module structure of a shift register unit according to an embodiment of the present disclosure.
  • the shift register unit is for converting the input clock signal into a voltage for controlling the turning on or off of each row of pixels, and applying it to the gate line line by line.
  • the shift register unit 100 may include an input module 10, a pull-up module 20, a pull-down module 30, and a reset module 40.
  • the input module 10 is connected to the first signal input terminal Input1 and the pull-up control node PU for controlling the potential of the pull-up control node PU according to the signal of the first signal input terminal Input1.
  • the first signal input terminal Input1 is used to initiate a shift operation of the shift register unit 100. Typically, when the shift register unit 100 outputs a low level signal and the control pixel row is turned off, the first signal input terminal Input1 causes the shift register unit 100 to prepare to output a high level signal to control the pixel row to be turned on.
  • the pull-up control node PU is a node for controlling the pull-up module 20. Typically, when the voltage of the pull-up control node PU is high, it can control the shift register unit 100 to output a high level signal.
  • the pull-up module 20 is connected to the pull-up control node PU, the second clock signal terminal CLK2, and the output terminal Output of the present stage, for the signal according to the second clock signal terminal CLK2 and the pull-up control node PU.
  • the potential of the current output is output from the output terminal of the current stage.
  • the pull up module 20 is enabled when the voltage of the pull up control node PU is high.
  • the pull-up module 20 outputs, for example, a signal of a high level of the second clock signal terminal CLK2 to the output terminal of the current stage.
  • the output of the stage can output a high level signal to control the pixel row to be turned on.
  • the signal of the second clock signal terminal CLK2 is typically at a high level.
  • the signal of the second clock signal terminal CLK2 may be a square wave signal and may correspond, for example, to the output of the shift register 100.
  • the output signal of the shift register 100 To enable the high level signal corresponding to the pixel row; the output signal of the shift register 100 is a low level signal that disables the corresponding pixel row, and the signal of the second clock signal terminal CLK2 is correspondingly used to disable the pullup module 20 Low level signal.
  • the input module 10 needs to pull up the potential of the pull-up control node PU.
  • the signal of the output end of the shift register of the upper stage can be supplied to the first signal input terminal Input1 of the input module 10 to pull up the pull-up control node PU before the pull-up module 20 outputs the high-level signal. Potential.
  • the output of the stage is converted to a low level signal as needed after outputting a high level signal for a certain period of time.
  • the pull-down module 30 is typically used to pull the signal of the output of the stage to a low level.
  • the pull-down module 30 is connected to the third clock signal terminal CLK3, the pull-up control node PU, the current-stage output terminal Output, and the power terminal Vss for the third clock signal terminal CLK3.
  • the signal pulls down the potential of the pull-up control node PU and the signal of the output of the current stage to a low level.
  • the power supply terminal Vss for example, outputs a constant low level signal.
  • the signal of the third clock signal terminal CLK3 is used to start the pull-down operation of the pull-down module 30, thereby pulling down the high-level signal outputted by the output terminal of the current stage to the low-level signal of the power terminal Vss.
  • the pull-down module 30 can also pull down the potential of the pull-up control node PU to a low level signal according to the control of the signal of the third clock signal terminal CLK3.
  • the signal of the third clock signal terminal CLK3 may be a square wave signal and may correspond, for example, to the output of the next stage shift register adjacent to the shift register 100.
  • the output signal of the next stage shift register is enabled for the corresponding pixel row.
  • a high level signal; the output signal of the shift register in the next stage is a low level signal that disables the corresponding pixel row, and the signal of the third clock signal terminal CLK3 is correspondingly a low level signal.
  • the reset module 40 of FIG. 1 is connected to the second signal input terminal Input2, the pull-up control node PU, the current-level output terminal Output and the power supply terminal Vss for resetting according to the signal of the second signal input terminal Input2.
  • the pull-up controls the potential of the node PU and pulls down the signal of the output of the current stage to a low level.
  • the reset module 40 causes the shift register unit 100 to reset to prepare for the next turn-on control.
  • the signal of the output of the stage of the shift register 100 changes from a high level to a low level
  • the signal at the output of the next stage shift register adjacent to the shift register 100 is Low level goes high to start with the next stage shift register
  • a signal of the output of the next stage shift register can be supplied to the second signal input terminal Input2 to control the operation of the reset module 40.
  • the signal of the second clock signal terminal CLK2 corresponds to the output signal of the current stage, and when the two are changed from the high level to the low level, the power terminal Vss
  • the provided signal provides a pull-down level reference for the pull-down module and provides a reset level reference for the reset module.
  • the signal in the second clock signal end can be provided to the power terminal to pull down the potential of the pull-up control node and the signal of the output of the current stage, which can be connected by connecting the power terminal and the The clock signal is implemented.
  • both the reset module 40 and the pull-down module 30 cause the enable signal to be quickly stopped and enter a reset state for the next enable. Signal output.
  • the reset module 40 and the pull-down module 30 avoid the effect of the last display of the pixel row corresponding to the shift register 100 on its next display.
  • the operation of the pull-down module can be controlled by using the third clock signal without a special pull-down control module, that is, the pull-down of the shift register unit is implemented in a simple manner. operating. Accordingly, the number of TFTs required for the shift register unit is reduced, power consumption in the shift register unit is reduced, and wiring in the shift register unit is reduced.
  • FIG. 2 is an equivalent circuit diagram schematically illustrating a specific implementation of the shift register unit 100 of FIG. 1.
  • FIG. 2 a specific implementation of the various modules of shift register unit 100 is shown.
  • the input module 10 includes a first transistor M1 having a first pole and a gate connected to the first signal input terminal Input1 and a second pole connected to the pull-up control node PU.
  • the first signal input terminal Input1 may be the output of the shift register unit of the previous stage.
  • the high level signal of the first signal input terminal Input1 causes the first transistor M1 to be turned on, and the shift register unit of the previous stage is turned on.
  • the output high level signal is transmitted to the pull up control node PU to increase the potential of the pull up control node PU.
  • the input module 10 is implemented as a first transistor M1 and connects both the first pole and the gate electrode to the first signal input terminal Input1.
  • a control signal may be provided for the gate of the first transistor M1, and the control signal may utilize other transistors.
  • the specific implementation structure, control mode, and the like of the input module 10 do not constitute a limitation on the embodiments of the present disclosure.
  • the pull-up module 20 may include a first capacitor C1 having a first end connected to the pull-up control node PU and a second transistor M2 having a first pole connected to the second clock signal.
  • the terminal CLK2 is connected to the second end of the first capacitor C1, and the second pole is connected to the output terminal of the current stage.
  • the first capacitor C1 is charged and stores electrical energy therein.
  • the second transistor M2 is turned on, and the signal of the second clock signal terminal CLK2 is transmitted to the output terminal of the current stage to output the output signal of the current stage.
  • the power storage function of the first capacitor C1 enables the second transistor M2 to maintain the high level of the output signal of the stage for a desired period of time.
  • the signal of the second clock signal terminal CLK2 may correspond to the output of the shift register 100.
  • the first capacitor C1 is merely an example, and other elements may be used to turn on the second transistor M2 corresponding to the output signal of the stage.
  • the pull-down module 30 After outputting a high level signal of a certain period of time, the pull-down module 30 lowers the level of the output signal of the current stage and lowers the level of the pull-up control node PU, so that the pull-up module 20 The output signal of this level of high level is no longer output.
  • the third clock signal terminal CLK3 may correspond, for example, to the output of the next-stage shift register adjacent to the shift register 100.
  • the pull-down module 30 includes a third transistor M3 and a fourth transistor M4.
  • the first electrode of the third transistor M3 is connected to the pull-up control node PU, the gate electrode thereof is connected to the third clock signal terminal CLK3, and the second electrode is connected to the power supply terminal Vss.
  • the third transistor M3 is turned on to connect the pull-up control node PU to the power supply terminal Vss. Since the power supply terminal Vss is at a low level, the conduction of the third transistor M3 lowers the level of the pull-up control node PU, that is, pulls down to a level equal to or close to the low level.
  • the first electrode of the fourth transistor M4 is connected to the output terminal Output of the present stage, the gate electrode is connected to the third clock signal terminal CLK3, and the second electrode is connected to the power source terminal Vss.
  • the fourth transistor M4 is turned on to connect the current stage output terminal to the power source terminal Vss. That is to say, the conduction of the fourth transistor M4 lowers the level of the output of the present stage, that is, the level of the pull-down to be equal to or close to the low level.
  • the pull-down module 30 described above is merely an example, and it may have other structures.
  • the transistor connected in parallel with the fourth transistor M4 is added in the pull-down module 30 to lower the level of the output signal of the present stage more quickly.
  • the first pole of the parallel connected transistor is connected to the output terminal Output of the present stage, the gate terminal thereof is connected to the third clock signal terminal CLK3, and the second pole thereof is connected to the power source terminal Vss.
  • the reset module 40 of FIG. 2 includes a fifth transistor M5 and a sixth transistor M6.
  • the first pole of the fifth transistor M5 is connected to the pull-up control node PU, the gate is connected to the second signal input terminal Input2, and the second pole is connected to the power supply terminal Vss.
  • the first electrode of the sixth transistor M6 is connected to the output terminal Output of the present stage, the gate electrode is connected to the second signal input terminal Input2, and the second electrode is connected to the power supply terminal Vss.
  • the second signal input terminal Input2 provides a reset signal Reset for resetting the shift register unit 100. As described above, the signal OutN at the output of the next stage shift register can be supplied to the second signal input terminal Input2, that is, the reset signal Reset is the signal OutN of the output terminal of the next stage shift register.
  • the reset module 40 performs a reset operation on the shift register unit according to the reset signal Reset. After the shift register unit 100 outputs a high level signal and controls the pixel row for display, the reset module 40 causes the shift register unit 100 to reset to prepare for the next turn-on control.
  • the reset module 40 described above is merely an example, and it may have other structures. For example, a transistor connected in parallel with the fifth transistor M5 may also be added to the reset module 40 to lower the level of the output signal of the present stage more quickly.
  • both the reset module 40 and the pull-down module 30 cause the enable signal to be quickly stopped and enter a reset state for the next enable. Signal output.
  • the reset module 40 and the pull-down module 30 avoid the effect of the last display of the pixel row corresponding to the shift register 100 on its next display.
  • FIG. 3 is a block diagram schematically illustrating a module structure of another shift register unit 300 according to an embodiment of the present disclosure.
  • the same modules as the shift register unit 100 of FIG. 1 are denoted by the same reference numerals.
  • the input module 10, the pull-up module 20, the pull-down module 30, and the reset module 40 in FIG. 3 respectively correspond to the respective modules in FIG. 1, and can be referred to the description above with reference to FIG.
  • the shift register unit 300 of FIG. 3 also includes an isolation module 50 with respect to the shift register unit 100 of FIG.
  • the isolation module 50 is connected to the second clock signal terminal CLK2, the second clock signal terminal CLK2, and the pull-up control node PU for reducing the second clock signal terminal CLK2 or the third clock signal.
  • the signal in the shift register unit caused by the signal of the terminal CLK3 fluctuates.
  • the clock signal in the second clock signal terminal CLK2 has an amplitude change in each clock cycle. This amplitude change may cause signal fluctuations in the wiring in the shift register unit, thereby affecting the operation of the shift register unit.
  • a change in the amplitude of the clock signal in the third clock signal terminal CLK3 also causes signal fluctuations in the wiring in the shift register unit, thereby affecting the operation of the shift register unit.
  • the isolation module 50 is employed to reduce signal fluctuations in the shift register unit caused by the respective clock signals.
  • FIG. 4 is an equivalent circuit diagram schematically illustrating a specific implementation of another shift register unit of FIG.
  • the same components as those of the shift register unit of FIG. 2 are denoted by the same reference numerals, and reference can be made to the description made above in connection with FIG.
  • FIG. 4 specifically illustrates the structure of the isolation module 50 of FIG. 3 and its connection relationship with other elements of FIG. 2.
  • the isolation module 50 is also connected to the first clock signal terminal CLK1 and includes a second capacitor C2, a third capacitor C3, and a fourth capacitor C4.
  • the first end of the second capacitor C2 is connected to the first clock signal terminal CLK1, and the second end thereof is connected to the pull-up control node PU.
  • a first end of the third capacitor C3 is connected to the third clock signal terminal CLK3, and a second end thereof is connected to the pull-up control node PU.
  • a first end of the fourth capacitor C4 is connected to the second clock signal terminal CLK2, and a second end thereof is connected to the pull-up control node PU.
  • the second capacitor C2 and the fourth capacitor C4 are used to avoid the influence of the second clock signal terminal CLK2 on the shift register unit.
  • the second capacitor C2 and the third capacitor C3 are used to avoid the influence of the third clock signal terminal CLK3 on the shift register unit. In practice, it can be appropriately selected as needed.
  • the isolation module 50 may include only the second capacitor C2 and the fourth capacitor C4, or only the second capacitor C2 and the third capacitor C3.
  • the first clock signal terminal CLK1 is connected to the pull-up control node PU via the second capacitor, and the second clock signal terminal CLK2 is connected to the pull-up control node PU via the fourth capacitor C4.
  • the signal of the second clock signal terminal CLK2 changes from high to low
  • the signal of the first clock signal terminal CLK1 can be inversely changed from low to high, and the opposite change can cancel the second clock signal pair.
  • the effect of the signal in the pull-up control node PU When the signal of the second clock signal terminal CLK2 is from When the low variation is high, the signal of the first clock signal terminal CLK1 can be inversely changed from high to low.
  • the first clock signal terminal CLK1 is connected to the pull-up control node PU via the second capacitor C2, and the third clock signal terminal CLK3 is connected to the pull-up control node PU via the third capacitor C3.
  • the signal of the third clock signal terminal CLK3 changes from high to low
  • the signal of the first clock signal terminal CLK1 can be inversely changed from low to high, and the opposite change can cancel the third clock signal pair.
  • the effect of the signal in the pull-up control node PU when the signal of the third clock signal terminal CLK3 changes from low to high, the signal of the first clock signal terminal CLK1 can be inversely changed from high to low.
  • the signal of the second clock signal end and the signal of the third clock signal end may correspond to the current stage output signal and the next stage output signal, respectively.
  • the signal of the first clock signal end may correspond to the output signal of the previous stage.
  • the upper stage output signal is an output signal of a previous stage shift register unit adjacent to the shift register unit.
  • FIG. 5 is a waveform diagram schematically illustrating an operation timing of the shift register unit of FIG. 4.
  • a signal in the first clock signal terminal CLK1, a signal in the second clock signal terminal CLK2, and a signal in the third clock signal terminal CLK3, and a previous output of the first signal input terminal Input1 are shown.
  • the upper stage output signal is an output signal of the upper stage shift register unit adjacent to the shift register unit.
  • the next stage output signal is an output signal of a next stage shift register unit adjacent to the shift register unit.
  • the signal in the first clock signal terminal CLK1, the signal of the second clock signal terminal CLK2, and the signal of the third clock signal terminal CLK3 are square wave signals, and are sequentially different by one.
  • the signal in the first clock signal terminal CLK1 corresponds to the previous stage output signal OutN-1; the signal of the second clock signal terminal CLK2 corresponds to the output signal OutN of the current stage; the signal of the third clock signal terminal CLK3 Corresponding to the next-level output signal OutN+1.
  • the output signal of the previous stage shift register is such that A high level signal corresponding to the pixel row; when the signal of the first clock signal terminal CLK1 is a low level signal for disabling the output, the output signal of the shift register of the previous stage is disabled for the low level of the corresponding pixel row signal.
  • FIG. 6 is a block diagram schematically illustrating a structure of a gate driving circuit 600 according to an embodiment of the present disclosure.
  • the gate drive circuit 600 includes a multi-stage shift register unit, that is, SR1, SR2, SR3, ..., SRN-1, SRN. Each stage of the shift register unit can employ the structure described above.
  • each stage shift register unit has three clock input terminals CLK1, CLK2, CLK3 and a power supply terminal Vss.
  • the clock signal in the three clock inputs can be, for example, a square wave signal as shown in FIG.
  • the power supply terminal Vss is used to input a low level signal to implement a pull-down operation and a reset operation at the end of the high-level output of the shift register unit.
  • the output of the shift register unit SRn-1 of the previous stage is connected to the shift register unit SRn
  • the first signal input terminal Input1 connects the output of the next stage shift register unit SRn+1 to the second signal input terminal Input2 of the shift register unit SRn, where n is a natural number and greater than 1 is less than N.
  • the scan enable signal STV-U is input to the first signal input terminal Input1 of the first pole shift register unit SR0 in each shift register unit, and the shift register units (SR1, SR2, SR37-8 The signal output terminal Output of the present stage of .SRN-1, SRN) sequentially outputs the scan signal to the corresponding gate lines (G1, G2, G3, ..., GN-1, GN).
  • the second signal input terminal Input2 of the last stage shift register unit SRN can input the scan end signal STV-E.
  • the scan end signal STV-E may be the output Output (GN) of the last stage shift register unit SRN.
  • the gate driving circuit 600 can be used to realize one-way scanning, two-way scanning, and the like. The way to scan.
  • FIG. 7 is a block diagram schematically illustrating a structure of an array substrate 700 according to an embodiment of the present disclosure.
  • the array substrate may include: a pixel array; a gate driving circuit according to an embodiment of the present disclosure, configured to generate a gate driving signal respectively corresponding to each row of pixels; and a data driving circuit for selecting Pass Each row of pixels provides data.
  • the gate drive signal outputted by the gate drive circuit of FIG. 7 drives a particular row in the pixel array, the pixels in that particular row are enabled, thereby enabling data signals to be received and flipped from the data drive circuitry.
  • FIG. 7 is merely an exemplary structure of an array substrate, which may further include other components such as a substrate, an insulating isolation layer, and the like.
  • a person skilled in the art can design a suitable array substrate including a gate driving circuit according to an embodiment of the present disclosure as needed.
  • FIG. 8 is a block diagram schematically illustrating a display device 800 in accordance with an embodiment of the present disclosure.
  • the display device may be, for example, a thin film transistor liquid crystal display (TFT LCD), an active matrix organic light emitting diode display (AMOLED), a twisted nematic (TN), or a wide viewing angle widescreen liquid crystal display (ADS).
  • TFT LCD thin film transistor liquid crystal display
  • AMOLED active matrix organic light emitting diode display
  • TN twisted nematic
  • ADS wide viewing angle widescreen liquid crystal display
  • the display device may include: the above array substrate; a color filter substrate disposed in opposition to the array substrate; and a liquid crystal layer disposed between the array substrate and the color filter substrate.
  • the display device may further include a backlight unit or the like for generating a backlight.
  • the operation of the pull-down module can be controlled by using the third clock signal without a special pull-down control module, thereby implementing the shift register unit in a simple manner. Pull down operation. Accordingly, the number of TFTs required for the array substrate and the display device is reduced, and power consumption and wiring in the array substrate and the display device are reduced.
  • FIG. 9 is a flow chart that schematically illustrates a driving method 900 for a shift register unit in accordance with an embodiment of the present disclosure.
  • the shift register unit to which the driving method 900 is applied may include an input module, a pull-up module, a pull-down module, and a reset module.
  • the input module is coupled to the first signal input and to the pull up control node.
  • the pull-up module is connected to the pull-up control node, the second clock signal end, and the current stage output end.
  • the pull-down module is connected to the third clock signal end, the pull-up control node, the current stage output end, and the power supply end.
  • the reset module is coupled to the second signal input terminal, the pull-up control node, the current stage output terminal, and the power supply terminal.
  • the structure of the shift register unit can be seen in the diagrams of FIGS. 1 and 2 and the related description.
  • the driving method may include: in a first stage, the input module pulls up a potential of the pull-up control node to a high level of the first signal input end by using a signal of the first signal input end,
  • the pull-up module stores a high level of the first signal input end (S910); in a second stage, the pull-up control node controls the pull-up module to provide a high level of the second clock signal end to the
  • the output terminal of the current stage outputs the output signal of the current stage (S920); in the third stage, the pull-down module converts the potential of the pull-up control node and the output of the current stage according to the signal of the third clock signal end
  • the signal is pulled down to the low level of the power terminal (S930); in the fourth stage, the reset module resets the potential of the pull-up control node according to the signal of the second signal input end
  • the low level and the signal of the output of the current stage are pulled down to a low level (S940).
  • S910 a shift operation of the shift register unit is started.
  • the output signal OutN-1 of the upper stage shift register (hereinafter simply referred to as the upper stage output signal) is supplied to the first signal input terminal.
  • the upper stage output signal OutN-1 is at a high level
  • execution of S910 is started.
  • the input module having the structure shown in FIG. 2 as an example, when the upper stage output signal OutN-1 is high, the first transistor M1 is turned on, and the upper level output signal OutN-1 of the high level is transmitted.
  • the pull-up control node PU is added to increase the potential of the pull-up control node PU.
  • the potential rise of the pull-up control node PU charges the first capacitor C1 in the pull-up module of FIG.
  • the pull-up module stores the high level of the first signal input terminal by using the first capacitor C1.
  • the first phase typically corresponds to a period in which the upper stage output signal OutN-1 in FIG. 5 is at a high level.
  • the second phase typically corresponds to a period in which the present stage output signal OutN in FIG. 5 is at a high level.
  • the second transistor M2 in the pull-up module of FIG. 2 is turned on, and the high-level signal of the second clock signal terminal CLK2 is transmitted to the output terminal of the current stage to output high. Level of this level of output signal.
  • the output current output signal enables the pixel row corresponding to the shift potential register such that the pixel receives the data for display.
  • the third phase typically corresponds to a period in which the next-stage output signal OutN+1 in FIG. 5 is at a high level.
  • the shift register unit stops outputting a high level to stop the display operation of its corresponding pixel row. That is to say, the output signal OutN of this stage is low in the third stage.
  • the pull-down module pulls down the potential of the pull-up control node and the signal of the output of the current stage to a low level of the power supply terminal according to the signal of the third clock signal terminal CLK3 in FIG.
  • the signal of the third clock signal terminal CLK3 is at a high level in the third phase.
  • the signal of the third clock signal terminal CLK3 enables the pull-down module to perform a pull-down operation.
  • the pull-down module including the third transistor M3 and the fourth transistor M4 as shown in FIG. 2 during a period in which the signal of the third clock signal terminal CLK3 is at a high level, the third transistor M3 is turned on to pull the pull-up
  • the control node PU is connected to the power supply terminal; the fourth transistor M4 is turned on to connect the current stage output terminal to the power supply terminal. Since the power supply terminal Vss is at a low level, the conduction of the third transistor M3 and the fourth transistor M4 respectively lowers the levels of the pull-up control node PU and the output terminal Output.
  • the fourth stage typically also corresponds to the next stage output signal OutN+1 in FIG. period.
  • the third stage is the operation of the pull-down module during the next stage when the output signal OutN+1 is at a high level.
  • the fourth stage is the operation of the reset module during the next stage output signal OutN+1 is high.
  • the reset module resets the potential of the pull-up control node to the low level according to the signal of the second signal input end, and pulls the signal of the output end of the current stage to a low level. .
  • the reset module including the fifth transistor M5 and the sixth transistor M6 as shown in FIG. 2, while the signal of the third clock signal terminal CLK3 is at a high level, the fifth transistor M5 is turned on to pull the pull-up
  • the control node PU is connected to the power terminal; a sixth transistor M6 is connected to the current output terminal to the power terminal. Since the power supply terminal Vss is at a low level, the conduction of the fifth transistor M5 and the sixth transistor M6 respectively lowers the levels of the pull-up control node PU and the output terminal Output. That is, the reset module resets the shift register unit according to the reset signal Reset (for example, the next-stage output signal OutN+1 described above), causing the shift register unit to prepare for the next turn-on control.
  • the reset signal Reset for example, the next-stage output signal OutN+1 described above
  • the shift register unit to which the driving method 900 is applied may further include an isolation module.
  • the structure of the isolation module and its connection relationship with other modules can be seen in the diagrams of FIGS. 3 and 4 and related descriptions.
  • the isolation module may also be connected to the first clock signal terminal.
  • the signal fluctuation in the first clock signal end may be opposite to the signal fluctuation of the second clock signal terminal to reduce the influence of the signal fluctuation of the second clock signal terminal.
  • the signal fluctuation in the first clock signal end may be opposite to the signal fluctuation of the third clock signal terminal to reduce the influence of the signal fluctuation of the third clock signal terminal.
  • the signal in the first clock signal end may be a square wave signal and corresponds to the upper stage output signal.
  • the upper stage output signal is an output signal of a previous stage shift register unit adjacent to the shift register unit.
  • the signal of the second clock signal end corresponds to the output signal of the current stage.
  • the signal of the third clock signal end corresponds to the next stage output signal.
  • the next stage output signal is an output signal of a next stage shift register unit adjacent to the shift register unit.
  • a technical solution for a driving method of a shift register unit it is possible to control an operation of a pull-down module using a third clock signal without a dedicated pull-down control mode
  • the block, that is, the pull-down operation of the shift register unit is implemented in a simple manner. Accordingly, the number of TFTs required for the shift register unit is reduced, and power consumption and wiring in the shift register unit are reduced. Furthermore, the influence of signal fluctuations of the respective clock signals can be reduced by using the signals in the isolation unit and the first clock signal terminal.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Shift Register Type Memory (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种移位寄存器单元（100，300）、选通驱动电路、显示装置（800）和用于该移位寄存器单元（100，300）的驱动方法。移位寄存器单元（100，300）包括：输入模块（10），根据第一信号输入端（Input1）的信号（OutN-1）来控制上拉控制节点（PU）的电位；上拉模块（20），根据第二时钟信号端（CLK2）的信号和上拉控制节点（PU）的电位从本级输出端（Output）输出本级输出信号（OutN）；下拉模块（30），根据第三时钟信号端（CLK3）的信号将上拉控制节点（PU）的电位和本级输出端（Output）的信号（OutN）下拉为低电平；复位模块（40），根据第二信号输入端（Input 2）的信号（OutN+1，Reset）复位上拉控制节点（PU）的电位，并将本级输出端（Output）的信号（OutN）下拉为低电平。

Description

移位寄存器单元、驱动电路和方法、阵列基板和显示装置 技术领域
本公开涉及显示技术领域，更具体地，涉及一种移位寄存器单元、选通驱动电路、阵列基板、显示装置和用于该移位寄存器单元的驱动方法。
背景技术
液晶显示器(Liquid Crystal Display，LCD)具有低辐射、体积小及低耗能等优点，被广泛地应用在笔记本电脑、平面电视或移动电话等电子产品中。液晶显示器典型地包括像素阵列、数据驱动电路和选通驱动电路。当液晶显示器进行显示时，数据驱动电路可以将输入的显示数据输入到液晶面板的数据线，选通驱动电路将输入的时钟信号经过移位寄存器转换成控制像素阵列中的像素开启/关断的电压，并逐行施加到液晶面板的选通线上。
为了进一步降低液晶显示器产品的生产成本，现有的选通驱动电路常采用阵列基板行驱动(GOA，Gate Driver on Array)设计，其中将薄膜晶体管(TFT，Thin Film Transistor)选通开关电路集成在显示面板的阵列基板上以形成对显示面板的扫描驱动。这不仅可以从材料成本和制作工艺两方面降低产品成本，而且使得显示面板具有美观的设计。
通常，在基于GOA技术的选通驱动电路的移位寄存器中，时钟信号通常成对地出现，例如为包括时钟信号CLK和反向的时钟信号CLKB。具体的对数可以为一对、两对、三对等，即2个时钟信号的结构、4个时钟信号的结构、6个时钟信号的结构等。移位寄存器中通常单独设置用于控制移位寄存器的下拉的下拉控制单元。在移位寄存器的上拉单元根据上拉控制节点的电位将其输出信号电平上拉之后，下拉控制单元控制执行下拉操作。下拉控制单元通常包括多个TFT，为了对移位寄存器的输出信号电平进行上拉和下拉，也需要多个TFT。诸多的TFT数量导致移位寄存器中的布线变复杂。因此，期望能够减少移位寄存器中的元件(特别是TFT)的数量，并简化移位寄存器的布线设计。
发明内容
本公开提供了一种移位寄存器单元、选通驱动电路、阵列基板、显示装 置和用于该移位寄存器单元的驱动方法，其能够减少移位寄存器单元所需的TFT的数量，减少移位寄存器单元中的功耗，并减少移位寄存器单元中的布线。
第一方面，提供了一种移位寄存器单元。该移位寄存器单元可包括输入模块、上拉模块、下拉模块和复位模块。输入模块连接到第一信号输入端、和上拉控制节点，用于根据所述第一信号输入端的信号来控制所述上拉控制节点的电位。上拉模块连接到所述上拉控制节点、第二时钟信号端和本级输出端，用于根据所述第二时钟信号端的信号和所述上拉控制节点的电位从所述本级输出端输出本级输出信号。下拉模块连接到第三时钟信号端、所述上拉控制节点、所述本级输出端和电源端，用于根据所述第三时钟信号端的信号将所述上拉控制节点的电位和所述本级输出端的信号下拉为低电平。复位模块，连接到第二信号输入端、所述上拉控制节点、所述本级输出端和电源端，用于根据所述第二信号输入端的信号复位所述上拉控制节点的电位，并将所述本级输出端的信号下拉为低电平。
结合第一方面，在第一方面的一种实现方式中，移位寄存器单元还可包括隔离模块。该隔离模块连接到所述第二时钟信号端和所述上拉控制节点，用于降低所述第二时钟信号端的信号所导致的移位寄存器单元中的信号波动。
结合第一方面及其上述实现方式，在第一方面的另一实现方式中，所述隔离模块还可连接到第一时钟信号端，并可包括：第二电容器，具有连接到第一时钟信号端的第一端和连接到所述上拉控制节点的第二端；第四电容器，具有连接到所述第二时钟信号端的第一端和连接到所述上拉控制节点的第二端。
结合第一方面及其上述实现方式，在第一方面的另一实现方式中，所述隔离模块还可连接到所述第三时钟信号端，并可包括：第三电容器，具有连接到所述第三时钟信号端的第一端和连接到所述上拉控制节点的第二端；第四电容器，具有连接到所述第二时钟信号端的第一端和连接到所述上拉控制节点的第二端。
结合第一方面及其上述实现方式，在第一方面的另一实现方式中，所述第一时钟信号端中的信号、所述第二时钟信号端的信号、和所述第三时钟信号端的信号可以为方波信号，并且分别对应于上一级输出信号、所述本级输 出信号和下一级输出信号。该上一级输出信号是与所述移位寄存器单元相邻的上一级移位寄存器单元的输出信号。所述下一级输出信号是与所述移位寄存器单元相邻的下一级移位寄存器单元的输出信号。
结合第一方面及其上述实现方式，在第一方面的另一实现方式中，所述电源端可连接到所述第二时钟信号端，从而将所述第二时钟信号端中的信号提供给所述电源端来下拉所述上拉控制节点的电位和所述本级输出端的信号。
结合第一方面及其上述实现方式，在第一方面的另一实现方式中，所述输入模块可包括：第一晶体管，其第一极和选通极连接到所述第一信号输入端，其第二极连接到所述上拉控制节点。
结合第一方面及其上述实现方式，在第一方面的另一实现方式中，所述上拉模块可包括：第一电容器，其第一端连接到所述上拉控制节点；第二晶体管，其第一极连接到所述第二时钟信号端，选通极连接到所述第一电容器的第二端，第二极连接到所述本级输出端。
结合第一方面及其上述实现方式，在第一方面的另一实现方式中，所述下拉模块可包括：第三晶体管，其第一极连接到所述上拉控制节点，选通极连接到所述第三时钟信号端，第二极连接到所述电源端；第四晶体管，其第一极连接到所述本级输出端，选通极连接到所述第三时钟信号端，第二极连接到所述电源端。
结合第一方面及其上述实现方式，在第一方面的另一实现方式中，所述复位模块可包括：第五晶体管，其第一极连接到所述上拉控制节点，选通极连接到所述第二信号输入端，第二极连接到所述电源端；第六晶体管，其第一极连接到所述本级输出端，选通极连接到所述第二信号输入端，第二极连接到所述电源端。
第二方面，提供了一种选通驱动电路，包括N个移位寄存器单元。该N个移位寄存器单元是第一移位寄存器单元至第N移位寄存器单元。每一个移位寄存器单元是如上所述的移位寄存器单元，其中N为自然数。所述第二移位寄存器单元至第N移位寄存器单元中的每个移位寄存器单元的第一信号输入端连接到与其相邻的上一级移位寄存器单元的输出端。所述第一移位寄存器单元至第N－1移位寄存器单元中的每个移位寄存器单元的第二信号输入端连接到与其相邻的下一级移位寄存器单元的输出端。
第三方面，提供了一种阵列基板，包括如上所述的选通驱动电路。
第四方面，提供了显示装置，包括如上所述的阵列基板。
第五方面，提供了一种用于移位寄存器单元的驱动方法。该移位寄存器单元包括输入模块、上拉模块、下拉模块、复位模块。该输入模块连接到第一信号输入端、和上拉控制节点。该上拉模块连接到所述上拉控制节点、第二时钟信号端和本级输出端。该下拉模块连接到第三时钟信号端、所述上拉控制节点、所述本级输出端和电源端。该复位模块连接到第二信号输入端、所述上拉控制节点、所述本级输出端和电源端。所述驱动方法可包括：第一阶段，输入模块通过所述第一信号输入端的信号将所述上拉控制节点的电位上拉至第一信号输入端的高电平，所述上拉模块存储所述第一信号输入端的高电平；第二阶段，所述上拉控制节点控制所述上拉模块将所述第二时钟信号端的高电平提供至所述本级输出端以输出所述本级输出信号；第三阶段，所述下拉模块根据所述第三时钟信号端的信号将所述上拉控制节点的电位和所述本级输出端的信号下拉为所述电源端的低电平；第四阶段，所述复位模块根据所述第二信号输入端的信号使所述上拉控制节点的电位复位到所述低电平，并将所述本级输出端的信号下拉为低电平。
结合第五方面，在第五方面的一种实现方式中，所述移位寄存器单元还包括隔离模块，该隔离模块连接到第一时钟信号端、所述第二时钟信号端、所述第三时钟信号端和所述上拉控制节点，并用于降低各个时钟信号端的信号所导致的移位寄存器单元中的信号波动。所述第一时钟信号端中的信号、所述第二时钟信号端的信号、和所述第三时钟信号端的信号为方波信号，并且分别对应于上一级输出信号、所述本级输出信号和下一级输出信号，该上一级输出信号是与所述移位寄存器单元相邻的上一级移位寄存器单元的输出信号，所述下一级输出信号是与所述移位寄存器单元相邻的下一级移位寄存器单元的输出信号。
在根据本公开的实施例的移位寄存器单元、选通驱动电路、显示装置和用于该移位寄存器单元的驱动方法的技术方案中，能够利用时钟信号和TFT来实现移位寄存器，即以简单的方式来实现移位寄存器单元的下拉操作，从而减少移位寄存器单元所需的TFT的数量，减少移位寄存器单元中的功耗，并减少移位寄存器单元中的布线。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，还可以根据这些附图获得其它的附图。
图1是示意性图示了根据本公开实施例的移位寄存器单元的模块结构的框图；
图2是示意性图示了图1中的移位寄存器单元的具体实现的等效电路图；
图3是示意性图示了根据本公开实施例的另一移位寄存器单元的模块结构的框图；
图4是示意性图示了图3中的另一移位寄存器单元的具体实现的等效电路图；
图5是示意性图示了本公开实施例的移位寄存器单元的工作时序的波形图；
图6是示意性图示了根据本公开实施例的选通驱动电路的结构的框图；
图7是示意性图示了根据本公开实施例的阵列基板的结构的框图；
图8是示意性图示了根据本公开实施例的显示装置的结构的框图；
图9是示意性图示了根据本公开实施例的用于移位寄存器单元的驱动方法的流程图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所述获得的所有其他实施例，都属于本公开保护的范围。
本公开所有的实施例中采用的薄膜晶体管是源极和漏极对称的，所有其源极和漏极在名称上可以互换。此外，按照薄膜晶体管的特性区分可以将薄膜晶体管分为N型晶体管或P型晶体管，在本公开实施例中，当采用N型薄膜晶体管时，其第一极可以是源极，第二极可以是选通极，第三极可以是 漏极。本公开实施例中采用的薄膜晶体管可以为N型晶体管，也可以为P型晶体管。在以下实施例中，以薄膜晶体管均为N型晶体管为例进行的说明，即选通极的信号是高电平时，薄膜晶体管导通。此外，在薄膜晶体管为P型晶体管的情况中，当选通极的信号是低电平时，薄膜晶体管导通，需要相应地调整驱动信号的时序。
图1是示意性图示了根据本公开实施例的移位寄存器单元的模块结构的框图。移位寄存器单元用于将输入的时钟信号转换成用于控制各行像素的开启或关断的电压，并逐行地施加到选通线上。如图1所示，移位寄存器单元100可包括：输入模块10、上拉模块20、下拉模块30和复位模块40。
所述输入模块10连接到第一信号输入端Input1、和上拉控制节点PU，用于根据所述第一信号输入端Input1的信号来控制所述上拉控制节点PU的电位。该第一信号输入端Input1用于启动移位寄存器单元100的移位操作。典型地，当移位寄存器单元100输出低电平信号而控制像素行关断时，第一信号输入端Input1促使移位寄存器单元100准备输出高电平信号而控制像素行开启。所述上拉控制节点PU是用于控制上拉模块20的节点。典型地，当该上拉控制节点PU的电压为高电平时，其可以控制移位寄存器单元100输出高电平信号。
所述上拉模块20连接到所述上拉控制节点PU、第二时钟信号端CLK2和本级输出端Output，用于根据所述第二时钟信号端CLK2的信号和所述上拉控制节点PU的电位从所述本级输出端Output输出本级输出信号。典型地，在上拉控制节点PU的电压为高电平时，使能上拉模块20。该上拉模块20例如将第二时钟信号端CLK2的为高电平的信号输出到本级输出端Output。相应地，本级输出端Output能够输出高电平的信号，以控制像素行开启。第二时钟信号端CLK2的信号典型地为高电平。
第二时钟信号端CLK2的信号可以为方波信号，并例如可以对应于移位寄存器100的输出。典型地，在第二时钟信号端CLK2的信号的一个时钟周期中，在第二时钟信号端CLK2的信号为用于使能上拉模块20的高电平信号时，移位寄存器100的输出信号为使能对应像素行的高电平信号；在移位寄存器100的输出信号为禁能对应像素行的低电平信号，第二时钟信号端CLK2的信号相应地是用于禁能上拉模块20的低电平信号。
通常，在多级移位寄存器中，当与移位寄存器100相邻的上一级移位寄 存器的输出端的信号从高电平变成低电平，移位寄存器100的本级输出端的信号从高电平变成低电平，以启动与移位寄存器100对应的像素行的显示。在上拉模块20输出高电平信号之前，所述输入模块10需要上拉所述上拉控制节点PU的电位。相应地，可以将上一级移位寄存器的输出端的信号提供给输入模块10的第一信号输入端Input1，以在上拉模块20输出高电平信号之前上拉所述上拉控制节点PU的电位。
本级输出端Output在输出特定时间段的高电平信号之后，根据需要将输出信号转换为低电平信号。所述下拉模块30典型地用于将本级输出端Output的信号下拉为低电平。
如图1所示，下拉模块30连接到第三时钟信号端CLK3、所述上拉控制节点PU、所述本级输出端Output和电源端Vss，用于根据所述第三时钟信号端CLK3的信号将所述上拉控制节点PU的电位和所述本级输出端Output的信号下拉为低电平。所述电源端Vss例如输出恒定的低电平信号。所述第三时钟信号端CLK3的信号用于启动所述下拉模块30的下拉操作，从而将本级输出端Output所输出的高电平信号下拉到所述电源端Vss的低电平信号。下拉模块30还可以根据第三时钟信号端CLK3的信号的控制将上拉控制节点PU的电位下拉至低电平信号。
第三时钟信号端CLK3的信号可以为方波信号，并例如可以对应于与移位寄存器100相邻的下一级移位寄存器的输出。典型地，在第三时钟信号端CLK3的信号的一个时钟周期中，在第三时钟信号端CLK3的信号为高电平信号时，下一级移位寄存器的输出信号为使能对应像素行的高电平信号；在下一级移位寄存器的输出信号为禁能对应像素行的低电平信号，第三时钟信号端CLK3的信号相应地是低电平信号。
图1中的复位模块40连接到第二信号输入端Input2、所述上拉控制节点PU、所述本级输出端Output和电源端Vss，用于根据所述第二信号输入端Input2的信号复位所述上拉控制节点PU的电位，并将所述本级输出端的信号下拉为低电平。典型地，在移位寄存器单元100输出高电平信号而控制像素行进行显示之后，复位模块40促使移位寄存器单元100复位以准备下一次的开启控制。通常，在多级移位寄存器中，当移位寄存器100的本级输出端的信号从高电平变成低电平时，与移位寄存器100相邻的下一级移位寄存器的输出端的信号从低电平变成高电平，以启动与所述下一级移位寄存器 对应的像素行的显示。相应地，可以将下一级移位寄存器的输出端的信号提供给所述第二信号输入端Input2，以控制复位模块40的操作。
此外，根据以上描述可知，在时钟信号的一个工作周期中，第二时钟信号端CLK2的信号对应于本级输出信号，并且二者在从高电平变为低电平时，所述电源端Vss所提供的信号为下拉模块提供了下拉后的电平基准，并且为复位模块提供了复位后的电平基准。相应地，可以将所述第二时钟信号端中的信号提供给所述电源端来下拉所述上拉控制节点的电位和所述本级输出端的信号，这可以通过连接所述电源端和所述时钟信号端来实现。此时，不需要为电源端Vss提供专门的低电平信号，而是利用第二时钟信号中的低电平部分提供电源端Vss的低电平信号。因此，节省了移位寄存器100中的电源线，并且简化了移位寄存器100中的布线设计。
在移位寄存器100输出用于使能对应像素行的使能信号之后，复位模块40和下拉模块30二者使得迅速地停止该使能信号，并进入复位状态，以用于下一次的使能信号输出。复位模块40和下拉模块30避免了与移位寄存器100对应的像素行的上一次显示对其下一次显示的影响。
在根据本公开的实施例的移位寄存器单元的技术方案中，能够利用第三时钟信号控制下拉模块的操作，而无需专门的下拉控制模块，即以简单的方式来实现移位寄存器单元的下拉操作。相应地，减少了移位寄存器单元所需的TFT的数量，减少了移位寄存器单元中的功耗，并减少移位寄存器单元中的布线。
图2是示意性图示了图1中的移位寄存器单元100的具体实现的等效电路图。在图2中，示出了移位寄存器单元100的各个模块的具体实现。
如图2所示，输入模块10包括：第一晶体管M1，其第一极和选通极连接到所述第一信号输入端Input1，其第二极连接到所述上拉控制节点PU。如上所述，第一信号输入端Input1可以是上一级移位寄存器单元的输出。在移位寄存器单元100输出用于使能对应像素行的高电平信号之前，第一信号输入端Input1的高电平信号使得第一晶体管M1导通，并且将上一级移位寄存器单元所输出的高电平信号传送到所述上拉控制节点PU，以提高所述上拉控制节点PU的电位。这里，输入模块10为实现为第一晶体管M1，并且将第一极和选通极二者连接到所述第一信号输入端Input1。替换地，还可以为第一晶体管M1的选通极提供控制信号，该控制信号可以利用其它晶体管 来提供。输入模块10的具体实现结构和控制方式等不构成对本公开实施例的限制。
在图2的实现中，上拉模块20可包括：第一电容器C1，其第一端连接到所述上拉控制节点PU；第二晶体管M2，其第一极连接到所述第二时钟信号端CLK2，选通极连接到所述第一电容器C1的第二端，第二极连接到所述本级输出端Output。在输入模块10提高所述上拉控制节点PU的电位的过程中，第一电容器C1充电，并在其中储存电能。所述上拉控制节点PU的电位上升之后，第二晶体管M2导通，并将第二时钟信号端CLK2的信号传送到本级输出端Output，以输出本级输出信号。第一电容器C1的电量储存功能使得第二晶体管M2能够将本级输出信号的高电平保持期望的时间段。第二时钟信号端CLK2的信号可以对应于移位寄存器100的输出。这里的第一电容器C1仅仅是示例，还可以采用其它的元件与本级输出信号对应地导通第二晶体管M2。
本级输出端Output在输出特定时间段的高电平信号之后，下拉模块30降低本级输出信号的电平，并降低所述上拉控制节点PU的电平，以使得所述上拉模块20不再输出高电平的本级输出信号。第三时钟信号端CLK3例如可以对应于与移位寄存器100相邻的下一级移位寄存器的输出。如图2所示，所述下拉模块30包括第三晶体管M3和第四晶体管M4。
第三晶体管M3的第一极连接到所述上拉控制节点PU，其选通极连接到所述第三时钟信号端CLK3，第二极连接到所述电源端Vss。例如，在第三时钟信号端CLK3的信号为高电平时，第三晶体管M3导通，以将所述上拉控制节点PU连接到所述电源端Vss。由于电源端Vss为低电平，所以第三晶体管M3的导通降低了所述上拉控制节点PU的电平，即下拉为等于或接近所述低电平的电平。
第四晶体管M4的第一极连接到所述本级输出端Output，选通极连接到所述第三时钟信号端CLK3，第二极连接到所述电源端Vss。例如，在第三时钟信号端CLK3的信号为高电平时，第四晶体管M4导通，以将所述本级输出端Output连接到所述电源端Vss。也就是说，第四晶体管M4的导通降低了所述本级输出端Output的电平，即下拉为等于或接近所述低电平的电平。
上述的下拉模块30仅仅是示例，其还可以具有其它结构。例如，还可 以在下拉模块30中增加与第四晶体管M4并联连接的晶体管，以更快地降低本级输出信号的电平。该并联连接的晶体管的第一极连接到所述本级输出端Output，其选通极连接到所述第三时钟信号端CLK3，其第二极连接到所述电源端Vss。
图2中的复位模块40包括第五晶体管M5和第六晶体管M6。第五晶体管M5的第一极连接到所述上拉控制节点PU，选通极连接到所述第二信号输入端Input2，第二极连接到所述电源端Vss。第六晶体管M6的第一极连接到所述本级输出端Output，选通极连接到所述第二信号输入端Input2，第二极连接到所述电源端Vss。第二信号输入端Input2提供用于使移位寄存器单元100复位的复位信号Reset。如上所述，可以将下一级移位寄存器的输出端的信号OutN提供给所述第二信号输入端Input2，即所述复位信号Reset为下一级移位寄存器的输出端的信号OutN。
典型地，在复位信号Reset为高电平时，第五晶体管M5导通而将所述上拉控制节点PU连接到所述电源端Vss，第六晶体管M6导通而将所述本级输出端Output连接到所述电源端Vss。由于电源端Vss为低电平，所以第五晶体管M5和第六晶体管M6的导通降低了所述上拉控制节点PU的电平。也就是说，复位模块40根据复位信号Reset对移位寄存器单元进行了复位操作。在移位寄存器单元100输出高电平信号而控制像素行进行显示之后，复位模块40促使移位寄存器单元100复位以准备下一次的开启控制。上述的复位模块40仅仅是示例，其还可以具有其它结构。例如，还可以在复位模块40中增加与第五晶体管M5并联连接的晶体管，以更快地降低本级输出信号的电平。
在移位寄存器100输出用于使能对应像素行的使能信号之后，复位模块40和下拉模块30二者使得迅速地停止该使能信号，并进入复位状态，以用于下一次的使能信号输出。复位模块40和下拉模块30避免了与移位寄存器100对应的像素行的上一次显示对其下一次显示的影响。
图3是示意性图示了根据本公开实施例的另一移位寄存器单元300的模块结构的框图。在图3中，与图1中的移位寄存器单元100相同的模块采用相同的附图标记来标示。图3中的输入模块10、上拉模块20、下拉模块30、复位模块40分别与图1中的各个模块对应，并可以参见上面结合图1进行的描述。
相对于图1中的移位寄存器单元100，图3中的移位寄存器单元300还包括隔离模块50。该隔离模块50连接到所述第二时钟信号端CLK2、所述第二时钟信号端CLK2和所述上拉控制节点PU，用于降低所述第二时钟信号端CLK2或所述第三时钟信号端CLK3的信号所导致的移位寄存器单元中的信号波动。所述第二时钟信号端CLK2中的时钟信号在每个时钟周期中会有幅度变化。该幅度变化可能导致移位寄存器单元中的布线中的信号波动，从而影响所述移位寄存器单元的工作。类似地，第三时钟信号端CLK3中的时钟信号的幅度变化也导致移位寄存器单元中的布线中的信号波动，从而影响所述移位寄存器单元的工作。例如，当上拉控制节点PU中的信号由于时钟信号而波动时，可以导致本级输出信号的波动。这里，采用隔离模块50降低各个时钟信号所导致的移位寄存器单元中的信号波动。
图4是示意性图示了图3中的另一移位寄存器单元的具体实现的等效电路图。在图4中，与图2中的移位寄存器单元相同的元件采用相同的附图标记来标示，并可以参见上面结合图2进行的描述。图4具体示出了图3中的隔离模块50的结构以及其与图2中的其它元件之间的连接关系。
如图4所示，隔离模块50还连接到第一时钟信号端CLK1，并包括第二电容器C2、第三电容器C3、和第四电容器C4。第二电容器C2的第一端连接到第一时钟信号端CLK1，其第二端连接到所述上拉控制节点PU。第三电容器C3的第一端连接到所述第三时钟信号端CLK3，其第二端连接到所述上拉控制节点PU。第四电容器C4的第一端连接到所述第二时钟信号端CLK2，其第二端连接到所述上拉控制节点PU。所述第二电容器C2和第四电容器C4用于避免第二时钟信号端CLK2对移位寄存器单元的影响。所述第二电容器C2和第三电容器C3用于避免第三时钟信号端CLK3对移位寄存器单元的影响。在实践中，可以根据需要适当地选择。例如，该隔离模块50可以仅仅包括所述第二电容器C2和第四电容器C4，或者仅包括所述第二电容器C2和第三电容器C3。
第一时钟信号端CLK1经由第二电容器连接到上拉控制节点PU，第二时钟信号端CLK2经由第四电容器C4连接到上拉控制节点PU。在同一时钟周期中，当第二时钟信号端CLK2的信号从高变化为低时，可以使第一时钟信号端CLK1的信号相反地从低变化为高，该相反变化可以抵消第二时钟信号对上拉控制节点PU中的信号的影响。当第二时钟信号端CLK2的信号从 低变化为高时，可以使第一时钟信号端CLK1的信号相反地从高变化为低。
第一时钟信号端CLK1经由第二电容器C2连接到上拉控制节点PU，第三时钟信号端CLK3经由第三电容器C3连接到上拉控制节点PU。在同一时钟周期中，当第三时钟信号端CLK3的信号从高变化为低时，可以使第一时钟信号端CLK1的信号相反地从低变化为高，该相反变化可以抵消第三时钟信号对上拉控制节点PU中的信号的影响。类似地，当第三时钟信号端CLK3的信号从低变化为高时，可以使第一时钟信号端CLK1的信号相反地从高变化为低。
如上所述，所述第二时钟信号端的信号、和所述第三时钟信号端的信号可以分别对应于所述本级输出信号和下一级输出信号。此时，第一时钟信号端的信号可以对应于上一级输出信号。该上一级输出信号是与所述移位寄存器单元相邻的上一级移位寄存器单元的输出信号。
图5是示意性图示了图4的移位寄存器单元的工作时序的波形图。在图5中，示出了第一时钟信号端CLK1中的信号、第二时钟信号端CLK2中的信号、和第三时钟信号端CLK3中的信号、第一信号输入端Input1的上一级输出信号OutN-1、本级输出信号OutN、和第二信号输入端Input2的下一级输出信号OutN+1。上一级输出信号是与所述移位寄存器单元相邻的上一级移位寄存器单元的输出信号。所述下一级输出信号是与所述移位寄存器单元相邻的下一级移位寄存器单元的输出信号。
根据图5可以看出，所述第一时钟信号端CLK1中的信号、所述第二时钟信号端CLK2的信号、和所述第三时钟信号端CLK3的信号为方波信号，并依次相差一个周期中的高电平持续时间。也就是说，在一个时钟周期中，第一至第三时钟信号端中的信号依次为高电平。
在一个时钟周期中，第一时钟信号端CLK1中的信号对应于上一级输出信号OutN-1；第二时钟信号端CLK2的信号对应于本级输出信号OutN；第三时钟信号端CLK3的信号对应于下一级输出信号OutN+1。例如，在第一时钟信号端CLK1的信号的一个时钟周期中，在第一时钟信号端CLK1的信号为用于使能输出的高电平信号时，上一级移位寄存器的输出信号为使能对应像素行的高电平信号；当第一时钟信号端CLK1的信号为用于禁能输出的低电平信号时，上一级移位寄存器的输出信号为禁能对应像素行的低电平信号。
如图5所示，在第二时钟信号端CLK2的信号从低变成高时，第一时钟信号端CLK1的信号相反地从高变成低，从而能有效地降低第二时钟信号端的信号波动对本级移位寄存器单元的输出信号的影响；在第三时钟信号端CLK3的信号从高变成低时，第一时钟信号端CLK1的信号相反地从低变成高，从而能有效地降低第三时钟信号端CLK3的信号波动对本级移位寄存器单元的输出信号的影响。
图6是示意性图示了根据本公开实施例的选通驱动电路600的结构的框图。选通驱动电路600包括多级移位寄存器单元，即SR1、SR2、SR3.......SRN-1、SRN。每级移位寄存器单元都可以采用上文中所描述的结构。
如图6所示，每级移位寄存器单元具有三个时钟输入端CLK1、CLK2、CLK3和电源端Vss。三个时钟输入端中的时钟信号例如可以是如图5所示的方波信号。电源端Vss用于输入低电平信号，以在移位寄存器单元的高电平输出结束时实现下拉操作和复位操作。
对于除了第一级移位寄存器单元和最后一级移位寄存器单元之外的其它移位寄存器单元SRn，将上一级移位寄存器单元SRn－1的输出端连接到该移位寄存器单元SRn的第一信号输入端Input1，并将下一级移位寄存器单元SRn+1的输出端连接到该移位寄存器单元SRn的第二信号输入端Input2，其中，n是自然数，并且大于1小于N。
在各级移位寄存器单元中的第一极移位寄存器单元SR0的第一信号输入端Input1，输入扫描启动信号STV-U，各级移位寄存器单元(SR1、SR2、SR3.......SRN-1、SRN)的本级信号输出端Output依次地将扫描信号输出到与其相对应的选通线(G1、G2、G3…GN-1、GN)上。最后一级移位寄存器单元SRN的第二信号输入端Input2可以输入扫描结束信号STV-E。该扫描结束信号STV-E可以是最后一级移位寄存器单元SRN的输出Output(GN)。通过控制第一极移位寄存器单元SR1的第一信号输入端Input1和最后一级移位寄存器单元SRN的第二信号输入端Input2，可以利用选通驱动电路600实现单向扫描、双向扫描等不同的扫描方式。
根据本公开实施例的选通驱动电路可应用于各种装置或模块。图7是示意性图示了根据本公开实施例的阵列基板700的结构的框图。如图7所示，阵列基板可包括：像素阵列；根据本公开实施例的选通驱动电路，用于产生与各行像素分别一一对应的选通驱动信号；数据驱动电路，用于向所选通的 各行像素提供数据。当图7中的选通驱动电路所输出的选通驱动信号驱动了像素阵列中的特定行时，该特定行中的像素被使能，从而能够从数据驱动电路接收数据信号和进行翻转。图7仅仅是阵列基板的示例性结构，其还可以包括其它组成部分，例如基板、绝缘隔离层等。本领域技术人员可以根据需要设计包括根据本公开实施例的选通驱动电路的合适阵列基板。
图8是示意性图示了根据本公开实施例的显示装置800的框图。该显示装置例如可以是薄膜晶体管液晶显示器(TFT LCD)、有源矩阵有机发光二极体显示器(AMOLED)、扭曲向列型(TN)、或广视角宽屏液晶显示器(ADS)等。以薄膜晶体管液晶显示器为例，显示装置可包括：上述的阵列基板；彩膜基板，与阵列基板对合地设置；液晶层：位于阵列基板和彩膜基板之间。此外，显示装置还可能包括用于产生背光的背光单元等。
在根据本公开的实施例的阵列基板和显示装置的技术方案中，能够利用第三时钟信号控制下拉模块的操作，而无需专门的下拉控制模块，从而以简单的方式来实现移位寄存器单元的下拉操作。相应地，减少了阵列基板和显示装置所需的TFT的数量，减少了阵列基板和显示装置中的功耗和布线。
图9是示意性图示了根据本公开实施例的用于移位寄存器单元的驱动方法900的流程图。驱动方法900所应用于的移位寄存器单元可包括输入模块、上拉模块、下拉模块、复位模块。输入模块连接到第一信号输入端、和上拉控制节点。上拉模块连接到所述上拉控制节点、第二时钟信号端和本级输出端。下拉模块连接到第三时钟信号端、所述上拉控制节点、所述本级输出端和电源端。该复位模块连接到第二信号输入端、所述上拉控制节点、所述本级输出端和电源端。移位寄存器单元的结构可以参见图1和图2的图示和相关的描述。
如图9所示，该所述驱动方法可包括：第一阶段，输入模块通过所述第一信号输入端的信号将所述上拉控制节点的电位上拉至第一信号输入端的高电平，所述上拉模块存储所述第一信号输入端的高电平(S910)；第二阶段，所述上拉控制节点控制所述上拉模块将所述第二时钟信号端的高电平提供至所述本级输出端以输出所述本级输出信号(S920)；第三阶段，所述下拉模块根据所述第三时钟信号端的信号将所述上拉控制节点的电位和所述本级输出端的信号下拉为所述电源端的低电平(S930)；第四阶段，所述复位模块根据所述第二信号输入端的信号使所述上拉控制节点的电位复位到 所述低电平，并将所述本级输出端的信号下拉为低电平(S940)。下面进一步结合图1、图2和图5描述各个步骤。
在S910中，启动移位寄存器单元的移位操作。将上一级移位寄存器的输出信号OutN-1(下文简称为上一级输出信号)提供给第一信号输入端。如图5所示，在上一级输出信号OutN-1为高电平时，开始执行S910。以输入模块具有图2中所示的结构为例，当上一级输出信号OutN-1为高时，第一晶体管M1导通，并且该高电平的上一级输出信号OutN-1被传送到所述上拉控制节点PU，以提高所述上拉控制节点PU的电位。上拉控制节点PU的电位升高对图2中的上拉模块中的第一电容器C1充电，直到上一级输出信号OutN-1的高电平结束时。也就是说，所述上拉模块利用第一电容器C1存储所述第一信号输入端的高电平。第一阶段典型地对应于图5中的上一级输出信号OutN-1为高电平的期间。
第二阶段典型地对应于图5中的本级输出信号OutN为高电平的期间。上拉控制节点PU的电位升高之后，图2的上拉模块中的第二晶体管M2导通，并将第二时钟信号端CLK2的高电平信号传送到本级输出端Output，以输出高电平的本级输出信号。在第二时钟信号端CLK2的信号的高电平持续时间期间，所输出的本级输出信号使能与该移动电位寄存器对应的像素行，使得该像素接收数据以进行显示。
第三阶段典型地对应于图5中的下一级输出信号OutN+1为高电平的期间。在此阶段，移位寄存器单元停止输出高电平，以停止其对应的像素行的显示操作。也就是说，本级输出信号OutN在第三阶段为低电平。下拉模块根据图5中的第三时钟信号端CLK3的信号将所述上拉控制节点的电位和所述本级输出端的信号下拉为所述电源端的低电平。
如图5所示，第三时钟信号端CLK3的信号在第三阶段中为高电平。该第三时钟信号端CLK3的信号使能下拉模块执行下拉操作。在如图2所示的包括第三晶体管M3和第四晶体管M4的下拉模块中，在第三时钟信号端CLK3的信号为高电平期间，第三晶体管M3导通，以将所述上拉控制节点PU连接到所述电源端；第四晶体管M4导通，以将所述本级输出端Output连接到所述电源端。由于电源端Vss为低电平，所以第三晶体管M3和第四晶体管M4的导通分别降低了所述上拉控制节点PU和输出端Output的电平。
第四阶段典型地也对应于图5中的下一级输出信号OutN+1为高电平的 期间。第三阶段是下拉模块在下一级输出信号OutN+1为高电平期间的操作。第四阶段是复位模块在下一级输出信号OutN+1为高电平期间的操作。在第四阶段中，所述复位模块根据所述第二信号输入端的信号使所述上拉控制节点的电位复位到所述低电平，并将所述本级输出端的信号下拉为低电平。
在如图2所示的包括第五晶体管M5和第六晶体管M6的复位模块中，在第三时钟信号端CLK3的信号为高电平期间，第五晶体管M5导通，以将所述上拉控制节点PU连接到所述电源端；第六晶体管M6，以将所述本级输出端Output连接到所述电源端。由于电源端Vss为低电平，所以第五晶体管M5和第六晶体管M6的导通分别降低了所述上拉控制节点PU和输出端Output的电平。也就是说，复位模块根据复位信号Reset(例如，上述的下一级输出信号OutN+1)对移位寄存器单元进行了复位操作，促使移位寄存器单元准备下一次的开启控制。
在移位寄存器输出用于使能对应像素行的使能信号之后，S930和S940中的操作使得移位寄存器单元迅速地停止该使能信号，并进入复位状态，以用于下一次的使能信号输出。相应地，避免了与移位寄存器对应的像素行的上一次显示对其下一次显示的影响。
驱动方法900所应用于的移位寄存器单元还可以包括隔离模块。该隔离模块的结构和其与其它模块的连接关系可以参见图3和图4的图示以及相关的描述。为了利用隔离模块降低第二和第三时钟信号端的信号所导致的移位寄存器单元中的信号波动，隔离模块还可以连接到第一时钟信号端。第一时钟信号端中的信号波动可以与第二时钟信号端的信号波动相反，以降低第二时钟信号端的信号波动的影响。第一时钟信号端中的信号波动可以与第三时钟信号端的信号波动相反，以降低第三时钟信号端的信号波动的影响。
如图5所示，所述第一时钟信号端中的信号可以为方波信号，并且对应于上一级输出信号。该上一级输出信号是与所述移位寄存器单元相邻的上一级移位寄存器单元的输出信号。所述第二时钟信号端的信号对应于所述本级输出信号。所述第三时钟信号端的信号对应于下一级输出信号。所述下一级输出信号是与所述移位寄存器单元相邻的下一级移位寄存器单元的输出信号。
在根据本公开的实施例的用于移位寄存器单元的驱动方法的技术方案中，能够利用第三时钟信号控制下拉模块的操作，而无需专门的下拉控制模 块，即以简单的方式来实现移位寄存器单元的下拉操作。相应地，减少了移位寄存器单元所需的TFT的数量，减少了移位寄存器单元中的功耗和布线。此外，利用隔离单元和第一时钟信号端中的信号能够降低各个时钟信号的信号波动的影响。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的驱动方法所应用于的移位寄存器单元的具体实现和结构，可以参考前面结合图1至图4描述的移位寄存器单元的实施例中的图示和操作，在此不再赘述。
在本公开所提供的实施例中，应该理解到，所揭露的装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，上述方法实施例中的部分步骤可以进行重新组合。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以权利要求的保护范围为准。
本申请要求于2015年4月9日递交的中国专利申请第201510164786.5号的优先权，在此全文引用该中国专利申请公开的内容作为本申请的一部分。

Claims (15)

  1. 一种移位寄存器单元，包括：
    输入模块，连接到第一信号输入端、和上拉控制节点，用于根据所述第一信号输入端的信号来控制所述上拉控制节点的电位；
    上拉模块，连接到所述上拉控制节点、第二时钟信号端和本级输出端，用于根据所述第二时钟信号端的信号和所述上拉控制节点的电位从所述本级输出端输出本级输出信号；
    下拉模块，连接到第三时钟信号端、所述上拉控制节点、所述本级输出端和电源端，用于根据所述第三时钟信号端的信号将所述上拉控制节点的电位和所述本级输出端的信号下拉为低电平；
    复位模块，连接到第二信号输入端、所述上拉控制节点、所述本级输出端和电源端，用于根据所述第二信号输入端的信号复位所述上拉控制节点的电位，并将所述本级输出端的信号下拉为低电平。
  2. 根据权利要求1的移位寄存器单元，还包括：隔离模块，连接到所述第二时钟信号端和所述上拉控制节点，用于降低所述第二时钟信号端的信号所导致的移位寄存器单元中的信号波动。
  3. 根据权利要求2的移位寄存器单元，其中，所述隔离模块还连接到第一时钟信号端，并包括：
    第二电容器，具有连接到第一时钟信号端的第一端和连接到所述上拉控制节点的第二端；
    第四电容器，具有连接到所述第二时钟信号端的第一端和连接到所述上拉控制节点的第二端。
  4. 根据权利要求2或3的移位寄存器单元，其中，所述隔离模块还连接到所述第三时钟信号端，并包括：
    第三电容器，具有连接到所述第三时钟信号端的第一端和连接到所述上拉控制节点的第二端；
    第四电容器，具有连接到所述第二时钟信号端的第一端和连接到所述上拉控制节点的第二端。
  5. 根据权利要求4的移位寄存器单元，其中，所述第一时钟信号端中的信号、所述第二时钟信号端的信号、和所述第三时钟信号端的信号为方波 信号，并且分别对应于上一级输出信号、所述本级输出信号和下一级输出信号，该上一级输出信号是与所述移位寄存器单元相邻的上一级移位寄存器单元的输出信号，所述下一级输出信号是与所述移位寄存器单元相邻的下一级移位寄存器单元的输出信号。
  6. 根据权利要求1的移位寄存器单元，其中，所述电源端连接到所述第二时钟信号端，从而将所述第二时钟信号端中的信号提供给所述电源端来下拉所述上拉控制节点的电位和所述本级输出端的信号。
  7. 根据权利要求1的移位寄存器单元，其中，所述输入模块包括：
    第一晶体管，其第一极和选通极连接到所述第一信号输入端，其第二极连接到所述上拉控制节点。
  8. 根据权利要求1的移位寄存器单元，其中，所述上拉模块包括：
    第一电容器，其第一端连接到所述上拉控制节点；
    第二晶体管，其第一极连接到所述第二时钟信号端，选通极连接到所述第一电容器的第二端，第二极连接到所述本级输出端。
  9. 根据权利要求1的移位寄存器单元，其中，所述下拉模块包括：
    第三晶体管，其第一极连接到所述上拉控制节点，选通极连接到所述第三时钟信号端，第二极连接到所述电源端；
    第四晶体管，其第一极连接到所述本级输出端，选通极连接到所述第三时钟信号端，第二极连接到所述电源端。
  10. 根据权利要求1的移位寄存器单元，其中，所述复位模块包括：
    第五晶体管，其第一极连接到所述上拉控制节点，选通极连接到所述第二信号输入端，第二极连接到所述电源端；
    第六晶体管，其第一极连接到所述本级输出端，选通极连接到所述第二信号输入端，第二极连接到所述电源端。
  11. 一种选通驱动电路，包括N个移位寄存器单元，该N个移位寄存器单元是第一移位寄存器单元至第N移位寄存器单元，每一个移位寄存器单元是如权利要求1至10中任一项所述的移位寄存器单元，其中N为自然数，
    所述第二移位寄存器单元至第N移位寄存器单元中的每个移位寄存器单元的第一信号输入端连接到与其相邻的上一级移位寄存器单元的输出端，
    所述第一移位寄存器单元至第N－1移位寄存器单元中的每个移位寄存器单元的第二信号输入端连接到与其相邻的下一级移位寄存器单元的输出 端。
  12. 一种阵列基板，包括如权利要求11所述的选通驱动电路。
  13. 一种显示装置，包括如权利要求12所述的阵列基板。
  14. 一种用于移位寄存器单元的驱动方法，该移位寄存器单元包括输入模块、上拉模块、下拉模块、复位模块，该输入模块连接到第一信号输入端、和上拉控制节点，该上拉模块连接到所述上拉控制节点、第二时钟信号端和本级输出端，该下拉模块连接到第三时钟信号端、所述上拉控制节点、所述本级输出端和电源端，该复位模块连接到第二信号输入端、所述上拉控制节点、所述本级输出端和电源端，所述驱动方法包括：
    第一阶段，输入模块通过所述第一信号输入端的信号将所述上拉控制节点的电位上拉至第一信号输入端的高电平，所述上拉模块存储所述第一信号输入端的高电平；
    第二阶段，所述上拉控制节点控制所述上拉模块将所述第二时钟信号端的高电平提供至所述本级输出端以输出所述本级输出信号；
    第三阶段，所述下拉模块根据所述第三时钟信号端的信号将所述上拉控制节点的电位和所述本级输出端的信号下拉为所述电源端的低电平；
    第四阶段，所述复位模块根据所述第二信号输入端的信号使所述上拉控制节点的电位复位到所述低电平，并将所述本级输出端的信号下拉为低电平。
  15. 根据权利要求14的驱动方法，其中，所述移位寄存器单元还包括隔离模块，该隔离模块连接到第一时钟信号端、所述第二时钟信号端、所述第三时钟信号端和所述上拉控制节点，并用于降低各个时钟信号端的信号所导致的移位寄存器单元中的信号波动，
    其中，所述第一时钟信号端中的信号、所述第二时钟信号端的信号、和所述第三时钟信号端的信号为方波信号，并且分别对应于上一级输出信号、所述本级输出信号和下一级输出信号，该上一级输出信号是与所述移位寄存器单元相邻的上一级移位寄存器单元的输出信号，所述下一级输出信号是与所述移位寄存器单元相邻的下一级移位寄存器单元的输出信号。
PCT/CN2015/089720 2015-04-09 2015-09-16 移位寄存器单元、驱动电路和方法、阵列基板和显示装置 WO2016161768A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/906,744 US10068658B2 (en) 2015-04-09 2015-09-16 Shift register unit, driving circuit and method, array substrate and display apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510164786.5 2015-04-09
CN201510164786.5A CN104715733A (zh) 2015-04-09 2015-04-09 移位寄存器单元、驱动电路和方法、阵列基板和显示装置

Publications (1)

Publication Number Publication Date
WO2016161768A1 true WO2016161768A1 (zh) 2016-10-13

Family

ID=53415001

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/089720 WO2016161768A1 (zh) 2015-04-09 2015-09-16 移位寄存器单元、驱动电路和方法、阵列基板和显示装置

Country Status (3)

Country Link
US (1) US10068658B2 (zh)
CN (1) CN104715733A (zh)
WO (1) WO2016161768A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020514940A (ja) * 2017-03-20 2020-05-21 京東方科技集團股▲ふん▼有限公司Ｂｏｅ Ｔｅｃｈｎｏｌｏｇｙ Ｇｒｏｕｐ Ｃｏ．，Ｌｔｄ． シフトレジスタユニット、ゲート駆動回路及び駆動方法

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104715733A (zh) 2015-04-09 2015-06-17 京东方科技集团股份有限公司 移位寄存器单元、驱动电路和方法、阵列基板和显示装置
CN105185339B (zh) 2015-10-08 2017-12-29 京东方科技集团股份有限公司 移位寄存器单元、栅线驱动装置以及驱动方法
CN105185412A (zh) 2015-10-19 2015-12-23 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路和显示装置
CN105869563B (zh) * 2016-05-30 2019-01-18 京东方科技集团股份有限公司 Goa单元电路及其驱动方法、goa电路
CN107086023A (zh) * 2017-05-04 2017-08-22 合肥鑫晟光电科技有限公司 像素驱动补偿电路及其驱动补偿方法、显示装置
CN106997755B (zh) * 2017-05-10 2019-06-04 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路、显示装置
CN108962154B (zh) 2017-05-17 2021-01-15 京东方科技集团股份有限公司 移位寄存器单元、阵列基板栅极驱动电路、显示器以及栅极驱动方法
CN107274856A (zh) * 2017-08-22 2017-10-20 京东方科技集团股份有限公司 一种移位寄存器及其驱动方法、栅极驱动电路
CN107516505B (zh) 2017-10-19 2021-01-15 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路和显示面板
CN110503927B (zh) * 2018-05-16 2020-11-10 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
CN109256083A (zh) * 2018-11-23 2019-01-22 合肥京东方光电科技有限公司 移位寄存器单元及其驱动方法、栅极驱动电路和显示装置
WO2021081703A1 (zh) * 2019-10-28 2021-05-06 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路和显示装置
TWI726523B (zh) 2019-12-06 2021-05-01 友達光電股份有限公司 驅動電路
CN113409717B (zh) * 2021-05-13 2022-06-10 北京大学深圳研究生院 移位寄存器单元电路，栅极驱动电路及显示器

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6052426A (en) * 1994-05-17 2000-04-18 Thomson Lcd Shift register using M.I.S. transistors of like polarity
CN101064085A (zh) * 2006-04-25 2007-10-31 三菱电机株式会社 移位寄存器电路和具备其的图像显示装置
CN101510443A (zh) * 2009-04-08 2009-08-19 友达光电股份有限公司 能降低耦合效应的移位寄存器
US20100245298A1 (en) * 2009-03-24 2010-09-30 Yung-Chih Chen Shift register capable of reducing coupling effect
CN103956133A (zh) * 2014-02-13 2014-07-30 友达光电股份有限公司 移位暂存电路及移位暂存器
CN104715733A (zh) * 2015-04-09 2015-06-17 京东方科技集团股份有限公司 移位寄存器单元、驱动电路和方法、阵列基板和显示装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102012591B (zh) * 2009-09-04 2012-05-30 北京京东方光电科技有限公司 移位寄存器单元及液晶显示器栅极驱动装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6052426A (en) * 1994-05-17 2000-04-18 Thomson Lcd Shift register using M.I.S. transistors of like polarity
CN101064085A (zh) * 2006-04-25 2007-10-31 三菱电机株式会社 移位寄存器电路和具备其的图像显示装置
US20100245298A1 (en) * 2009-03-24 2010-09-30 Yung-Chih Chen Shift register capable of reducing coupling effect
CN101510443A (zh) * 2009-04-08 2009-08-19 友达光电股份有限公司 能降低耦合效应的移位寄存器
CN103956133A (zh) * 2014-02-13 2014-07-30 友达光电股份有限公司 移位暂存电路及移位暂存器
CN104715733A (zh) * 2015-04-09 2015-06-17 京东方科技集团股份有限公司 移位寄存器单元、驱动电路和方法、阵列基板和显示装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020514940A (ja) * 2017-03-20 2020-05-21 京東方科技集團股▲ふん▼有限公司Ｂｏｅ Ｔｅｃｈｎｏｌｏｇｙ Ｇｒｏｕｐ Ｃｏ．，Ｌｔｄ． シフトレジスタユニット、ゲート駆動回路及び駆動方法
JP7076462B2 (ja) 2017-03-20 2022-05-27 京東方科技集團股▲ふん▼有限公司 シフトレジスタユニット、ゲート駆動回路及び駆動方法

Also Published As

Publication number Publication date
US10068658B2 (en) 2018-09-04
CN104715733A (zh) 2015-06-17
US20170092376A1 (en) 2017-03-30

Similar Documents

Publication Publication Date Title
WO2016161768A1 (zh) 移位寄存器单元、驱动电路和方法、阵列基板和显示装置
US9990897B2 (en) Shift register unit, gate driving circuit and driving method thereof, and array substrate
USRE49782E1 (en) Shift register and driving method thereof gate driving circuit and display apparatus
US10043473B2 (en) GOA circuit
WO2020015569A1 (zh) 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
US8229058B2 (en) Shift register of LCD devices
US9293223B2 (en) Shift register unit, gate driving circuit and display device
KR102135432B1 (ko) 표시 장치
US20190333597A1 (en) Shift register, driving method thereof, gate driving circuit, and display device
US10043474B2 (en) Gate driving circuit on array substrate and liquid crystal display (LCD) using the same
WO2016188367A1 (zh) 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
WO2018161611A1 (zh) 移位寄存器电路及其驱动方法、栅极驱动电路、显示装置
CN107358902B (zh) 显示面板驱动器、显示装置及驱动显示面板的方法
WO2017181700A1 (zh) 移位寄存器单元、栅极驱动装置、显示装置和驱动方法
US10043585B2 (en) Shift register unit, gate drive device, display device, and control method
KR20130083151A (ko) 게이트 구동 회로 및 이를 구비한 표시 장치
KR20150019098A (ko) 게이트 구동 회로 및 이를 구비한 표시 장치
US9799293B2 (en) Liquid crystal display device and gate driving circuit
US10204579B2 (en) GOA circuits, display devices and the driving methods of the GOA circuits
TW201525963A (zh) 顯示裝置及其閘極移位暫存器的初始化方法
WO2018196084A1 (zh) 扫描驱动电路、阵列基板与显示面板
EP3564941B1 (en) Goa circuit
KR20170102134A (ko) 게이트 구동 회로 및 이를 포함하는 표시 장치
KR101980754B1 (ko) 게이트 쉬프트 레지스터 및 이를 이용한 평판 표시 장치
TWI460702B (zh) 顯示裝置及其移位暫存電路

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14906744

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15888321

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15888321

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 15888321

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205 DATED 12/04/2018)

122 Ep: pct application non-entry in european phase

Ref document number: 15888321

Country of ref document: EP

Kind code of ref document: A1