WO2017054381A1 - 阵列基板、制造方法以及相应的显示面板和电子装置 - Google Patents

阵列基板、制造方法以及相应的显示面板和电子装置 Download PDF

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Publication number
WO2017054381A1
WO2017054381A1 PCT/CN2016/072168 CN2016072168W WO2017054381A1 WO 2017054381 A1 WO2017054381 A1 WO 2017054381A1 CN 2016072168 W CN2016072168 W CN 2016072168W WO 2017054381 A1 WO2017054381 A1 WO 2017054381A1
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Prior art keywords
array substrate
pad layer
data line
gate line
layer
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PCT/CN2016/072168
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English (en)
French (fr)
Inventor
郝金刚
吴东琨
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/308,643 priority Critical patent/US10598995B2/en
Priority to KR1020177000764A priority patent/KR102011315B1/ko
Priority to JP2016569897A priority patent/JP6762236B2/ja
Priority to EP16787703.4A priority patent/EP3358401B1/en
Publication of WO2017054381A1 publication Critical patent/WO2017054381A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the array substrate, and corresponding display panels and electronic devices.
  • the structure of the array substrate includes a base substrate and gate lines, insulating layers, and data lines disposed on the base substrate.
  • the gate line provides a scan signal from the gate drive circuit and the data line provides a data signal from the data drive.
  • ESD Electrostatic Discharge
  • At least one embodiment of the present invention provides an array substrate, a method of fabricating an array substrate, and a display panel and an electronic device having the array substrate to reduce the probability of a short circuit between the gate line and the data line due to electrostatic discharge.
  • At least one embodiment of the present invention provides an array substrate including: a substrate substrate and a gate line, an insulating layer, a data line, and a first active pad layer disposed on the substrate substrate, wherein the insulating layer Provided on the gate line, the data line is disposed on the gate line and intersecting with the gate line via the insulating layer, and the first active pad layer is disposed on the insulating layer The gate line and the gate line overlap, and the first active pad layer is disposed between the gate line and the data line Outside the stacked area.
  • the first active pad layer may have an irregular shape.
  • the first active pad layer can have a tip structure.
  • an edge of a portion of the gate line overlapping the first active pad layer may be formed with a tip structure.
  • the array substrate may further include a data line pad layer, wherein the data line pad layer is disposed on the first active pad layer and overlaps the first active pad layer.
  • the data line pad can be electrically insulated from the data line.
  • the data line mat may have a serrated edge.
  • the array substrate may further include a second active pad layer, wherein the second active pad layer is disposed over the insulating layer and located in an area where the gate line and the data line overlap .
  • the array substrate may further include at least one of the first active pad layers.
  • At least one embodiment of the present invention provides a method of fabricating an array substrate including a substrate substrate and a gate line, an insulating layer, a data line, and an active pad layer disposed on the substrate substrate,
  • the manufacturing method includes: disposing the insulating layer on the gate line, disposing the data line on the gate line via the insulating layer, and crossing the gate line, and the active pad A layer is disposed on the gate line across the gate line and overlaps the gate line, and the active pad layer is disposed outside a region where the gate line and the data line overlap each other.
  • At least one embodiment of the present invention provides a display panel having the above array substrate.
  • At least one embodiment of the present invention provides an electronic device having the above array substrate.
  • 1a is a top plan view of a sub-pixel unit of an array substrate
  • Figure 1b is a cross-sectional view taken along line AA of Figure 1a;
  • 1c is a top plan view showing a thin film of a source/drain metal layer formed on an active pad
  • Figure 1d is a schematic cross-sectional view taken along line BB of Figure 1c;
  • FIG. 2a is a schematic top plan view of an array substrate according to an embodiment of the present invention.
  • FIG. 2b is a cross-sectional view of the array substrate of FIG. 2a taken along line C1-C2;
  • FIG. 2c is a cross-sectional view of the array substrate of FIG. 2a taken along line C3-C4;
  • FIG. 3 is a top plan view of an array substrate according to an embodiment of the invention.
  • Figure 3b is a cross-sectional view taken along line DD of Figure 3a;
  • 3c is a schematic top plan view of an array substrate not including a second active pad layer according to an embodiment of the present invention.
  • 3d is a partially enlarged schematic view showing a first active pad layer and a gate line in an array substrate according to an embodiment of the present invention
  • 4a and 4b are top plan views showing the zigzag edges of the array lines in the array substrate provided by the embodiment of the present invention.
  • 5a is a top plan view of an array substrate including a data line pad provided by an embodiment of the present invention.
  • Figure 5b is a cross-sectional view taken along line EE of Figure 5a according to an embodiment of the present invention.
  • FIG. 6 is a top plan view of an array substrate having a plurality of first active pad layers according to an embodiment of the present invention
  • FIG. 7a to 7e are schematic views of steps of fabricating an array substrate by using the fabrication method provided by the embodiment of the present invention.
  • FIG. 8 is a cross-sectional view of a display panel according to an embodiment of the invention.
  • each sub-pixel unit includes a thin film transistor 110 as a switching element and a pixel electrode 109 for controlling the arrangement of liquid crystals.
  • each sub-pixel unit may further include a common electrode that cooperates with a pixel electrode to form an electric field that drives liquid crystal molecules, as needed.
  • the gate 112 of the thin film transistor 110 is electrically connected to the corresponding gate line 102 (for example, the two are integrally formed), and the source 118 is electrically connected to the corresponding data line 108 (for example, the two are integrally formed).
  • the drain electrode 119 is electrically connected to the corresponding pixel electrode 109 (for example, the two are integrally formed).
  • Figure 1b is a cross-sectional view taken along line AA of Figure 1a.
  • the thin film transistor 110 in the array substrate includes a gate electrode 112, a gate insulating layer 114 disposed on the gate electrode 112, an active layer 116 disposed on the gate insulating layer 114, and an active layer disposed on the active layer
  • the source 118 and the drain 119 are electrically connected to 116, respectively; the pixel electrode 109 can be electrically connected to the drain 119 through the via 1091 in the passivation layer 107, for example.
  • the array substrate shown in FIG. 1b may include, for example, steps S01 to S04 as described below.
  • Step S01 forming a gate metal layer film on the base substrate 101, and preparing a gate metal layer including the gate electrode 112 and the gate line 102 by one patterning process.
  • Step S02 forming a gate insulating layer 114 on the gate metal layer.
  • Step S03 An active layer film is formed on the gate insulating layer 114, and the active layer 116 is formed by one patterning process.
  • Step S04 forming a source/drain metal layer film on the active layer 116, and forming a source/drain metal layer including the source electrode 118, the drain electrode 119, and the data line 108 by one patterning process.
  • Step S05 forming a passivation layer 107 and a via hole 1091 in the passivation layer 107 on the source/drain metal layer by one patterning process.
  • Step S06 The pixel electrode 109 is formed on the passivation layer 107 by one patterning process, and the pixel electrode 109 is electrically connected to the drain electrode 119 through the via hole 1091 in the passivation layer 107.
  • the traces of the display panel mainly include the gate lines 102 in the gate metal layer and the data lines 108 in the source/drain metal layers.
  • the two layers of traces transmit different signals, so that no short circuit can occur between the two.
  • step S03 affected by the legacy technology of the four-time patterning process (in the four-time patterning process, the above-mentioned step S03 and step S04 are merged into the same patterning process), in step S03, as shown in FIG. 1b, in step S03, a step is formed.
  • an active pad layer 126 (retained portion of the active layer film) is formed under the data line 108, and the active pad layer 126 includes a portion disposed where the gate line and the data line cross each other .
  • a source/drain metal layer film 108' is formed over the active pad layer 126, and an electrostatic charge may be accumulated during the preparation process, since the static electricity may be along the source and drain metal on the entire substrate substrate 101.
  • the layer film 108' is free to move, and if the active pad layer 126 has a tip at a contact portion of the edge thereof with the insulating layer 114, electric charges are easily collected at the tip, which easily causes the position where the gate line 102 and the data line 108 intersect. An electrostatic discharge phenomenon occurs, so that the gate line 102 and the data line 108 may be turned on, causing a short circuit.
  • the probability of occurrence of electrostatic discharge between the gate line and the data line can be reduced to reduce The probability that the gate line and the data line are short-circuited due to ESD.
  • FIG. 2a through 3d illustrate an array substrate 200 provided by at least one embodiment of the present invention.
  • 2a is a schematic top view of the array substrate according to the embodiment of the present invention
  • FIG. 2b is a cross-sectional view of the array substrate of FIG. 2a along the line C1-C2
  • FIG. 2c is the array substrate 200 of FIG. 2a along the C3- A schematic cross-sectional view of the C4 line.
  • the array substrate 200 includes a base substrate 201, a gate line 202 disposed on the base substrate 201, an insulating layer 204 disposed on the gate line 202, and a gate line 202 disposed via an insulating layer 204.
  • the first active pad layer 216 is disposed on the gate line 202 via the insulating layer 204 and overlaps the gate line 202, and the first The source pad layer 216 is disposed outside a region where the gate line 202 and the data line 208 overlap each other.
  • the overlapping of the first active pad layer 216 and the gate line 202 means that the two structures have overlapping portions on the orthographic projection of the surface on which the substrate substrate is located.
  • the array substrate 200 can include a second active pad layer 226 in addition to the first active pad layer 216.
  • the second active pad layer 226 is disposed between the insulating layer 204 and the data line 208 in a direction perpendicular to the plane of the substrate substrate and is located in a region where the gate line 202 and the data line 208 overlap.
  • the array substrate provided by the embodiment of the present invention may include two active pad layers, which are respectively the first active pad layer 216 disposed in the embodiment of the present invention and due to, for example, four patterning processes.
  • a second active pad layer 226 is retained by the legacy technology.
  • the source is formed by the patterning process.
  • the probability of static buildup on the two active pads Prior to the poles, drains, and data lines, the probability of static buildup on the two active pads is the same.
  • the first active pad layer 216 shares the probability of ESD appearing on the second active pad layer 226. That is, by providing the first active pad layer 216, the probability of ESD appearing on the second active pad layer 226 between the gate line 202 and the data line 208 is lowered, so that the gate line 202 and the data line 208 can be lowered. The probability of a short circuit due to ESD.
  • the array substrate 200 may also include only the first active pad layer 216, and does not include the second active pad layer 226.
  • a source/drain metal layer film electrically connected thereto is formed on the first active pad layer 216 and before the source, drain, and data lines are formed by a patterning process, the first active pad layer 216 may be
  • the array substrate provides an electrostatic discharge channel to reduce static buildup on the array substrate.
  • the array substrate 200 may further include a thin film transistor 210 including an active layer 206, a drain 219, and a source 218. Also, for example, in a direction perpendicular to the plane in which the base substrate 201 is located, there is no insulating layer between the active layer 206 and the drain electrode 219, that is, the active layer 206 and the drain electrode 219 are not electrically passed through via holes or other conductive members. connection. In this way, since the source/drain metal layer film is in direct contact with the first active pad layer before the source, the drain and the data line are formed, static electricity can be relatively easily accumulated on the first active pad layer to reduce the gate line. The probability of ESD occurring between the data line and the data line.
  • Embodiments of the invention include, but are not limited to, such.
  • a via is provided at a position corresponding to the first active pad layer of the layer to expose the first active pad layer
  • the surface may be such that it is electrically connected to the first active pad layer when the source/drain metal layer film is formed.
  • the planar shape of the first active pad layer 216 may be any shape, such as a circle, an ellipse, or a polygon (eg, a triangle, a quadrangle) or the like.
  • the planar shape of the first active pad layer 216 may have an irregular shape.
  • the first active layer pad layer 216 can have a serrated edge. Under the action of a strong electric field, the electric field strength of the surface of the object having a large curvature (such as the tip of a sharp, fine object) is sharply increased, and it is easier to discharge. Therefore, setting the planar shape of the first active pad layer 216 to an irregular shape can further The probability of ESD appearing on the first active pad layer 216 is increased, ie, the probability of ESD occurring at the second active pad layer 226 is further reduced.
  • the first active pad layer 216 can have a tip structure 216a. Since electrostatic discharge typically occurs at the tip, by having the first active pad layer 216 have the tip structure 216a, static electricity can be attracted to the first active pad layer 216, thereby increasing ESD at the first active pad layer 216. The probability.
  • the tip structure 216a can extend in a direction in which the first active pad layer 216 is located.
  • the orthographic projection of the tip end of the tip structure 216a on the face of the gate line 202 can be outside of the gate line 202.
  • the tip d of the tip structure 216a (the end away from the middle of the first active pad layer 216) to the edge 2021 of the gate line 202 (the edge 2021 is located on the side where the tip structure 216a is located) may have a distance d of less than or equal to 3 ⁇ m.
  • the angle of the tip end of the tip structure 216a can be set to less than 90 degrees, which also facilitates further directing electrostatic discharge to the gate line via the tip structure.
  • At least one edge of the portion of the gate line 202 that overlaps the first active pad layer 216 (shown by the dashed box in Figure 4b) (in the figure The edge is described as an example. It may also be formed to have a tip structure 202a. That is, at least one edge of the gate line 202 (eg, two opposing edges 2021 and 2022) has a tip structure 202a at a location where the gate line 202 overlaps the first active pad layer 216.
  • the tip structure 202a can be disposed with reference to the tip structure 216a of the first active pad layer described above, and the repeated portions are not described again.
  • ESD can be further reduced in the gate. Probability on the second active pad 226 between the line and the data line.
  • the array substrate 200 may further include a data line pad 408 disposed on the first active pad layer 216 and The first active pad layers 216 overlap.
  • a data line pad 408 disposed on the first active pad layer 216 and The first active pad layers 216 overlap.
  • the embodiments of the present invention include, but are not limited to, the following.
  • the data line pad layer 408 is disposed in the same layer as the data line 208, that is, formed using a source/drain metal layer film. Since the data line pad 408 is made of a metal material, a metal material such as Cu, Mo, Al, Cu alloy, Mo alloy, and Al alloy.
  • the data line pad 408 is electrically insulated from the data line 208. In this way, even if a short circuit phenomenon occurs between the gate line 202 and the data line pad layer 408 via the first active pad layer 216, normal operation of the sub-pixel unit is not affected. Therefore, this can further increase the probability that ESD will appear at the first active pad layer 216. That is to say, the probability that ESD appears on the second active pad layer 226 between the gate line 202 and the data line 208 can be further reduced. Still further, the data line pad 408 is not electrically connected to any portion of the pixel unit, for example, horizontally.
  • the array substrate provided by the embodiment of the present invention can simultaneously form an active layer, a source, a drain, and a data line by using a patterning process (for example, the array substrate is prepared by a four-time patterning process).
  • the data line The underlayer and the first active underlayer are formed by the same patterning process such that the orthographic projections of the two on the surface of the substrate substrate substantially coincide, ie, the edges of the two are substantially aligned.
  • the embodiments of the present invention can also be used to form an active layer and an array substrate of a source/drain metal layer including a source, a drain, and a data line, respectively, by different patterning processes.
  • the data line pad layer and the first active pad layer are formed by different patterning processes, so that both are on the surface of the substrate substrate.
  • the orthographic projections on the top may also not coincide, for example, one projection falls into the projection of the other, or the two partially overlap.
  • planar shape of the data line mat 408 can be any shape, such as, for example, a circle, an ellipse, or a polygon (eg, a triangle, a quadrangle) or the like.
  • the data line pad 408 can be configured to have a serrated edge that facilitates further directing electrostatic discharge through the tip structure to the data line pad 408.
  • the array substrate can include at least another first active pad layer.
  • the probability of ESD appearing on the second active pad layer between the gate lines and the data lines can be further reduced.
  • the array substrate 200 includes two first active pad layers 216.
  • ESD may occur on both of the first active pads, so that the probability of ESD appearing on the second active pad between the gate lines and the data lines can be further reduced.
  • the number of first active pad layers in the embodiments of the present invention is not limited to two shown in FIGS. 5a and 5b, but may include a plurality of first active pad layers.
  • the above array substrate can reduce the probability that ESD appears on the second active pad between the gate line and the data line, thereby reducing the probability of short circuit between the gate line and the data line due to ESD.
  • the data line and the second active pad layer may be formed by the same patterning process.
  • the array substrate may adopt a four-time patterning process.
  • the orthographic projections of the data lines and the second active pad layer on the face of the substrate substrate substantially coincide, that is, the edges of the two are substantially aligned.
  • the embodiments of the present invention can also be used to form an active layer and an array substrate of a source/drain metal layer including a source, a drain, and a data line respectively by different patterning processes (for example, using five or more patterning processes).
  • Array substrate the active layer and the source/drain of the thin film transistor are formed by different patterning processes, and accordingly, the data line and the second active pad layer located thereunder are also formed by different patterning processes, thereby The orthographic projections of the two on the surface on which the substrate substrate is located may not coincide.
  • the array substrate provided by the embodiment of the present invention may further include a pixel electrode 209, and the array base
  • the thin film transistor in the board also includes a source 218 as shown in FIG.
  • Embodiments of the present invention also provide a method of fabricating an array substrate including a substrate substrate and a gate line, an insulating layer, a data line, and a first active pad layer disposed on the substrate substrate, the manufacturing method
  • the method includes: disposing the insulating layer on the gate line, disposing the data line on the gate line via the insulating layer, and crossing the gate line, and setting the first active pad layer through the insulating layer And intersecting the gate line on the gate line, and the first active pad layer is disposed outside a region where the gate line and the data line overlap each other.
  • the method of fabricating may further include forming a data line pad disposed on the first active pad layer and overlapping the first active pad layer.
  • the data line pad can be formed to be electrically isolated from the data line.
  • the data line mat may be in the shape of a triangle, a quadrangle, or a polygon.
  • the data line mat may be formed to have a serrated edge.
  • the data line and the first active pad layer may be formed by different patterning processes, in which case the method may include steps S21 and S23 described below.
  • Step S21 as shown in FIG. 7a, a gate metal layer including the gate lines 202 is formed on the base substrate 201 by the first patterning process.
  • a gate metal layer film is formed on a base substrate 201 (for example, a glass substrate, a plastic substrate, or a quartz substrate) by a sputtering process; then, using a mask, formed by, for example, one exposure, development, and wet etching processes Grid line.
  • the gate metal layer may be an alloy of at least one or more of metals such as Cr, Mo, Al, and Cu.
  • a gate electrode 212 may also be formed in the gate metal layer.
  • Step S22 As shown in Fig. 7b, an active layer film 206' is formed on the gate line 202; thereafter, as shown in Fig. 7c, the active layer 206 and the first active pad layer 216 are formed by a second patterning process.
  • Step S23 forming a source/drain metal layer film 208' on the active layer 206 and the first active pad layer 216 as shown in FIG. 7d; thereafter, as shown in FIG. 7e, forming a source through a third patterning process 218, drain 219 and data lines (not shown).
  • a data line pad 408 may also be formed.
  • the pattern of the first active pad layer may be formed to have an irregular shape.
  • a portion of the gray tone translucent reticle corresponding to the first active pad layer may have an irregular shape such that the first active pad layer may be formed to have an irregular shape.
  • the first active pad layer can be formed to have a pointed structure.
  • the angle of the tip structure can be formed to be less than 90 degrees.
  • the distance from the tip end of the tip structure to the edge of the corresponding gate line which is on the side where the tip structure is located may be formed to be less than or equal to 3 ⁇ m.
  • an edge of a portion of the gate line overlapping the first active pad layer may be formed to have a tip structure. That is, a portion of the edge of the gate line may have a tip structure.
  • the method of manufacturing may further include forming at least one other first active pad layer, ie, forming a plurality of first active pad layers.
  • the manufacturing method provided by at least one embodiment of the present invention further includes forming an insulating layer that insulates the gate lines from the data lines from each other, the insulating layer being formed, for example, by the same patterning process as the gate lines, or with the data lines and the first
  • the active pad layer is formed by the same patterning process, or may be formed after the first patterning process of forming the gate line and before the second patterning process.
  • the insulating layer is usually a gate insulating layer. The embodiments of the present invention are not limited.
  • the probability that ESD appears between the gate line and the data line during the preparation process is lowered, thereby reducing the probability of short circuit between the gate line and the data line due to ESD.
  • the manufacturing method provided by the embodiment of the present invention may further include a patterning process of forming a pixel electrode.
  • a process of forming a passivation layer and a patterning process for the passivation layer may be included after the patterning process of forming the data lines and before the patterning process of forming the pixel electrodes.
  • At least one embodiment of the present invention provides a display panel including the above array substrate.
  • the display panel provided by the embodiment of the invention can reduce the short circuit between the gate line and the data line caused by ESD, thereby reducing the probability of generating split screen and full screen horizontal stripes, and improving the display surface.
  • the yield of the board is the above array substrate.
  • the display panel of the embodiment of the present invention may include an array substrate 200 and a counter substrate 300.
  • the array substrate 200 and the opposite substrate 300 are opposed to each other and pass through the sealant 350 to form a liquid crystal cell.
  • the cell is filled with a liquid crystal material 400.
  • the counter substrate 300 is, for example, a color filter substrate.
  • the pixel electrode of each pixel unit of the array substrate 200 is used to apply an electric field to control the degree of rotation of the liquid crystal material to perform a display operation.
  • the electronic device may include any product or component having a display function such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, a watch, and the like.
  • a display function such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, a watch, and the like.

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Abstract

一种阵列基板（200）、阵列基板（200）的制造方法以及具有阵列基板（200）的显示面板和电子装置。阵列基板（200）包括衬底基板（201）和在衬底基板（201）上设置的栅线（202）、绝缘层（204）、数据线（208）以及第一有源垫层（216），绝缘层（204）设置在栅线（202）上，数据线（208）隔着绝缘层（204）设置在栅线（202）上且和栅线（202）交叉设置，第一有源垫层（216）隔着绝缘层（204）设置在栅线（202）上且和栅线（202）相交叠，且第一有源垫层（216）设置在栅线（202）与数据线（208）彼此交叠的区域之外。

Description

阵列基板、制造方法以及相应的显示面板和电子装置 技术领域
本发明的实施例涉及阵列基板、该阵列基板的制造方法以及相应的显示面板和电子装置。
背景技术
阵列基板的结构包括衬底基板和在该衬底基板上设置的栅线、绝缘层、数据线。栅线提供来自栅极驱动电路的扫描信号，而数据线提供来自数据驱动的数据信号。在制作阵列基板的过程中，在衬底基板与阵列设备摩擦或在真空墙体作业时，电荷在衬底基板表面聚集，从而形成静电。当电荷积累到一定程度就会形成放电，即，静电放电(Electro Static Discharge，简称为ESD)。ESD会破坏在衬底基板上已经形成的膜层，造成不同膜层之间的短路，形成缺陷。ESD造成的短路会导致所制备的显示面板产生分屏和全屏横纹，这也是阵列基板制程中的常规缺陷之一。
发明内容
本发明的至少一实施例提供一种阵列基板、阵列基板的制造方法以及具有该阵列基板的显示面板和电子装置，以降低栅线和数据线之间因静电放电而发生短路的几率。
本发明的至少一实施例提供一种阵列基板，包括：衬底基板和在所述衬底基板上设置的栅线、绝缘层、数据线以及第一有源垫层，其中，所述绝缘层设置在所述栅线上，所述数据线隔着所述绝缘层设置在所述栅线上且和所述栅线交叉设置，所述第一有源垫层隔着所述绝缘层设置在所述栅线上且和所述栅线相交叠，且所述第一有源垫层设置在所述栅线与所述数据线彼此交 叠的区域之外。
例如，所述第一有源垫层可以具有非规则形状。
例如，所述第一有源垫层可以具有尖端结构。
例如，所述栅线与所述第一有源垫层相交叠的部分的边缘可以形成有尖端结构。
例如，所述阵列基板还可以包括数据线垫层，其中，所述数据线垫层设置在所述第一有源垫层上且与所述第一有源垫层相交叠。
例如，所述数据线垫层可以与所述数据线电绝缘。
例如，所述数据线垫层可以具有锯齿状边缘。
例如，所述阵列基板还可以包括第二有源垫层，其中，所述第二有源垫层设置在所述绝缘层之上且位于所述栅线和所述数据线相交叠的区域内。
例如，所述阵列基板还可以包括至少一个所述第一有源垫层。
本发明的至少一实施例提供一种阵列基板的制造方法，所述阵列基板包括衬底基板和在所述衬底基板上设置的栅线、绝缘层、数据线以及有源垫层，所述制造方法包括：将所述绝缘层设置在所述栅线上，将所述数据线隔着所述绝缘层设置在所述栅线上且和所述栅线交叉设置，将所述有源垫层隔着所述绝缘层设置在所述栅线上且和所述栅线相交叠，且将所述有源垫层设置在所述栅线与所述数据线彼此交叠的区域之外。
本发明的至少一实施例提供一种具有上述阵列基板的显示面板。
本发明的至少一实施例提供一种具有上述阵列基板的电子装置。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1a是一种阵列基板的子像素单元的俯视示意图；
图1b是沿图1a中AA线的剖视示意图；
图1c是一种在有源垫层上形成源漏金属层薄膜的俯视示意图；
图1d是沿图1c中BB线的剖视示意图；
图2a是本发明实施例提供的阵列基板的俯视示意图；
图2b是图2a的阵列基板沿着C1-C2线的剖视示意图；
图2c是图2a的阵列基板沿着C3-C4线的剖视示意图；
图3a是本发明实施例提供的阵列基板的俯视示意图；
图3b是沿图3a中DD线的剖视示意图；
图3c是本发明实施例提供的不包括第二有源垫层的阵列基板的俯视示意图；
图3d是本发明实施例提供的阵列基板中第一有源垫层和栅线的局部放大示意图；
图4a和图4b分别是本发明实施例提供的阵列基板中栅线设置有锯齿状边缘的俯视示意图；
图5a是本发明实施例提供的包括数据线垫层的阵列基板的俯视示意图；
图5b是本发明实施例提供的沿图5a中EE线的剖视示意图；
图6是本发明实施例提供的具有多个第一有源垫层的阵列基板的俯视示意图；
图7a至图7e是采用本发明实施例提供的制作方法制作阵列基板的各步骤的示意图；
图8是本发明实施例提供的显示面板的剖视示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
以用于液晶显示面板的阵列基板为例，如图1a所示，阵列基板通常包括多条栅线102和多条数据线108，这些栅线102和数据线108彼此交叉由此限定了排列为矩阵的子像素单元(图1a中仅具体示出了一个子像素单元)，每个子像素单元包括作为开关元件的薄膜晶体管110和用于控制液晶的排列的像素电极109。例如，根据需要，在IPS或ADS型的液晶显示面板的阵列基板中，每个子像素单元还可以包括和像素电极配合以形成驱动液晶分子的电场的公共电极。例如，每个子像素单元中，薄膜晶体管110的栅极112与相应的栅线102电连接(例如，二者一体形成)，源极118与相应的数据线108电连接(例如，二者一体形成)，漏极119与相应的像素电极109电连接(例如，二者一体形成)。
图1b为沿图1a中AA线的剖视示意图。如图1b所示，例如，阵列基板中的薄膜晶体管110包括栅极112、设置于栅极112上的栅绝缘层114、设置于栅绝缘层114上的有源层116以及设置于有源层116上且分别与其电连接的源极118和漏极119；像素电极109例如可以通过钝化层107中的过孔1091与漏极119电连接。
图1b所示的阵列基板例如可以包括如下所述的步骤S01至步骤S04。
步骤S01：在衬底基板101上形成栅金属层薄膜，并通过一次构图工艺制备包括栅极112和栅线102的栅金属层。
步骤S02：在栅金属层上形成栅绝缘层114。
步骤S03：在栅绝缘层114上形成有源层薄膜，通过一次构图工艺形成有源层116。
步骤S04：在有源层116上形成源漏金属层薄膜，并通过一次构图工艺形成包括源极118、漏极119和数据线108的源漏金属层。
步骤S05：通过一次构图工艺，在源漏金属层上形成钝化层107以及位于钝化层107中的过孔1091。
步骤S06：通过一次构图工艺，在钝化层107上形成像素电极109，像素电极109通过钝化层107中的过孔1091与漏极119电连接。
在研究中，本申请的发明人注意到如下问题。目前，显示面板的走线主要包括栅金属层中的栅线102和源漏金属层中的数据线108，这两层走线传递不同的信号，因此这二者之间不能发生短路。但是，受四次构图工艺(在四次构图工艺中，上述步骤S03和步骤S04合并为同一次构图工艺)遗留技术的影响，在步骤S03中，如图1b所示，在步骤S03中，形成有源层116的同时，在数据线108之下形成有有源垫层126(有源层薄膜的保留部分)，该有源垫层126包括设置在栅线和数据线彼此交叉之处的部分。如图1c和图1d所示，在有源垫层126之上形成源漏金属层薄膜108’，在制备过程可能积累静电荷，由于这些静电可在整个衬底基板101上沿着源漏金属层薄膜108’随意移动，如果该有源垫层126在其边缘与绝缘层114的接触部位处具有尖端，则电荷容易在该尖端处聚集，这容易导致栅线102和数据线108交叉的位置处发生静电放电现象，从而栅线102和数据线108可能被导通，造成短路。
本发明实施例通过设置与栅线有重叠部分且位于栅线与数据线交叠区域之外的第一有源垫层，可以降低在栅线与数据线之间出现静电放电的概率，以降低栅线与数据线由于ESD而发生短路的概率。
图2a至图3d图示了本发明的至少一个实施例提供的阵列基板200。其中，图2a是本发明实施例提供的阵列基板的俯视示意图，图2b是图2a的阵列基板沿着C1-C2线的剖视示意图，而图2c是图2a的阵列基板200沿着C3-C4线的剖视示意图。如图3a所示，该阵列基板200包括衬底基板201和设置在衬底基板201上的栅线202、设置在栅线202上的绝缘层204、隔着绝缘层204设置在栅线202上且与栅线202相交的数据线208、以及第一有源垫层216，第一有源垫层216隔着绝缘层204设置在栅线202上且和栅线202相交叠，且第一有源垫层216设置在栅线202与数据线208彼此交叠的区域之外。
本公开中，如图3b所示，第一有源垫层216和和栅线202相交叠指这两个结构在衬底基板所在面上的正投影有重叠部分。
例如，在一个实施例中，除了第一有源垫层216之外，该阵列基板200还可以包括第二有源垫层226。沿垂直于衬底基板所在面的方向上，第二有源垫层226设置于绝缘层204和数据线208之间且位于栅线202和数据线208相交叠的区域内。与图1c所示的情形相比，本发明实施例提供的阵列基板可以包括两种有源垫层，分别是本发明实施例中设置的第一有源垫层216和由于例如四次构图工艺遗留技术而保留的第二有源垫层226。在制备源极、漏极和数据线的过程中，由于之前工艺积累的静电可以沿着用于形成源极、漏极和数据线的源漏金属层薄膜而随意迁移，所以在通过构图工艺形成源极、漏极和数据线之前，静电聚集在该两种有源垫层上的概率是相同的。因此，第一有源垫层216分担了在第二有源垫层226上出现ESD的概率。即，通过设置第一有源垫层216，使得ESD出现在栅线202与数据线208之间的第二有源垫层226上的概率降低，从而可以降低在栅线202与数据线208之间由于发生ESD而短路的概率。
例如，如图3c所示，阵列基板200也可以仅包括第一有源垫层216，不包括第二有源垫层226。在这种情况下，在第一有源垫层216上形成与其电连接的源漏金属层薄膜且在通过构图工艺形成源极、漏极和数据线之前，第一有源垫层216可以为阵列基板提供静电释放渠道，以减少阵列基板上的静电积累。
示例性地，阵列基板200还可以包括薄膜晶体管210，其包括有源层206、漏极219和源极218。并且，例如，沿垂直于衬底基板201所在面的方向上，有源层206与漏极219之间无绝缘层，即，有源层206与漏极219不是通过过孔或其他导电部件电连接。这样，由于在形成源极、漏极和数据线之前，源漏金属层薄膜与第一有源垫层直接接触，从而静电可以比较容易地聚集在第一有源垫层上，以降低栅线和数据线之间发生ESD的概率。本发明实施例包括、但不限于此。例如，如果在形成有源层和第一有源垫层之后且在形成源漏金属层薄膜之前，在有源层和第一有源垫层上形成有另一绝缘层，则只要在该绝缘层的对应第一有源垫层的位置处设置过孔以暴露出第一有源垫层 的表面(以便在形成源漏金属层薄膜时使其与第一有源垫层电连接)即可。
示例性地，第一有源垫层216的平面形状(即，在其所在面上的形状)可以为任意形状，例如圆形、椭圆形或者多边形(例如，三角形、四边形)等。
示例性地，第一有源垫层216的平面形状可以具有非规则形状。例如，第一有源层垫层216可以具有锯齿状边缘。在强电场作用下，物体表面曲率大的地方(如尖锐、细小物的顶端)电场强度剧增，而更容易放电，因此将第一有源垫层216的平面形状设置为非规则形状可以进一步增加ESD出现在第一有源垫层216上的概率，即，进一步降低第二有源垫层226处出现ESD的几率。
示例性地，如图3d所示，第一有源垫层216可以具有尖端结构216a。由于静电放电通常出现在尖端，所以通过使得第一有源垫层216具有尖端结构216a，可以吸引静电聚集在第一有源垫层216上，从而增加在第一有源垫层216处出现ESD的概率。
示例性地，尖端结构216a可以沿第一有源垫层216所在面的方向延伸。例如，尖端结构216a的顶端在栅线202所在面上的正投影可以位于栅线202之外。例如，尖端结构216a的顶端(远离第一有源垫层216中部的一端)到栅线202的边缘2021(该边缘2021位于尖端结构216a所在侧)的距离d可以小于或等于3μm，以此方式，有利于进一步引导静电经由该尖端结构向该栅线放电。例如，该尖端结构216a的顶端的角度可以设置为小于90度，这样也有利于进一步引导静电经由该尖端结构向该栅线放电。
示例性地，如图4a和图4b所示，栅线202的与第一有源垫层216相交叠的部分(如图4b中的虚线框所示)的至少一个边缘(图中以两个边缘为例进行说明)也可以形成为具有尖端结构202a。也就是说，栅线202的至少一个边缘(例如两个相对的边缘2021和2022)在栅线202与第一有源垫层216相交叠的位置处具有尖端结构202a。该尖端结构202a可以参考上述第一有源垫层的尖端结构216a进行设置，重复之处不再赘述。
在上述示例中，通过将第一有源垫层216和栅线202的与第一有源垫层216相交叠的部分的边缘中的至少一个设置为具有尖端结构，可以进一步降低ESD出现在栅线与数据线之间的第二有源垫层226上的概率。
示例性地，在另一个实施例中，参见图5a和图5b，该阵列基板200还可以进一步包括数据线垫层408，该数据线垫层408设置在第一有源垫层216上且与该第一有源垫层216相交叠。这样便于在后续步骤中提供静电释放渠道。例如，在形成源极、漏极和数据线之后，在源极、漏极和数据线之上形成像素电极薄膜以形成像素电极，在形成像素电极薄膜之后且在形成像素电极之前，如果使像素电极薄膜与数据线垫层电连接，则数据线垫层可以吸引像素电极薄膜上的静电，以进一步降低栅线和数据线之间发生ESD的概率。当然，本发明实施例包括、但不限于此。
数据线垫层408与数据线208同层设置，即利用源漏金属层薄膜形成。由于数据线垫层408采用金属材料制作，诸如Cu、Mo、Al、Cu合金、Mo合金和Al合金之类的金属材料。
示例性地，该数据线垫层408与数据线208电绝缘。以此方式，即使短路现象经由该第一有源垫层216发生在栅线202与数据线垫层408之间，也不会影响子像素单元的正常工作。因此，这可以进一步增加ESD在第一有源垫层216处出现的概率。也就说，可以进一步降低ESD出现在栅线202与数据线208之间的第二有源垫层226上的概率。更进一步，数据线垫层408例如在水平上不与像素单元的任何部分电连接。
本发明实施例提供的阵列基板例如可以采用一次构图工艺同步形成有源层、源极、漏极和数据线(例如，该阵列基板采用四次构图工艺制备)，在这种情况下，数据线垫层和第一有源垫层通过同一次构图工艺形成，因此二者在衬底基板所在面上的正投影大致重合，即，二者的边缘大致对齐。
当然，本发明实施例也可以用于通过不同构图工艺分别形成有源层和包括源极、漏极和数据线的源漏金属层的阵列基板。在这种情况下，数据线垫层和第一有源垫层通过不同的构图工艺形成，从而，二者在衬底基板所在面 上的正投影也可以不重合，例如一个的投影落入另一个的投影之中，或者二者部分重叠。
例如，数据线垫层408的平面形状可以为任意形状，例如，例如圆形、椭圆形或者多边形(例如，三角形、四边形)等。
例如，数据线垫层408可以设置为具有锯齿状边缘，这样有利于进一步引导静电经由该尖端结构向数据线垫层408放电。
示例性地，在另一个实施例中，第一有源垫层216之外，该阵列基板可以包括至少另一个第一有源垫层。通过设置另外的第一有源垫层，即设置多个第一有源垫层，可以进一步降低ESD出现在栅线与数据线之间的第二有源垫层上的概率。例如，如图6所示，阵列基板200包括两个第一有源垫层216。在此情况下，这两个第一有源垫层上都可能发生ESD，从而可以进一步降低ESD出现在栅线与数据线之间的第二有源垫层上的概率。本领域技术人员应当理解，本发明实施例中的第一有源垫层的数量不限于图5a和图5b中所示的两个，而是可以包括多个第一有源垫层。
上述阵列基板可以降低ESD出现在栅线与数据线之间的第二有源垫层上的概率，从而降低在栅线与数据线之间由于ESD而短路的概率。
本发明实施例提供的阵列基板中，数据线和第二有源垫层可以通过同一次构图工艺形成，例如，该阵列基板可以采用四次构图工艺。在这种情况下，数据线和第二有源垫层在衬底基板所在面上的正投影大致重合，即，二者的边缘大致对齐。
当然，本发明实施例也可以用于通过不同构图工艺分别形成有源层和包括源极、漏极和数据线的源漏金属层的阵列基板(例如，采用五次或更多次构图工艺制作的阵列基板)。在这种情况下，薄膜晶体管的有源层和源/漏极通过不同的构图工艺形成，相应地，数据线和位于其下方的第二有源垫层也通过不同的构图工艺形成，从而，二者在衬底基板所在面上的正投影也可以不重合。
当然，本发明实施例提供的阵列基板还可以包括像素电极209，阵列基 板中的薄膜晶体管还包括源极218，如图2所示。
本发明的实施例还提供一种阵列基板的制造方法，该阵列基板包括衬底基板和在该衬底基板上设置的栅线、绝缘层、数据线以及第一有源垫层，该制造方法包括：将该绝缘层设置在该栅线上，将该数据线隔着该绝缘层设置在该栅线上且和该栅线交叉设置，将该第一有源垫层隔着该绝缘层设置在该栅线上且和该栅线相交叠，且将该第一有源垫层设置在该栅线与该数据线彼此交叠的区域之外。
示例性地，在另一个实施例中，制造方法可以进一步包括形成数据线垫层，该数据线垫层设置在该第一有源垫层上且与该第一有源垫层相交叠。例如，该数据线垫层可以形成为与该数据线电绝缘。例如，该数据线垫层的形状可以是三角形、四边形、或多边形。例如，该数据线垫层可以形成为具有锯齿状边缘。
示例性地，在该阵列基板的制造方法中，可以通过不同的构图工艺形成数据线和第一有源垫层，在这种情况下，该方法可以包括以下所述的步骤S21和步骤S23。
步骤S21，如图7a所示，通过第一次构图工艺，在衬底基板201上形成包括栅线202的栅金属层。
例如，在衬底基板201(例如，玻璃基板、塑料基板或石英基板)上通过溅射工艺形成栅金属层薄膜；然后，采用掩膜版，通过例如一次曝光、显影和湿法刻蚀工艺形成栅线。例如，栅金属层可采用Cr、Mo、Al和Cu等金属中的至少一种或几种的合金。
在该步骤中，栅金属层中还可以形成有栅极212。
步骤S22：如图7b所示，在栅线202上形成有源层薄膜206’；之后，如图7c所示，通过第二次构图工艺形成有源层206和第一有源垫层216。
步骤S23：如图7d所示，在有源层206和第一有源垫层216上形成源漏金属层薄膜208’；之后，如图7e所示，通过第三次构图工艺，形成源极218、漏极219以及数据线(图中未示出)。
例如，在该步骤中，还可以形成有数据线垫层408。
示例性地，第一有源垫层的图案可以形成为具有非规则形状。例如，灰色调半透明掩模版的对应第一有源垫层的部分可以具有非规则形状，从而使得第一有源垫层可以形成为具有非规则形状。
示例性地，该第一有源垫层可以形成为具有尖端结构。例如，该尖端结构的角度可以形成为小于90度。此外，例如，该尖端结构的顶端到对应的栅线的边缘(该边缘位于该尖端结构所在侧)的距离可以形成为小于或等于3μm。
此外，在形成栅线的第一次构图工艺中，该栅线与该第一有源垫层相交叠的部分的边缘可以形成为具有尖端结构。也就是说，栅线的边缘的一部分可以具有尖端结构。
示例性地，该制造方法还可以包括形成至少另一个第一有源垫层，即，形成多个第一有源垫层。
当然，本发明的至少一个实施例提供的制造方法还包括形成将栅线与数据线彼此绝缘的绝缘层，该绝缘层例如可以与栅线通过同一次构图工艺形成，或者与数据线和第一有源垫层通过同一次构图工艺形成，或者也可以在形成栅线的第一次构图工艺之后且在第二次构图工艺之前，形成该绝缘层。本发明实施例中，上述绝缘层通常为栅绝缘层。本发明实施例不做限定。
通过上述制造方法，使得制备过程中ESD出现在栅线与数据线之间的概率降低，从而降低在栅线与数据线之间由于ESD而短路的概率。
此外，对于用于液晶显示面板的阵列基板，例如，本发明实施例提供的制造方法还可以包括形成像素电极的构图工艺。例如，在形成数据线的构图工艺之后和形成像素电极的构图工艺之前，还可以包括形成钝化层的工艺以及针对该钝化层的构图工艺。
本发明的至少一个实施例提供一种包括上述阵列基板的显示面板。通过采用上述阵列基板，本发明实施例提供的显示面板可以减少ESD造成栅线和数据线之间的短路，从而可以降低产生分屏和全屏横纹的概率，提高显示面 板的良品率。
例如，如图8所示，本发明实施例的显示面板可以包括阵列基板200与对置基板300，阵列基板200与对置基板300彼此对置且通过封框胶350以形成液晶盒，在液晶盒中填充有液晶材料400。该对置基板300例如为彩膜基板。阵列基板200的每个像素单元的像素电极用于施加电场以对液晶材料的旋转程度进行控制从而进行显示操作。
本发明的至少一个实施例提供一种包括上述显示面板的电子装置。例如，该电子装置可以包括：液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、手表等任何具有显示功能的产品或部件。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请要求于2015年9月28日递交的中国专利申请第201510627008.5号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (20)

  1. 一种阵列基板，包括：衬底基板和在所述衬底基板上设置的栅线、绝缘层、数据线以及第一有源垫层，
    其中，所述绝缘层设置在所述栅线上，所述数据线隔着所述绝缘层设置在所述栅线上且和所述栅线交叉设置，所述第一有源垫层隔着所述绝缘层设置在所述栅线上且和所述栅线相交叠，且所述第一有源垫层设置在所述栅线与所述数据线彼此交叠的区域之外。
  2. 如权利要求1所述的阵列基板，其中，所述第一有源垫层具有非规则形状。
  3. 如权利要求1或2所述的阵列基板，其中，所述第一有源垫层具有尖端结构。
  4. 如权利要求1-3的任一项所述的阵列基板，其中，所述栅线与所述第一有源垫层相交叠的部分的边缘具有尖端结构。
  5. 如权利要求1-4的任一项所述的阵列基板，进一步包括数据线垫层，其中，所述数据线垫层设置在所述第一有源垫层上且与所述第一有源垫层相交叠。
  6. 如权利要求1-5的任一项所述的阵列基板，其中，所述数据线垫层与所述数据线电绝缘。
  7. 如权利要求1-6的任一项所述的阵列基板，其中，所述数据线垫层具有锯齿状边缘。
  8. 如权利要求1-7的任一项所述的阵列基板，还包括第二有源垫层，其中，所述第二有源垫层设置在所述绝缘层和所述数据线之间，且位于所述栅线和所述数据线相交叠的区域内。
  9. 如权利要求1-8的任一项所述的阵列基板，还包括至少另一个第一有源垫层。
  10. 一种阵列基板的制造方法，所述阵列基板包括衬底基板和在所述衬 底基板上设置的栅线、绝缘层、数据线以及第一有源垫层，所述制造方法包括：
    将所述栅线形成在所述衬底基板上，
    将所述绝缘层形成在所述栅线上，
    将所述数据线隔着所述绝缘层形成在所述栅线上且和所述栅线交叉设置，
    将所述第一有源垫层隔着所述绝缘层形成在所述栅线上且和所述栅线相交叠，且将所述第一有源垫层设置在所述栅线与所述数据线彼此交叠的区域之外。
  11. 如权利要求10所述的阵列基板的制造方法，其中，所述第一有源垫层形成为具有非规则形状。
  12. 如权利要求10-11的任一项所述的阵列基板的制造方法，其中，所述第一有源垫层形成为具有尖端结构。
  13. 如权利要求10-12的任一项所述的阵列基板的制造方法，其中，所述栅线与所述第一有源垫层相交叠的部分的边缘形成为具有尖端结构。
  14. 如权利要求10-13的任一项所述的阵列基板的制造方法，进一步包括形成数据线垫层，其中，所述数据线垫层设置在所述第一有源垫层上且与所述第一有源垫层相交叠。
  15. 如权利要求10-14的任一项所述的阵列基板的制造方法，其中，所述数据线垫层形成为与所述数据线电绝缘。
  16. 如权利要求10-15的任一项所述的阵列基板的制造方法，其中，所述数据线垫层形成为具有锯齿状边缘。
  17. 如权利要求10-16的任一项所述的阵列基板的制造方法，还包括形成第二有源垫层，其中，所述第二有源垫层设置在所述绝缘层和所述数据线之间且位于所述栅线和所述数据线相交叠的区域内。
  18. 如权利要求10-17的任一项所述的阵列基板的制造方法，还包括形成至少另一个第一有源垫层。
  19. 一种包括如权利要求1-9任一项所述的阵列基板的显示面板。
  20. 一种包括如权利要求19所述的显示面板的电子装置。
PCT/CN2016/072168 2015-09-28 2016-01-26 阵列基板、制造方法以及相应的显示面板和电子装置 WO2017054381A1 (zh)

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