WO2016011716A1 - 阵列基板和显示装置 - Google Patents
阵列基板和显示装置 Download PDFInfo
- Publication number
- WO2016011716A1 WO2016011716A1 PCT/CN2014/089031 CN2014089031W WO2016011716A1 WO 2016011716 A1 WO2016011716 A1 WO 2016011716A1 CN 2014089031 W CN2014089031 W CN 2014089031W WO 2016011716 A1 WO2016011716 A1 WO 2016011716A1
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- WIPO (PCT)
- Prior art keywords
- thin film
- pixel electrode
- array substrate
- film transistor
- pixel electrodes
- Prior art date
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- 239000000758 substrate Substances 0.000 title claims abstract description 40
- 239000010409 thin film Substances 0.000 claims abstract description 49
- 238000000034 method Methods 0.000 claims description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 8
- 210000002858 crystal cell Anatomy 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
Images
Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
Definitions
- Embodiments of the present invention relate to an array substrate and a display device.
- Liquid crystal display has become a mainstream product in flat panel display devices due to its small size, low power consumption, and no radiation.
- a liquid crystal display device generally includes an array substrate on which a thin film transistor and a pixel electrode are disposed, and a pixel electrode is connected to a drain of the thin film transistor. At the time of display, charging of the pixel electrode is performed by the switching control of the thin film transistor for display.
- an insulating layer is disposed between the thin film transistor and the pixel electrode, and the pixel electrode is connected to the drain of the thin film transistor through a via hole opened in the insulating layer.
- the layout area of the pixel electrode is smaller and smaller, and while the via holes are overlapped between the pixel electrode and the drain, it is also ensured that a sufficient spacing is maintained between the pixel electrode patterns. To avoid a short circuit between the pixel electrode patterns.
- At least one embodiment of the present invention provides an array substrate and a display device.
- the array substrate By arranging the pixel electrode to cover a partial edge of the via hole in the forward projection direction, the array substrate not only avoids a short circuit between the pixel electrodes, but also can improve the aperture ratio of the display product while improving the resolution of the display product.
- At least one embodiment of the present invention provides an array substrate including a thin film transistor and a pixel electrode disposed above the thin film transistor, an insulating layer interposed between the pixel electrode and the thin film transistor, and the pixel electrode is opened A via hole in the insulating layer is connected to a drain of the thin film transistor, and the pixel electrode covers a partial edge of the via hole in a right projection direction.
- At least one embodiment of the present invention also provides a display device including the above array substrate.
- 1 is a top plan view showing a partial structure of an array substrate
- FIG. 2 is a top plan view showing a partial structure of an array substrate according to an embodiment of the present invention.
- FIG 3 is a top plan view showing a partial structure of an array substrate according to another embodiment of the present invention.
- the thin film transistor 1 that controls the adjacent two pixel electrodes 2 is usually disposed in the interval region between the adjacent two pixel electrodes 2.
- the inventors have found that, in the structure shown in FIG. 1, since the pixel electrode 2 is usually connected to the drain 11 of the thin film transistor 1 by completely covering the via hole 3 in the insulating layer after preparation, this causes two pixels.
- the distance L between the electrodes 2 and the two connecting portions 6 connected to the corresponding drains 11 is close, which easily causes a short circuit between the two pixel electrodes 2. If the distance between the two connecting portions 6 is increased, a sufficient distance between the two connecting portions 6 is left, which in turn causes the graphic area of the pixel electrode 2 to be relatively reduced, thereby adversely affecting the aperture ratio when the display panel is displayed.
- the impact, at the same time, will also cause some difficulties in the improvement of the display panel resolution.
- At least one embodiment of the present invention provides an array substrate, as shown in FIG. 2, including a thin film transistor 1 and a pixel electrode 2 disposed above the thin film transistor 1, and an insulating layer between the pixel electrode 2 and the thin film transistor 1
- the electrode 2 is connected to the drain 11 of the thin film transistor 1 through a via 3 opened in the insulating layer, and the pixel electrode 2 covers a partial edge of the via 3 in the forward projection direction.
- the size of the pixel electrode 2 at the junction with the drain 11 of the thin film transistor 1 can be reduced, so that the pitch between the pixel electrodes 2 at the junction of the respective drain electrodes 11 is increased, avoiding the pixel electrode 2 A short circuit occurs between them.
- the array substrate further includes a plurality of gate lines 4 and a plurality of data lines 5, and the gate lines 4 and the data lines 5 are spatially intersected to divide the array substrate into a plurality of regions (pixel units), and each region corresponds to At least one pixel electrode 2 and at least one thin film transistor 1 are included, and thus the pixel electrode 2 includes a plurality of, and the thin film transistor 1 includes a plurality of, for example, the pixel electrode 2 is connected to the thin film transistor 1 in one-to-one correspondence.
- any two adjacent pixel electrodes 2 are respectively disposed in two regions spaced apart from each other by two gate lines 4, and two thin film transistors 1 connected to two adjacent pixel electrodes 2 are disposed. In the interval region between two adjacent pixel electrodes 2 (between the two gate lines 4). With this arrangement, the pitch between the patterns of the adjacent pixel electrodes 2 can be increased, thereby avoiding a short circuit phenomenon between the pixel electrodes 2.
- the drain 11 of the thin film transistor 1 connected to the adjacent two pixel electrodes 2 is disposed at a diagonal position of the interval region between the adjacent two pixel electrodes 2, and adjacent two The via holes 3 corresponding to the pixel electrodes 2 are respectively located in the orthogonal projection direction of the drain 11.
- the arrangement is such that the distance between the drains 11 respectively connected to the adjacent two pixel electrodes 2 is maximized, so that the distance between the junctions of the adjacent two pixel electrodes 2 and the drain 11 is maximized, which is advantageous to avoid A short circuit occurs between the pixel electrodes 2.
- two adjacent pixel electrodes 2 respectively cover opposite side edges of the two via holes 3 corresponding thereto in the right projection direction. Since the pixel electrode 2 is connected to the drain 11 of the thin film transistor 1 through the via 3, the pixel electrode 2 can be connected to the drain 11 of the thin film transistor 1 through the via 3 on the one hand, thereby ensuring the realization of the pair of pixels of the thin film transistor 1.
- the distance between the adjacent two pixel electrodes 2 at the position of the via 3 is made larger, thereby avoiding a short circuit between the pixel electrodes 2; meanwhile, since the adjacent two pixel electrodes 2 are The distance at the position of the via hole 3 becomes large, so that the area of the region where the thin film transistor 1 is disposed can be reduced correspondingly, so that the area of the disposed region of the pixel electrode 2 is increased, so that the area of the pixel electrode 2 can be correspondingly increased, thereby improving the area. Shows the aperture ratio of the product.
- the maximum width of the portion of the pixel electrode 2 that overlaps the via 3 in the forward projection direction is smaller than the maximum aperture of the via 3. That is, the pixel electrode 2 overlaps only partially with the via 3 in the forward projection direction, which makes the size of the junction of the pixel electrode 2 and the drain 11 of the thin film transistor 1 It is greatly reduced, so that the distance between the pixel electrodes 2 can be increased, and short-circuiting between the pixel electrodes 2 due to too close a distance can be avoided.
- the pixel electrode 2 covers a side edge of the via hole 3 close to the pixel electrode 2 in the forward projection direction.
- the shape of the pixel electrode 2 and the connecting portion 23 of the thin film transistor 1 are trapezoidal, and the shorter base 21 of the trapezoid is overlapped with the via 3.
- the shorter base edge 21 of the trapezoid has a length of less than 2 ⁇ m. This causes the longitudinal spacing Y and the lateral spacing X between the adjacent two pixel electrodes 2 to be connected to the drain portion 11 of the thin film transistor 1 (i.e., the portion overlapping the via hole 3) to be increased, which enables A short circuit between the pixel electrodes 2 is avoided.
- the area of the region where the thin film transistor 1 is located can be appropriately reduced in the case where the short circuit does not occur between the pixel electrodes 2 (that is, between the two drains 11)
- the longitudinal pitch Y and the lateral pitch X are appropriately shortened.
- the area of the region where the pixel electrode 2 is located can be increased correspondingly, so that the area of the pixel electrode 2 can be appropriately increased, and the aperture ratio of the display product can be improved.
- the increase in the area of the pixel electrode 2 can also increase the number of the pixel electrodes 2, thereby improving the resolution of the display product.
- At least one embodiment of the present invention provides an array substrate. Unlike the above embodiment, as shown in FIG. 3, the shape of the pixel electrode 2 corresponding to the connecting portion 23 of the thin film transistor 1 is rectangular, and a wide side of the rectangle 22 overlaps the via 3 . For example, the length of the wide side 22 of the rectangle is less than 2 ⁇ m.
- the above structural arrangement can also make the longitudinal spacing Y and the lateral spacing X between the adjacent two pixel electrodes 2 and the connecting portion 23 of the drain electrode 11 of the thin film transistor 1 (ie, the overlapping portion with the via 3)
- the increase prevents the occurrence of a short circuit between the pixel electrodes 2.
- the distance between the pixel electrodes 2 is increased, it is possible to appropriately reduce the area of the region where the thin film transistor 1 is located in the case where the short circuit does not occur between the pixel electrodes 2 (that is, between the two drains 11)
- the longitudinal pitch Y and the lateral pitch X are appropriately shortened.
- the area of the region where the pixel electrode 2 is located can be increased correspondingly, so that the area of the pixel electrode 2 can be appropriately increased, and the aperture ratio of the display product can be improved.
- the increase in the area of the pixel electrode 2 can also increase the number of the pixel electrodes 2, thereby improving the resolution of the display product.
- the distance between adjacent two pixel electrodes is significantly increased by covering the pixel electrode in a front projection direction with a partial edge of the via hole, which not only avoids short circuit between the pixel electrodes. .
- the distance between the pixel electrodes is significantly increased, it is able to In the case of ensuring that no short circuit occurs between the pixel electrodes, the area of the region where the thin film transistor is located is appropriately reduced, so that the area of the region where the pixel electrode is located is correspondingly increased, so that the area of the pixel electrode is appropriately increased, thereby improving Shows the aperture ratio of the product.
- the increase of the area of the pixel electrode area can also increase the number of pixel electrodes, thereby improving the resolution of the display product.
- At least one embodiment of the present invention provides a display device including any one of the array substrates described above.
- the display device includes an array substrate and a counter substrate; the array substrate and the opposite substrate face each other to form a liquid crystal cell, and the liquid crystal cell is filled with a liquid crystal material.
- the opposite substrate is, for example, a color filter substrate.
- the liquid crystal display device further includes a backlight that provides backlighting for the array substrate.
- the aperture ratio and resolution of the display device can be further improved.
- the display device may be any product or component having a display function such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, a watch, and the like.
- a display function such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, a watch, and the like.
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Abstract
Description
Claims (11)
- 一种阵列基板,包括至少一个薄膜晶体管和设置在所述至少一个薄膜晶体管上方的至少一个像素电极,其中,所述至少一个像素电极和所述至少一个薄膜晶体管之间夹设有绝缘层,所述至少一个像素电极通过开设在所述绝缘层中的过孔与所述至少一个薄膜晶体管的漏极连接,所述至少一个像素电极在正投影方向上覆盖所述过孔的局部边缘。
- 根据权利要求1所述的阵列基板,还包括多条栅线和数据线,其中,所述栅线和所述数据线空间交叉将所述阵列基板划分为多个区域,所述至少一个像素电极包括多个像素电极,所述至少一个薄膜晶体管包括多个薄膜晶体管,所述多个像素电极与所述多个薄膜晶体管一一对应连接;任意相邻的两个像素电极分别对应设置在相互间隔开的两个所述区域内,与所述相邻两个像素电极连接的薄膜晶体管设置在所述相邻两个像素电极之间得的间隔区域内。
- 根据权利要求2所述的阵列基板,其中,与所述相邻两个像素电极连接的薄膜晶体管的漏极分设在所述相邻两个像素电极之间的间隔区域的对角位置上,与所述相邻两个像素电极相对应的过孔分别对应位于所述漏极的正投影方向上。
- 根据权利要求3所述的阵列基板,其中,所述相邻两个像素电极在正投影方向上分别覆盖与其相对应的两个所述过孔的相对且相互远离的一侧边缘。
- 根据权利要求1-4任一所述的阵列基板,其中,所述像素电极在正投影方向上与所述过孔相重叠部分的最大宽度小于所述过孔的最大孔径。
- 根据权利要求5所述的阵列基板,其中,所述像素电极在正投影方向上覆盖所述过孔的靠近所述像素电极的一侧边缘。
- 根据权利要求6所述的阵列基板,其中,所述像素电极的对应于所述薄膜晶体管的相连接部分的形状呈梯形,所述梯形的较短的底边与所述过孔相覆叠。
- 根据权利要求7所述的阵列基板,其中,所述梯形的较短的底边的长 度小于2μm。
- 根据权利要求6所述的阵列基板,其中,所述像素电极的对应于所述薄膜晶体管的相连接部分的形状呈矩形,所述矩形的一宽边与所述过孔相覆叠。
- 根据权利要求9所述的阵列基板,其中,所述矩形的宽边的长度小于2μm。
- 一种显示装置,包括权利要求1-10任意一项所述的阵列基板。
Priority Applications (1)
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US14/770,561 US10133136B2 (en) | 2014-07-25 | 2014-10-21 | Array substrate and display device |
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CN201410360563.1 | 2014-07-25 | ||
CN201410360563.1A CN104181740B (zh) | 2014-07-25 | 2014-07-25 | 一种阵列基板和显示装置 |
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US (1) | US10133136B2 (zh) |
CN (1) | CN104181740B (zh) |
WO (1) | WO2016011716A1 (zh) |
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US10754216B2 (en) * | 2015-05-26 | 2020-08-25 | Boe Technology Group Co., Ltd. | Array substrate and driving method thereof, liquid crystal display panel, and liquid crystal display device |
CN105895639A (zh) * | 2016-06-29 | 2016-08-24 | 京东方科技集团股份有限公司 | 阵列基板及其制备方法、显示器件 |
TWI645557B (zh) | 2017-12-08 | 2018-12-21 | 友達光電股份有限公司 | 畫素陣列基板 |
US11937478B2 (en) | 2021-07-16 | 2024-03-19 | Avalon Holographics Inc. | Multi-colored microcavity OLED array having DBR for high aperture display and method of fabricating the same |
CN113917750B (zh) * | 2021-10-19 | 2023-10-20 | 京东方科技集团股份有限公司 | 一种阵列基板、彩膜基板、显示面板及显示装置 |
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- 2014-07-25 CN CN201410360563.1A patent/CN104181740B/zh active Active
- 2014-10-21 WO PCT/CN2014/089031 patent/WO2016011716A1/zh active Application Filing
- 2014-10-21 US US14/770,561 patent/US10133136B2/en active Active
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CN203084393U (zh) * | 2013-02-05 | 2013-07-24 | 北京京东方光电科技有限公司 | 一种阵列基板及液晶显示面板 |
CN103744236A (zh) * | 2013-12-27 | 2014-04-23 | 深圳市华星光电技术有限公司 | 像素结构 |
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US20160363828A1 (en) | 2016-12-15 |
CN104181740A (zh) | 2014-12-03 |
US10133136B2 (en) | 2018-11-20 |
CN104181740B (zh) | 2017-01-18 |
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