WO2017128711A1 - 阵列基板及显示装置 - Google Patents

阵列基板及显示装置 Download PDF

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Publication number
WO2017128711A1
WO2017128711A1 PCT/CN2016/096727 CN2016096727W WO2017128711A1 WO 2017128711 A1 WO2017128711 A1 WO 2017128711A1 CN 2016096727 W CN2016096727 W CN 2016096727W WO 2017128711 A1 WO2017128711 A1 WO 2017128711A1
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WIPO (PCT)
Prior art keywords
pattern
metal layer
array substrate
storage electrode
substrate
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PCT/CN2016/096727
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English (en)
French (fr)
Inventor
郝学光
程鸿飞
乔勇
吴新银
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to JP2017532849A priority Critical patent/JP6827929B2/ja
Priority to KR1020177017981A priority patent/KR102003359B1/ko
Priority to EP16871782.5A priority patent/EP3410181A4/en
Priority to US15/535,635 priority patent/US10158024B2/en
Publication of WO2017128711A1 publication Critical patent/WO2017128711A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133553—Reflecting elements
    • G02F1/133555—Transflectors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7003—Alignment type or strategy, e.g. leveling, global alignment
    • G03F9/7042—Alignment for lithographic apparatus using patterning methods other than those involving the exposure to radiation, e.g. by stamping or imprinting
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    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7088—Alignment mark detection, e.g. TTR, TTL, off-axis detection, array detector, video detection
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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Definitions

  • Embodiments of the present disclosure relate to an array substrate and a display device.
  • Display modes of the display device include twisted nematic (TN), vertical alignment (VA), in-plane switching (IPS), and fringe field conversion (FFS).
  • Pixel structures typically employ different storage capacitor structures depending on the display mode.
  • the TN and VA modes typically employ a storage capacitor between the common electrode line and the pixel electrode.
  • IPS and FFS typically employ a storage capacitor between the common electrode and the pixel electrode.
  • the structure of the storage capacitor is related to the stability of the pixel voltage, thus directly affecting the quality and yield of the display.
  • At least one embodiment of the present disclosure is directed to an array substrate and a display device for reducing crosstalk and display failure of the display device.
  • An aspect of the present disclosure provides an array substrate including a substrate substrate and a gate metal layer, an active layer, and a source/drain metal layer disposed on the substrate;
  • the gate metal layer includes a gate line and a storage electrode line extending in parallel with the gate line;
  • the active layer including a first pattern as a TFT channel region and a second pattern at least partially overlapping the storage electrode line in a thickness direction of the substrate,
  • the source/drain metal layer includes a data line pattern and a metal layer pattern at least partially overlapping the storage electrode line in a thickness direction of the substrate.
  • the active layer includes a first pattern as a TFT channel region and a second pattern at least partially overlapping the storage electrode line in a thickness direction of the substrate
  • the source The drain metal layer includes a data line pattern and a metal layer pattern at least partially overlapping the storage electrode line in a thickness direction of the substrate.
  • the active layer is disposed between the base substrate and the gate metal layer.
  • the gate metal layer is disposed on the substrate substrate and the Between the source layers.
  • the second pattern is coupled to the first pattern.
  • the second pattern includes a connection portion and an overlap portion connected to the connection portion; the connection portion is connected to the first pattern, and the overlap portion is opposite to the storage electrode line
  • the substrates overlap in the thickness direction.
  • the overlapping portion is disposed at an intersection of the storage electrode line and the data line.
  • the connecting portion is the same as the extending direction of the data line, and an orthographic projection of the connecting portion on the first main surface of the base substrate is located in the data line in the lining Within the orthographic projection of the first major surface of the base substrate.
  • the width of the overlapping portion is larger than the size of the connecting portion in the width direction of the data line.
  • the overlapping portion is a plate-like structure.
  • the storage electrode line includes a widening portion at a position crossing the data line.
  • an orthographic projection of the widened portion on a first major surface of the substrate substrate coincides with an orthographic projection of the overlapping portion on a first major surface of the substrate substrate.
  • the metal layer pattern is disposed at an intersection of the storage electrode line and the data line.
  • the metal layer pattern is integral with the data line.
  • the metal layer pattern is a plate-like structure.
  • the size of the metal layer pattern in the width direction of the data line is larger than the width of the data line.
  • the size of the metal layer pattern in the width direction of the storage electrode line is not larger than the width of the storage electrode line.
  • the storage electrode line includes a widening portion at a position crossing the data line.
  • an orthographic projection of the widened portion on a first major surface of the substrate substrate coincides with an orthographic projection of the metal layer pattern on a first major surface of the substrate substrate .
  • Another aspect of the present disclosure provides a display device including the array substrate as described above.
  • 1 is a schematic structural view of a base substrate
  • FIG. 2a is a top plan view showing an array substrate forming a storage capacitor through an active layer and a storage electrode line according to an embodiment of the present disclosure
  • FIG. 2b is a schematic structural view of an active layer according to an embodiment of the present disclosure.
  • 3a is a schematic structural view of an active layer according to an embodiment of the present disclosure.
  • 3b is a top plan view of an array substrate including the active layer structure of FIG. 3a;
  • FIG. 4a is a schematic view of a storage electrode line including a widened portion according to an embodiment of the present disclosure
  • FIG. 4b is a schematic structural diagram of a storage electrode line including a widened portion and the widened portion and a storage layer form a storage capacitor according to an embodiment of the present disclosure
  • FIG. 5 is a schematic top plan view showing an array substrate forming a storage capacitor through a source/drain metal layer and a storage electrode line according to an embodiment of the present disclosure
  • FIG. 6 is a schematic view showing the relationship between the metal layer pattern and the data line in the width direction of the data line according to the present disclosure
  • FIG. 7 is a schematic diagram showing the relationship between the metal layer pattern and the storage electrode line in the width direction of the storage electrode line according to the embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a storage electrode line including a widened portion according to an embodiment of the present disclosure
  • FIG. 9 is a schematic diagram of a widened portion of a storage electrode line and a metal layer pattern forming a storage capacitor according to an embodiment of the present disclosure.
  • the liquid crystal display device usually includes a backlight module, a lower substrate, an upper substrate, and a peripheral driving circuit. section.
  • the lower substrate is usually an array substrate
  • the upper substrate is usually a color film substrate.
  • the array substrate further includes a base substrate (typically a glass substrate) and a structure such as a gate line, an active layer, a data line, a common electrode line, and a pixel electrode disposed on the base substrate.
  • 1 is a schematic structural view of a base substrate. Referring to FIG. 1, the base substrate 10 includes a first major surface 11 and a second major surface 12 that are opposed to each other. For example, a structure such as a gate line, an active layer, a data line, a common electrode line, and a pixel electrode is provided on the first main surface 11 side of the base substrate 10.
  • a thin film transistor In a liquid crystal display device, a thin film transistor (TFT) is generally employed as a switch for controlling a data signal applied to a pixel electrode.
  • the TFT includes a source, a drain, a gate, and a channel region separating the source and drain.
  • the channel region of the TFT is characterized in that the source and drain of the TFT can be turned on when a certain on-voltage is applied.
  • the channel region can be made of a semiconductor material such as amorphous silicon, polysilicon, an oxide semiconductor, or the like.
  • the TFT is connected in such a manner that the gate is connected to the gate line to receive the on-voltage signal applied by the gate line, and the on-voltage signal is applied to the channel region through the gate of the TFT to control the conduction of the channel region.
  • the source is connected to the data line to receive the voltage signal from the data line; the drain is connected to the pixel electrode to charge the pixel electrode after the source and drain of the TFT are turned on through the channel region. That is to say, after the source and drain of the TFT are turned on, the signal on the data line can be applied to the pixel electrode through the source and drain of the TFT, thereby being used to control the deflection of the liquid crystal molecules.
  • the deflection of the liquid crystal molecules is generally performed and completed in the holding time after the charging of the pixel electrodes is completed. That is to say, after the pixel electrode finishes charging, a stable charging voltage is required to continuously drive the liquid crystal molecules to rotate.
  • the pixel load capacitance which mainly includes the liquid crystal capacitor and the storage capacitor.
  • the function of the storage capacitor is, for example, to maintain the stability of the pixel voltage and improve the display quality.
  • the storage capacitors are formed differently in different display modes.
  • the TN and VA modes typically employ a storage capacitor between the common electrode line and the pixel electrode; IPS, FFS, and ADS typically employ a storage capacitor between the common electrode and the pixel electrode.
  • the structure of the storage capacitor will directly affect the quality and yield of the display.
  • Embodiments of the present disclosure provide an array substrate including a substrate substrate and a gate metal layer, an active layer, and a source/drain metal layer disposed on the substrate; wherein the gate metal layer includes a gate line and a storage electrode line extending in parallel with the gate line; the active layer includes a first pattern as a TFT channel region and a second pattern at least partially overlapping the storage electrode line in a thickness direction of the substrate, or the source/drain metal layer includes The data line pattern and the storage electrode line are at least partially heavy in the thickness direction of the substrate Stacked metal layer pattern.
  • the array substrate of the embodiment of the present disclosure can obtain a large storage capacitor and improve the display quality of the display device.
  • the embodiment of the present disclosure forms a storage capacitor with a source/drain metal layer and/or an active layer by a storage electrode line (which may also be referred to as a common electrode line, hereinafter referred to as a storage electrode line).
  • a storage electrode line which may also be referred to as a common electrode line, hereinafter referred to as a storage electrode line.
  • the metal layer pattern may be, for example, an integral structure directly connected to the data line.
  • the metal layer pattern may be, for example, also disconnected from the data lines, that is, the source/drain metal layer includes a metal layer pattern separately disposed outside the data lines and the storage electrode lines overlapping each other in the thickness direction of the array substrate.
  • the active layer and the storage electrode line form a storage capacitor structure, the active layer includes at least two pattern portions.
  • One of the pattern portions is, for example, a pattern as a channel region of the TFT; the other pattern portion includes, for example, at least a portion overlapping the storage electrode lines in the thickness direction of the array substrate to form a storage capacitor. Also, the above two patterns of the active layer may be connected to each other, for example, or not.
  • the active layer includes a first pattern as a TFT channel region and a second pattern at least partially overlapping the storage electrode line in a thickness direction of the substrate.
  • 2a is a top plan view showing an array substrate forming a storage capacitor through an active layer and a storage electrode line according to an embodiment of the present disclosure.
  • 2b is a schematic structural view of an active layer according to an embodiment of the present disclosure.
  • the array substrate includes a substrate substrate and a gate metal layer disposed on the substrate, an active layer (hatched pattern in Figures 2a and 2b), and a source/drain metal layer.
  • the gate metal layer includes a gate line 102 (and a gate electrode 112 branched from the gate line) and a storage electrode line 100 extending in parallel with the gate line.
  • An active layer (bottom gate structure) is disposed above the gate metal layer, the active layer 106 includes a first pattern as a channel region of the TFT, and includes a portion overlapping with the storage electrode line at least partially overlapping the thickness direction of the substrate substrate Two patterns.
  • the portion of the active layer below the pixel electrode layer is shown with low visibility in Figure 2a; the active layer is not visible directly below the data line, but for the sake of clarity, the active layer is on the array substrate. In the way of setting, low visual processing is also applied to this part of the active layer in Figure 2a. Similarly, the active layer is also treated the same in Figures 3b and 5 below, and is indicated here. Referring to FIG. 2b, a portion of the active layer surrounded by a broken line is, for example, a second pattern, and a portion of the active layer other than the broken line is, for example, a first pattern. Referring to FIG.
  • a portion of the first pattern (a portion above the gate) serves as a TFT channel region, and the second pattern at least partially overlaps the storage electrode line 100 in the substrate thickness direction.
  • a substantially square portion of the second pattern overlaps the storage electrode line 100 in the substrate thickness direction to form a storage battery
  • the volume (the part enclosed by the dotted line in Figure 2a).
  • an active drain metal layer is further disposed on the active layer.
  • the source/drain metal layer includes a data line 108 crossing the gate line 102, and a source 118 and a drain 119 of the TFT are formed.
  • a pixel electrode 109 may be disposed over the source and drain metal layers.
  • the source 118 of the TFT is connected to the data line 108, and the drain 119 is connected to the pixel electrode 109, for example, via a via hole (not shown) formed in the insulating layer, and the gate is connected to the gate line 102.
  • an active layer may be disposed between the base substrate and the gate metal layer. That is, the array substrate of the embodiment of the present disclosure may be a top gate structure.
  • the top gate structure an active layer including at least a first pattern and a second pattern is first formed on the base substrate, and then a gate insulating layer is formed on the active layer, and a gate metal layer is formed over the gate insulating layer.
  • the gate metal layer includes gate lines and storage electrode lines extending in parallel. The second pattern and the storage electrode line at least partially overlap in the substrate thickness direction to form a storage capacitor.
  • the gate metal layer is disposed between the base substrate and the active layer.
  • the array substrate of the embodiment of the present disclosure may be a bottom gate structure.
  • Figure 2a shows an embodiment of an array substrate having a bottom gate structure.
  • a gate metal layer including parallel extending gate lines and storage electrode lines is first formed on the base substrate, and then a gate insulating layer is formed over the gate metal layer, and formation over the gate insulating layer includes at least The first pattern and the second pattern active layer.
  • the second pattern and the storage electrode line at least partially overlap in the substrate thickness direction to form a storage capacitor.
  • the second pattern is coupled to the first pattern.
  • Figure 3a shows a structure of an active layer of an embodiment of the present disclosure.
  • Figure 3b is a top plan view of an array substrate including the active layer structure of Figure 3a.
  • the active layer includes a first pattern (a portion not included in the broken line in the drawing) and a second pattern (including a portion within a dotted line in the drawing).
  • the second pattern is directly connected to the first pattern, that is, the second pattern is integrated with the first pattern.
  • the second pattern may also be separated from the second pattern from each other, that is, two separate patterns are formed on the active layer.
  • the second pattern includes a connecting portion and an overlapping portion connected to the connecting portion; the connecting portion is connected to the first pattern, and the overlapping portion and the storage electrode line overlap in a thickness direction of the substrate.
  • the second pattern (the portion enclosed by the dashed line in the figure) includes a connecting portion 1062 and an overlapping portion 1063.
  • the connection portion 1062 is connected to the first pattern, and the overlapping portion 1063 is for overlapping with the storage electrode line 100 in the substrate thickness direction to form a storage capacitor.
  • the first pattern shown in Figure 3a includes a channel region 1061 of the TFT.
  • the channel region 1061 of the first pattern receives the turn-on voltage from the gate 112, the channel region 1061 is turned on.
  • the voltage signal of the data line is transmitted from the source of the TFT through the channel region 1061 to the drain of the TFT to charge the pixel electrode.
  • the shape of the first pattern of the active layer is not limited to the structure shown in FIG. 3a, and for example, the first pattern may have other shapes.
  • the overlapping portion may be, for example, a rectangle, a square, a circle, an ellipse or other regular or irregular plate-like structure.
  • the specific structure shown in Figure 3a is not intended to limit the disclosure.
  • the overlapping portion is disposed at an intersection of the storage electrode line and the data line.
  • the overlapping portion 1063 is disposed at an intersection of the storage electrode line 100 and the data line 108.
  • the connecting portion is the same as the extending direction of the data line, and the orthographic projection of the connecting portion on the first main surface of the base substrate is located in the orthographic projection of the data line on the first main surface of the base substrate.
  • the connecting portion 1062 is the same as the extending direction of the data line 108, and the orthographic projection of the connecting portion 1062 on the first major surface of the substrate substrate is located at the orthographic projection of the data line 108 on the first major surface of the substrate substrate. within.
  • the size of the overlapping portion 1063 is larger than the size of the connecting portion 1062 to obtain a larger storage capacitance.
  • the overlapping portion is a plate-like structure.
  • the size of the storage capacitor is determined by the facing area of the metal plates opposite to each other; on the other hand, it depends on the distance between the metal plates.
  • the facing area of the position of the overlapping portion and the storage electrode line can be increased, thereby increasing the storage capacitance to effectively prevent flicker and crosstalk.
  • the shape of the plate-like structure referred to herein is, for example, a rectangle, a square, a circle, and other regular or irregular shapes.
  • the storage electrode line includes a widening portion at a position crossing the data line.
  • 4a is a schematic diagram of a storage electrode line including a widened portion of an embodiment of the present disclosure.
  • 4b is a schematic structural view of a storage electrode line including a widened portion and a storage layer forming a storage capacitor according to an embodiment of the present disclosure.
  • the storage electrode line 100 is provided with a widened portion 1001 at a position crossing the data line 108 (only one widened portion is shown in the drawing).
  • the function of the widened portion 1001 is to increase the area facing the overlapping portion 1063 to increase the storage capacitance and improve the display effect.
  • the widened portion 1001 is set to have a rectangular shape, a square shape, a circular shape, or the like.
  • the widened portion 1001 is provided to have the same shape as the overlapping portion 1063 of the active layer described above to increase the storage capacitance.
  • the widened portion 1001 and the overlapping portion 1063 have the same shape and area, and are disposed opposite to each other.
  • the orthographic projection of the widened portion 1001 on the first major surface of the base substrate coincides with the orthographic projection of the overlapping portion 1063 on the first major surface of the base substrate.
  • the widened portion of the storage electrode line needs to be fitted to the overlapping portion.
  • the widened portion and the overlapping portion are equal in size and in the same shape, the area in which the widened portion and the overlapping portion face each other can be maximized, thereby obtaining a large storage capacitance.
  • the source/drain metal layer includes a data line pattern and a metal layer pattern that at least partially overlaps the storage electrode line in a thickness direction of the substrate.
  • FIG. 5 is a top plan view of the array substrate forming a storage capacitor through a source/drain metal layer and a storage electrode line according to an embodiment of the present disclosure.
  • the array substrate includes a base substrate and a gate metal layer, an active layer, and a source/drain metal layer disposed on the array substrate.
  • the gate metal layer includes gate lines 102 (and gates) and storage electrode lines 100 that extend in parallel.
  • the active layer is provided with a channel region of the TFT.
  • the source/drain metal layer includes a data line pattern and a metal layer pattern 110 overlapping the storage electrode line 100 in the substrate thickness direction (ie, a portion of the source/drain metal layer surrounded by a broken line in FIG. 5).
  • the metal layer pattern 110 thus forms a storage capacitor with the storage electrode line 100.
  • Such a manner of forming a storage capacitor through the source/drain metal layer and the storage electrode line can obtain a large storage capacitor and improve the display effect of the display device.
  • an active layer may be disposed between the base substrate and the gate metal layer. That is, the array substrate can be a top gate structure.
  • the top gate structure an active layer is first formed on the base substrate, and then a gate insulating layer covering the active layer is formed over the active layer, and a gate metal layer is formed on the gate insulating layer.
  • the gate metal layer includes gate lines and storage electrode lines extending in parallel.
  • an interlayer insulating layer is formed on the gate metal layer, and the source/drain metal layer is formed in the interlayer insulating layer.
  • the source/drain metal layer should include at least a data line pattern and the above metal layer pattern.
  • a gate metal layer is disposed between the base substrate and the active layer. That is, the array substrate can be a bottom gate structure.
  • a gate metal layer including parallel extending gate lines and storage electrode lines is first formed on the base substrate, then a gate insulating layer is formed over the gate metal layer, and an active layer is formed on the gate insulating layer .
  • a source/drain metal layer is then formed over the active layer.
  • the source/drain metal layer should include at least a data line pattern and the above metal layer pattern.
  • the active layer may further include a first pattern as a TFT channel region and a second pattern at least partially overlapping the storage electrode line in the substrate thickness direction. That is, the active layer includes the structure as described above and related deformation structures.
  • the storage electrode line forms a storage capacitor with the source/drain metal layer and the active layer at the same time, which can further improve the storage capacitance, thereby better avoiding crosstalk and display failure of the display device.
  • the metal layer pattern is disposed at the intersection of the storage electrode line and the data line to prevent the aperture ratio from being lowered.
  • the metal layer pattern 110 is disposed at a position where the storage electrode line 100 and the data line 108 cross each other.
  • the metal layer pattern 110 is, for example, integrated with the data line 108, for example, both are obtained by the same metal layer through a patterning process.
  • the metal layer pattern 110 includes a portion of the data line that intersects the storage electrode line and a portion that protrudes from the portion of the data line toward both sides of the data line. The integrated arrangement of the data line and the metal layer pattern can avoid reducing the aperture ratio of the display device.
  • the metal layer pattern is a plate-like structure.
  • the shape of the metal layer pattern may be a rectangle, a square, or other regular or irregular shape.
  • FIG. 6 is a schematic diagram showing the relationship between the metal layer pattern and the data line in the width direction of the data line according to the embodiment of the present disclosure.
  • a data layer 108 is provided with a metal layer pattern 110, that is, a portion indicated by hatching in the figure.
  • the data line 108 and the metal layer pattern 110 are both disposed on the source and drain metal layers.
  • the size of the metal layer pattern 110 in the width direction of the data line 108 (the direction indicated by the arrow in FIG. 6) is larger than the width of the data line 108.
  • the metal layer pattern 110 and the data line 108 may be a unitary structure, as obtained by a patterning process from the same metal layer.
  • the width of the metal layer pattern By making the width of the metal layer pattern larger than the width of the data line, a large storage capacitance can be obtained, preventing crosstalk and display failure of the display device.
  • FIG. 7 is a schematic diagram showing the relationship between the metal layer pattern and the storage electrode line in the width direction of the storage electrode line according to the embodiment of the present disclosure.
  • the data line 108 and the storage electrode line 100 are disposed to cross each other.
  • the metal layer pattern 110 is disposed at an intersection of the data line 108 and the storage electrode line 100.
  • the size of the metal layer pattern 110 is not larger than the width of the storage electrode line 100, for example, It may be equal to or slightly smaller than the width of the storage electrode line 100. To prevent reducing the aperture ratio of the display device.
  • the storage electrode line includes a widening portion at a position crossing the data line.
  • FIG. 8 is a schematic diagram of a storage electrode line including a widened portion according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of a widened portion of a storage electrode line and a metal layer pattern forming a storage capacitor according to an embodiment of the present disclosure.
  • the storage electrode line 100 is provided with a widening portion 1001 at a position crossing the data line 108 (only one intersection position is illustrated in the drawing).
  • the function of the widened portion 1001 is to increase the facing area with, for example, the metal layer pattern to increase the storage capacitance.
  • the widened portion 1001 may be set to a rectangular or square shape or other regular or irregular shape.
  • the same shape as the metal layer pattern described above increases the storage capacitance.
  • the orthographic projection of the widened portion 1001 on the first main surface 11 of the base substrate coincides with the orthographic projection of the metal layer pattern 110 on the first main surface 11 of the base substrate, further increasing the storage. capacitance.
  • the widened portion of the storage electrode line needs to be disposed in cooperation with the above metal layer pattern to obtain a larger storage capacitor.
  • the widened portion and the metal layer pattern are set to be equal in size and have the same shape, so that the facing area of the widened portion and the metal layer pattern can be maximized, thereby obtaining a large storage capacitance.
  • the embodiment of the present disclosure provides an array substrate preparation method, but the array substrate preparation method of the present disclosure is not limited to the following method.
  • the array substrate of the present disclosure will be described below by taking only the first pattern as the TFT channel and the second pattern at least partially overlapping the storage electrode line in the thickness direction of the substrate, and the array substrate having the top gate structure as an example.
  • the preparation method is as follows:
  • a metal layer on the substrate by, for example, sputtering, and then etching using a first mask to obtain a gate line and a gate connected to the gate line, and simultaneously forming a gate line and a gate line and a gate line Parallel extended storage electrode lines.
  • the metal layer may, for example, comprise aluminum, an aluminum alloy, and copper or other suitable material.
  • an insulating layer is formed as a gate insulating layer.
  • a semiconductor layer is then formed over the insulating layer and patterned to form an active layer of the TFT.
  • the active layer is disposed over the insulating layer and includes a first pattern corresponding to the gate.
  • the active layer can be prepared, for example, by photolithography, by designing the mask as a pattern corresponding to the active layer, and removing the active layer in other regions by, for example, photolithography, thereby obtaining a first portion including the gate electrode.
  • a pattern and an active layer of the second pattern at least partially overlapping the storage electrode line in the thickness direction of the substrate.
  • the material for forming the active layer may be, for example, amorphous silicon, polycrystalline silicon, an oxide semiconductor, or other suitable material.
  • the active layer formed includes, for example, at least a first pattern as a channel of the TFT and a second pattern at least partially overlapping the storage electrode line in the thickness direction of the substrate.
  • the pattern on the mask includes at least a portion corresponding to the first pattern and the second pattern described above. As described above, the first pattern and the second pattern may be connected to each other or separated from each other, for example.
  • a metal layer is further formed on the substrate on which the active layer is formed.
  • the material of the metal layer can be, for example, aluminum, aluminum alloy, copper or other suitable material.
  • the method of forming the metal layer may be, for example, CVD or sputtering.
  • a photolithography process is performed using a mask having a source, a drain, and a data line pattern to pattern the metal layer, thereby forming a data line crossing the gate line and the storage electrode line, and a source spaced apart from each other over the active layer. , drain.
  • a structure in which a passivation layer, a passivation layer via, or the like is further formed on the source, the drain, and the data line may be formed.
  • a transparent conductive layer for example, ITO
  • photolithography is performed through a mask to obtain an array substrate structure of one embodiment of the present disclosure.
  • the mask pattern or the photolithography step may be changed to perform photolithography, and details are not described herein.
  • Another aspect of the present disclosure provides a display device including the array substrate as described above.
  • An example of the display device is a liquid crystal display device in which an array substrate and a counter substrate are opposed to each other to form a liquid crystal cell in which a liquid crystal material is filled.
  • the opposite substrate is, for example, a color filter substrate.
  • the pixel electrode of each pixel unit of the array substrate is used to apply an electric field to control the degree of rotation of the liquid crystal material to perform a display operation.
  • the liquid crystal display device further includes a backlight that provides backlighting for the array substrate.
  • OLED organic electroluminescence display device
  • an organic light emitting material stack is formed on an array substrate, and a pixel electrode of each pixel unit serves as an anode or The cathode is used to drive the organic luminescent material to emit light for display operation.
  • Still another example of the display device is an electronic paper display device in which an electronic ink layer is formed on an array substrate, and a pixel electrode of each pixel unit serves as a voltage for applying a charged microparticle moving in the driving electronic ink to perform a display operation .
  • the terms “mounted,” “connected,” and “connected” are used in a broad sense, and may be, for example, a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection, It can also be an electrical connection; it can be directly connected, or it can be connected indirectly through an intermediate medium, which can be the internal connection of two components.
  • the specific meanings of the above terms in the present disclosure can be understood by those skilled in the art on a case-by-case basis.

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Abstract

一种阵列基板及显示装置。阵列基板包括衬底基板(10)和在所述衬底基板（10）上设置的栅极金属层、有源层（106）和源漏金属层；所述栅极金属层包括栅线(102)和与所述栅线（102）平行延伸的存储电极线(100)；所述有源层(106)包括作为薄膜晶体管(TFT)沟道区域的第一图案和与所述存储电极线(100)在所述衬底基板(10)的厚度方向上至少部分重叠的第二图案，或者所述源漏金属层包括数据线图案和与所述存储电极线（100）在所述基板（10）的厚度方向上至少部分重叠的金属层图案(110)。该阵列基板可以获得较大的存储电容，从而提高显示装置的显示效果。

Description

阵列基板及显示装置 技术领域
本公开的实施例涉及一种阵列基板及显示装置。
背景技术
显示装置的显示模式包括扭曲向列型(TN)、垂直配向(VA)、面内转换(IPS)和边缘场转换(FFS)等。像素结构通常根据不同的显示模式采用不同的存储电容结构。例如，TN和VA模式通常采用公共电极线与像素电极之间形成存储电容。IPS和FFS通常采用在公共电极和像素电极之间形成存储电容。存储电容的结构关系像素电压的稳定性，因此直接影响显示屏的品质和良率。
发明内容
针对上述问题，本公开的至少一个实施例涉及一种阵列基板和显示装置，用于降低显示装置的串扰和显示不良。
本公开的一个方面提供了一种阵列基板，包括衬底基板和在所述衬底基板上设置的栅极金属层、有源层和源漏金属层；所述栅极金属层包括栅线和与所述栅线平行延伸的存储电极线；所述有源层包括作为TFT沟道区域的第一图案和与所述存储电极线在所述基板的厚度方向上至少部分重叠的第二图案，或者所述源漏金属层包括数据线图案和与所述存储电极线在所述基板的厚度方向上至少部分重叠的金属层图案。
在一个实施例中，例如，所述有源层包括作为TFT沟道区域的第一图案和与所述存储电极线在所述基板的厚度方向上至少部分重叠的第二图案，并且所述源漏金属层包括数据线图案和与所述存储电极线在所述基板的厚度方向上至少部分重叠的金属层图案。
在一个实施例中，例如，所述有源层设置于所述衬底基板和所述栅极金属层之间。
在一个实施例中，例如，所述栅极金属层设置于所述衬底基板和所述有 源层之间。
在一个实施例中，例如，所述第二图案与所述第一图案连接。
在一个实施例中，例如，所述第二图案包括连接部和与所述连接部连接的重叠部；所述连接部与所述第一图案连接，所述重叠部与所述存储电极线在所述基板的厚度方向上重叠。
在一个实施例中，例如，所述重叠部设置于所述存储电极线与所述数据线的交叉位置。
在一个实施例中，例如，所述连接部与所述数据线的延伸方向相同，且所述连接部在所述衬底基板的第一主表面的正投影位于所述数据线在所述衬底基板的第一主表面的正投影之内。
在一个实施例中，例如，在所述数据线的宽度方向上，所述重叠部的尺寸大于所述连接部的尺寸。
在一个实施例中，例如，所述重叠部为板状结构。
在一个实施例中，例如，所述存储电极线在与所述数据线交叉的位置包括加宽部。
在一个实施例中，例如，所述加宽部在所述衬底基板的第一主表面上的正投影与所述重叠部在所述衬底基板的第一主表面上的正投影重合。
在一个实施例中，例如，所述金属层图案设置于所述存储电极线和所述数据线的交叉位置。
在一个实施例中，例如，所述金属层图案与所述数据线为一体结构。
在一个实施例中，例如，所述金属层图案为板状结构。
在一个实施例中，例如，所述金属层图案在所述数据线宽度方向上的尺寸大于所述数据线的宽度。
在一个实施例中，例如，所述金属层图案在所述存储电极线宽度方向上的尺寸不大于所述存储电极线的宽度。
在一个实施例中，例如，所述存储电极线在与所述数据线交叉的位置包括加宽部。
在一个实施例中，例如，所述加宽部在所述衬底基板的第一主表面上的正投影与所述金属层图案在所述衬底基板的第一主表面上的正投影重合。
本公开的另一个方面提供了一种显示装置，包括如上所述的阵列基板。 附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为衬底基板的结构示意图；
图2a为本公开实施例的阵列基板通过有源层与存储电极线形成存储电容的俯视示意图；
图2b为本公开实施例的有源层结构示意图；
图3a为本公开实施例的有源层的结构示意图；
图3b为包括图3a的有源层结构的阵列基板的俯视示意图；
图4a为本公开实施例的存储电极线包括加宽部的示意图；
图4b为本公开实施例的存储电极线包括加宽部且该加宽部与有源层形成存储电容的结构示意图；
图5为本公开实施例的阵列基板通过源漏金属层与存储电极线形成存储电容的俯视示意图；
图6为本公开的金属层图案与数据线在数据线宽度方向上的尺寸关系示意图；
图7为本公开实施例的金属层图案与存储电极线在存储电极线宽度方向上的尺寸关系示意图。
图8为本公开的实施例包括加宽部的存储电极线的示意图；
图9为本公开实施例的存储电极线的加宽部与金属层图案形成存储电容的示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
液晶显示装置通常包括背光模组、下基板、上基板以及***驱动电路等 部分。下基板通常为阵列基板，上基板通常为彩膜基板。阵列基板进一步包括衬底基板(通常为玻璃基板)以及设置于衬底基板之上的栅线、有源层、数据线、公共电极线以及像素电极等结构。图1为衬底基板的结构示意图。参照图1，衬底基板10包括彼此相对的第一主表面11和第二主表面12。例如，栅线、有源层、数据线、公共电极线以及像素电极等结构设置在衬底基板10的第一主表面11一侧。
在液晶显示装置中，通常采用薄膜晶体管(TFT)作为控制像素电极上施加的数据信号的开关。TFT包括源极、漏极、栅极以及将源漏极分开的沟道区域。TFT的沟道区域的特点是在被施加一定的导通电压时可将TFT的源漏极导通。例如，沟道区域可以由半导体材料(例如非晶硅、多晶硅、氧化物半导体等)制备。例如，TFT的连接方式如下：栅极与栅线连接以接收栅线施加的导通电压信号，导通电压信号通过TFT的栅极施加至沟道区域，以控制该沟道区域的导通与截止；源极与数据线连接，以接收来自数据线的电压信号；漏极与像素电极连接，以在TFT的源漏极通过沟道区域导通后，向像素电极充电。也就是说，在TFT的源漏极导通后，数据线上的信号即可通过TFT的源漏极施加至像素电极，从而可用于控制液晶分子的偏转。
在液晶显示装置中，由于像素电极的充电时间远远小于液晶分子的响应时间，因此，液晶分子的偏转一般是在像素电极充电结束后的保持时间内进行并完成的。也就是说，在像素电极结束充电后，需要一个稳定的充电电压来持续驱动液晶分子转动。承载这个持续充电电压的就是像素负荷电容，该负荷电容主要包括液晶电容和存储电容。存储电容的作用例如是保持像素电压的稳定，提高显示品质。在不同的显示模式中，存储电容的形成方式不同。例如，TN和VA模式通常采用公共电极线与像素电极之间形成存储电容；IPS、FFS和ADS通常采用在公共电极和像素电极之间形成存储电容。存储电容的结构将直接影响到显示屏的品质和良率。
本公开的实施例提供了一种阵列基板，包括衬底基板和在所述衬底基板上设置的栅极金属层、有源层和源漏金属层；其中，栅极金属层包括栅线和与所述栅线平行延伸的存储电极线；有源层包括作为TFT沟道区域的第一图案和与存储电极线在基板的厚度方向上至少部分重叠的第二图案，或者源漏金属层包括数据线图案和与存储电极线在所述基板的厚度方向上至少部分重 叠的金属层图案。本公开实施例的阵列基板可以获得较大的存储电容，提高显示装置的显示品质。
需要说明的是，本公开的实施例通过存储电极线(也可称为公共电极线，以下称为存储电极线)与源漏金属层和/或有源层形成存储电容。如果源漏金属层与存储电极线形成存储电容结构，则金属层图案例如可以是与数据线直接相连的一体结构。该金属层图案例如还可以是与数据线彼此不相连，即源漏金属层包括在数据线之外单独设置与存储电极线在阵列基板厚度方向上彼此重叠的金属层图案。如果有源层与存储电极线形成存储电容结构，则有源层至少包括两个图案部分。其中一个图案部分例如是作为TFT沟道区域的图案；另一个图案部分例如至少包括与存储电极线在阵列基板厚度方向上彼此重叠的部分，以形成存储电容。同样，有源层的上述两个图案例如可以彼此连接或者不连接。
在一个实施例中，有源层包括作为TFT沟道区域的第一图案和与存储电极线在基板的厚度方向上至少部分重叠的第二图案。
图2a为本公开实施例的阵列基板通过有源层与存储电极线形成存储电容的俯视示意图。图2b为本公开实施例的有源层结构示意图。
参照图2a-2b，阵列基板包括衬底基板和在该衬底基板上设置的栅极金属层、有源层(图2a和图2b中带阴影线的图案)、源漏金属层。栅极金属层包括栅线102(以及从栅线分出来的栅极112)和与该栅线平行延伸的存储电极线100。栅极金属层的上方设置有源层(底栅结构)，有源层106包括作为TFT沟道区域的第一图案，和包括与存储电极线在衬底基板厚度方向上至少部分彼此重叠的第二图案。这里需要指出，有源层位于像素电极层之下的部分在图2a中以低可视度示意；有源层在数据线正下方的部分不可见，但为了清楚的示意有源层在阵列基板中的设置方式，故在图2a中也对有源层的该部分采用了低可视处理。类似地，下面的图3b和图5中也对有源层进行了相同处理，在此一并指出。参照图2b，有源层在虚线所包围的部分例如为第二图案，有源层在虚线之外的部分例如为第一图案。结合参考图2a，该第一图案的一部分(位于栅极上方的部分)作为TFT沟道区域，该第二图案在基板厚度方向上与存储电极线100至少部分重叠。例如第二图案中的基本上为正方形的部分与存储电极线100在基板厚度方向上彼此重叠，以形成存储电 容(即图2a中虚线所包围的部分)。
需要说明的是，有源层之上还进一步设置有源漏金属层。参照图2a，源漏金属层包括与栅线102交叉的数据线108，并且形成TFT的源极118和漏极119。可在源漏金属层之上设置像素电极109。如上所述，TFT的源极118连接数据线108，漏极119例如通过形成在绝缘层中的过孔(图中未示出)连接像素电极109，栅极连接栅线102。
在该实施例中，例如，有源层可以设置于衬底基板和栅极金属层之间。也就是说，本公开实施例阵列基板可以为顶栅结构。对于顶栅结构，在衬底基板上首先形成至少包括第一图案和第二图案的有源层，然后在有源层上形成栅绝缘层，在栅绝缘层之上形成栅极金属层。如上所述，栅极金属层包括平行延伸的栅线和存储电极线。上述第二图案与存储电极线在基板厚度方向上至少部分重叠，以形成存储电容。
在该实施例中，例如，所述栅极金属层设置于所述衬底基板和所述有源层之间。也就是说，本公开的实施例的阵列基板可以为底栅结构。例如，图2a所示即为具有底栅结构的阵列基板的实施例。对于底栅结构，在衬底基板上首先形成包括平行延伸的栅线和存储电极线的栅极金属层，然后在栅极金属层之上形成栅绝缘层，在栅绝缘层之上形成至少包括第一图案和第二图案有源层。上述第二图案与存储电极线在基板厚度方向上至少部分重叠，以形成存储电容。
在该实施例中，例如，第二图案与第一图案连接。图3a示出了本公开实施例有源层的一种结构。图3b为包括图3a所示有源层结构的阵列基板的俯视示意图。参照图3a，有源层包括第一图案(未包含在图中虚线之内的部分)和第二图案(包含在图中虚线范围之内的部分)。第二图案与第一图案直接相连，也就是说，第二图案与第一图案为一体结构。例如，第二图案也可以与第二图案彼此分开，即在有源层上形成两个彼此分离的图案。
在该实施例中，例如，第二图案包括连接部和与连接部连接的重叠部；连接部与所述第一图案连接，重叠部与存储电极线在基板的厚度方向上重叠。继续参照图3a，第二图案(图中虚线包围的部分)包括连接部1062和重叠部1063。连接部1062连接到第一图案，重叠部1063用于与存储电极线100在基板厚度方向上彼此重叠，以形成存储电容。
图3a所示的第一图案包括TFT的沟道区域1061。参照图3b，第一图案的沟道区域1061在接收到来自栅极112的导通电压时，沟道区域1061导通。数据线的电压信号从TFT的源极通过沟道区域1061传输到TFT的漏极，以对像素电极充电。需要说明的是，有源层的第一图案的形状并不限于图3a所示的结构，例如该第一图案也可以为其它形状。另外，重叠部例如可以为长方形、正方形、圆形、椭圆形或者其它规则或者不规则的板状结构。图3a中所示的具体结构并非构成对本公开的限制。
在该实施例中，例如，重叠部设置于存储电极线与数据线的交叉位置。参照图3b，重叠部1063设置于存储电极线100与数据线108的交叉位置。采用在存储电极线与数据线的交叉位置设置重叠部，可以防止降低开口率。
在该实施例中，例如，连接部与数据线的延伸方向相同，且连接部在衬底基板的第一主表面的正投影位于数据线在该衬底基板的第一主表面的正投影之内。继续参照图3b，连接部1062与数据线108的延伸方向相同，且连接部1062在衬底基板的第一主表面的正投影位于数据线108在该衬底基板的第一主表面的正投影之内。通过设置连接部的延伸方向及尺寸，可以避免降低显示装置的开口率。
在该实施例中，例如，在数据线108的宽度方向上，重叠部1063的尺寸大于连接部1062的尺寸，以获得较大的存储电容。
在该实施例中，例如，所述重叠部为板状结构。一方面，存储电容的大小决定于彼此相对的金属板的正对面积；另一方面取决于金属板之间的距离。通过将重叠部设置为板状，可以增大重叠部与存储电极线对应位置的正对面积，进而增大存储电容，以有效防止闪烁和串扰。这里所说的板状结构的形状例如为长方形、正方形、圆形以及其它规则或不规则的形状。
在该实施例中，例如，所述存储电极线在与所述数据线交叉的位置包括加宽部。图4a为本公开实施例的存储电极线包括加宽部的示意图。图4b为本公开的实施例包括加宽部的存储电极线与有源层形成存储电容的结构示意图。
参照图4a，例如，存储电极线100在与数据线108交叉的位置均设置加宽部1001(图中仅示出一个加宽部)。该加宽部1001的作用是增大与重叠部1063的正对面积，以增大存储电容，提高显示效果。例如，进一步地，可 以将该加宽部1001设置为长方形、正方形、圆形或其它形状。例如，加宽部1001设置为具有与前文所述的有源层的重叠部1063相同的形状，以提高存储电容。例如，加宽部1001与重叠部1063的形状和面积均相同，且彼此正对设置。参照图4b，例如，加宽部1001在衬底基板的第一主表面上的正投影与重叠部1063在该衬底基板的第一主表面上的正投影重合。通过限定加宽部和重叠部的形状和面积，可以有效利用重叠部以及加宽部的面积以获得较大的存储电容，提高显示装置的显示效果。
需要说明的是，一般来说，存储电极线的加宽部设置需要与上述重叠部配合。例如，如上文所述，通过将加宽部与重叠部设置为大小相等，形状相同，可以使加宽部与重叠部彼此正对的面积最大，进而获得较大的存储电容。
在一个实施例中，源漏金属层包括数据线图案和与存储电极线在所述基板的厚度方向上至少部分重叠的金属层图案。
图5为本公开实施例的阵列基板通过源漏金属层与存储电极线形成存储电容的俯视示意图。参照图5，阵列基板包括衬底基板和在该阵列基板上设置的栅极金属层、有源层、源漏金属层。栅极金属层包括平行延伸的栅线102(以及栅极)和存储电极线100。有源层设置有TFT的沟道区。源漏金属层包括数据线图案以及与存储电极线100在基板厚度方向重叠的金属层图案110(即源漏金属层在图5中虚线包围的部分)。从而金属层图案110与存储电极线100形成存储电容。这种通过源漏金属层与存储电极线形成存储电容的方式，可以获得较大的存储电容，提高显示装置的显示效果。
在该实施例中，例如，有源层可以设置于衬底基板和栅极金属层之间。也就是说，阵列基板可以为顶栅结构。对于顶栅结构，在衬底基板上首先形成有源层，然后在有源层之上形成覆盖有源层的栅绝缘层，在栅绝缘层上形成栅极金属层。如上所述，栅极金属层包括平行延伸的栅线和存储电极线。之后，例如，在栅极金属层形成层间绝缘层，在层间绝缘层形成上述源漏金属层。源漏金属层应当至少包括数据线图案和上述金属层图案。
在该实施例中，例如，栅极金属层设置于衬底基板和有源层之间。也就是说，阵列基板可以为底栅结构。对于底栅结构，在衬底基板上首先形成包括平行延伸的栅线和存储电极线的栅极金属层，然后在栅极金属层之上形成栅绝缘层，在栅绝缘层上形成有源层。之后在有源层之上形成源漏金属层。 源漏金属层应当至少包括数据线图案和上述金属层图案。
需要说明的是，在该实施例中，有源层还可以包括作为TFT沟道区域的第一图案和与存储电极线在基板厚度方向至少部分重叠的第二图案。即有源层包括如前文所述的结构及相关变形结构。存储电极线同时与源漏金属层和有源层形成存储电容，可以进一步提高存储电容，从而更好的避免显示装置的串扰和显示不良。
在该实施例中，例如，金属层图案设置于存储电极线和数据线的交叉位置，防止降低开口率。继续参照图5，金属层图案110设置在存储电极线100与数据线108彼此交叉的位置。该金属层图案110例如与数据线108为一体结构，例如二者由同一个金属层通过构图工艺得到。例如，金属层图案110包括数据线的与存储电极线交叉的部分以及从数据线的该部分向数据线两侧凸出的部分。数据线与金属层图案采用一体的设置结构，可以避免降低显示装置的开口率。
在该实施例中，例如，金属层图案为板状结构。例如，金属层图案的形状可以为长方形、正方形或其它规则或不规则的形状。
在该实施例中，例如，金属层图案在数据线宽度方向上的尺寸大于数据线的宽度。图6为本公开实施例的金属层图案与数据线在数据线宽度方向上尺寸关系示意图。参照图6，数据线108上设置有金属层图案110，即图中阴影线所示的部分。如前所述，数据线108与该金属层图案110均设置于源漏金属层。该金属层图案110在数据线108的宽度方向上(如图6中箭头所示的方向)的尺寸大于数据线108的宽度。例如，如前文所述，该金属层图案110与该数据线108可以为一体结构，二者如由同一金属层通过构图工艺得到。通过使金属层图案的宽度大于数据线的宽度，可以获得较大的存储电容，防止显示装置的串扰和显示不良。
在该实施例中，例如，金属层图案在存储电极线的宽度方向上的尺寸不大于存储电极线的宽度。图7为本公开实施例的金属层图案与存储电极线在存储电极线宽度方向的尺寸关系示意图。参照图7，如前所述，数据线108与存储电极线100彼此交叉设置。金属层图案110设置于数据线108与存储电极线100的交叉位置。在存储电极线100的宽度方向上(即如图7中箭头所示的方向)，金属层图案110的尺寸不大于存储电极线100的宽度，例如 可以等于或者略小于存储电极线100的宽度。以防止降低显示装置的开口率。
在该实施例中，例如，存储电极线在与数据线交叉的位置包括加宽部。图8为本公开实施例的存储电极线包括加宽部的示意图。图9为本公开实施例的存储电极线的加宽部与金属层图案形成存储电容的示意图。参照图8，例如，存储电极线100在与数据线108交叉的位置(图中仅示意出一个交叉位置)均设置加宽部1001。该加宽部1001的作用是增大与例如金属层图案的正对面积，以增大存储电容。例如，进一步的，可以将该加宽部1001设置为长方形或正方形或其它规则或不规则的形状。例如，与前文所述的金属层图案相同的形状，提高存储电容。进一步的，参照图9，加宽部1001在衬底基板的第一主表面11上的正投影与金属层图案110在衬底基板的第一主表面11上的正投影重合，进一步增大存储电容。通过在存储电极线与数据线交叉的位置设置加宽部，可以获得较大的存储电容，从而提高显示装置的显示效果。
需要说明，一般来说，存储电极线设置的加宽部需要与上述金属层图案配合设置，以获得较大的存储电容。例如，如上文所述，将加宽部与金属层图案设置为大小相等，形状相同，可以使加宽部与金属层图案的正对面积最大，进而获得较大的存储电容。
以上具体实施例之间可相互组合，并不超出本公开公开的范围，且能够带来更好的组合效果。
针对上述实施例的阵列基板，本公开的实施例提供了阵列基板制备方法，但本公开的阵列基板制备方法不限于以下方法。
下面仅以制备有源层包括作为TFT沟道的第一图案和与存储电极线在基板厚度方向上至少部分重叠的第二图案，且具有顶栅结构的阵列基板为例说明本公开的阵列基板的制备方法，例如具体如下：
在基板上通过例如溅射的方法形成一层金属层，然后采用第一掩模进行蚀刻得到栅线和与所述栅线连接的栅极，以及与栅线和栅极同时形成且与栅线平行延伸的存储电极线。该金属层例如可以包括铝、铝合金，以及铜或其它适合材料。进行第一次掩模工艺以进行构图后，阵列基板上即形成有栅线、与栅线连接的栅极和与栅线平行延伸的存储电极线。
在形成有栅线和栅极的阵列基板上，形成一层绝缘层以作为栅绝缘层。 随后在绝缘层之上形成一层半导体层，并通过构图工艺以形成TFT的有源层。该有源层设置于绝缘层之上，且包括与栅极对应的第一图案。有源层的制备例如可以采用光刻法，将掩模设计为与有源层对应的图案，并通过例如光刻方法去除其它区域中的有源层，从而得到包括与栅极对应的第一图案和与存储电极线在基板厚度方向上至少部分重叠的第二图案的有源层。用于形成有源层的材料例如可以为非晶硅、多晶硅、氧化物半导体或其它适合的材料。
需要说明的是，形成的有源层例如至少包括作为TFT沟道的第一图案和与存储电极线在基板厚度方向上至少部分重叠的第二图案。掩模上的图案至少包括与上述第一图案和第二图案对应的部分。如上所述，第一图案和第二图案例如可以彼此连接或者彼此分离。
此后，在形成有有源层的基板上，进一步形成一层金属层。该金属层的材料例如可以为铝、铝合金、铜或其它适合材料。形成金属层的方法例如可以为CVD或溅射法。采用具有源极、漏极以及数据线图案的掩模进行光刻工艺以对该金属层构图，进而在有源层的上方形成与栅线和存储电极线交叉的数据线、彼此间隔的源极、漏极。
之后，可以形成进一步在源极、漏极、数据线之上形成钝化层、钝化层过孔等结构。
随后，在钝化层上方继续覆盖一层透明导电层(例如ITO)，并通过掩模进行光刻，获得本公开的一个实施例的阵列基板结构。
对于本公开上述其它的实施例，可相应的改变掩模图案或者光刻步骤进行光刻，在此不再赘述。
本公开的另一个方面提供了一种显示装置，包括如上所述的阵列基板。
该显示装置的一个示例为液晶显示装置，其中，阵列基板与对置基板彼此对置以形成液晶盒，在液晶盒中填充有液晶材料。该对置基板例如为彩膜基板。阵列基板的每个像素单元的像素电极用于施加电场对液晶材料的旋转的程度进行控制从而进行显示操作。在一些示例中，该液晶显示装置还包括为阵列基板提供背光的背光源。
该显示装置的另一个示例为有机电致发光显示装置(OLED)，其中，阵列基板上形成有有机发光材料叠层，每个像素单元的像素电极作为阳极或 阴极用于驱动有机发光材料发光以进行显示操作。
该显示装置的再一个示例为电子纸显示装置，其中，阵列基板上形成有电子墨水层，每个像素单元的像素电极作为用于施加驱动电子墨水中的带电微颗粒移动以进行显示操作的电压。
在本文中，诸如“第一”、“第二”等术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不要求或者暗示这些实体或操作之间存在任何关系或者顺序。术语“包括”、“包含”这些表述为开放式的，并不排除所包括的过程、方法、物品，还存在其他要素。还需要说明的是，“上”、“下”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本公开中的具体含义。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。
本申请要求于2016年1月27日提交的名称为“阵列基板及显示装置”的中国专利申请No.201620080097.6的优先权，其全文通过引用合并于本文。

Claims (20)

  1. 一种阵列基板，包括衬底基板和在所述衬底基板上设置的栅极金属层、有源层和源漏金属层；
    其中，所述栅极金属层包括栅线和与所述栅线平行延伸的存储电极线，所述有源层包括作为薄膜晶体管(TFT)沟道区域的第一图案和与所述存储电极线在所述基板的厚度方向上至少部分重叠的第二图案，或者所述源漏金属层包括数据线图案和与所述存储电极线在所述基板的厚度方向上至少部分重叠的金属层图案。
  2. 根据权利要求1所述的阵列基板，其中，所述有源层包括作为TFT沟道区域的所述第一图案和与所述存储电极线在所述基板的厚度方向上至少部分重叠的所述第二图案，并且所述源漏金属层包括数据线图案和与所述存储电极线在所述基板的厚度方向上至少部分重叠的所述金属层图案。
  3. 根据权利要求1或2所述的阵列基板，其中，所述有源层设置于所述衬底基板和所述栅极金属层之间。
  4. 根据权利要求1或2所述的阵列基板，其中，所述栅极金属层设置于所述衬底基板和所述有源层之间。
  5. 根据权利要求1所述的阵列基板，其中，所述第二图案与所述第一图案连接。
  6. 根据权利要求5所述的阵列基板，其中，所述第二图案包括连接部和与所述连接部连接的重叠部；所述连接部与所述第一图案连接，所述重叠部与所述存储电极线在所述基板的厚度方向上重叠。
  7. 根据权利要求6所述的阵列基板，其中，所述重叠部设置于所述存储电极线与所述数据线的交叉位置。
  8. 根据权利要求7所述的阵列基板，其中，所述连接部与所述数据线的延伸方向相同，且所述连接部在所述衬底基板的第一主表面的正投影位于所述数据线在所述衬底基板的第一主表面的正投影之内。
  9. 根据权利要求8所述的阵列基板，其中，在所述数据线的宽度方向上，所述重叠部的尺寸大于所述连接部的尺寸。
  10. 根据权利要求6-9任意一项所述的阵列基板，其中，所述重叠部为 板状结构。
  11. 根据权利要求6-9任意一项所述的阵列基板，其中，所述存储电极线在与所述数据线交叉的位置包括加宽部。
  12. 根据权利要求11所述的阵列基板，其中，所述加宽部在所述衬底基板的第一主表面上的正投影与所述重叠部在所述衬底基板的第一主表面上的正投影重合。
  13. 根据权利要求1以及权利要求6-9任意一项所述的阵列基板，其中，所述金属层图案设置于所述存储电极线和所述数据线的交叉位置。
  14. 根据权利要求13所述的阵列基板，其中，所述金属层图案与所述数据线为一体结构。
  15. 根据权利要求14所述的阵列基板，其中，所述金属层图案为板状结构。
  16. 根据权利要求14所述的阵列基板，其中，所述金属层图案在所述数据线宽度方向上的尺寸大于所述数据线的宽度。
  17. 根据权利要求16所述的阵列基板，其中，所述金属层图案在所述存储电极线宽度方向上的尺寸不大于所述存储电极线的宽度。
  18. 根据权利要求13所述的阵列基板，其中，所述存储电极线在与所述数据线交叉的位置包括加宽部。
  19. 根据权利要求18所述的阵列基板，其中，所述加宽部在所述衬底基板的第一主表面上的正投影与所述金属层图案在所述衬底基板的第一主表面上的正投影重合。
  20. 一种显示装置，包括如权利要求1-19任意一项所述的阵列基板。
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