WO2017029767A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- WO2017029767A1 WO2017029767A1 PCT/JP2015/073444 JP2015073444W WO2017029767A1 WO 2017029767 A1 WO2017029767 A1 WO 2017029767A1 JP 2015073444 W JP2015073444 W JP 2015073444W WO 2017029767 A1 WO2017029767 A1 WO 2017029767A1
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- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
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- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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Definitions
- the present invention relates to a semiconductor device, for example, a technique effective when applied to a semiconductor device in which a plurality of semiconductor components such as a semiconductor chip are electrically connected to each other via an interposer.
- Patent Document 1 describes an embodiment in which a wiring film is attached to a chip mounting surface of a wiring board, and a plurality of semiconductor chips are arranged to face each other on the wiring film.
- FIG. 1 of Non-Patent Document 1 describes a semiconductor device in which a first semiconductor component and a second semiconductor component are electrically connected via a wiring board having a plurality of through-hole wirings. ing.
- a semiconductor device includes a first semiconductor component and a second semiconductor component that are electrically connected to each other via an interposer.
- the interposer includes a plurality of first signal wiring paths and a plurality of second signal wiring paths whose path distance is shorter than each of the plurality of first signal wiring paths.
- the first semiconductor component includes a first electrode, a second electrode, and a third electrode, which are sequentially arranged along the first direction.
- the second semiconductor component includes a fourth electrode, a fifth electrode, and a sixth electrode, which are sequentially arranged along the first direction.
- the first electrode is connected to the fourth electrode through the first signal wiring path
- the second electrode is connected to the fifth electrode through the first signal wiring path.
- Three electrodes are connected to the sixth electrode through the first signal wiring path.
- the reliability of the semiconductor device can be improved.
- FIG. 2 is a bottom view of the semiconductor device shown in FIG. 1.
- FIG. 2 is a cross-sectional view taken along line AA in FIG.
- FIG. 4 is an explanatory diagram showing a circuit configuration example when the semiconductor device shown in FIGS. 1 to 3 is mounted on a mounting substrate.
- FIG. 4 is an enlarged sectional view of a part of a peripheral edge portion of the interposer shown in FIG. 3.
- FIG. 5 is an explanatory diagram schematically illustrating an example of a layout of a signal transmission path that connects the logic chip and the memory chip illustrated in FIG. 4. It is explanatory drawing which shows typically the example of the planar layout of the some electrode shown in FIG.
- FIG. 8 is an explanatory view schematically showing an example of a wiring layout for electrically connecting a plurality of through-hole wirings shown in FIG.
- FIG. 9 is a cross-sectional view schematically showing main parts of a semiconductor device which is a modification example of the semiconductor device shown in FIGS. It is explanatory drawing which shows typically the example of a layout of the signal transmission path
- FIG. 5 is an explanatory diagram illustrating a circuit configuration example when a semiconductor device that is a modification example of the semiconductor device illustrated in FIG. 4 is mounted on a mounting substrate;
- FIG. 21 is an explanatory diagram schematically illustrating an example of a method for connecting a power supply wiring and a reference potential wiring in the circuit configuration illustrated in FIG. 20. It is explanatory drawing which shows the modification with respect to FIG.
- FIG. 22 is an essential part enlarged cross-sectional view showing an arrangement example of electrodes of the logic chip shown in FIG. 21.
- FIG. 23 is an essential part enlarged cross-sectional view showing an arrangement example of electrodes of the logic chip shown in FIG. 22; It is sectional drawing which shows the modification with respect to FIG.
- FIG. 26 is an explanatory diagram showing an outline of a manufacturing process of the semiconductor device described with reference to FIGS. 1 to 25; It is explanatory drawing which shows the example of examination with respect to FIG.
- X consisting of A is an element other than A unless specifically stated otherwise and clearly not in context. It does not exclude things that contain.
- the component it means “X containing A as a main component”.
- silicon member is not limited to pure silicon, but includes a SiGe (silicon-germanium) alloy, other multi-component alloys containing silicon as a main component, and other additives. Needless to say, it is also included.
- gold plating, Cu layer, nickel / plating, etc. unless otherwise specified, not only pure materials but also members mainly composed of gold, Cu, nickel, etc. Shall be included.
- hatching or the like may be omitted even in a cross section when it becomes complicated or when it is clearly distinguished from a gap.
- the contour line of the background may be omitted even if the hole is planarly closed.
- hatching or a dot pattern may be added in order to clearly indicate that it is not a void or to clearly indicate the boundary of a region.
- One aspect of the semiconductor package is a semiconductor device in which a semiconductor component such as a semiconductor chip or a semiconductor chip stacked body in which a plurality of semiconductor chips are stacked is mounted on a wiring board.
- the electrodes of semiconductor components have a tendency to increase in density.
- a semiconductor component in which a large number of electrodes are arranged at high density on a wiring board a plurality of electrodes provided in the semiconductor component and a plurality of terminals provided in the wiring board are arranged to face each other, and a conductive member such as solder is provided. In many cases, it is mounted by a so-called flip-chip connection method in which the terminals are electrically connected via each other.
- a semiconductor device that is described by way of example includes a memory chip (second semiconductor component) in which a memory circuit is formed, and a control circuit and an arithmetic processing circuit that control the operation of the memory circuit of the memory chip. And a logic chip (first semiconductor component) formed thereon.
- a semiconductor device in which a system is formed in one package in this way is called a SiP (System in Package).
- a semiconductor device in which a plurality of semiconductor chips are mounted in one package is called an MCM (Multi Chip Module).
- the inventor of the present application is examining a technique for mounting a plurality of semiconductor components on an interposer in a SiP type semiconductor device.
- a memory chip and a logic chip included in a semiconductor device described in the following description are electrically connected via an interposer, and a system is formed in one package.
- signal transmission may be performed between a plurality of semiconductor components mounted in one package.
- the plurality of signal transmission paths connecting the plurality of semiconductor components include many signal transmission paths that may not be connected to the outside of the semiconductor package as long as the plurality of semiconductor components are connected.
- the wiring arrangement density of the wiring board can be reduced. For this reason, the structure of the wiring board can be simplified.
- FIG. 1 is a top view of the semiconductor device of the present embodiment
- FIG. 2 is a bottom view of the semiconductor device shown in FIG.
- FIG. 3 is a sectional view taken along line AA in FIG.
- FIG. 4 is an explanatory diagram showing a circuit configuration example when the semiconductor device shown in FIGS. 1 to 3 is mounted on a mounting substrate.
- the number of terminals is reduced for ease of viewing.
- the number of terminals includes various modifications in addition to the modes shown in FIGS.
- the number of solder balls 11 shown in FIG. 2 may be larger than the number shown in FIG.
- the present application describes a technique for solving a problem that occurs when the number of wiring paths that electrically connect a plurality of semiconductor chips 30 is increased. Therefore, the number of terminals of the plurality of semiconductor chips 30 shown in FIG. 3 is, for example, a number exceeding 1000 each.
- each of the wiring board 10 and the interposer 20A shown in FIG. 3 has a plurality of wiring layers.
- a part of a plurality of wirings formed in each wiring layer is schematically shown for easy viewing.
- a typical transmission path among the many transmission paths included in the semiconductor device PKG1 is exemplarily illustrated.
- the semiconductor device PKG1 of the present embodiment is mounted on a wiring board (package board) 10, an interposer (relay board) 20A mounted on the wiring board 10, and an interposer 20A.
- a plurality of semiconductor chips (semiconductor components) 30 are provided. The plurality of semiconductor chips 30 are mounted side by side on the interposer 20A.
- the semiconductor component mounted on the interposer 20A is not limited to the semiconductor chip 30, and there are various modifications.
- a semiconductor chip stack semiconductor component
- a semiconductor package semiconductor component
- a semiconductor chip semiconductor component
- a semiconductor chip semiconductor package
- a semiconductor chip is mounted on a wiring material such as a wiring board is mounted on the interposer 20A.
- Each of the semiconductor chips 30 or a part of the plurality of semiconductor chips 30 may be replaced.
- one of the plurality of semiconductor components is a memory chip 30A including a memory circuit, and the other is the above-described memory.
- An example of a logic chip 30B including a control circuit that controls the circuit will be described.
- a stacked body in which a plurality of memory chips are stacked may be mounted on the interposer 20A.
- a stacked body in which a plurality of memory chips and a controller chip including a control circuit for controlling operations of the plurality of memory chips is stacked is mounted on the interposer 20A.
- the stacking order is not particularly limited.
- one or a plurality of memory chips (and a controller chip) are electrically connected to a wiring board (package board) (not shown), and a plurality of external terminals are connected to the wiring board.
- a semiconductor package in which is formed may be mounted on the interposer 20A.
- a plurality of solder balls (external terminals) 11 that are external terminals of the semiconductor device PKG1 are arranged in a matrix (array shape) on the lower surface 10b of the wiring board 10 that is the mounting surface of the semiconductor device PKG1. , In a matrix).
- Each of the plurality of solder balls 11 is connected to a land (external terminal) 12 (see FIG. 3).
- a semiconductor device in which a plurality of external terminals (solder balls 11 and lands 12) are arranged in a matrix on the mounting surface side like the semiconductor device PKG1 is referred to as an area array type semiconductor device. Since the area array type semiconductor device PKG1 can effectively use the mounting surface (lower surface 10b) side of the wiring substrate 10 as a space for arranging external terminals, the mounting area of the semiconductor device PKG1 is increased even if the number of external terminals increases. It is preferable at the point which can suppress increase of this. In other words, the semiconductor device PKG1 in which the number of external terminals increases with higher functionality and higher integration can be mounted in a space-saving manner.
- the wiring board 10 includes an upper surface (surface, chip mounting surface) 10t on which a plurality of semiconductor chips 30 are mounted via an interposer 20A, and a lower surface (surface, mounting) opposite to the upper surface 10t. Surface) 10b, and a side surface 10s disposed between the upper surface 10t and the lower surface 10b. Further, the wiring board 10 has a rectangular outer shape in plan view as shown in FIG.
- the interposer 20A includes an upper surface (surface, chip mounting surface) 20t on which a plurality of semiconductor chips (semiconductor components) 30 are mounted, and a lower surface (surface, mounting surface) opposite to the upper surface 20t. 20b, and a side surface 20s disposed between the upper surface 20t and the lower surface 20b. Further, the interposer 20A has a quadrangular outer shape in plan view as shown in FIG.
- each of the plurality of semiconductor chips 30 includes a front surface (main surface, upper surface) 30t, a rear surface (main surface, lower surface) 30b opposite to the front surface 30t, and a front surface 30t and a rear surface 30b. Side surface 30s located between the two.
- Each of the plurality of semiconductor chips 30 has a quadrangular outer shape in plan view as shown in FIG.
- one of the plurality of semiconductor chips 30 is a memory chip 30A including a memory circuit
- the other is a logic chip 30B including a control circuit that controls the memory circuit.
- each of the memory chip 30A and the logic chip 30B is directly connected to the interposer 20A. In other words, no substrate or other chip component is inserted between the memory chip 30A and the interposer 20A and between the logic chip 30B and the interposer 20A.
- the semiconductor device PKG1 of the present embodiment includes a system that operates by transmitting signals between the logic chip 30B and the memory chip 30A.
- the memory chip 30A includes a main memory circuit (memory circuit) that stores data communicated with the logic chip 30B.
- the logic chip 30B includes a control circuit that controls the operation of the main memory circuit of the memory chip 30A.
- the logic chip 30B includes an arithmetic processing circuit that performs arithmetic processing on the input data signal.
- main circuits such as an arithmetic processing circuit and a control circuit are shown as a core circuit (main circuit) CORE1.
- the circuit included in the core circuit CORE1 may include circuits other than those described above.
- the logic chip 30B may be formed with an auxiliary storage circuit (storage circuit) having a storage capacity smaller than that of the main storage circuit of the memory chip 30A, such as a cache memory that temporarily stores data.
- the logic chip 30B is formed with an external interface circuit (input / output circuit, external input / output circuit) IF1 for inputting / outputting signals to / from the external device 40.
- a signal line SIG for transmitting a signal between the logic chip 30B and the external device 40 is connected to the external interface circuit IF1.
- the external interface circuit IF1 is also connected to the core circuit CORE1, and the core circuit CORE1 can transmit signals to the external device 40 via the external interface circuit IF1.
- the logic chip 30B is formed with an internal interface circuit (input / output circuit, internal input / output circuit) IF2 for inputting / outputting signals to / from an internal device (for example, the memory chip 30A).
- the internal interface circuit IF2 is connected to a data line (signal line) DQ for transmitting a data signal and a control signal line (signal line) CMD for transmitting a control data signal such as an address signal and a command signal.
- the data line DQ and the control signal line CMD are each connected to the internal interface circuit IF2 of the memory chip 30A.
- the logic chip 30B includes a power supply circuit DRV1 to which a potential for driving the core circuit CORE1 and the input / output circuit is supplied.
- a power supply line VD1 that supplies a power supply potential and a reference potential line VS1 that supplies a reference potential are connected to the power supply circuit DRV1.
- the potential for driving the core circuit CORE1 and the input / output circuit is supplied to each circuit from the power supply 50 provided outside the semiconductor device PKG1 via the power supply circuit DRV1.
- FIG. 4 shows an example in which the pair of power supply line VD1 and reference potential line VS1 are connected to the logic chip 30B, but the potential supplied to the logic chip 30B is not limited to the above two types.
- the power supply circuit DRV1 is supplied with a voltage for driving the external interface circuit IF1 of the logic chip 30B.
- the power supply circuit DRV1 is supplied with a voltage for driving the external interface power supply circuit and the core circuit CORE1 of the logic chip 30B.
- a power supply circuit may include an internal interface power supply circuit to which a voltage for driving the internal interface circuit IF2 of the logic chip 30B is supplied. In this case, a plurality of power supply lines VD1 that supply a plurality of different power supply potentials are connected to the logic chip 30B.
- the potential supplied to the reference potential line VS1 shown in FIG. 4 is, for example, a ground potential.
- the potential supplied to the reference potential line VS1 may be a potential other than the ground potential.
- SoC System on chip
- the memory chip 30A includes a main memory circuit.
- the main memory circuit is shown as the core circuit (main circuit) CORE2 of the memory chip 30A.
- the circuit included in the core circuit CORE2 may include a circuit other than the main memory circuit.
- the memory chip 30A is formed with an internal interface circuit (internal input / output circuit) IF2 for inputting / outputting signals to / from an internal device (for example, the logic chip 30B).
- an internal interface circuit internal input / output circuit
- the memory chip 30A includes a power supply circuit DRV2 to which a potential for driving the core circuit CORE2 is supplied.
- a power supply line VD2 that supplies a power supply potential and a reference potential line VS1 that supplies a reference potential are connected to the power supply circuit DRV2.
- the power supply potential supplied to the power supply line VD1, the power supply potential supplied to the power supply line VD2, and the power supply potential supplied to the power supply line VD3 are the power supplies provided outside the semiconductor device PKG1. 50.
- FIG. 4 shows an example in which the pair of power supply line VD2 and reference potential line VS1 are connected to the memory chip 30A.
- the logic chip 30B and the memory chip 30A are electrically connected through the power supply line VD3 to which the power supply potential for driving the internal interface circuit IF2 is supplied and the reference potential line VS2, respectively.
- the method of supplying a potential to the memory chip 30A has various modifications other than the above.
- the power supply potential for driving the internal interface circuit IF2 of the logic chip 30B and the power supply potential for driving the internal interface circuit IF2 of the memory chip 30A may be supplied independently.
- the plurality of transmission paths that electrically connect the logic chip 30B and the memory chip 30A include the reference potential line VS2 in addition to the data line DQ and the control signal line CMD.
- the reference potential line VS2 is a path for transmitting a reference signal of a data signal transmitted through the data line DQ, for example.
- a ground potential is supplied as a reference potential to the reference potential line VS2.
- the potential is more stable when the reference potential line VS2 and the reference potential line VS1 are connected. Therefore, as shown with a dotted line in FIG.
- the reference potential line VS2 and the reference potential line VS1 are connected in the interposer 20A.
- the reference reference potential line VS2 may be supplied with a potential other than the ground potential as long as variation in potential in the transmission path can be reduced.
- the power supply potential of the input / output power supply circuit may be used as a reference potential for reference.
- the power supply line VD2 for supplying the power supply potential to the memory chip 30A and the reference potential line VS1 for supplying the reference potential to the memory chip 30A are not connected to the memory chip 30A. It is connected to the.
- the power supply line VD1 and the reference potential line VS1 may be connected to the memory chip 30A via the logic chip 30B.
- FIG. 5 is an enlarged cross-sectional view of a part of the periphery of the interposer shown in FIG.
- the wiring board 10 shown in FIGS. 1 to 5 is a board provided with a transmission path for supplying electric signals and potentials between the semiconductor device PKG1 and the mounting board 60 (see FIG. 4).
- the wiring board 10 has a plurality of wiring layers (eight layers in the example shown in FIG. 3) that electrically connect the upper surface 10t side and the lower surface 10b side.
- the plurality of wirings 13 provided in each wiring layer are covered with an insulating layer 14 that insulates between the plurality of wirings 13 and between adjacent wiring layers.
- the wiring board 10 shown in FIG. 3 is a so-called multilayer wiring board having a plurality of laminated wiring layers.
- the wiring board 10 includes a total of eight wiring layers including wiring layers L1, L2, L3, L4, L5, L6, L7, and a wiring layer L8 in order from the upper surface 10t side.
- Each of the plurality of wiring layers has a conductor pattern such as the wiring 13, and adjacent conductor patterns are covered with an insulating layer 14.
- the number of wiring layers included in the wiring board 10 is not limited to the example illustrated in FIG. 3, and may be, for example, less than eight layers or more than eight layers.
- the wiring board 10 has a core layer (core material, core insulating layer, insulating layer) 14c as a base material, and a plurality of wiring layers are laminated on the upper surface and the lower surface of the core layer 14c. It has a structure.
- the core layer 14c is an insulating layer serving as a base material of the wiring board 10, and is made of, for example, an insulating material in which a fiber material such as glass fiber is impregnated with a resin material such as an epoxy resin.
- stacked on each of the upper surface and lower surface of the core layer 14c consists of organic insulating materials, such as a thermosetting resin, for example.
- stacked on the upper surface and lower surface of the core layer 14c is formed by the buildup method, for example.
- a so-called coreless substrate that does not have the core layer 14c may be used.
- the wiring board 10 includes via wirings 15 that are provided between the wiring layers and are interlayer conductive paths that connect the stacked wiring layers in the thickness direction.
- a plurality of bonding pads (terminals, interposer mounting surface side terminals, electrodes) 16 are formed on the upper surface 10t of the wiring board 10.
- the wiring 13 provided in the uppermost wiring layer is formed integrally with the bonding pad 16.
- the bonding pad 16 can be considered as a part of the wiring 13.
- the portion exposed from the insulating film 17 on the upper surface 10t of the wiring substrate 10 is defined as the bonding pad 16 and the portion covered with the insulating film 17 is defined as the wiring 13. Can do.
- solder balls 11 are connected to each of the plurality of lands 12, and the mounting substrate 60 and the semiconductor device PKG1 shown in FIG. 4 are electrically connected via the solder balls 11 shown in FIG. That is, the plurality of solder balls 11 function as external connection terminals of the semiconductor device PKG1.
- the plurality of solder balls 11 and the plurality of lands 12 are electrically connected to the plurality of bonding pads 16 on the upper surface 10 t side via the plurality of wirings 13 of the wiring substrate 10.
- the wiring 13 provided in the lowermost wiring layer (the wiring layer on the lowermost surface 10 b side) is formed integrally with the land 12.
- the land 12 can be considered as a part of the wiring 13.
- the portion exposed from the insulating film 17 on the lower surface 10 b of the wiring substrate 10 can be defined as the land 12, and the portion covered with the insulating film 17 can be defined as the wiring 13. .
- the land 12 itself functions as an external connection terminal.
- the solder balls 11 are not connected to the lands 12, and each of the lands 12 is exposed from the insulating film 17 on the lower surface 10 b of the wiring substrate 10.
- a thin solder film may be connected instead of the ball-shaped solder ball 11, and this solder film may function as an external connection terminal.
- a gold (Au) film formed by, for example, a plating method may be formed on the exposed surface, and this gold film may be used as an external connection terminal.
- the external connection terminal may be formed in a pin shape (bar shape).
- the upper surface 10 t and the lower surface 10 b of the wiring substrate 10 are covered with an insulating film (solder resist film) 17.
- the wiring 13 formed on the upper surface 10 t of the wiring substrate 10 is covered with an insulating film 17.
- An opening is formed in the insulating film 17, and at least a part (bonding region) of the plurality of bonding pads 16 is exposed from the insulating film 17 in the opening.
- the wiring 13 formed on the lower surface 10 b of the wiring substrate 10 is covered with an insulating film 17.
- An opening is formed in the insulating film 17, and at least a part of the plurality of lands 12 (joined portions with the solder balls 11) is exposed from the insulating film 17 in the opening.
- the semiconductor device PKG1 includes an interposer 20A mounted on the wiring board 10.
- the interposer 20A is mounted on the upper surface 10t of the wiring board 10 so that the lower surface 20b faces the upper surface 10t of the wiring board 10.
- the interposer 20 ⁇ / b> A is a relay board that is interposed between the wiring board 10 and the plurality of semiconductor chips 30.
- the interposer 20A of the present embodiment is a relay board provided with a wiring path that electrically connects the plurality of semiconductor chips 30 to each other.
- the interposer 20A of the present embodiment has a function of electrically connecting the semiconductor chip 30 and the wiring board 10 and a function of electrically connecting a plurality of semiconductor chips 30 mounted on the interposer 20A. ing.
- the interposer 20A is a so-called multilayer wiring board including a plurality of wiring layers stacked.
- the interposer 20A includes a total of eight wiring layers including wiring layers M1, M2, M3, M4, M5, M6, M7, and a wiring layer M8 in order from the upper surface 20t side.
- Each of the plurality of wiring layers has a conductor pattern such as the wiring 22, and adjacent conductor patterns are covered with an insulating layer 21.
- the number of wiring layers provided in the interposer 20A is not limited to the example illustrated in FIG. 3, and may be, for example, less than eight layers or more than eight layers.
- the interposer 20A has a structure in which a plurality of wiring layers are laminated on the upper surface and the lower surface of the core layer 21c using a core layer (core material, core insulating layer, insulating layer) 21c as a base material. It has become.
- the core layer 21c is an insulating layer serving as a base material for the interposer 20A, and is made of, for example, an insulating material in which a fiber material such as glass fiber is impregnated with a resin material such as an epoxy resin.
- stacked on each of the upper surface and lower surface of the core layer 21c consists of organic insulating materials, such as a thermosetting resin, for example.
- the insulating layer 21 may be formed of a glass material (inorganic insulating material) such as silicon dioxide (SiO 2 ).
- the flatness of the insulating layer 21 constituting the base of each wiring layer can be improved, so that the wiring width of the plurality of wirings 22 can be reduced or the plurality of wirings 22 can be reduced. Can be made higher than the arrangement density of the wirings 13 of the wiring board 10.
- stacked on the upper surface and lower surface of the core layer 21c is formed by the buildup method, for example.
- the plurality of wiring layers provided in the interposer 20A are electrically connected via via wirings 23 and through-hole wirings 24 which are interlayer conductive paths.
- the core layer 21c includes an upper surface 21t and a lower surface 21b positioned on the opposite side of the upper surface 21t.
- the core layer 21c has a plurality of through holes penetrating from one of the upper surface 21t and the lower surface 21b to the other, and a plurality of through hole wirings 24 formed by embedding conductors in the plurality of through holes. .
- Each of the plurality of through-hole wirings 24 includes an interlayer conductive path that electrically connects the wiring layer M4 provided on the upper surface 21t of the core layer 21c and the wiring layer M5 provided on the lower surface 21b of the core layer 21c. Become.
- each of the wiring layer M4, the wiring layer M3, the wiring layer M2, and the wiring layer M1 stacked on the upper surface 21t side of the core layer 21c is electrically connected to each other through a plurality of via wirings 23.
- each of the wiring layer M5, the wiring layer M6, the wiring layer M7, and the wiring layer M8 stacked on the lower surface 21b side of the core layer 21c is electrically connected to each other via a plurality of via wirings 23.
- the number of wiring layers stacked on the upper surface 21t side of the core layer 21c and the core layer 21c may be different.
- the wiring route that does not interpose the through-hole wiring 24 The thickness of the interposer 20A can be reduced while increasing the number of wiring layers.
- the via wiring 23 is formed as follows. First, after providing the insulating layer 21 so as to cover the underlying wiring layer, an opening is provided in a part of the insulating layer 21 to expose a part of the underlying wiring layer. The via wiring 23 is formed by embedding a conductor in the opening. In addition, after the via wiring 23 is formed, another wiring layer is stacked on the via wiring 23 so that the upper wiring layer and the lower wiring layer are electrically connected.
- a plurality of upper surface terminals (bonding pads, terminals, semiconductor component mounting surface side terminals, component connection terminals) 25 are formed on the upper surface 10t of the interposer 20A.
- Each of the plurality of upper surface terminals 25 is electrically connected to an electrode (surface electrode, component electrode, pad) 33 of the semiconductor chip 30 via a bump electrode 35 made of, for example, solder.
- the via wiring 23 connected to the upper surface terminal 25 is formed immediately below the upper surface terminal 25 (position overlapping in the thickness direction). In this case, a space for connecting the via wiring 23 and the upper surface terminal 25 becomes unnecessary, so that the arrangement density of the plurality of upper surface terminals 25 can be increased.
- FIG. 5 Although not shown, as a modification to FIG.
- a lead wiring (not shown) connected to the upper surface terminal 25 is formed in the wiring layer M1.
- the via wiring 23 and the upper surface terminal 25 may be connected via a lead wiring.
- the arrangement density of the plurality of upper surface terminals 25 is reduced as compared with the example shown in FIG. 5, but the workability of the upper surface terminals 25 is improved, so that the processing accuracy of the upper surface terminals 25 can be improved.
- the structure of the bump electrode 35 has various modifications.
- a pillar bump (columnar electrode) in which a solder film is formed on the tip surface of a conductor column made of copper (Cu) or nickel (Ni) may be used as the bump electrode 35.
- a plurality of lower surface terminals (terminals, solder connection pads, lands, wiring board connection terminals) 26 are formed on the lower surface 10b of the interposer 20A.
- Each of the plurality of lower surface terminals 26 is electrically connected to each of the plurality of bonding pads 16 of the wiring board 10 via bump electrodes 27 made of, for example, solder.
- the via wiring 23 connected to the lower surface terminal 26 is formed immediately above the lower surface terminal 26 (position overlapping in the thickness direction). In this case, a space for connecting the via wiring 23 and the lower surface terminal 26 is not necessary, so that the arrangement density of the plurality of lower surface terminals 26 can be increased.
- the surface area of the lower surface terminal 26 is larger than the surface area of the upper surface terminal 25.
- the lead wiring (connected to the lower surface terminal 26 is connected to the wiring layer M ⁇ b> 8.
- the via wiring 23 and the lower surface terminal 26 may be connected via a lead wiring. In this case, compared to the example shown in FIG. 5, the arrangement density of the plurality of lower surface terminals 26 is reduced, but the workability of the lower surface terminals 26 is improved.
- each of the plurality of upper surface terminals 25 and the plurality of lower surface terminals 26 is not covered with the insulating film but exposed from the insulating layer 21.
- an insulating film (solder resist film) covering the plurality of upper surface terminals 25 and an insulating film (solder resist film) covering the plurality of lower surface terminals 26 may be provided.
- an opening is formed in the insulating film, and if a part of each of the plurality of upper surface terminals 25 and the plurality of lower surface terminals 26 is exposed from the insulating film in the opening, the bump electrode 35 is formed on the upper surface terminal 25.
- the bump electrodes 27 can be connected to the lower surface terminals 26, respectively.
- the interposer 20A has various modifications in addition to the above-described modifications of the number of wiring layers.
- a so-called coreless substrate that does not include the core layer 21 c may be used.
- a so-called silicon interposer in which a semiconductor substrate such as silicon (Si) is used as a base material and a plurality of wiring layers are stacked on the main surface of the semiconductor substrate may be used.
- the method of providing the core layer 21c and laminating the wiring layers on the upper surface 21t and the lower surface 21b of the core layer 21c as in the present embodiment increases the number of wiring layers and makes the wiring layers flat. It is preferable in that the degree can be improved.
- the semiconductor device PKG1 includes a plurality of semiconductor chips 30 mounted on the upper surface 20t of the interposer 20A.
- each of the plurality of semiconductor chips 30 includes a silicon substrate (base material) 31 having a main surface 31t, and a wiring layer 32 disposed on the main surface 31t.
- one wiring layer 32 is shown.
- the wiring layer 32 shown in FIG. 5 has a thickness larger than that of the wiring layers M1, M2, and M3 of the interposer 20A.
- a plurality of thin wiring layers are stacked.
- a plurality of wirings are formed in each of the plurality of wiring layers 32.
- the plurality of wirings are covered with an insulating layer that insulates between the plurality of wirings and between adjacent wiring layers.
- the insulating layer is an inorganic insulating layer made of an oxide of a semiconductor material such as silicon oxide (SiO).
- a plurality of semiconductor elements such as transistor elements or diode elements are formed on the main surface 31t of the silicon substrate 31 included in each of the plurality of semiconductor chips 30.
- the plurality of semiconductor elements are electrically connected to the plurality of electrodes 33 formed on the surface 30 t side through the plurality of wirings of the wiring layer 32.
- each of the plurality of semiconductor chips 30 is mounted on the upper surface 20t of the interposer 20A with the surface 30t and the upper surface 20t of the interposer 20A facing each other.
- a mounting method is called a face-down mounting method or a flip-chip connection method.
- the semiconductor chip 30 and the interposer 20A are electrically connected as follows.
- a plurality of electrodes (surface electrodes, component electrodes, pads) 33 are formed on the wiring layer 32 of the semiconductor chip 30. A part of each of the plurality of electrodes 33 is exposed from the passivation film 34 which is a protective insulating film on the surface 30 t of the semiconductor chip 30.
- the electrode 33 is electrically connected to the upper surface terminal 25 of the interposer 20 ⁇ / b> A via a bump electrode 35 connected to the exposed portion of the electrode 33.
- a part of the plurality of transmission paths connected to the memory chip 30A is not connected to the wiring board 10, and the logic chip 30B is connected via the interposer 20A. Connected to.
- the data line DQ and the control signal line CMD are electrically separated from the wiring board 10.
- the power supply line VD2 and the reference potential line VS1 for supplying the power supply potential for driving the circuit of the memory chip 30A are electrically connected to the wiring board 10. ing.
- the reference potential line VS2 used for reference of the signal line may be separated from the wiring board 10.
- FIG. 6 is an explanatory diagram schematically showing an example of the layout of the signal transmission path connecting the logic chip and the memory chip shown in FIG.
- FIG. 7 is an explanatory diagram schematically illustrating an example of a planar layout of the plurality of electrodes, the plurality of through-hole wirings, and the wirings that electrically connect the plurality of electrodes illustrated in FIG. 6.
- FIG. 8 is an explanatory view schematically showing an example of a wiring layout for electrically connecting a plurality of through-hole wirings shown in FIG.
- FIGS. 6 to 8 are schematic diagrams for explaining the difference in the connection method (relationship between the lead-out direction of the wiring and the arrangement of the electrodes) between the wiring path (signal wiring path) WP1 and the wiring path (signal wiring path) WP2. is there.
- FIGS. 6 to 8 schematically show a part of a large number of electrodes included in the logic chip 30B and the memory chip 30A and wiring paths connected to these electrodes.
- the number of wiring paths provided in the interposer 20A is not limited to the examples shown in FIGS. 6 to 8, and may be larger than the examples shown in FIGS.
- FIG. 6 is a cross-sectional view in which each of the plurality of wiring paths WP2 and each of the plurality of wiring paths WP1 are routed by different wiring layers. However, a plurality of wiring paths WP2 or a plurality of wiring paths WP1 may be routed in one wiring layer.
- 7 and 8 show a planar positional relationship between the wiring route WP1 and the wiring route WP2 (see FIG. 7).
- FIG. 7 shows a layout of wiring layers for four layers above the core layer 21c (see FIG. 5) provided with a plurality of through-hole wirings 24, and
- FIG. 8 shows a plurality of through-hole wirings 24 provided.
- the layout of the wiring layers for four layers below the core layer 21c is shown. 7 and 8, the position of the semiconductor chip 30 is indicated by a two-dot chain line.
- a plurality of upper surface terminals 25 are formed in the first wiring layer of the interposer 20 ⁇ / b> A, and the plurality of electrodes 33 of the semiconductor chip 30 are respectively connected to the plurality of upper surface terminals 25. It is arrange
- the plurality of electrodes 33 are indicated by solid lines in order to show a planar positional relationship between the plurality of electrodes 33 and the plurality of wiring paths. Therefore, on the upper surface 20t (see FIG. 5) of the interposer 20A, a plurality of upper surface terminals 25 (see FIG. 5) are provided at positions overlapping the plurality of electrodes 33 shown in FIG.
- first group electrodes inner electrodes, signal electrodes, short-distance connection electrodes
- second group electrodes outer electrodes, signal electrodes, bypass connection electrodes
- each of the plurality of first group electrodes GM1 connected to the plurality of wiring paths WP2 is on the upper surface 20t (see FIG. 6) of the interposer 20A. Are disposed in a region relatively inside (center side of the upper surface 20t) relative to the plurality of second group electrodes GM2.
- each of the plurality of first group electrodes GL1 connected to the plurality of wiring paths WP2 includes a plurality of electrodes on the upper surface 20t of the interposer 20A.
- the second group electrode GL2 is disposed in a relatively inner region (center side of the upper surface 20t).
- the first group electrodes GL1, GM1 can also be referred to as “inner” electrodes.
- the second group electrodes GL2 and GM2 may be referred to as “outer” electrodes.
- the plurality of second group electrodes GL2 and GM2 shown in FIG. 6 are electrodes that are electrically connected to each other via a wiring route WP1 that is a bypass wiring route described later.
- a wiring route WP1 that is a bypass wiring route described later.
- each of the plurality of second group electrodes GM2 connected to the plurality of wiring paths WP1 is on the upper surface 20t of the interposer 20A (see FIG. 6).
- the first group electrode GM1 is disposed outside the plurality of first group electrodes GM1 (on the peripheral edge side of the upper surface 20t).
- each of the plurality of second group electrodes GL2 connected to the plurality of wiring paths WP1 includes a plurality of electrodes on the upper surface 20t of the interposer 20A. It arrange
- first group electrodes GM1, GL1 and all the second group electrodes GM2, GL2 do not have to be clearly partitioned.
- some of the first group electrodes GM1 and GL1 are partially at the boundary between the region where the plurality of first group electrodes GM1 and GL1 are disposed and the region where the plurality of second group electrodes GM2 and GL2 are disposed. You may arrange
- each of the plurality of data lines DQ is designed to transmit a data signal at a transmission rate of 1 Gbps (1 gigabit per second) or more.
- high clocking In order to increase the transmission speed of each of the plurality of signal transmission paths, it is necessary to increase the number of transmissions per unit time (hereinafter referred to as high clocking).
- bus width expansion As another method for improving the signal transmission speed between the logic chip 30B and the memory chip 30A, there is a method of increasing the amount of data transmitted at a time by increasing the width of the data bus of the internal interface (Hereinafter referred to as bus width expansion). Further, there is a method of applying a combination of the above-described bus width expansion and high clock. In this case, many high-speed signal transmission paths are required.
- the data bus width is 1024 bits or more.
- the number of transmissions per unit time of each terminal is increased, and the transfer rate per terminal is, for example, 1 Gbps or more.
- the interposer 20 ⁇ / b> A is not provided on the wiring board 10, and all the signal transmission paths are routed only by the wiring board 10.
- the wiring structure of the wiring board 10 becomes complicated.
- the case where the number of wiring layers of the wiring board 10 exceeds 30 is also conceivable. Therefore, when there are a large number of signal transmission paths that electrically connect the semiconductor chips 30, a method of connecting these signal paths with a wiring layer of a relay board (interposer) provided separately from the wiring board is effective. is there.
- a method of electrically connecting the logic chip 30B and the memory chip 30A via the interposer 20A as in the present embodiment is effective.
- the structure of the wiring board 10 can be simplified.
- the number of wiring layers (the total of the number of wiring layers of the wiring board 10 and the number of wiring layers of the interposer 20A) can be reduced.
- the signal transmission path for electrically connecting the semiconductor chips 30 is connected by using wiring extending from one semiconductor chip 30 toward the other semiconductor chip 30 so as to connect at the shortest distance possible.
- the signal transmission path for electrically connecting the semiconductor chips 30 is connected by using wiring extending from one semiconductor chip 30 toward the other semiconductor chip 30 so as to connect at the shortest distance possible.
- it is.
- the side surface among the plurality of first group electrodes GL ⁇ b> 1 provided on the side surface 30 s ⁇ b> 1 and the plurality of electrodes 33 included in the memory chip 30 ⁇ / b> A is electrically connected via a wiring (signal wiring) 22B extending from one semiconductor chip 30 toward the other semiconductor chip 30. .
- each of the electrodes PL1, PL2, PL3, PL4 arranged in order along the direction DL1 from the side close to the side surface 30s1 of the logic chip 30B to the side far from the side, and the side far from the side near the side surface 30s2 of the memory chip 30A.
- This will be described in detail using a plurality of wiring paths WP2 that connect each of the electrodes PM1, PM2, PM3, and PM4, which are sequentially arranged along the direction DL2 that goes in the direction.
- Each of the plurality of wirings 22B constituting the plurality of wiring paths WP2 has one end at a position overlapping with the logic chip 30B in the thickness direction, and extends toward the memory chip 30A.
- Each of the plurality of wirings 22B includes the other end portion at a position overlapping the memory chip 30A.
- each of the plurality of wirings 22B has one end at a position that overlaps the memory chip 30A in the thickness direction, extends toward the logic chip 30B, and the other at a position that overlaps the logic chip 30B in the thickness direction. End.
- each of the wirings 22B is an inter-chip connection wiring that linearly connects between the memory chip 30A and the logic chip 30B. As shown in FIG.
- each of the plurality of wirings 22 ⁇ / b> B includes a detour portion that makes a small detour along the outline of the electrode in order to pass between adjacent electrodes.
- the above-mentioned “straight connection” includes a connection path having a portion that makes a small detour along the contour of the conductor pattern in order to avoid contact with a small conductor pattern such as an electrode.
- the wiring path WP2 When the electrodes are connected to each other via a wiring 22B extending from directly below one semiconductor chip 30 to just below the other semiconductor chip 30 as in the wiring path WP2, the wiring is compared with the wiring path WP1 shown in FIG. The route distance can be shortened. For this reason, the signal waveform of the wiring path WP2 is less likely to attenuate than the wiring path WP1. Further, the wiring path WP2 can reduce the influence of crosstalk noise between adjacent wiring paths compared to the wiring path WP1.
- the wiring path WP2 includes a wiring layer M5, a wiring layer M6, a wiring layer M7, and a wiring layer on the lower layer side (lower surface 20b side) than the core layer 21c provided with the plurality of through-hole wirings 24. It is not formed in the layer M8.
- each of the plurality of wiring paths WP2 is one of the wiring layer M1, the wiring layer M2, the wiring layer M3, and the wiring layer M4 on the upper layer side (upper surface 20t side) than the core layer 21c. It is formed as described above.
- the wiring route distance can be shortened.
- the wiring paths WP2 it is preferable to increase the number of wiring paths that can shorten the wiring path distance, such as the wiring path WP2. Further, by arranging the wiring paths WP2 at a high density, it is possible to suppress an increase in the number of wiring layers even when the number of signal transmission paths is increased.
- a portion where a plurality of wiring paths WP2 cross each other three-dimensionally (hereinafter referred to as a three-dimensional intersection).
- a plurality of via wirings and a plurality of wirings are densely arranged at the three-dimensionally intersecting portion.
- the efficient wiring layout is hindered, and the number of bypass wirings and bypass via wirings increases. If the portion where the plurality of wiring paths WP2 cross each other is reduced, the number of bypass wirings and via wirings can be reduced, and the arrangement density of the wiring paths WP2 can be improved.
- the plurality of first group electrodes GL1 and the plurality of first group electrodes GM1 connected to the plurality of wiring paths WP2 shown in FIG. 6 are line symmetric with respect to the intermediate point between the memory chip 30A and the logic chip 30B. Are arranged as follows.
- the electrode PL1 provided in the column closest to the side surface 30s1 of the logic chip 30B is the column closest to the side surface 30s2 of the memory chip 30A among the plurality of first group electrodes GM1.
- Is connected to the electrode PM1 provided in The electrode PL2 provided in the column adjacent to the electrode PL1 is connected to the electrode PM2 provided in the column adjacent to the electrode PM1.
- the electrode PL3 provided in the column adjacent to the electrode PL2 is connected to the electrode PM3 provided in the column adjacent to the electrode PM2, and the electrode PL4 provided in the column adjacent to the electrode PL3 is connected to the electrode PM3. It is connected to the electrode PM4 provided in the adjacent row.
- the plurality of first group electrodes GL1 and first group electrodes GM1 are arranged in the first column, the second column from the side close to the side surface 30s1 and the side surface 30s2, with the side surface 30s1 and the side surface 30s2 facing each other as a reference.
- the first group electrode GL1 in the nth column of the logic chip 30B and the first group electrode GM1 in the nth column of the memory chip 30A are electrically connected to each other.
- such an electrode arrangement method and connection method are referred to as a mirror arrangement method.
- the plurality of first group electrodes GL1 and the plurality of first group electrodes GM1 are arranged by the mirror arrangement method, the plurality of first group electrodes GL1 and the plurality of first group electrodes GM1 are randomly connected. Compared with the case where it does, each of several wiring path
- the wiring path WP2 provided by the mirror arrangement method.
- the path WP2 is provided so as to pass between the first group electrodes GL1 and GM1 electrodes that are relatively close to the side surfaces 30s1 and 30s2.
- the wiring path WP2 connected to the electrode PL4 in the fourth column is between the plurality of electrodes PL3 arranged on the side surface 30s1 side from the electrode PL4. Between the plurality of electrodes PL1. Further, among the plurality of first group electrodes GM1, the wiring path WP2 connected to the electrode PM4 in the fourth column is between the plurality of electrodes PM3 arranged on the side surface 30s2 side from the electrode PM4, and the plurality of electrodes PM2 And between the plurality of electrodes PM1.
- the number of necessary signal transmission paths exceeds the limit of the number of wiring paths WP2, a part of the plurality of signal transmission paths linearly connects the memory chip 30A and the logic chip 30B. It is necessary to connect by a detour wiring route detoured from the connection route.
- the plurality of wiring paths WP1 that electrically connect the plurality of second group electrodes GL2 and the plurality of second group electrodes GM2 correspond to bypass wiring paths.
- each of the plurality of wiring paths WP1 included in the interposer 20A includes a wiring (signal wiring) 22A, a wiring (signal wiring) 22C, and a wiring (signal wiring) 22D.
- Each of the plurality of wirings 22A constituting the plurality of wiring paths WP1 has one end at a position overlapping the logic chip 30B in the thickness direction, and extends in a direction away from the memory chip 30A.
- Each of the plurality of wirings 22C constituting the plurality of wiring paths WP1 has one end at a position overlapping the memory chip 30A in the thickness direction, and extends in a direction away from the logic chip 30B.
- Each of the plurality of wirings 22D constituting the plurality of wiring paths WP1 includes wiring layers M1, M2, M3, M4 in which a plurality of wirings 22A are formed, and wiring layers M1, M2, in which a plurality of wirings 22C are formed, It is formed in wiring layers M5, M6, M7, and M8 different from M3 and M4, and electrically connects the plurality of wirings 22A and the plurality of wirings 22C, respectively.
- the detour wiring paths such as the plurality of wiring paths WP1 are arranged so as to detour the portion where the plurality of wiring paths WP2 shown in FIG. 6 are arranged. For this reason, even if the number of bypass wiring paths is increased, the layout of the plurality of wiring paths WP2 is not hindered. Therefore, by providing the plurality of wiring paths WP1 in addition to the plurality of wiring paths WP2, the number of signal transmission paths provided in the interposer 20A can be increased.
- each of the plurality of wirings 22D constituting the plurality of wiring paths WP1 is formed in at least one of the wiring layers M1, M2, M3, and M4. May be. However, in that case, the detour route distance for detouring the portion where the wiring route WP2 is arranged becomes longer. Therefore, from the viewpoint of shortening the path distance of the bypass wiring path, each of the plurality of wirings 22D constituting the plurality of wiring paths WP1 includes the plurality of wirings 22A, the plurality of wirings 22B, and the like, as in the present embodiment. It is preferable that the wiring layers M5, M6, M7, and M8 are formed differently from the wiring layers M1, M2, M3, and M4 on which the plurality of wirings 22C are formed.
- FIG. 27 is an explanatory diagram of an example of study with respect to FIG.
- the interposer 20H shown in FIG. 27 is different from the interposer 20A shown in FIG. 6 in that each of the plurality of wiring paths WP1 is connected by the mirror arrangement method described above.
- the inventor of the present application has a plurality of second group electrodes connected to the plurality of wiring paths WP2 in order to improve the arrangement density of the plurality of wiring paths WP1 which are bypass wiring paths.
- a method of connecting each of GL2 and the plurality of second group electrodes GM2 by the above-described mirror arrangement method was examined.
- the arrangement density of the wiring paths WP1 and WP2 can be improved.
- the mirror arrangement method is adopted in the wiring route WP1 which is a detour wiring route
- the following problems arise from the viewpoint of signal transmission reliability. That is, in the case of the above-described mirror arrangement method, as shown in FIG. 27, the electrodes are connected in order from the electrodes provided at positions close to the side surface 30s1 and the side surface 30s2. For this reason, the route distances of the plurality of wiring routes are not constant. For example, in the example shown in FIG.
- the wiring route distance is greatly different from the route WP1. Such a difference in wiring path distance when the mirror arrangement method is employed also occurs in the plurality of wiring paths WP2. However, in the wiring route WP2, since the original route distance is short, the difference in the route distance is difficult to increase.
- the wiring route WP1 which is a detour wiring route has a longer original wiring route distance than the wiring route WP2, the difference in the wiring route distance is likely to be large. Further, as shown in FIG. 27, when the through hole wiring 24 is included in the wiring path WP1, the bypass distance becomes long in order to match the arrangement pitch of the through hole wiring 24. As a result, the difference in the wiring route distance is likely to be further increased.
- the width of the EYE aperture is narrowed due to an increase in transmission delay error of the signal transmission path.
- the signal waveform is steeply raised because the signal waveform is less attenuated, so that the original EYE opening is wide.
- the original wiring path distance is long as in the wiring path WP1
- the signal waveform rises gently because the attenuation of the signal waveform is large. Therefore, the original EYE opening is narrow.
- the width of the EYE opening becomes narrow due to a propagation delay error, the influence on transmission reliability is great. In other words, if the width of the EYE opening becomes narrow due to a propagation delay error, it may cause a decrease in transmission reliability.
- the inventor of the present application has studied a technique for reducing the difference in the wiring path distance for a plurality of wiring paths WP1 having a relatively long wiring path distance, and found the configurations shown in FIGS.
- the plurality of wiring paths WP1 included in the interposer 20A of the present embodiment are not in the above-described mirror arrangement method.
- a plurality of second group electrodes GM2 and a plurality of second group electrodes GL2 connected to each other are arranged in the same order along one direction DL1.
- the plurality of second group electrodes GL2 of the logic chip 30B are arranged along the direction DL1 from the side closer to the side surface 30s1 to the side farther from the side 30s1 in a plan view, and the electrode (first electrode) PL5 and the electrode (first 2 electrode) PL6, electrode PL7, and electrode (3rd electrode) PL8 are included.
- the electrode PL5 is disposed in the first row, which is closest to the side surface 30s1.
- the electrode PL8 is arranged in the fourth row, which is farthest from the side surface 30s1.
- the plurality of second group electrodes GM2 of the memory chip 30A are arranged along the direction DL1 from the side far from the side surface 30s2 toward the side closer to the side in the plan view, the electrode (fourth electrode) PM5 and the electrode (fifth). Electrode) PM6, electrode PM7, and electrode (sixth electrode) PM8 are included.
- the plurality of second group electrodes GM2 of the memory chip 30A are arranged along the direction DL2 from the side closer to the side surface 30s2 to the side farther from the side surface 30s2 in plan view, the electrode (sixth electrode) PM8, the electrode PM7, An electrode (fifth electrode) PM6 and an electrode (fourth electrode) PM5 are included.
- the electrode PM5 is arranged in the fourth row, which is farthest from the side surface 30s2.
- the electrode PM8 is arranged in the first row that is closest to the side surface 30s2.
- the electrode PL5 of the logic chip 30B and the electrode PM5 of the memory chip 30A are electrically connected via the wiring path WP1. Further, the electrode PL6 of the logic chip 30B and the electrode PM6 of the memory chip 30A are electrically connected via another wiring path WP1. Further, the electrode PL7 of the logic chip 30B and the electrode PM7 of the memory chip 30A are electrically connected via another wiring path WP1. Further, the electrode PL8 of the logic chip 30B and the electrode PM8 of the memory chip 30A are electrically connected via another wiring path WP1.
- the plurality of second group electrodes GL2 and second group electrodes GM2 are arranged in the first column, the second column from the side close to the side surface 30s1 and the side surface 30s2, with the side surface 30s1 and the side surface 30s2 facing each other as a reference.
- the second group electrode GL2 in the n-th column of the logic chip 30B and the second group electrode GM2 in the (mn) column of the memory chip 30A are electrically connected, respectively. Connected.
- the wiring route WP1 which is a bypass wiring route
- a plurality of wiring routes WP1 cross each other in the middle of the route as shown in FIG. . Details of the method of making the plurality of wiring paths WP1 cross each other will be described later.
- the plurality of wiring paths WP1 are three-dimensionally crossed as described above, the difference in the path distance between the plurality of wiring paths WP1 is reduced, as is apparent when comparing the wiring path WP1 illustrated in FIG. 6 and the wiring path WP1 illustrated in FIG. it can.
- the wiring 22A having the longest wiring length among the plurality of wirings 22A is the wiring 22A connected to the electrode PL8 and routed by the wiring layer M1 (uppermost wiring layer).
- the wiring 22C having the shortest wiring length is connected to the electrode PM8, and is routed by the wiring layer M4 (the lowermost wiring layer among the wiring layers above the core layer 21c).
- Wiring 22C is the wiring 22A connected to the electrode PL5 and routed by the wiring layer M4.
- the wiring 22C having the longest wiring length is a wiring 22C connected to the electrode PM4 and routed by the wiring layer M1.
- the wiring 22A having the longest wiring length and the wiring 22C having the shortest wiring length are connected to form one of the wiring paths WP1.
- the wiring 22A having the shortest wiring length and the wiring 22C having the longest wiring length are connected to form another wiring path WP1.
- the lengths of the plurality of wirings 22D are approximately the same (within an error range that can be regarded as the same considering the reliability of signal transmission). Therefore, according to the present embodiment, it is possible to make the total distances of the wirings 22A, 22C, and 22D constituting each of the plurality of wiring paths WP1 equal.
- the inventor of the present application has examined a case where the present invention is applied to a semiconductor device having about 1,000 signal transmission paths.
- a plurality of wiring paths WP1 By applying the above-described parallel movement arrangement method to a plurality of wiring paths WP1, a plurality of It was found that the difference in the route distance of the wiring route WP1 can be suppressed to at least less than 1 mm.
- the difference in the path distances of the plurality of wiring paths WP1 is about 15 mm.
- the plurality of wiring paths WP1 are made equal in length by applying the parallel movement arrangement method described above to the plurality of wiring paths WP1 that are bypass wiring paths. Can do. For this reason, the transmission delay error for each signal transmission path can be reduced. As a result, it is possible to improve the reliability of signal transmission in the wiring path WP1 having a longer path distance than the wiring path WP2. Further, since the plurality of wiring paths WP1 can be used as signal transmission paths in addition to the plurality of wiring paths WP2, an increase in the number of wiring layers can be suppressed even when the number of signal transmission paths is increased.
- each of the plurality of wiring paths WP1 includes the through-hole wiring 24 penetrating the core layer 21c, there is a preferable aspect in the arrangement of the through-hole wiring 24.
- the plurality of through-hole wirings 24 are arranged along the direction DL1 from the side closer to the side 30s1 of the logic chip 30B to the side farther from the side 30s1.
- Hole wiring) TL5 through-hole wiring (second through-hole wiring) TL6, through-hole wiring TL7, and through-hole wiring (third through-hole wiring) TL8.
- the plurality of through-hole wirings 24 are arranged along the direction DL1 from the side far from the side surface 30s2 of the memory chip 30A to the near side DL1, the fourth through-hole wiring TM5, and the through-hole wiring (first through-hole wiring).
- the electrode PL5 of the logic chip 30B and the electrode PM5 of the memory chip 30A are electrically connected via the through-hole wiring TL5 and the through-hole wiring TM5. Further, the electrode PL6 of the logic chip 30B and the electrode PM6 of the memory chip 30A are electrically connected through the through-hole wiring TL6 and the through-hole wiring TM6. Further, the electrode PL7 of the logic chip 30B and the electrode PM7 of the memory chip 30A are electrically connected via the through-hole wiring TL7 and the through-hole wiring TM7. Further, the electrode PL8 of the logic chip 30B and the electrode PM8 of the memory chip 30A are electrically connected through a through-hole wiring TL8 and a through-hole wiring TM8.
- the plurality of second group electrodes GL2 and the plurality of through-hole wirings 24 are arranged in the order of the first column, the second column,..., The m-th column from the side close to the side surface 30s1, with the side surface 30s1 as a reference.
- the second group electrode GL2 in the nth column of the logic chip 30B is electrically connected to the through-hole wiring 24 in the nth column.
- the plurality of through-hole wirings 24 are counted from the side close to the side surface 30s2 in the order of the first column, the second column,.
- the second group electrode GM2 in the nth column and the through hole wiring 24 in the nth column are electrically connected.
- the n-th through-hole wiring 24 on the side close to the logic chip 30B and the (mn) -th through-hole wiring 24 on the side close to the memory chip 30A are electrically connected to each other.
- the plurality of second group electrodes GL2, the second group electrode GM2, and the plurality of through-hole wirings 24 are arranged in the same order along the direction DL1.
- a method for three-dimensionally intersecting the plurality of wiring paths WP1 will be described in detail.
- the “three-dimensional intersection of wiring paths” referred to in the present application can be defined in the following manner.
- a plurality of first wiring paths (signal transmission paths) routed through each of the plurality of first wirings and the first wiring layer are: Consider an interposer having a plurality of second wiring paths (signal transmission paths) routed through each of a plurality of second wirings in different second wiring layers.
- a plurality of first interlayer conductive paths connected to the plurality of first wiring paths are arranged in the second wiring layer.
- a plurality of second interlayer conductive paths connected to the plurality of second wiring paths are disposed in the first wiring layer.
- the first wiring layer when a part or all of the plurality of second interlayer conductive paths are arranged between the plurality of first wirings, the first wiring path and The second wiring path is a state in which a three-dimensional intersection is made in the first wiring layer.
- the second wiring path is a state in which a three-dimensional intersection is made in the first wiring layer.
- the second wiring path when some or all of the plurality of first interlayer conductive paths are arranged between the plurality of second wirings, the first wiring path;
- the second wiring path is a state where three-dimensional crossing is performed in the second wiring layer.
- the first wiring path when a part or all of the plurality of second wirings are arranged between the plurality of first interlayer conductive paths, the first wiring path;
- the second wiring path is a state where three-dimensional crossing is performed in the second wiring layer.
- the above-mentioned “to be routed” means that, in one wiring layer among a plurality of stacked wiring layers, an upper layer connecting interlayer conductive path connected to a wiring layer one layer above the wiring layer A state in which the lower layer connection interlayer conductive path connected to the lower layer wiring layer which is one lower layer of the wiring layer and disposed at a position different from the upper layer connection interlayer conductive path is connected via the wiring.
- three-dimensional intersection of wiring routes can also be expressed as follows. That is, “three-dimensional intersection of wiring paths” means that “a wiring that constitutes a certain wiring path in one wiring layer is a plurality of via wirings that constitute a plurality of other wiring paths that are routed in another wiring layer. It refers to the state of being placed between.
- three-dimensional intersection of wiring routes means that “in one wiring layer, a plurality of wirings constituting a plurality of wiring routes routed in the wiring layer are routed in another wiring layer. This refers to a state where via wirings constituting other wiring paths are arranged.
- the first group electrode GL1, the second group electrode GL2, the first group electrode GM1 and the second group electrode GM2 are each provided in four rows.
- the first group electrode GL1, the second group electrode GL2, the first group electrode GM1, and the second group electrode GM2 A description will be given using the interposer 20B classified into two groups.
- the interposer 20B has the same structure as the interposer 20A except for the difference between the interposer 20A (see FIG. 6) described below and the interposer 20B. For this reason, although the overlapping description is omitted, the interposer 20B can be replaced with the above-described interposer 20A except for the differences described below.
- FIG. 9 is a cross-sectional view schematically showing an essential part of a semiconductor device which is a modification of the semiconductor device shown in FIGS. 10 to 17 are explanatory diagrams schematically showing layout examples of signal transmission paths provided in the interposer shown in FIG.
- FIG. 10 shows the first wiring layer M1 located on the chip mounting surface side shown in FIG. 9, and FIG. 11 shows the second wiring layer M2 immediately below the first layer.
- FIG. 12 shows a third wiring layer M3 immediately below the second layer, and
- FIG. 13 shows a fourth wiring layer M4 immediately below the third layer.
- FIG. 14 shows a fifth wiring layer M5 immediately below the fourth layer, and
- FIG. 15 shows a sixth wiring layer M6 located on the opposite side of the fifth layer.
- FIG. 20B shown in FIG.
- FIG. 16 shows a seventh wiring layer M7 immediately below the sixth layer
- FIG. 17 shows an eighth wiring layer M8 immediately below the seventh layer.
- the wiring layer M9 shown in FIG. 9 mainly includes power supply lines VD1, VD2, and VD3 that supply a power supply potential, a reference potential line VS1 that supplies a reference potential, among the plurality of wiring paths described with reference to FIG.
- a signal line SIG for transmitting a signal between the VS2 or the logic chip 30B and the external device 40 is formed.
- a plurality of lower surface terminals 26 connected to the wiring substrate 10 shown in FIG. 5 are formed in the wiring layer M10 shown in FIG.
- the interposer 20B included in the semiconductor device PKG2 shown in FIG. 9 is mounted on the wiring board 10 similarly to the interposer 20A shown in FIG.
- the signal transmission path for electrically connecting the semiconductor chips 30 is formed mainly from the wiring layer M1 to the wiring layer M8 shown in FIG. .
- the wiring substrate 10 mainly includes power supply lines VD1, VD2, and VD3 that supply a power supply potential, reference potential lines VS1 and VS2 that supply a reference potential, or A signal line SIG for transmitting a signal between the logic chip 30B and the external device 40 is formed.
- a plurality of upper surface terminals 25 are formed in the first wiring layer M ⁇ b> 1 of the interposer 20 ⁇ / b> B, and the plurality of electrodes 33 of the semiconductor chip 30 are connected to the plurality of upper surface terminals 25. They are arranged at positions facing each other.
- the positions of the plurality of electrodes 33 are solid lines (the plurality of first group electrodes GM1 and GL1 are dotted lines). Is shown.
- FIGS. 12 to 17 for the sake of easy understanding, reference numerals indicating the types of electrodes are shown in the same manner as FIGS. 10 and 11 for easy understanding of the planar positional relationship with FIGS. ing.
- FIGS. 10 to 17 include power supply lines VD1, VD2, and VD3 for supplying a power supply potential, and a reference potential line VS1 for supplying a reference potential among the plurality of wiring paths described with reference to FIG. , VS2 are included. Therefore, in FIGS. 10 to 17, the power supply potential supply path and the reference potential supply path are provided with patterns in order to distinguish the signal transmission path and the power supply path.
- power supply lines VD1, VD2, and VD3 that supply a power supply potential and reference potential lines VS1 and VS2 that supply a reference potential are hatched differently.
- the electrodes 33 that supply the power supply potential and the reference potential are hatched differently.
- the via wiring for supplying the power supply potential and the via wiring for supplying the reference potential are filled.
- the through-hole wiring 24 that supplies the power supply potential and the through-hole wiring that supplies the reference potential are hatched differently.
- the interposer 20B shown in FIG. 10 has electrodes 33 (see FIG. 9) arranged in more rows than the interposer 20A shown in FIG.
- the plurality of first group electrodes GL1 of the logic chip 30B are electrodes IL1, IL2, IL3, IL4, IL5, IL6, IL7 arranged in order along the direction DL1 from the side closer to the side surface 30s1 of the logic chip 30B to the side farther from the side.
- an electrode IL8 an electrode IL8.
- the plurality of second group electrodes GL2 of the logic chip 30B are arranged in order along the direction DL1 from the side closer to the side 30s1 of the logic chip 30B toward the side far from the side OLs, OL2, OL3, OL4, OL5, OL6.
- the plurality of first group electrodes GM1 of the memory chip 30A are arranged in order along the direction DL2 from the side closer to the side 30s2 of the memory chip 30A to the side farther from the side 30s2, and the electrodes IM1, IM2, IM3, IM4, IM5, IM6 , IM7, and electrode IM8.
- the plurality of second group electrodes GM2 of the memory chip 30A are electrodes OM1, OM2, which are sequentially arranged along the direction DL1 which is the reverse direction to the direction DL2 from the side close to the side surface 30s2 of the memory chip 30A to the side far from the side. It has OM3, OM4, OM5, OM6, OM7, and electrode OM8.
- FIGS. 9 to 17 in order to explain the above-described “three-dimensional intersection of wiring routes”, FIGS.
- the wiring route WP1 and the wiring route WP2 described in (1) are classified into two groups.
- the plurality of wiring paths WP1 are the wirings routed through the plurality of wirings (signal wirings) 22A1 formed in the wiring layer M3 (see FIG. 12) in the region 20L.
- the plurality of wiring paths WP2 are wirings routed through a plurality of wirings (signal wirings) 22B1 formed in the wiring layer M3 (see FIG. 12) in the region 20L.
- a path (signal wiring path) WP5 a wiring path (signal wiring path) WP6 routed through a plurality of wirings 22 (signal wiring) B2 formed in the wiring layer M4 (see FIG. 13) in the region 20L, Is included.
- the types of the wiring routes described above are distinguished by the shape of the lines. That is, the wiring 22A1 (see FIG. 12), the wiring 22C2 (see FIG. 13), and the wiring 22D1 (see FIG. 16) constituting a part of the wiring path WP3 are shown by solid lines. Also, the wiring (signal wiring) 22C1 (see FIG. 12), the wiring 22A2 (see FIG. 13), and the wiring 22 (signal wiring) D2 (see FIG. 16) that constitute a part of the wiring path WP4 are shown by alternate long and short dashed lines. Yes. Further, the wiring 22B1 (see FIG. 12) constituting a part of the wiring path WP5 is indicated by a dotted line. Further, the wiring 22B2 (see FIG. 13) constituting a part of the wiring path WP6 is indicated by a dotted line having a length longer than that of the wiring 22B1.
- the plurality of via wirings 23 shown in FIG. 9 are also classified according to the wiring route to be connected in the same manner as described above. That is, as shown in FIGS. 12 to 17, the plurality of via wirings 23 (see FIG. 9) includes a via wiring 23A that forms part of the wiring path WP3 and a via wiring 23B that forms part of the wiring path WP4. And a via wiring 23C constituting a part of the wiring path WP5 and a via wiring 23D constituting a part of the wiring path WP6.
- the plurality of signal transmission electrodes 33 included in each of the logic chip 30B and the memory chip 30A shown in FIG. 10 are classified as follows according to the wiring path to be connected.
- the plurality of first group electrodes GL1 of the logic chip 30B and the plurality of first group electrodes GM1 of the memory chip 30A are connected to the electrode group GR3 connected via the wiring path WP5 shown in FIG. 12, and FIGS.
- the electrode group GR3 of the logic chip 30B includes electrodes IL1, IL2, IL3, and an electrode IL4.
- the electrode group GR3 of the memory chip 30A includes the electrodes IM1, IM2, IM3, and the electrode IM4, each of which is connected to each of the electrodes IL1, IL2, IL3, and the electrode IL4 through the wiring path WP5. Has been.
- the electrode group GR4 of the logic chip 30B includes electrodes IL5, IL6, IL7, and an electrode IL8.
- the electrode group GR4 of the memory chip 30A includes the electrodes IM5, IM6, IM7, and the electrode IM8, each of which is connected to each of the electrodes IL5, IL6, IL7, and the electrode IL8 via the wiring path WP6. Has been.
- the plurality of second group electrodes GL2 of the logic chip 30B and the plurality of second group electrodes GM2 of the memory chip 30A are connected to the electrode group GR1 connected via the wiring path WP3 shown in FIGS.
- the electrode group GR1 of the logic chip 30B includes electrodes OL5, OL6, OL7, and an electrode OL8.
- the electrode group GR1 of the memory chip 30A includes electrodes OM5, OM6, OM7, and an electrode OM8, each of which is connected to each of the electrodes OL5, OL6, OL7, and the electrode OL8 via the wiring path WP3. Has been.
- the electrode group GR2 of the logic chip 30B includes electrodes OL1, OL2, OL3, and an electrode OL4.
- the electrode group GR2 of the memory chip 30A includes electrodes OM1, OM2, OM3, and an electrode OM4, each of which is connected to each of the electrodes OL1, OL2, OL3, and the electrode OL4 via the wiring path WP4. Has been.
- the connection method of the interposer 20B shown in FIGS. 9 to 17 will be described.
- the electrode group GR3 provided at a position relatively close to the side surface 30s1 and the side surface 30s2.
- a wiring path WP5 (see FIG. 12) for connecting is routed through the wiring 22B1 formed in the wiring layer M3 shown in FIG.
- the wiring 22B1 has one end (via wiring 23C) at a position overlapping the logic chip 30B (see FIG. 10) in the thickness direction, and extends toward the memory chip 30A (see FIG. 10).
- the other end (via wiring 23C) of the wiring 22B1 exists at a position overlapping the memory chip 30A in the thickness direction.
- the wiring layer M1 shown in FIG. 10 to the wiring layer M3 shown in FIG. 12 are connected via via wirings 23C (see FIG. 12) laminated so as to overlap each other in the thickness direction.
- the wiring path WP5 is not formed in the wiring layer below the wiring layer M3 shown in FIG. That is, the wiring path WP5 that electrically connects the plurality of electrodes that constitute the electrode group GR3 is mainly routed by the wiring layer M3.
- the wiring path WP6 (see FIG. 13) connecting the electrode group GR4 is routed through the wiring 22B2 formed in the wiring layer M4 shown in FIG.
- the wiring 22B2 has one end (via wiring 23D) at a position overlapping the logic chip 30B (see FIG. 10) in the thickness direction, and extends toward the memory chip 30A (see FIG. 10).
- the other end (via wiring 23D) of the wiring 22B2 exists at a position overlapping the memory chip 30A in the thickness direction.
- the wiring layer M1 shown in FIG. 10 to the wiring layer M4 shown in FIG. 13 are connected via via wirings 23D (see FIG. 12 and FIG. 13) stacked so as to overlap each other in the thickness direction.
- the wiring path WP6 is not formed in the wiring layer below the wiring layer M4 shown in FIG. That is, the wiring path WP6 that electrically connects the plurality of electrodes that constitute the electrode group GR4 is mainly routed by the wiring layer M4.
- the plurality of first group electrodes GM1 of the logic chip 30B and the plurality of first group electrodes GM1 of the memory chip 30A are connected by the above-described mirror arrangement method. Therefore, in each layer from the wiring layer M1 shown in FIG. 10 to the wiring layer M4 shown in FIG. 13, the plurality of wiring paths WP5 and the plurality of wiring paths WP6 do not cross each other.
- the wiring path WP3 (see FIG. 12) for connecting the electrode group GR1 is shown in FIG.
- the wiring 22A1 has one end (via wiring 23A) at a position overlapping the logic chip 30B (see FIG. 10) in the thickness direction, and extends in a direction away from the memory chip 30A (see FIG. 10).
- the wiring 22C2 has one end at a position overlapping the memory chip 30A in the thickness direction, and extends in a direction away from the logic chip 30B (see FIG. 10).
- via wiring 23A (see FIG. 12), which is laminated so as to overlap each other in the thickness direction, from the wiring layer M1 shown in FIG. 10 to the one end of the wiring 22A1 of the wiring layer M3 shown in FIG. Connected through. Further, the via wiring 23A (see FIGS. 12, 13, and 16) laminated so as to overlap each other in the thickness direction from the other end of the wiring 22A1 shown in FIG. 12 to the wiring layer M7 shown in FIG. ), And through-hole wiring 24 (see FIGS. 14 and 15). Also, the via wiring 23A shown in FIG. 16 is one end of the wiring 22D1.
- the wiring 22D1 formed in the wiring layer M7 shown in FIG. 16 straddles the side surface 30s1 and the side surface 30s2 in order from the one end portion (via wiring 23A) to the other end portion (via wiring 23A). It extends like so. Therefore, the wiring 22D1 includes at least a portion overlapping the logic chip 30B (see FIG. 10) in the thickness direction, a portion overlapping the memory chip 30A (see FIG. 10) in the thickness direction, and the logic chip 30B and the memory chip 30A. And a portion that does not overlap in the thickness direction.
- via wirings 23A are stacked so as to overlap each other in the thickness direction from the wiring layer M1 shown in FIG. 10 to the other end of the wiring 22C2 of the wiring layer M4 shown in FIG. Connected) through Also, via wiring 23A (stacked so as to overlap each other in the thickness direction from the one end of the wiring 22C2 shown in FIG. 13 to the other end of the wiring 22D1 of the wiring layer M7 shown in FIG. 13 and 16), and through-hole wiring 24 (see FIGS. 14 and 15).
- the wiring path WP4 (see FIG. 12) for connecting the electrode group GR2 is shown in FIG. Is routed through a wiring 22C1 formed in the wiring layer M3 shown in FIG. 17, a wiring (signal wiring) 22D2 formed in the wiring layer M8 shown in FIG. 17, and a wiring 22A2 formed in the wiring layer M4 shown in FIG.
- the wiring 22A2 has one end (via wiring 23A) at a position overlapping the logic chip 30B (see FIG. 10) in the thickness direction, and extends in a direction away from the memory chip 30A (see FIG. 10).
- the wiring 22C1 has one end at a position overlapping the memory chip 30A in the thickness direction, and extends in a direction away from the logic chip 30B (see FIG. 10).
- via wiring 23B (see FIG. 12), which is laminated so as to overlap each other in the thickness direction, from the wiring layer M1 shown in FIG. 10 to the one end of the wiring 22A2 of the wiring layer M4 shown in FIG. Connected through.
- the via wiring 23B (FIGS. 12, 13, 16, and 16) stacked so as to overlap each other in the thickness direction from the other end of the wiring 22A2 shown in FIG. 13 to the wiring layer M8 shown in FIG. 17) and through-hole wiring 24 (see FIGS. 14 and 15).
- the via wiring 23B shown in FIG. 17 is one end of the wiring 22D2.
- the wiring 22D2 formed in the wiring layer M8 shown in FIG. 17 straddles the side surface 30s1 and the side surface 30s2 in order from the one end portion (via wiring 23B) to the other end portion (via wiring 23B). It extends like so. Therefore, the wiring 22D2 includes at least a portion overlapping the logic chip 30B (see FIG. 10) in the thickness direction, a portion overlapping the memory chip 30A (see FIG. 10) in the thickness direction, and the logic chip 30B and the memory chip 30A. And a portion that does not overlap in the thickness direction.
- via wiring 23B (see FIG. 12), which is laminated so as to overlap each other in the thickness direction, from the wiring layer M1 shown in FIG. 10 to the other end of the wiring 22C1 of the wiring layer M3 shown in FIG. Connected through.
- via wiring 23B (stacked so as to overlap each other in the thickness direction from the one end of the wiring 22C1 shown in FIG. 12 to the other end of the wiring 22D2 of the wiring layer M8 shown in FIG. 12, 13, 16 and 17) and through-hole wiring 24 (see FIGS. 14 and 15).
- the wiring path WP3 that electrically connects the plurality of electrodes constituting the electrode group GR1 is mainly routed by the wiring layers M3 and M7 and the wiring layer M4.
- the wiring path WP4 that electrically connects the plurality of electrodes constituting the electrode group GR2 is mainly routed by the wiring layers M4 and M8 and the wiring layer M3.
- the electrode group GR1 and the electrode group GR2 are connected by the above-described parallel movement arrangement method. For this reason, the wiring path WP3 and the wiring path WP4 are three-dimensionally crossed somewhere in the interposer 20B. In the example of the present embodiment, the wiring path WP3 and the wiring path WP4 are three-dimensionally crossed at the portion A of the wiring layer M7 surrounded by a two-dot chain line in FIG.
- the wiring layer M7 is part of the wiring path WP4 between the plurality of wirings 22D1 which are part of the wiring path WP3.
- Via wiring 23B is arranged.
- a plurality of wirings 22D1 that are part of the wiring path WP3 are arranged between the via wirings 23B that are part of the wiring path WP4. Since the interposer 20B is formed so as to reduce the portion where the wiring paths intersect three-dimensionally as much as possible, there is no portion where the wiring paths intersect three-dimensionally other than the portion A shown in FIG.
- the arrangement density of wiring routes becomes higher than other portions, so it is necessary to avoid contact between the wiring routes.
- the detour distance of the wiring 22D1 is increased in order to avoid contact between the wiring paths, the signal transmission distance is increased.
- a plurality of via wirings are provided along the extending direction of the plurality of wirings 22D1 at a portion where the plurality of wiring paths WP3 and the plurality of wiring paths WP4 intersect each other.
- 23B are arranged side by side.
- the plurality of via wirings 23B are arranged in a line between two wirings 22D1 extending adjacent to each other along the direction DL1.
- the plurality of wirings 22D1 and the plurality of via wirings 23B arranged in a row are alternately arranged. Yes.
- each of the plurality of wirings 22D1 can be arranged so as to extend linearly. As a result, it is possible to suppress an increase in the signal transmission path distance in a portion where the plurality of wiring paths WP3 and the plurality of wiring paths WP4 intersect three-dimensionally.
- the wiring route WP3 and the wiring path WP4 may cross three-dimensionally in a part of the region 20M shown in FIG.
- the core layer 21c is a layer lower than the core layer 21c (see FIG. 9) having the plurality of through-hole wirings 24 (see FIG. 9) (on the lower surface 20b side shown in FIG. 9). There is more wiring space than the upper layer (upper surface 20t side shown in FIG. 9). Therefore, it is particularly preferable to make a three-dimensional intersection in the wiring layer M7 (see FIG. 16) below the core layer 21c as in the present embodiment.
- each is arranged in a zigzag (in a staggered pattern).
- the wiring route distance can be shortened.
- the region that does not overlap with the memory chip 30A and the logic chip 30B in the thickness direction as shown in FIGS. 12 and 13, in a region overlapping with the memory chip 30 ⁇ / b> A (see FIG. 10) and the logic chip 30 ⁇ / b> B (see FIG. 10) in the thickness direction.
- the plurality of via wirings 23 extend in the extending direction of the plurality of wirings. It is lined up along.
- the region that does not overlap with the memory chip 30A and the logic chip 30B in the thickness direction is a region where a part of the wiring path WP1 is disposed.
- the plurality of via wirings 23 are arranged along the extending direction of the plurality of wirings in the region where a part of the wiring path WP1 is provided. Specifically, in the wiring path WP1, in a region where a part of the plurality of wirings 22A1 shown in FIG. 12, a part of the plurality of wirings 22C1, a part of the plurality of wirings 22A2 shown in FIG. 13, and a part of the plurality of wirings 22C2 are provided.
- the plurality of via wirings 23 are arranged along the extending direction of the plurality of wirings. Further, in the region where the entire plurality of wirings 22D1 shown in FIG. 16 and the entire plurality of wirings 22D2 shown in FIG.
- the plurality of via wirings 23 are arranged along the extending direction of the plurality of wirings. Yes. For this reason, since a plurality of wires constituting the wiring route WP1 can be extended linearly, the route distances of the plurality of wiring routes WP1 can be shortened.
- the via wirings 23A, 23B, 23C and the via wiring 23D are stacked so as to overlap each other in the thickness direction. Described.
- FIG. 9 in the case of the method of laminating the via wiring 23 in which the center line of another via wiring 23 is arranged on the center line of the lower via wiring 23, the manufacturing process becomes complicated. .
- FIG. 18 the via wiring 23 connected to the lower layer and the via wiring 23 connected to the upper layer are arranged adjacent to each other, and the conductor pattern CDP is provided between the adjacent via wirings 23 to be connected. There is a way.
- the length of the conductor pattern CDP is as long as the routing wiring (for example, the wiring 22A1 shown in FIG. 12), it is necessary to consider the influence on the length of the signal transmission path. However, as shown in FIG. 18, if the conductor pattern CDP is long enough to connect between the via wirings 23 formed adjacent to each other, the influence on the signal transmission characteristics by the conductor pattern CDP is , Small enough to ignore.
- the plurality of via wirings 23B constituting a part of the signal transmission path constitute a part of the reference potential supply path (reference potential lines VS1, VS2 shown in FIG. 18). It is arranged between the via wiring 23 to be performed. Specifically, the plurality of via wirings 23B and the plurality of reference potential supply via wirings 23 are alternately arranged along the extending direction of the wiring 22D1. 12 to 17, in each of the plurality of wiring layers, the via wiring 23A and the via wiring 23B that constitute a part of the wiring path WP1 are connected to the memory chip 30A (see FIG.
- the via wiring 23A and the via wiring 23B that constitute a part of the wiring path WP1, and the plurality of reference potential supply via wirings 23 are alternately arranged along the extending direction of the wiring 22D1.
- the signal transmission path via wirings 23A and 23B are arranged between the reference potential supply via wirings 23, the signal transmission path is used when the reference potential supply via wiring 23 is used as a signal return path. And the return path route is closer. For this reason, the influence of noise on the signal transmission path can be reduced. If the via wirings 23A and 23B for the signal transmission path are arranged between the via wirings 23 for supplying the reference potential, it becomes easy to arrange the shield line next to the signal transmission path.
- a part of the plurality of through-hole wirings 24 in the plan view includes a plurality of second group electrodes GL2 (see FIG. 10) and It overlaps with a part of the plurality of second group electrodes GM2 (see FIG. 10).
- the plurality of second group electrodes GL2 of the logic chip 30B and the plurality of second group electrodes GM2 of the memory chip 30A are connected via the wiring path WP3 shown in FIGS.
- the electrode group GR2 connected via the wiring path WP4 shown in FIG. 12 to FIG.
- a part of the plurality of through-hole wirings 24 may overlap with a part of the plurality of second group electrodes GL2 and the plurality of second group electrodes GM2. Contact of a plurality of wiring paths can be avoided.
- the semiconductor device PKG1 can be downsized.
- the longest wiring among the wirings constituting the wiring path WP1 is the wiring 22D1 shown in FIG. 16 and the wiring 22D2 shown in FIG. For this reason, when considering the equal length of the wiring path WP1, it is particularly preferable to equalize the lengths of the plurality of wirings 22D1 shown in FIG. 16 and the plurality of wirings 22D2 shown in FIG.
- FIGS. 16, 17, and 19 the direction in which each of the plurality of wirings 22D1 and the plurality of wirings 22D2 is connected to the via wiring 23 is devised to provide a plurality of wirings 22D1.
- the plurality of wirings 22D2 are made equal in length.
- FIG. 19 is an enlarged plan view schematically showing the layout of the signal transmission wirings shown in FIGS. 16 and 17.
- the plurality of via wirings 23 connected to the plurality of wirings 22D1 and the plurality of wirings 22D2 It arrange
- each of the plurality of wirings 22D1 and the plurality of wirings 22D2 bends at a portion immediately before being connected to at least the via wiring 23 (in other words, a portion that bypasses). It is necessary to have.
- the detour paths of the plurality of wirings 22D1 and the plurality of wirings 22D2 become complicated, and the length may vary.
- the wiring layer M7 includes a plurality of via wirings (end via wiring) 23d1 to which one end of the plurality of wirings 22D1 is connected and a plurality of via wirings (ends to which the other end of the plurality of wirings 22D1 is connected. Partial via wiring) 23d2.
- the wiring layer M8 includes a plurality of via wirings (end via wiring) 23d3 to which one end of the plurality of wirings 22D2 is connected, and a plurality of via wirings to which the other end of the plurality of wirings 22D2 is connected. (End via wiring) 23d4 is provided.
- Each of the plurality of via wirings 23d1, the plurality of via wirings 23d2, the plurality of via wirings 23d3, and the plurality of via wirings 23d4 has a portion VP1 and a portion VP2 that face each other via a boundary line (virtual line) VL1. is doing. Further, the part VP1 and the part VP2 are arranged in order along the direction DL3 among the direction DL3 orthogonal to the direction DL1 (or the direction DL2) and the direction DL4 opposite to the direction DL3.
- one end of the plurality of wirings 22D1 is connected to the first part of each of the plurality of via wirings 23d1.
- the other end of the plurality of wirings 22D1 is connected to the second part of each of the plurality of via wirings 23d2.
- One end of the plurality of wirings 22D2 is connected to each portion VP1 of the plurality of via wirings 23d3.
- the other ends of the plurality of wirings 22D2 are connected to the respective portions VP2 of the plurality of via wirings 23d4.
- the lengths of the plurality of wirings 22D1 and the plurality of wirings 22D2 are made equal by defining the direction in which each of the plurality of wirings 22D1 and the plurality of wirings 22D2 is connected to the via wiring 23. can do.
- each of the plurality of wirings 22D1 and the plurality of wirings 22D2 has two bent portions BP1 and BP2.
- the length of the part RT1 from the bent part BP1 to the via wiring 23 is longer than the length of the part RT2 from the bent part BP2 to the part BP2 to the via wiring 23.
- the length of the plurality of portions RT1 and the length of the plurality of portions RT2 are equal.
- the lengths of the plurality of wirings 22D1 and the plurality of wirings 22D2 from the bent portion BP1 to the bent portion BP2 are equal. Accordingly, the lengths of the plurality of wirings 22D1 and the plurality of wirings 22D2 are equal.
- FIG. 20 is an explanatory diagram showing a circuit configuration example when a semiconductor device which is a modification of the semiconductor device shown in FIG. 4 is mounted on a mounting substrate.
- FIG. 21 is an explanatory diagram schematically showing an example of a method for connecting the power supply wiring and the reference potential wiring in the circuit configuration shown in FIG.
- FIG. 22 is an explanatory view showing a modification to FIG.
- FIG. 23 is an enlarged cross-sectional view of a main part showing an arrangement example of the electrodes of the logic chip shown in FIG.
- FIG. 24 is an enlarged cross-sectional view of a main part showing an arrangement example of the electrodes of the logic chip shown in FIG.
- 21 to 24 are cross-sectional views, but hatching is omitted for easy viewing.
- the electrodes 33 shown in FIGS. 23 and 24 are hatched differently from each other between the signal transmission electrode 33 and the power supply potential or reference potential supply electrode 33.
- the signal transmission path is indicated by a one-dot chain line for easy identification of the signal transmission path and the supply path for the power supply potential and the reference potential (however, the through holes shown in FIGS. 21 and 22). Excluding wiring 24).
- FIG. 21 and FIG. 22 an example of the layout of the signal line SIG for transmitting a signal between the logic chip 30B and the external device 40 shown in FIG.
- the power supply line VD1, the power supply line VD2, and the power supply line VD3 are each independently connected to the interposer 20A.
- the interposer 20C included in the semiconductor device PKG3 and the interposer 20D included in the semiconductor device PKG4 illustrated in FIG. 20 are supplied with the power supply potential for the operation of the logic chip 30B from the power supply line VD1 and to the memory from the power supply line VD2.
- the power supply potential for operation of the logic chip 30A is supplied to the chip 30A.
- the logic chip 30B has a voltage conversion circuit CVT that converts the voltage level of the signal.
- the voltage level is converted in order to input and output signals between the memory chip 30A and the logic chip 30B. Further, a reference potential such as a ground potential is supplied from the reference potential line VS1 to the interposer 20C included in the semiconductor device PKG3 and the interposer 20D included in the semiconductor device PKG4 illustrated in FIG. 20, and is supplied to each of the memory chip 30A and the logic chip 30B. Supplied.
- the arrangement of the electrodes 33 provided in the logic chip 30B and the memory chip 30A is the same as the semiconductor device PKG1 shown in FIG. 6 and the semiconductor device PKG2 shown in FIG.
- the plurality of first group electrodes GL1 and the plurality of second group electrodes GL2 are collectively arranged on the side surface 30s1 side of the logic chip 30B, and the power supply electrode PVD for supplying the power supply potential and the reference are separated from the side surface 30s1.
- a potential electrode PVS is provided.
- first group electrodes GM1 and a plurality of second group electrodes GM2 are collectively arranged on the side surface 30s1 side of the memory chip 30A, and a power supply electrode PVD that supplies a power supply potential and a reference are separated from the side surface 30s1.
- a potential electrode PVS is provided.
- the arrangement of the electrodes 33 provided in the logic chip 30B is different from the case of the semiconductor device PKG3 shown in FIG.
- the plurality of electrodes 33 provided in the logic chip 30B of the semiconductor device PKG4 are arranged as follows. Between the plurality of second group electrodes GL2 and the plurality of first group electrodes GL1 included in the logic chip 30B of the semiconductor device PKG4, a power supply electrode PVD that supplies a power supply potential to the logic chip 30B, and a reference potential to the logic chip 30B. And a reference electric potential electrode PVS for supplying.
- the logic chip 30B includes a control circuit that controls the operation of the main memory circuit of the memory chip 30A. Further, the logic chip 30B includes an arithmetic processing circuit that performs arithmetic processing on the input data signal.
- main circuits such as an arithmetic processing circuit and a control circuit are shown as a core circuit (main circuit) CORE1.
- the logic chip 30B converts the voltage level of the signal between the voltage level used in the input / output buffer and the voltage level used in the internal circuit or the like.
- a conversion circuit CVT is provided. Further, the core circuit CORE1 and the voltage conversion circuit CVT of the logic chip 30B and the electrode 33 of the logic chip 30B are connected via a plurality of wirings 36 formed in the wiring layer 32 of the logic chip 30B.
- the core circuit CORE1 of the logic chip 30B has a larger power consumption per unit area than the core circuit CORE2 of the memory chip 30A shown in FIG. For this reason, if the supply amount of power is momentarily insufficient, a phenomenon such as a voltage drop occurs, and there is a concern that the circuit operation becomes unstable.
- the cross-sectional area (cross-sectional area of the wiring path) of each of the plurality of wirings 36 formed on the logic chip 30B is, for example, from the cross-sectional area (cross-sectional area of the wiring path) of the plurality of wirings 22 of the interposer 20A shown in FIG. small. For this reason, when the transmission distance by the wiring 36 becomes long, a voltage may fall.
- the core circuit CORE1 is interposed between the voltage conversion circuit CVT and the power supply electrode PVD for supplying the power supply potential to the voltage conversion circuit CVT. For this reason, when the power consumption in the core circuit CORE1 rapidly increases, there is a concern that the voltage supplied to the voltage conversion circuit CVT is insufficient.
- the core circuit CORE1 is not interposed between the voltage conversion circuit CVT and the power supply electrode PVD for supplying the power supply potential to the voltage conversion circuit CVT. For this reason, the voltage supplied to the voltage conversion circuit CVT is difficult to decrease due to a change in power demand in the core circuit CORE1.
- the power supply electrode PVD and the reference potential electrode PVS are provided between the plurality of first group electrodes GL1 and the plurality of second group electrodes GL2, the power supply electrode PVD and the reference potential electrode PVS are provided.
- route distance to the voltage conversion circuit CVT can be suppressed.
- the plurality of second group electrodes GL2 are provided between the plurality of power supply electrodes PVD and the plurality of reference potential electrodes PVS. For this reason, it is possible to reduce the possibility of an instantaneous voltage drop in the path for supplying power to the core circuit CORE1.
- the semiconductor device PKG4 shown in FIGS. 22 and 24 is preferable from the viewpoint of stabilizing the circuit operation of the logic chip 30B as described above.
- the semiconductor device PKG3 shown in FIGS. 21 and 23 the plurality of first group electrodes GL1 and the plurality of second group electrodes GL2 are arranged so as to be adjacent to each other, so that the wiring path WP1 shown in FIG. Can be shortened.
- the arrangement of the electrodes 33 provided in the memory chip 30A of the semiconductor device PKG4 is the same as that of the semiconductor device PKG3 shown in FIG. That is, the plurality of second group electrodes GM2 and the plurality of first group electrodes GM1 provided in the memory chip 30A of the semiconductor device PKG4 are arranged so as to be adjacent to each other. Thereby, an increase in the route distance of the wiring route WP1 shown in FIG. 22 can be suppressed.
- the electrodes 33 may be arranged in the same manner as the logic chip 30B. That is, between the plurality of second group electrodes GM2 and the plurality of first group electrodes GM1 provided in the memory chip 30A, the power supply electrode PVD that supplies the power supply potential to the memory chip 30A and the reference potential to the memory chip 30A.
- a reference potential electrode PVS may be arranged.
- FIG. 25 is a cross-sectional view showing a modification of FIG.
- the interposer 20E shown in FIG. 25 is different from the interposer 20C shown in FIG. 21 in that it includes a silicon substrate (base material) 28 having a main surface 28t. Further, the interposer 20E is different from the interposer 20C in that it does not have the core layer 21c and the plurality of through-hole wirings 24 shown in FIG.
- the interposer 20E includes a plurality of through electrodes 29 that penetrate the silicon substrate 28 in the thickness direction (the direction from one surface to the other surface of the main surface 28t and the lower surface 20b).
- the plurality of through electrodes 29 are conductive paths formed by embedding a conductor such as copper (Cu) in a through hole formed so as to penetrate the silicon substrate 28 in the thickness direction.
- Each of the plurality of through electrodes 29 has one end connected to the lower surface terminal 26 and the other end connected to the wiring 22 of the wiring layer.
- a through electrode 29 is interposed in a path that electrically connects 10 (see FIG. 20).
- the interposer 20E has a plurality of wiring layers arranged on the main surface 28t, and a plurality of wiring paths WP1 and WP2 are formed in each of the plurality of wiring layers. This is the same as the interposer 20C shown in FIG.
- the plurality of wiring paths WP1 and WP2 may be electrically separated from the wiring board 10 (see FIG. 20). For this reason, the wiring path WP1 and the wiring path WP2 are separated from the plurality of through electrodes 29.
- the wiring layer provided in the interposer 20E is manufactured in the same manner as the process of forming a wiring layer electrically connected to the semiconductor element on the semiconductor chip, such as the wiring layer 32 of the logic chip 30B shown in FIG. The For this reason, wiring with a smaller cross-sectional area than the plurality of wirings included in the interposer 20C shown in FIG. 21 can be formed with high density.
- an interposer that uses the silicon substrate 28 as a base material is called a silicon interposer.
- the difference in the route distance of the wiring route WP1 tends to be particularly large when the through-hole wiring 24 is interposed between the wiring routes WP1.
- the plurality of wirings 22D include the wiring layers M1, M2, M3, and the wiring layer M4 in which the plurality of wirings 22A, the plurality of wirings 22B, and the plurality of wirings 22C shown in FIG.
- An example in which different wiring layers are formed has been described.
- each of the plurality of wiring layers 22D may be formed on the same wiring layer as the wiring layer on which the plurality of wirings 22B are formed.
- the detour distance of the wiring 22D is further increased. Therefore, by applying the parallel movement arrangement method described above, the difference in the path distance of the wiring 22D can be reduced.
- the semiconductor chip is taken up as the semiconductor component mounted on the interposer.
- various modifications can be applied to the semiconductor component.
- a semiconductor chip stacked body in which a plurality of semiconductor chips are stacked may be used.
- a semiconductor package in which a semiconductor chip is mounted on a base material such as a wiring board may be used.
- FIG. 26 is an explanatory diagram showing an outline of the manufacturing process of the semiconductor device described with reference to FIGS.
- interposer preparation step First, in the interposer preparation step, the interposer 20A shown in FIGS. 5 to 8, the interposer 20B shown in FIGS. 10 to 17, the interposer 20C shown in FIG. 21, the interposer 20D shown in FIG. 22, or the interposer 20E shown in FIG. To do.
- a method for manufacturing the interposers 20A, 20B, 20C, and 20D includes forming a plurality of through-hole wirings 24 in the core layer 21c, A plurality of wiring layers are stacked on each of the upper surface 21t and the lower surface 21b. The wiring layer is laminated by repeating the insulating layer deposition step, conductor burying step, and polishing step.
- a silicon substrate 28 (see FIG. 25), which is a semiconductor wafer, is prepared, and a plurality of wiring layers are stacked on the silicon substrate 28.
- the wiring layer is laminated by repeating the insulating layer deposition process, the conductor embedding process, and the polishing process, for example, in the same manner as the interposer 20A described above.
- a plurality of semiconductor chips 30 are mounted on the interposer 20A as shown in FIG.
- the plurality of semiconductor chips 30 are sequentially mounted so that the surfaces 30t of the plurality of semiconductor chips 30 and the upper surface 20t of the interposer 20A face each other.
- the mounting order is not particularly limited, when there is a difference in the thickness of the plurality of semiconductor chips 30, it is preferable to mount the semiconductor chip 30 having a relatively small thickness first.
- the memory chip 30A there is one memory chip 30A, but a stacked body in which a plurality of memory chips 30A are stacked may be used as the memory chip 30A.
- the stacked body of the memory chips 30A is likely to be thicker than the logic chip 30B. Therefore, it is preferable to mount the logic chip 30B first.
- the plurality of electrodes 33 of the semiconductor chip 30 and the plurality of upper surface terminals 25 of the interposer 20 ⁇ / b> A are electrically connected via the plurality of bump electrodes 35.
- the plurality of bump electrodes 35 are exposed, but underfill resin (not shown) is provided between the semiconductor chip 30 and the interposer 20A so as to cover the periphery of the plurality of bump electrodes 35. May be arranged.
- the underfill resin is an insulating resin, and can cover the bump electrodes 35 by covering the periphery of the plurality of bump electrodes 35.
- the interposer mounting step as shown in FIG. 3, the wiring substrate 10 that is a package substrate is prepared, and the interposer 20 ⁇ / b> A on which a plurality of semiconductor chips 30 are mounted is mounted on the wiring substrate 10. In this step, mounting is performed so that the lower surface 20b of the interposer 20A and the upper surface 10t of the wiring board 10 face each other.
- the plurality of lower surface terminals 26 of the interposer 20 ⁇ / b> A and the plurality of bonding pads 16 of the wiring substrate 10 are electrically connected via bump electrodes 27.
- the plurality of bump electrodes 27 are exposed, but an underfill resin (not shown) is provided between the interposer 20A and the wiring board 10 so as to cover the periphery of the plurality of bump electrodes 27. May be arranged.
- the underfill resin is an insulating resin, and can cover the bump electrodes 27 by covering the periphery of the bump electrodes 27.
- the solder balls 11 are disposed on each of the plurality of lands 12 exposed on the lower surface 10b of the wiring board 10. Then, the plurality of solder balls 11 and the lands 12 are joined by heating the plurality of solder balls 11. Through this step, the plurality of solder balls 11 are electrically connected to the plurality of semiconductor chips 30 (logic chip 30B and memory chip 30A) via the wiring substrate 10.
- the technique described in this embodiment is not limited to a so-called BGA (Ball Grid Array) type semiconductor device in which solder balls 11 are joined in an array.
- the solder ball 11 is not formed and the land 12 is exposed, or the land 12 is shipped with a solder paste thinner than the solder ball 11 so-called LGA.
- the present invention can be applied to a (Land Grid Array) type semiconductor device. In the case of an LGA type semiconductor device, the ball mounting process can be omitted.
- the manufacturing method of the semiconductor device an example of the manufacturing process of the semiconductor devices PKG1, PKG2, PKG3, PKG4, and PKG5 has been described.
- the manufacturing method in which the interposer is mounted on the wiring board after the semiconductor component (semiconductor chip) is mounted on the interposer has been described.
- a plurality of semiconductor components may be mounted on the interposer mounted on the wiring board.
- the interposer after mounting some of the plurality of semiconductor components on the interposer, the interposer may be mounted on the wiring board, and the remaining semiconductor components may be mounted on the interposer on the wiring board.
- the plurality of semiconductor chips when using a laminated body in which a plurality of semiconductor chips are stacked as a semiconductor component, after mounting the interposer on the wiring board, the plurality of semiconductor chips may be sequentially stacked on the interposer mounted on the wiring board. good.
- the modified examples can be applied in combination within a range not departing from the gist of the technical idea described in the above embodiment.
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Abstract
Description
本願において、実施の態様の記載は、必要に応じて、便宜上複数のセクション等に分けて記載するが、特にそうでない旨明示した場合を除き、これらは相互に独立別個のものではなく、記載の前後を問わず、単一の例の各部分、一方が他方の一部詳細または一部または全部の変形例等である。また、原則として、同様の部分は繰り返しの説明を省略する。また、実施の態様における各構成要素は、特にそうでない旨明示した場合、理論的にその数に限定される場合および文脈から明らかにそうでない場合を除き、必須のものではない。
半導体パッケージの態様の一つとして、半導体チップ、あるいは複数の半導体チップが積層された半導体チップ積層体などの半導体部品が、配線基板上に搭載された半導体装置がある。また近年、半導体部品に対する小型化の要求、あるいは高性能化の要求に対応して、半導体部品が有する電極は高密度化する傾向にある。多数の電極が高密度で配列された半導体部品を配線基板に搭載する場合、半導体部品が備える複数の電極と配線基板が備える複数の端子とを、対向配置させて、半田などの導電性部材を介して電気的に接続する、所謂フリップチップ接続方式で搭載する場合が多い。
まず、図1~図4を用いて本実施の形態の半導体装置の構造の概要について説明する。図1は本実施の形態の半導体装置の上面図、図2は、図1に示す半導体装置の下面図である。また、図3は、図1のA-A線に沿った断面図である。また、図4は、図1~図3に示す半導体装置を実装基板に搭載した時の回路構成例を示す説明図である。
回路が含まれていても良い。例えば、ロジックチップ30Bには、例えば一次的にデータを記憶するキャッシュメモリなど、メモリチップ30Aの主記憶回路よりも記憶容量が小さい補助記憶回路(記憶回路)が形成されていても良い。
次に、図1~図4に示す半導体装置PKG1を構成する主な部品について順に説明する。図5は、図3に示すインタポーザの周縁部の一部の拡大断面図である。
次に、図4に示すようにロジックチップ30Bとメモリチップ30Aとを電気的に接続する信号伝送経路の詳細について説明する。図6は、図4に示すロジックチップとメモリチップとを接続する信号伝送経路のレイアウトの例を模式的に示す説明図である。また、図7は、図6に示す複数の電極、複数のスルーホール配線、および複数の電極間を電気的に接続する配線の平面的なレイアウトの例を模式的に示す説明図である。また、図8は、図7に示す複数のスルーホール配線間を電気的に接続する配線のレイアウトの例を模式的に示す説明図である。
次に、複数の配線経路WP1を立体交差させる方法について詳細に説明する。本願で言う「配線経路の立体交差」とは、以下の態様で定義できる。まず、任意に定めた第1の配線層において、複数の第1の配線のそれぞれを介して引き回された複数の第1の配線経路(信号伝送経路)と、上記第1の配線層とは異なる第2の配線層において、複数の第2の配線のそれぞれを介して引き回された複数の第2の配線経路(信号伝送経路)と、を有するインタポーザを考える。上記第2の配線層には、上記複数の第1の配線経路に接続される複数の第1の層間導電路が配置されている。また、上記第1の配線層には、上記複数の第2の配線経路に接続される複数の第2の層間導電路が配置されている。
配線層M7は、複数の配線22D1の一方の端部が接続される複数のビア配線(端部ビア配線)23d1、および複数の配線22D1の他方の端部が接続される複数のビア配線(端部ビア配線)23d2を有している。また、配線層M8は、複数の配線22D2の一方の端部が接続される複数のビア配線(端部ビア配線)23d3、および複数の配線22D2の他方の端部が接続される複数のビア配線(端部ビア配線)23d4を有している。
本実施の形態では、実施の形態の説明中にも複数の変形例について説明したが、以下では、上記以外の変形例について説明する。なお、以下に説明する図20~図24に示す変形例では、電源を供給する経路の配置について詳しく説明するため、信号伝送経路の数は、図6に示す半導体装置PKG1よりもさらに減らして示している。
次に、図1~図25を用いて説明した半導体装置PKG1、PKG2、PKG3、PKG4、PKG5の製造工程について説明する。ただし、上記した半導体装置PKG1、PKG2、PKG3、PKG4、および半導体装置PKG5は、インタポーザに配線層を積層する際の工程が異なる以外は同様の製造方法で製造される。したがって、以下の説明では、代表例として半導体装置PKG1の製造方法を説明する。また、以下の説明では、製造工程の流れを示すフロー図と、図1~図25を必要に応じて参照しながら説明する。図26は、図1~図25を用いて説明した半導体装置の製造工程の概要を示す説明図である。
まず、インタポーザ準備工程では、図5~図8に示すインタポーザ20A、図10~図17に示すインタポーザ20B、図21に示すインタポーザ20C、図22に示すインタポーザ20D、または図25に示すインタポーザ20Eを準備する。インタポーザ20A、20B、20C、20D(以下、製造工程の説明において、代表的にインタポーザ20Aと記載する)の製造方法は、コア層21cに複数のスルーホール配線24を形成した後、コア層21cの上面21tおよび下面21bのそれぞれに対して複数の配線層を積層する。配線層の積層方法は、絶縁層堆積工程、導体埋め込み工程、および研磨工程を繰り返すことにより行う。
次にダイボンド工程では、図3に示すようにインタポーザ20A上に複数の半導体チップ30を搭載する。本工程では、複数の半導体チップ30の表面30tとインタポーザ20Aの上面20tとがそれぞれ対向するように、複数の半導体チップ30を順に搭載する。搭載順序は特に限定されないが、複数の半導体チップ30の厚さに差がある場合には、相対的に厚さが薄い半導体チップ30を先に搭載することが好ましい。
次にインタポーザ搭載工程では、図3に示すようにパッケージ基板である配線基板10を準備して、複数の半導体チップ30が搭載されたインタポーザ20Aを配線基板10上に搭載する。本工程では、インタポーザ20Aの下面20bと配線基板10の上面10tとが対向するように搭載する。
次に、ボールマウント工程では、図3に示すように、配線基板10の下面10bに形成された複数のランド12に、外部端子になる複数の半田ボール11を接合する。
10b 下面(面、実装面)
10s 側面
10t 上面(面、チップ搭載面)
11 半田ボール(外部端子)
12 ランド(外部端子、半田接続用パッド)
13 配線
14 絶縁層
14c コア層(コア材、コア絶縁層、絶縁層)
15 ビア配線
16 ボンディングパッド(端子、インタポーザ搭載面側端子、電極)
17 絶縁膜(ソルダレジスト膜)
20A、20B、20C、20D、20E、20H インタポーザ(中継基板)
20b 下面(面、実装面)
20L、20M 領域
20s 側面
20t 上面(面、チップ搭載面)
21 絶縁層
21b 下面
21c コア層(コア材、コア絶縁層、絶縁層)
21t 上面
22 配線
22A、22A1、22A2、22B、22B1、22B2、22C、22C1、22C2、22D、22D1、22D2 配線(信号配線)
22d1、22d2、22d3、22d4 ビア配線(端部ビア配線)
23、23A、23B、23C、23D ビア配線
24 スルーホール配線
25 上面端子(ボンディングパッド、端子、半導体部品搭載面側端子、部品接続用端子)
26 下面端子(端子、半田接続用パッド、ランド、配線基板接続用端子)
27 バンプ電極
28 シリコン基板(基材)
28t 主面
29 貫通電極
30 半導体チップ(半導体部品)
30A メモリチップ
30b 裏面(主面、下面)
30B ロジックチップ
30B ロジックチップチップ
30s、30s1、30s2 側面
30t 表面(主面、上面)
31 シリコン基板(基材)
31t 主面
32 配線層
33 電極(表面電極、部品電極、パッド)
34 パッシベーション膜
35 バンプ電極
36 配線
40 外部機器
50 電源
60 実装基板
Au 金
B2 (信号配線)
BP1、BP2 屈曲部
BP2 部分
CDP 導体パターン
CMD 制御信号線(信号線)
CORE1、CORE2 コア回路(主回路)
CVT 電圧変換回路
D2 (信号配線)
DL1、DL2、DL3、DL4 方向
DQ データ線(信号線)
DRV1、DRV2 電源回路
GL1、GM1 第1グループ電極(信号用電極、グループ電極)
GL2、GM2 第2グループ電極(信号用電極、グループ電極)
GR1、GR2、GR3、GR4 電極群
IF1 外部インタフェース回路(入出力回路、外部入出力回路)
IF2 内部インタフェース回路(入出力回路、内部入出力回路)
IL1、IL2、IL3、IL4、IL5、IL6、IL7、IL8、IM1、IM2、IM3、IM4、IM5、IM6、IM7、IM8、OL1、OL2、OL3、OL4、OL5、OL6、OL7 、OL8、OM1、OM2、OM3、OM4、OM5、OM6、OM7、OM8、PL1、PL2、PL3、PL4、PL5、PL6、PL7、PL8、PM1、PM2、PM3、PM4、PM5、PM6、PM7、PM8 電極
L1、L2、L3、L4、L5、L6、L7、L8、M1、M2、M3、M4、M5、M6、M7、M8、M9、M10 配線層
PKG1、PKG2、PKG3、PKG4、PKG5 半導体装置
PVD 電源電極
PVS 基準電位電極
RT1、RT2 部分
SIG 信号線
TL5、TL6、TL7、TL8、TM5、TM6、TM7、TM8 スルーホール配線
VD1、VD2、VD3、VDD 電源線
VL1 境界線(仮想線)
VP1、VP2 部分
VS1、VS2 基準電位線
WP1、WP2、WP3、WP4WP5、WP6 配線経路(信号配線経路)
Claims (18)
- 複数の半導体部品が搭載される第1面、前記第1面の反対側に位置する第2面、および前記第1面に設けられた複数の部品接続用端子を備えるインタポーザと、
第1主面、前記第1主面と交差する第1側面、および前記第1主面に設けられた複数の第1部品電極を備え、前記第1主面と前記インタポーザの前記第1面とが対向した状態で前記インタポーザの前記第1面上に搭載される第1半導体部品と、
第2主面、前記第2主面と交差する第2側面、および前記第2主面に設けられた複数の第2部品電極を備え、前記第2主面と前記インタポーザの前記第1面とが対向し、かつ、前記第2側面と前記第1半導体部品の前記第1側面とが対向した状態で前記インタポーザの前記第1面上に搭載される第2半導体部品と、
を有し、
前記インタポーザは、
平面視において、前記第1半導体部品と重なる位置に端部を有し、前記第2半導体部品から遠ざかる方向に延びる複数の第1信号配線と、
平面視において、前記第1半導体部品と重なる位置に端部を有し、前記第2半導体部品に近づく方向に延びる複数の第2信号配線と、
平面視において、前記第2半導体部品と重なる位置に端部を有し、前記第1半導体部品から遠ざかる方向に延びる複数の第3信号配線と、
前記第1信号配線と前記第2信号配線とを電気的に接続する複数の第4信号配線と
前記複数の第1信号配線、前記複数の第3信号配線、および前記複数の第4信号配線を介して前記第1半導体部品と前記第2半導体部品とを電気的に接続する複数の第1信号配線経路と、
前記複数の第1信号配線、前記複数の第3信号配線および前記複数の第4信号配線を介さず、かつ、前記複数の第2信号配線を介して前記第1半導体部品と前記第2半導体部品とを電気的に接続する複数の第2信号配線経路と、
を備え、
前記第1半導体部品の前記複数の第1部品電極は、前記複数の第1信号配線経路に接続される複数の信号用第1電極、および前記複数の第2信号配線経路に接続される複数の信号用第2電極を有し、
前記第2半導体部品の前記複数の第2部品電極は、前記複数の第1信号配線経路を介して前記第1半導体部品の前記複数の信号用第1電極に接続される複数の信号用第3電極、および前記複数の第2信号配線経路を介して前記複数の信号用第2電極に接続される複数の信号用第4電極を有し、
前記第1半導体部品の前記複数の信号用第1電極は、平面視において、前記第1側面に近い側から遠い側に向かう第1方向に沿って配列される、第1電極、第2電極、および第3電極を含み、
前記第2半導体部品の前記複数の信号用第3電極は、平面視において、前記第2側面から遠い側から近い側に向かう前記第1方向に沿って配列される、第4電極、第5電極、および第6電極を含み、
前記第1半導体部品の前記第1電極は、前記第2半導体部品の前記第4電極と電気的に接続され、前記第1半導体部品の前記第2電極は、前記第2半導体部品の前記第5電極と電気的に接続され、前記第1半導体部品の前記第3電極は、前記第2半導体部品の前記第6電極と電気的に接続される、半導体装置。 - 請求項1において、
前記複数の第4信号配線のそれぞれは、前記複数の第1信号配線、前記複数の第2信号配線、および前記複数の第3信号配線が形成された配線層とは異なる配線層に形成されている、半導体装置。 - 請求項2において、
前記インタポーザは、
第1面と前記第2面との間に位置する第3面、前記第3面の反対側に位置し、かつ、前記第3面と前記第2面との間に設けられた第4面、および前記第3面および前記第4面のうちの一方から他方までを貫通している複数のスルーホール配線を含むコア絶縁層、を備え、
前記複数のスルーホール配線は、
前記第1半導体部品の前記第1側面に近い側から遠い側に向かう第1方向に沿って配列される、第1スルーホール配線、第2スルーホール配線、および第3スルーホール配線と、
前記第2半導体部品の前記第2側面から遠い側から近い側に向かう前記第1方向に沿って配列される、第4スルーホール配線、第5スルーホール配線、および第6スルーホール配線を含み、
前記第1半導体部品の前記第1電極は、前記第1スルーホール配線および前記第4スルーホール配線を介して、前記第2半導体部品の前記第4電極と電気的に接続され、前記第1半導体部品の前記第2電極は、前記第2スルーホール配線および前記第5スルーホール配線を介して、前記第2半導体部品の前記第5電極と電気的に接続され、前記第1半導体部品の前記第3電極は、前記第3スルーホール配線および前記第6スルーホール配線を介して、前記第2半導体部品の前記第6電極と電気的に接続される、半導体装置。 - 請求項3において、
前記インタポーザは、
前記第1面と前記コア絶縁層との間に設けられた複数の第1面側配線層と、
前記第2面と前記コア絶縁層との間に設けられた複数の第2面側配線層と、
を有し、
前記複数の第1信号配線、前記複数の第2信号配線、および前記複数の第3信号配線のそれぞれは、前記複数の第1面側配線層のうちのいずれかに形成され、
前記複数の第4信号配線のそれぞれは、前記複数の第2面側配線層のうちのいずれかに形成されている、半導体装置。 - 請求項3において、
前記複数の第2信号配線経路のそれぞれは、前記複数のスルーホール配線には接続されていない、半導体装置。 - 請求項1において、
前記第1半導体部品の前記複数の信号用第2電極は、平面視において、前記第1側面に近い側から遠い側に向かう第1方向に沿って配列される、第7電極、第8電極、および第9電極を含み、
前記第2半導体部品の前記複数の信号用第4電極は、平面視において、前記第2側面から近い側から遠い側に向かう第2方向に沿って配列される、第10電極、第11電極、および第12電極を含み、
前記第1半導体部品の前記第7電極は、前記第2半導体部品の前記第10電極と電気的に接続され、前記第1半導体部品の前記第8電極は、前記第2半導体部品の前記第11電極と電気的に接続され、前記第1半導体部品の前記第9電極は、前記第2半導体部品の前記第12電極と電気的に接続されている、半導体装置。 - 請求項1において、
前記複数の第1信号配線は、前記インタポーザの第1配線層に配置された複数の第1配線と、前記第1配線層よりも前記インタポーザの前記第2面側に位置する第2配線層に配置された複数の第2配線と、を含み、
前記複数の第3信号配線は、前記第1配線層に配置された複数の第3配線と、前記第2配線層に配置された複数の第4配線と、を含み、
前記複数の第1信号配線経路は、前記複数の第1配線および前記複数の第4配線を介して前記第1半導体部品と前記第2半導体部品とを電気的に接続する複数の第1配線経路と、前記複数の第2配線および前記複数の第3配線を介して前記第1半導体部品と前記第2半導体部品とを電気的に接続する複数の第2配線経路と、を含み、
前記第1半導体部品の前記第1電極と、前記第2半導体部品の前記第4電極とは、前記複数の第1配線経路および前記複数の第2配線経路のうちの一方を介して電気的に接続され、
前記第1半導体部品の前記第3電極と、前記第2半導体部品の前記第6電極とは、前記複数の第1配線経路および前記複数の第2配線経路のうちの他方を介して電気的に接続されている、半導体装置。 - 請求項7において、
前記複数の第4信号配線は、前記第2配線層よりも前記インタポーザの前記第2面側に位置する第5配線層に配置された複数の第5配線と、前記第5配線層よりも前記インタポーザの前記第2面側に位置する第6配線層に配置された複数の第6配線と、を含み、
前記第1配線経路および前記第2配線経路のうちの一方には、前記複数の第5配線が含まれ、前記第1配線経路および前記第2配線経路のうちの他方には、前記複数の第6配線が含まれている、半導体装置。 - 請求項8において、
前記第5配線層には、前記第6配線層の前記複数の第6配線に接続される複数のビア配線が形成され、
前記複数のビア配線は、前記複数の第5配線のうちの隣り合う二本の配線の間に、前記二本の配線の延在方向に沿って並んでいる、半導体装置。 - 請求項8において、
前記第5配線層は、前記複数の第5配線の一方の端部が接続される複数の第1端部ビア配線、および前記複数の第5配線の他方の端部が接続される複数の第2端部ビア配線を有し、
前記第6配線層は、前記複数の第6配線の一方の端部が接続される複数の第3端部ビア配線、および前記複数の第6配線の他方の端部が接続される複数の第4端部ビア配線を有し、
前記複数の第1端部ビア配線、前記複数の第2端部ビア配線、前記複数の第3端部ビア配線、および前記複数の第4端部ビア配線のそれぞれは、第1仮想線を介して互いに対向する第1部分および第2部分を有し、
前記第1部分および前記第2部分は、前記第1方向に直交する第3方向および前記第3方向の反対の第4方向のうち、前記第3方向に沿って順に並び、
前記複数の第5配線の一方の端部は、前記複数の第1端部ビア配線のそれぞれの前記第1部分に接続され、
前記複数の第5配線の他方の端部は、前記複数の第2端部ビア配線のそれぞれの前記第2部分に接続され、
前記複数の第6配線の一方の端部は、前記複数の第3端部ビア配線のそれぞれの前記第1部分に接続され、
前記複数の第6配線の他方の端部は、前記複数の第4端部ビア配線のそれぞれの前記第2部分に接続されている、半導体装置。 - 請求項7において、
前記インタポーザは、
第1面と前記第2面との間に位置する第3面、前記第3面の反対側に位置し、かつ、前記第3面と前記第2面との間に設けられた第4面、および前記第3面および前記第4面のうちの一方から他方までを貫通している複数のスルーホール配線を含むコア絶縁層、を備え、
前記複数のスルーホール配線は、
前記第1半導体部品の前記第1側面に近い側から遠い側に向かう第1方向に沿って配列される、第1スルーホール配線、第2スルーホール配線、および第3スルーホール配線と、
前記第2半導体部品の前記第2側面から遠い側から近い側に向かう前記第1方向に沿って配列される、第4スルーホール配線、第5スルーホール配線、および第6スルーホール配線を含み、
前記第1半導体部品の前記第1電極は、前記第1スルーホール配線および前記第4スルーホール配線を介して、前記第2半導体部品の前記第4電極と電気的に接続され、前記第1半導体部品の前記第2電極は、前記第2スルーホール配線および前記第5スルーホール配線を介して、前記第2半導体部品の前記第5電極と電気的に接続され、前記第1半導体部品の前記第3電極は、前記第3スルーホール配線および前記第6スルーホール配線を介して、前記第2半導体部品の前記第6電極と電気的に接続される、半導体装置。 - 請求項7において、
前記複数の第2信号配線は、前記第1配線層に配置された複数の第7配線と、前記第2配線層に配置された複数の第8配線と、を含み、
前記複数の第2信号配線経路は、前記複数の第7配線を介して前記第1半導体部品と前記第2半導体部品とを電気的に接続する複数の第3配線経路と、前記複数の第8配線を介して前記第1半導体部品と前記第2半導体部品とを電気的に接続する複数の第4配線経路と、を含み、
前記第1半導体部品の前記複数の信号用第2電極は、平面視において、前記第1側面に近い側から遠い側に向かう第1方向に沿って配列される、第7電極、第8電極、および第9電極を含み、
前記第2半導体部品の前記複数の信号用第4電極は、平面視において、前記第2側面から近い側から遠い側に向かう第2方向に沿って配列される、第10電極、第11電極、および第12電極を含み、
前記第1半導体部品の前記第7電極は、前記複数の第3配線経路および前記複数の第4配線経路のうちの一方を介して前記第2半導体部品の前記第10電極と電気的に接続され、
前記第1半導体部品の前記第8電極は、前記複数の第3配線経路および前記複数の第4配線経路のうちのいずれかを介して前記第2半導体部品の前記第11電極と電気的に接続され、
前記第1半導体部品の前記第9電極は、前記複数の第3配線経路および前記複数の第4配線経路のうちの他方を介して前記第2半導体部品の前記第12電極と電気的に接続されている、半導体装置。 - 請求項7において、
前記インタポーザは、
第1面と前記第2面との間に位置する第3面、前記第3面の反対側に位置し、かつ、前記第3面と前記第2面との間に設けられた第4面、および前記第3面および前記第4面のうちの一方から他方までを貫通している複数のスルーホール配線を含むコア絶縁層、を備え、
平面視において、複数のスルーホール配線のうちの一部は、前記複数の信号用第1電極および前記複数の信号用第3電極のうちの一部と重なっている、半導体装置。 - 請求項1において、
前記インタポーザは、複数の配線層と、前記複数の配線層の間を電気的に接続する複数のビア配線と、を有し、
平面視において、前記複数の第1信号配線、前記複数の第3信号配線、および前記複数の第4信号配線がもうけられた領域では、前記複数のビア配線は、前記複数の第1信号配線、前記複数の第3信号配線、および前記複数の第4信号配線のうちの隣り合う二本の配線の間に、前記二本の配線との延在方向に沿って並んでいる、半導体装置。 - 請求項2において、
前記インタポーザは、複数の配線層と、前記複数の配線層の間を電気的に接続する複数のビア配線と、を有し、
前記複数の配線層のそれぞれにおいて、
前記複数のビア配線のうち、前記第1信号配線経路の一部分を構成する複数の第1ビア配線は、前記複数のビア配線のうち、前記第1半導体部品または前記第2半導体部品に基準電位を供給する複数の第2ビア配線の間に配置されている、半導体装置。 - 請求項1において、
前記第2半導体部品は、メモリ回路を有し、
前記第1半導体部品は、前記第2半導体部品の前記メモリ回路の動作を制御する制御回路、および演算処理回路を有し、
前記第1半導体部品が備える前記複数の信号用第1電極と前記複数の信号用第2電極との間には、前記第1半導体部品に電源電位を供給する第1電源電極と、前記第1半導体部品に基準電位を供給する第1基準電位電極と、が配置されている、半導体装置。 - 請求項1において、
第3面、前記第3面の反対側に位置する第4面、前記第3面に設けられた複数のインタポーザ接続用端子、および前記第4面に設けられた複数の外部端子を備える配線基板、を更に有し、
前記インタポーザは、前記第2面が前記配線基板の前記第3面と対向した状態で、前記配線基板の前記第3面上に搭載されている、半導体装置。 - 複数の半導体部品が搭載される第1面、前記第1面の反対側に位置する第2面、および前記第1面に設けられた複数の部品接続用端子を備えるインタポーザと、
第1主面、前記第1主面と交差する第1側面、および前記第1主面に設けられた複数の第1部品電極を備え、前記第1主面と前記インタポーザの前記第1面とが対向した状態で前記インタポーザの前記第1面上に搭載される第1半導体部品と、
第2主面、前記第2主面と交差する第2側面、および前記第2主面に設けられた複数の第2部品電極を備え、前記第2主面と前記インタポーザの前記第1面とが対向し、かつ、前記第2側面と前記第1半導体部品の前記第1側面とが対向した状態で前記インタポーザの前記第1面上に搭載される第2半導体部品と、
を有し、
前記インタポーザは、
第1面と前記第2面との間に設けられた第3面、前記第3面の反対側に位置し、かつ、前記第3面と前記第2面との間に設けられた第4面、および前記第3面および前記第4面のうちの一方から他方までを貫通している設けられた複数のスルーホール配線を備えるコア絶縁層と、
前記第1面と前記コア絶縁層との間に設けられた複数の第1面側配線層と、
前記第2面と前記コア絶縁層との間に設けられた複数の第2面側配線層と、
前記複数のスルーホール配線を介して前記第1半導体部品と前記第2半導体部品とを電気的に接続する複数の第1信号配線経路と、
前記複数のスルーホール配線を介さずに前記第1半導体部品と前記第2半導体部品とを電気的に接続する複数の第2信号配線経路と、
を備え、
前記第1半導体部品の前記複数の第1部品電極は、前記複数の第1信号配線経路に接続される複数の信号用第1電極、および前記複数の第2信号配線経路に接続される複数の信号用第2電極を有し、
前記第2半導体部品の前記複数の第2部品電極は、前記複数の第1信号配線経路を介して前記第1半導体部品の前記複数の信号用第1電極に接続される複数の信号用第3電極、および前記複数の第2信号配線経路を介して前記複数の信号用第2電極に接続される複数の信号用第4電極を有し、
前記第1半導体部品の前記複数の信号用第1電極は、平面視において、前記第1側面に近い側から前記第1側面から遠い側に向かう第1方向に沿って配列される、第1電極、第2電極、および第3電極を含み、
前記第2半導体部品の前記複数の信号用第3電極は、平面視において、前記第2側面に近い側から前記第2側面から遠い側に向かう第2方向に沿って配列される、第4電極、第5電極、および第6電極を含み、
前記第1半導体部品の前記第1電極は、前記第2半導体部品の前記第6電極と電気的に接続され、前記第1半導体部品の前記第2電極は、前記第2半導体部品の前記第5電極と電気的に接続され、前記第1半導体部品の前記第3電極は、前記第2半導体部品の前記第4電極と電気的に接続される、半導体装置。
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US10403599B2 (en) * | 2017-04-27 | 2019-09-03 | Invensas Corporation | Embedded organic interposers for high bandwidth |
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