WO2016206452A1 - 一种阵列基板及其制作方法、显示面板、显示装置 - Google Patents

一种阵列基板及其制作方法、显示面板、显示装置 Download PDF

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WO2016206452A1
WO2016206452A1 PCT/CN2016/079355 CN2016079355W WO2016206452A1 WO 2016206452 A1 WO2016206452 A1 WO 2016206452A1 CN 2016079355 W CN2016079355 W CN 2016079355W WO 2016206452 A1 WO2016206452 A1 WO 2016206452A1
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common electrode
line
sub
pixel units
data line
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PCT/CN2016/079355
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English (en)
French (fr)
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蔡振飞
宋星星
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US15/513,970 priority Critical patent/US20190051667A1/en
Publication of WO2016206452A1 publication Critical patent/WO2016206452A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134381—Hybrid switching mode, i.e. for applying an electric field with components parallel and orthogonal to the substrates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate, a method for fabricating the same, a display panel, and a display device.
  • Thin Film Transistor Liquid Crystal Display is a commonly used flat panel display. Thin film transistor liquid crystal displays are widely studied and applied for their low voltage, low power consumption, suitable for circuit integration, light and portable.
  • a conventional high-intensity-high-area field-switching (HADS) mode thin film transistor (TFT) substrate is shown in FIG. 1.
  • the HADS mode TFT substrate has a common extending in the horizontal direction.
  • the electrode line 11 and the gate line 12 are data lines 13 extending in the vertical direction.
  • the drain of the TFT 15 is connected to a first Indium Tin Oxide (ITO) layer (not shown) to provide a pixel electrode signal, and a second ITO layer (not shown) passes through the via 14 and the common
  • ITO Indium Tin Oxide
  • the electrode lines 11 are connected to each other to load a common electrode signal.
  • the common electrode line 11 in FIG. 1 is formed using a metal in the same layer as the gate line 12, so that the resistance of the common electrode line 11 is much smaller than the resistance of the second ITO layer. Since the resistance is small, the ability to transmit an electrical signal is strong, and the uniformity of the common electrode signal can be improved.
  • this design requires the via 14 to be separately designed to be connected to the second ITO layer. The design of the via occupies the display area in the pixel, resulting in a decrease in the aperture ratio of the TFT substrate pixel, which is disadvantageous for the improvement of product performance.
  • the design improves the uniformity of the common electrode signal to a certain extent
  • the common electrode line 11 and the common electrode ie, the second ITO layer
  • the contact area is small.
  • the contact resistance is large, so the uniformity of the common electrode signal is still poor. Since the contact resistance is large, it is generally required to design the via 14 every three pixels or each pixel, and the design of the via further reduces the aperture ratio of the pixel.
  • the aperture ratio of the pixel of the prior art HADS mode TFT substrate is low, and the uniformity of the common electrode signal is poor.
  • the embodiment of the invention provides an array substrate and a manufacturing method thereof, a display panel and a display device, which are used for improving the uniformity of the common electrode signal and increasing the aperture ratio of the pixel.
  • An aspect of the present invention provides an array substrate including a plurality of gate lines and a plurality of data lines, a plurality of sub-pixel units arranged in an array, and a thin film transistor corresponding to the plurality of sub-pixel units in one-to-one correspondence, wherein Including a common electrode and a common electrode line;
  • the common electrode line is parallel to the data line, and the data line and the common electrode line are distributed between two adjacent columns of the sub-pixel units, and the common electrode line is in direct contact with the common electrode. Connected, each data line is connected to two columns of sub-pixel units adjacent to the data line;
  • Each row of sub-pixel units has a gate line distributed on two sides thereof, and two gate lines are distributed between adjacent two rows of sub-pixel units, and adjacent two sub-pixel units connected to the same data line in each row are respectively Connected to different gate lines distributed on both sides of the row of sub-pixel units.
  • the common electrode and the common electrode line are electrically connected through the via hole.
  • the common electrode line is directly in contact with the common electrode, and the contact area is large, and the contact resistance is small, so that the common electrode signal can be improved. Uniformity.
  • the common electrode and the common electrode line are in direct contact with the electrical connection, and the through hole is not required, so that the aperture ratio of the pixel can be improved. .
  • the common electrode line and the data line are disposed in the same layer.
  • the common electrode line and the data line are the data lines according to the odd number in the row direction, and the even number is the common electrode line;
  • the common electrode line and the data line are the data lines according to the even number in the row direction, and the odd number is the common electrode line.
  • the array substrate includes a first insulating layer, the first insulating layer is located between the gate line and the common electrode line, and the common electrode is located on the common electrode line, and The common electrode line is in direct contact with the electrical connection.
  • the array substrate includes a pixel electrode that is positioned above the common electrode.
  • the array substrate includes a second insulating layer between the common electrode and the pixel electrode.
  • Another aspect of the present invention provides a display panel comprising the array substrate of any of the above.
  • Another aspect of the present invention provides a display device including the above display panel.
  • Another aspect of the present invention provides a method of fabricating an array substrate, the method comprising:
  • a gate electrode and a gate line are formed on the base substrate, and one gate line is distributed on each side of each row of sub-pixel units and two gate lines are distributed between adjacent two rows of sub-pixel units;
  • each A data line is connected to two columns of sub-pixel units adjacent to the data line, and adjacent two sub-pixel units connected to the same data line in each row respectively have different gate lines distributed on both sides of the row of sub-pixel units connection;
  • a pixel electrode is fabricated, the pixel electrode being electrically connected to the source or the drain through the via.
  • fabricating the common electrode includes:
  • the exposed transparent conductive layer is removed by etching, and the remaining photoresist is removed to form a common electrode.
  • FIG. 1 is a schematic plan view showing a planar structure of a prior art array substrate
  • FIG. 2 is a schematic plan view showing a planar structure of an array substrate according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of a planar structure of another array substrate according to an embodiment of the present invention.
  • Figure 4 is a schematic cross-sectional view taken along line AA1 of Figure 2 or Figure 3;
  • Figure 5 is a schematic cross-sectional view taken along line BB1 of Figure 2 or Figure 3;
  • FIG. 6 is a flowchart of a method for fabricating an array substrate according to an embodiment of the present invention.
  • the embodiment of the invention provides an array substrate and a manufacturing method thereof, a display panel and a display device, which are used for improving the uniformity of the common electrode signal and increasing the aperture ratio of the pixel.
  • an embodiment of the present invention provides an array substrate including a plurality of gate lines 22, a plurality of data lines 23, a plurality of sub-pixel units 20 arranged in an array, and the plurality of sub-pixel units.
  • the common electrode line 25 is parallel to the data line 23, and the data line 23 and the common electrode line 25 are spaced apart from each other between the adjacent two columns of sub-pixel units 20.
  • the common electrode line 25 is in direct contact electrical connection with the common electrode 24, and each of the data lines 23 The two columns of sub-pixel units 20 adjacent to the data line 23 are connected.
  • the common electrode line 25 and the data line 23 may be disposed in the same layer.
  • Each row of sub-pixel units 20 is distributed with a gate line 22 on both sides thereof, and two gate lines are distributed between adjacent two rows of sub-pixel units, and adjacent rows of adjacent two sub-connections on the same data line 23 are connected in each row.
  • the pixel units 20 are respectively connected to different gate lines 22 distributed on both sides of the row of sub-pixel units 20.
  • the common electrode line 25 and the data line 23 may be the data line according to the odd number in the row direction, and the even number is the common electrode line.
  • the first column in the figure is the data line Data1
  • the second column is the common electrode line Com1
  • the third column is the data line Data2
  • the fourth column is the common electrode line Com2
  • the fifth column is the data line Data3.
  • the common electrode line 25 and the data line 23 may be the data line according to the even number in the row direction, and the odd number is the common electrode line.
  • the first column in the figure is the common electrode line Com1
  • the second column is the data line Data1
  • the third column is the common electrode line Com2
  • the fourth column is the data line Data2.
  • the array substrate includes a first insulating layer 41, and the first insulating layer 41 is located between the gate line 22 and the common electrode line 25.
  • the common electrode 24 is located on the common electrode line 25 and is in direct electrical contact with the common electrode line 25.
  • the gate line 22 in the embodiment of the present invention is located on the base substrate 40.
  • the array substrate includes a pixel electrode 51 and a second insulating layer 52, wherein the pixel electrode 51 is located above the common electrode 24, and the second insulating layer 52 is located at the common electrode. Between 24 and the pixel electrode 51.
  • the pixel electrode 51 in the specific embodiment of the present invention is a slit electrode.
  • the common electrode 24 and the common electrode line 25 are in direct contact electrical connection, and the contact area is the entire common electrode line 25.
  • the common electrode and the common electrode line are connected through the via hole, and the contact area of the common electrode and the common electrode line in the embodiment of the invention is large, and the contact resistance is low, so that the uniformity of the common electrode signal can be improved.
  • an embodiment of the present invention further provides a method for fabricating an array substrate, the method comprising:
  • S601 forming a gate and a gate line on the base substrate, one gate line is distributed on each side of each row of sub-pixel units, and two gate lines are distributed between adjacent two rows of sub-pixel units;
  • a metal film layer is deposited on the substrate, and then a gate process (not shown) and a gate line 22 are formed by patterning the metal film layer.
  • the patterning process may include coating, exposing, developing, etching, and removing some or all of the photoresist.
  • the base substrate may be a glass substrate.
  • the base substrate may also be a substrate of a type such as a ceramic substrate.
  • the metal film layer deposited on the base substrate is a single layer film of a metal such as molybdenum (Mo) or metal aluminum (Al). Or a composite film composed of a plurality of metals, the embodiment of the present invention does not specifically limit the material of the metal film layer.
  • the first insulating layer 41 and the semiconductor active layer 26 are formed by a patterning process on the base substrate on which the above steps are completed.
  • the material of the first insulating layer may be a single layer film of silicon oxide (SiO2) or silicon nitride (SiN), or may be a composite film composed of SiO2 and SiN.
  • the embodiment of the present invention does not specifically limit the material of the first insulating layer.
  • the method of fabricating the first insulating layer and the semiconductor active layer may be the same as the prior art, and details are not described herein again.
  • a metal film layer is deposited on the substrate on which the above steps are completed, and then the metal film layer is patterned to form a source (not shown), a drain (not shown), and a data line. 23 and a common electrode line 25.
  • the common electrode line 25 is parallel to the data line 23, and the common electrode line 25 is spaced apart from the data line 23 between adjacent two columns of sub-pixel units 20.
  • the data line 23 and the common electrode line 25 can be fabricated by one patterning process, and the production process is not required, which is simpler and more convenient in the actual production process.
  • the material of the metal film layer deposited on the substrate substrate in this step may be the same as the material of the metal film layer deposited when the gate electrode and the gate line are formed.
  • the metal film layer deposited in this step The material can also be different from the material of the metal film layer deposited when the gate and gate lines are formed.
  • the embodiment of the present invention does not specifically define the material of the metal film layer deposited in the step.
  • a transparent conductive layer is deposited on the substrate on which the above steps are completed.
  • the deposited transparent conductive layer may be an indium tin oxide (ITO) film layer, or may be an indium zinc oxide (IZO) film layer, or may be a composite film layer composed of ITO and IZO.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • the embodiment of the present invention does not specifically limit the material of the transparent conductive layer.
  • a photoresist is coated on the transparent conductive layer, and the photoresist is exposed and developed to retain the photoresist of the common electrode line and the pixel region, and the photoresist in the remaining region is removed, and the photoresist removal region is exposed.
  • Transparent conductive layer is coated on the transparent conductive layer, and the photoresist is exposed and developed to retain the photoresist of the common electrode line and the pixel region, and the photoresist in the remaining region is removed, and the photoresist removal region is exposed.
  • the exposed transparent conductive layer is removed by etching, preferably by wet etching. At this time, only the transparent conductive layer located above the common electrode line and the pixel region is retained, and the transparent conductive layers of the remaining regions are removed. Finally, the remaining photoresist is removed, and a common electrode 24 is formed over the common electrode line and the pixel region, and the common electrode 24 is in direct contact electrical connection with the common electrode line 25.
  • a second insulating layer 52 and a via hole 27 penetrating the second insulating layer 52 are formed by a patterning process on the base substrate on which the above steps are completed.
  • the material of the second insulating layer 52 may be the same as the material of the first insulating layer 41.
  • the material of the second insulating layer and the material of the first insulating layer may also be different.
  • the embodiment of the invention does not apply to the second insulating layer The specific materials are limited.
  • the method for fabricating the second insulating layer and the via hole penetrating the second insulating layer 52 in the embodiment of the present invention may be the same as the prior art, and details are not described herein again.
  • a transparent conductive layer is deposited on the substrate on which the above steps are completed, and then the pixel electrode 51 is formed by patterning the transparent conductive layer, and the pixel electrode 51 is electrically connected to the source or the drain through the via 27.
  • the material of the transparent conductive layer forming the pixel electrode may be the same as the material of the transparent conductive layer forming the common electrode.
  • the material of the transparent conductive layer forming the pixel electrode and the material of the transparent conductive layer forming the common electrode are also Can be different.
  • the embodiment of the present invention does not specifically define the material of the transparent conductive layer forming the pixel electrode.
  • an embodiment of the present invention provides an array substrate, a manufacturing method thereof, a display panel, and a display device.
  • the array substrate includes a plurality of gate lines and a plurality of data lines, a plurality of sub-pixel units arranged in an array, and a thin film transistor corresponding to the plurality of sub-pixel units, wherein the common electrode and the common electrode line are further included;
  • the common electrode line is parallel to the data line, and the data line and the common electrode line are distributed between two adjacent columns of the sub-pixel units, and the common electrode line is in direct contact with the common electrode.
  • each data line is connected with two columns of sub-pixel units adjacent to the data line; each row of sub-pixel units is distributed with one gate line on both sides and two gates are arranged between adjacent two rows of sub-pixel units
  • the polar lines, the adjacent two sub-pixel units connected to the same data line in each row are respectively connected to different gate lines distributed on both sides of the row of sub-pixel units.
  • the common electrode and the common electrode line are electrically connected through the via hole.
  • the common electrode line is directly in electrical contact with the common electrode, the contact area is large, and the contact resistance is relatively small, so that the common electrode can be improved. Signal uniformity.
  • the common electrode and the common electrode line are in direct contact with the electrical connection, and the through hole is not required, so that the aperture ratio of the pixel can be improved. .

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Abstract

一种阵列基板及其制作方法、显示面板、显示装置。阵列基板包括多条栅极线（22）和多条数据线（23），按阵列排列的多个亚像素单元（20）以及与多个亚像素单元（20）一一对应的薄膜晶体管（21），其中，还包括公共电极（24）和公共电极线（25）；公共电极线（25）与数据线（23）平行，相邻两列亚像素单元（20）之间间隔分布有数据线（23）和公共电极线（25），公共电极线（25）与公共电极（24）直接接触电连接，每一条数据线（23）与和其相邻的两列亚像素单元（20）连接；每一行亚像素单元（20）两侧均分布有一条栅极线（22）且相邻两行亚像素单元（20）之间分布有两条栅极线（22），每一行中连接到同一数据线（23）上的相邻两个亚像素单元（20）分别与其所在行亚像素单元（20）两侧分布的不同栅极线（22）连接。

Description

一种阵列基板及其制作方法、显示面板、显示装置 技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板及其制作方法、显示面板、显示装置。
背景技术
薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display，TFT-LCD)是目前常用的平板显示器。薄膜晶体管液晶显示器以其低电压、低功耗、适宜于电路集成、轻巧便携等优点而受到广泛的研究与应用。
目前传统的高开口率-高级超维场转换(High-Advanced Super Dimension Switch，HADS)模式薄膜晶体管(Thin Film Transistor，TFT)基板如图1所示，HADS模式TFT基板具有沿水平方向延伸的公共电极线11和栅极线12，沿竖直方向延伸的数据线13。TFT 15的漏极与第一氧化铟锡(Indium Tin Oxide，ITO)层(图中未示出)相连，提供像素电极信号，第二ITO层(图中未示出)通过过孔14与公共电极线11相连，加载公共电极信号。
图1中的公共电极线11采用与栅极线12同层的金属制作形成，因此公共电极线11的电阻远小于第二ITO层的电阻。由于电阻小，因而传输电信号的能力强，进而能够提高公共电极信号的均匀性。但是，这种设计需要单独设计过孔14从而与第二ITO层相连，过孔的设计会占用像素内的显示面积，导致TFT基板像素的开口率降低，不利于产品性能的提高。另外，这种设计虽然在一定程度上提高了公共电极信号的均匀性，但公共电极线11与公共电极(即第二ITO层)是通过过孔14连接的，属于点接触，接触面积小，接触电阻较大，因此公共电极信号的均匀性仍然较差。由于接触电阻较大，一般需要每隔三个像素或每个像素都设计过孔14，过孔的设计进一步降低了像素的开口率。
综上所述，现有技术HADS模式TFT基板像素的开口率较低，公共电极信号的均匀性较差。
发明内容
本发明实施例提供了一种阵列基板及其制作方法、显示面板、显示装置，用以提高公共电极信号的均匀性，提高像素的开口率。
本发明的一个方面提供一种阵列基板，包括多条栅线和多条数据线，按阵列排列的多个亚像素单元以及与所述多个亚像素单元一一对应的薄膜晶体管，其中，还包括公共电极和公共电极线；
所述公共电极线与所述数据线平行，相邻两列所述亚像素单元之间间隔分布有所述数据线和所述公共电极线，所述公共电极线与所述公共电极直接接触电连接，每一条数据线与和该数据线相邻的两列亚像素单元连接；
每一行亚像素单元两侧均分布有一条栅极线且相邻两行亚像素单元之间分布有两条栅极线，每一行中连接在同一数据线上的相邻两个亚像素单元分别与该行亚像素单元两侧分布的不同栅极线连接。
与现有技术公共电极和公共电极线通过过孔电连接相比，本发明实施例中公共电极线与公共电极直接接触电连接，接触面积较大，接触电阻较小，因此能够提高公共电极信号的均匀性。另外，与现有技术公共电极和公共电极线连接时需要设置过孔相比，本发明实施例中公共电极和公共电极线直接接触电连接，不需要设置过孔，因此能够提高像素的开口率。
在一个实施例中，所述公共电极线和所述数据线同层设置。
在一个实施例中，所述公共电极线与所述数据线按照在行方向上第奇数条为数据线，第偶数条为公共电极线分布；或者
所述公共电极线与所述数据线按照在行方向上第偶数条为数据线，第奇数条为公共电极线分布。
在一个实施例中，所述阵列基板包括第一绝缘层，所述第一绝缘层位于所述栅极线和所述公共电极线之间，所述公共电极位于所述公共电极线上，与所述公共电极线直接接触电连接。
在一个实施例中，所述阵列基板包括像素电极，所述像素电极位于所述公共电极上方。
在一个实施例中，所述阵列基板包括第二绝缘层，所述第二绝缘层位于所述公共电极和所述像素电极之间。
本发明的另一个方面提供了一种显示面板，所述显示面板包括上述任一项的阵列基板。
本发明的另一个方面提供了一种显示装置，所述显示装置包括上述的显示面板。
本发明的另一个方面提供了一种阵列基板的制作方法，所述方法包括：
在衬底基板上制作栅极和栅极线，每一行亚像素单元两侧均分布有一条栅极线且相邻两行亚像素单元之间分布有两条栅极线；
依次制作第一绝缘层和半导体有源层；
制作源极、漏极、数据线和公共电极线，所述公共电极线与所述数据线平行，所述公共电极线与所述数据线间隔分布在相邻两列亚像素单元之间，每一条数据线与和该数据线相邻的两列亚像素单元连接，每一行中连接在同一数据线上的相邻两个亚像素单元分别与该行亚像素单元两侧分布的不同栅极线连接；
制作公共电极，所述公共电极与所述公共电极线直接接触电连接；
制作第二绝缘层和贯穿所述第二绝缘层的过孔；
制作像素电极，所述像素电极通过所述过孔与所述源极或所述漏极电连接。
在一个实施例中，制作公共电极包括：
沉积一层透明导电层；
在所述透明导电层上涂覆光刻胶，并对所述光刻胶进行曝光、显影，保留公共电极线和像素区的光刻胶；
通过刻蚀，去除暴露出的透明导电层，并去除剩余的光刻胶，形成公共电极。
附图说明
图1为现有技术阵列基板的平面结构示意图；
图2为本发明实施例提供的一种阵列基板的平面结构示意图；
图3为本发明实施例提供的另一种阵列基板的平面结构示意图；
图4为图2或图3中沿AA1方向的截面结构示意图；
图5为图2或图3中沿BB1方向的截面结构示意图；
图6为本发明实施例提供的一种阵列基板的制作方法流程图。
具体实施方式
本发明实施例提供了一种阵列基板及其制作方法、显示面板、显示装置，用以提高公共电极信号的均匀性，提高像素的开口率。
为了使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明作进一步地详细描述。显然，所描述的实施例仅仅是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动的前提下所获得的所有其它实施例，都属于本发明保护的范围。
附图中各层薄膜的厚度、大小和形状不反映各膜层的真实比例，目的只是示意说明本发明内容。
下面结合附图详细介绍本发明实施例提供的阵列基板。
如图2所示，本发明实施例提供了一种阵列基板，包括多条栅线22、多条数据线23，、按阵列排列的多个亚像素单元20以及与所述多个亚像素单元20一一对应的薄膜晶体管21、公共电极24和公共电极线25。
公共电极线25与数据线23平行，相邻两列亚像素单元20之间间隔分布有数据线23和公共电极线25，公共电极线25与公共电极24直接接触电连接，每一条数据线23与和该数据线23相邻的两列亚像素单元20连接。公共电极线25和数据线23可以同层设置。
每一行亚像素单元20两侧均分布有一条栅极线22且相邻两行亚像素单元之间分布有两条栅极线，每一行中连接在同一数据线23上的相邻两个亚像素单元20分别与该行亚像素单元20两侧分布的不同栅极线22连接。
本发明实施例中公共电极线25与数据线23可以按照在行方向上第奇数条为数据线，第偶数条为公共电极线分布。如图2所示，图中第一列为数据线Data1，第二列为公共电极线Com1，第三列为数据线Data2，第四列为公共电极线Com2，第五列为数据线Data3。
本发明实施例中公共电极线25与数据线23可以按照在行方向上第偶数条为数据线，第奇数条为公共电极线分布。如图3所示，图中第一列为公共电极线Com1，第二列为数据线Data1，第三列为公共电极线Com2，第四列为数据线Data2。
图2或图3中沿AA1方向的截面图如图4所示，阵列基板包括第一绝缘层41，第一绝缘层41位于栅极线22和公共电极线25之间，公 共电极24位于公共电极线25上，与公共电极线25直接接触电连接。具体地，本发明实施例中的栅极线22位于衬底基板40上。
图2或图3中沿BB1方向的截面图如图5所示，阵列基板包括像素电极51和第二绝缘层52，其中，像素电极51位于公共电极24上方，第二绝缘层52位于公共电极24和像素电极51之间。本发明具体实施例中的像素电极51为狭缝状电极。
由图4和图5可以看到，本发明实施例中公共电极24和公共电极线25直接接触电连接，接触面积为整条公共电极线25。与现有技术中公共电极和公共电极线通过过孔连接相比，本发明实施例中公共电极和公共电极线的接触面积较大，接触电阻较低，因此能够提高公共电极信号的均匀性。
如图6所示，本发明实施例还提供了一种阵列基板的制作方法，所述方法包括：
S601、在衬底基板上制作栅极和栅极线，每一行亚像素单元两侧均分布有一条栅极线且相邻两行亚像素单元之间分布有两条栅极线；
S602、依次制作第一绝缘层和半导体有源层；
S603、制作源极、漏极、数据线和公共电极线，所述公共电极线与所述数据线平行，所述公共电极线与所述数据线间隔分布在相邻两列亚像素单元之间，每一条数据线与和该数据线相邻的两列亚像素单元连接，每一行中连接在同一数据线上的相邻两个亚像素单元分别与该行亚像素单元两侧分布的不同栅极线连接；
S604、制作公共电极，所述公共电极与所述公共电极线直接接触电连接；
S605、制作第二绝缘层和贯穿所述第二绝缘层的过孔；
S606、制作像素电极，所述像素电极通过所述过孔与所述源极或所述漏极电连接。
具体地，参见图2-图5，首先，在衬底基板上沉积一层金属膜层，之后对该金属膜层采用构图工艺形成栅极(图中未示出)和栅极线22。构图工艺可以包括光刻胶的涂覆、曝光、显影、刻蚀以及去除光刻胶的部分或全部过程。具体地，衬底基板可以为玻璃基板，当然，在实际生产过程中，衬底基板还可以为陶瓷基板等类型的基板。在衬底基板上沉积的金属膜层为金属钼(Mo)、金属铝(Al)等金属的单层膜， 或由多种金属组成的复合膜，本发明实施例并不对金属膜层的材料作具体限定。
接着，在完成上述步骤的衬底基板上通过构图工艺制作第一绝缘层41和半导体有源层26。第一绝缘层的材料可以为氧化硅(SiO2)或氮化硅(SiN)的单层膜，或者可以为SiO2和SiN组成的复合膜。本发明实施例并不对第一绝缘层的材料作具体限定。制作第一绝缘层和半导体有源层的方法可以与现有技术相同，这里不再赘述。
接着，在完成上述步骤的衬底基板上沉积一层金属膜层，之后对该金属膜层采用构图工艺形成源极(图中未示出)、漏极(图中未示出)、数据线23和公共电极线25。公共电极线25与数据线23平行，公共电极线25与数据线23间隔分布在相邻两列亚像素单元20之间。本发明实施例通过一次构图工艺即可制作出数据线23和公共电极线25，不需要增加生产工序，在实际生产过程中更加简单、方便。该步骤中在衬底基板上沉积的金属膜层的材料可以与制作栅极和栅极线时沉积的金属膜层的材料相同，当然，在实际生产过程中，该步骤中沉积的金属膜层的材料也可以与制作栅极和栅极线时沉积的金属膜层的材料不同。本发明实施例并不对该步骤中沉积的金属膜层的材料作具体限定。
接着，在完成上述步骤的衬底基板上沉积一层透明导电层。沉积的透明导电层可以为氧化铟锡(ITO)膜层，或者可以为氧化铟锌(IZO)膜层，或者可以为ITO和IZO组成的复合膜层。本发明实施例并不对透明导电层的材料作具体限定。之后，在透明导电层上涂覆光刻胶，并对光刻胶进行曝光、显影，保留公共电极线和像素区的光刻胶，去除其余区域的光刻胶，光刻胶去除区暴露出透明导电层。之后，通过刻蚀，优选地通过湿法刻蚀，去除暴露出的透明导电层。此时，只有位于公共电极线和像素区上方的透明导电层被保留，其余区域的透明导电层均被去掉。最后，去除剩余的光刻胶，在公共电极线和像素区上方形成公共电极24，公共电极24与公共电极线25直接接触电连接。
接着，在完成上述步骤的衬底基板上通过构图工艺制作第二绝缘层52和贯穿第二绝缘层52的过孔27。第二绝缘层52的材料可以与第一绝缘层41的材料相同，当然，在实际生产过程中，第二绝缘层的材料与第一绝缘层的材料也可以不同。本发明实施例并不对第二绝缘层 的具体材料作限定。本发明实施例中制作第二绝缘层和贯穿第二绝缘层52的过孔的方法可以与现有技术相同，这里不再赘述。
接着，在完成上述步骤的衬底基板上沉积一层透明导电层，之后对该透明导电层采用构图工艺形成像素电极51，像素电极51通过过孔27与源极或漏极电连接。形成像素电极的透明导电层的材料可以与形成公共电极的透明导电层的材料相同，当然，在实际生产过程中，形成像素电极的透明导电层的材料与形成公共电极的透明导电层的材料也可以不同。本发明实施例并不对形成像素电极的透明导电层的材料作具体限定。
综上所述，本发明实施例提供一种阵列基板及其制作方法、显示面板、显示装置。阵列基板包括多条栅极线和多条数据线、按阵列排列的多个亚像素单元以及与所述多个亚像素单元一一对应的薄膜晶体管，其中，还包括公共电极和公共电极线；所述公共电极线与所述数据线平行，相邻两列所述亚像素单元之间间隔分布有所述数据线和所述公共电极线，所述公共电极线与所述公共电极直接接触电连接，每一条数据线与和该数据线相邻的两列亚像素单元连接；每一行亚像素单元两侧均分布有一条栅极线且相邻两行亚像素单元之间分布有两条栅极线，每一行中连接在同一数据线上的相邻两个亚像素单元分别与该行亚像素单元两侧分布的不同栅极线连接。与现有技术公共电极和公共电极线通过过孔电连接相比，本发明实施例中公共电极线与公共电极直接接触电连接，接触面积较大，接触电阻相对较小，因此能够提高公共电极信号的均匀性。另外，与现有技术公共电极和公共电极线连接时需要设置过孔相比，本发明实施例中公共电极和公共电极线直接接触电连接，不需要设置过孔，因此能够提高像素的开口率。
显然，本领域的技术人员可以对本发明实施例进行各种修改和变型而不脱离本发明的精神和范围。这样，倘若本发明实施例的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些修改和变型在内。

Claims (10)

  1. 一种阵列基板，包括多条栅极线和多条数据线、按阵列排列的多个亚像素单元以及与所述多个亚像素单元一一对应的薄膜晶体管，其特征在于，还包括公共电极和公共电极线；
    所述公共电极线与所述数据线平行，相邻两列所述亚像素单元之间间隔分布有所述数据线和所述公共电极线，所述公共电极线与所述公共电极直接接触电连接，每一条数据线与和该数据线相邻的两列亚像素单元连接；
    每一行亚像素单元两侧均分布有一条栅极线且相邻两行亚像素单元之间分布有两条栅极线，每一行中连接在同一数据线上的相邻两个亚像素单元分别与该行亚像素单元两侧分布的不同栅极线连接。
  2. 根据权利要求1所述的阵列基板，其特征在于，所述公共电极线和所述数据线同层设置。
  3. 根据权利要求1所述的阵列基板，其特征在于，所述公共电极线与所述数据线按照在行方向上第奇数条为数据线、第偶数条为公共电极线的方式分布；或者
    所述公共电极线与所述数据线按照在行方向上第偶数条为数据线、第奇数条为公共电极线的方式分布。
  4. 根据权利要求1所述的阵列基板，其特征在于，包括第一绝缘层，所述第一绝缘层位于所述栅极线和所述公共电极线之间，所述公共电极位于所述公共电极线上，与所述公共电极线直接接触电连接。
  5. 根据权利要求1所述的阵列基板，其特征在于，包括像素电极，所述像素电极位于所述公共电极上方。
  6. 根据权利要求5所述的阵列基板，其特征在于，包括第二绝缘层，所述第二绝缘层位于所述公共电极和所述像素电极之间。
  7. 一种显示面板，其特征在于，所述显示面板包括权利要求1-6中任一项所述的阵列基板。
  8. 一种显示装置，其特征在于，所述显示装置包括权利要求7所述的显示面板。
  9. 一种阵列基板的制作方法，其特征在于，所述方法包括：
    在衬底基板上制作栅极和栅极线，每一行亚像素单元两侧均分布 有一条栅极线且相邻两行亚像素单元之间分布有两条栅极线；
    依次制作第一绝缘层和半导体有源层；
    制作源极、漏极、数据线和公共电极线，所述公共电极线与所述数据线平行，所述公共电极线与所述数据线间隔分布在相邻两列亚像素单元之间，每一条数据线与和该数据线相邻的两列亚像素单元连接，每一行中连接在同一数据线上的相邻两个亚像素单元分别与该行亚像素单元两侧分布的不同栅极线连接；
    制作公共电极，所述公共电极与所述公共电极线直接接触电连接；
    制作第二绝缘层和贯穿所述第二绝缘层的过孔；
    制作像素电极，所述像素电极通过所述过孔与所述源极或所述漏极电连接。
  10. 根据权利要求9所述的方法，其特征在于，制作公共电极包括：
    沉积一层透明导电层；
    在所述透明导电层上涂覆光刻胶，并对所述光刻胶进行曝光、显影，保留公共电极线和像素区的光刻胶；
    通过刻蚀，去除暴露出的透明导电层，并去除剩余的光刻胶，形成公共电极。
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