WO2016194132A1 - 半導体記憶装置 - Google Patents
半導体記憶装置 Download PDFInfo
- Publication number
- WO2016194132A1 WO2016194132A1 PCT/JP2015/065898 JP2015065898W WO2016194132A1 WO 2016194132 A1 WO2016194132 A1 WO 2016194132A1 JP 2015065898 W JP2015065898 W JP 2015065898W WO 2016194132 A1 WO2016194132 A1 WO 2016194132A1
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- Prior art keywords
- insulating layer
- memory chip
- thin film
- memory device
- input unit
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Definitions
- the present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device including a thin film bypass capacitor.
- Patent Document 1 a technique disclosed in Patent Document 1 is known as a semiconductor memory device including a membrane bypass capacitor.
- the memory chip has a center pad, and the center pad and the substrate wiring formed on the surface opposite to the mounting surface of the substrate are connected to each other by wire bonding through an opening formed on the mounting substrate. It is connected.
- a thin film decoupling capacitor thin film bypass capacitor
- Patent Document 1 discloses a technique for minimizing the parasitic inductance on the electrode structure by forming a thin film bypass capacitor in an adjacent region of the memory chip.
- the clock frequency of the semiconductor memory device is as high as 400 MHz or more, and with the increase in the data bit width, in the semiconductor memory device, the stability of the power supply voltage and the noise reduction at the interface of the multi-bit I / O are reduced. The demands are severe.
- a bypass capacitor ie, a parasitic capacitance between electrodes
- the center pad and an external circuit are connected by wire bonding through the opening of the mounting substrate.
- a bypass capacitor ie, a parasitic capacitance between electrodes
- the required charge cannot be sufficiently supplied at a short distance.
- a semiconductor memory device including a memory chip having a center pad, an effect of reducing power supply noise in a high-frequency interface is improved, and an opening for external connection is required on the memory chip mounting substrate.
- a semiconductor memory device is provided.
- a semiconductor memory device disclosed in the present specification includes a memory chip having a circuit surface including a center pad region in which a plurality of center pads are formed, and a back surface that is a surface opposite to the circuit surface.
- a thin film capacitor provided at a position facing the circuit surface except for the center pad region, and a first insulating layer formed on a side opposite to the memory chip with respect to the thin film capacitor.
- a first insulating layer having a transmission line formed thereon, and the thin film capacitor is supplied with a first power input section to which a power supply voltage of one polarity is supplied to the memory chip.
- a first surface electrode including a first power supply output portion provided in the vicinity of the center pad region for outputting the power supply voltage of the one polarity to the center pad;
- a paraelectric or ferroelectric thin film dielectric layer formed on the first surface electrode excluding the force section and the first power supply output section; and a second surface electrode formed on the thin film dielectric layer.
- a second surface electrode including a second power output unit provided in the transmission line, wherein the transmission path includes a signal input unit to which a signal to the memory chip is supplied, and the supplied signal to the center pad. And a signal output unit provided in the vicinity of the center pad region.
- the thin film capacitor is provided at a position facing the circuit surface of the memory chip except for the center pad region.
- the first surface electrode and the second surface electrode of the thin film capacitor are provided with a power supply output unit for applying a power supply voltage to the center pad, and a signal such as an address signal is applied to the center pad on the transmission line.
- a signal output unit is provided. Therefore, in a semiconductor memory device including a memory chip having a center pad, a high-capacity insulating layer using a paraelectric material or a high dielectric material is formed at a short distance from the center pad, and a high frequency of several GHz or more is formed in the power supply system. Provides an environment where sufficient charge can be applied in the region, lowers the power impedance at high frequencies, improves the power noise reduction effect, and does not require an external connection opening on the board on which the memory chip is mounted A semiconductor memory device can be provided.
- the semiconductor memory device includes: a substrate on which the memory chip is mounted face up; and a second insulating layer formed on the circuit surface of the memory chip, wherein the first surface electrode of the thin film capacitor is Formed on the second insulating layer, the first insulating layer is formed on the second surface electrode excluding the second power input portion and the second power output portion, and the substrate is formed on the first power source.
- the first power output unit, the second power output unit, the signal output unit, and the plurality of center pads are connected by wire bonding. It may be.
- the thin film capacitor and the transmission path can be connected to the substrate, and the thin film capacitor and the transmission path can be connected to the center pad of the memory chip by known wire bonding. At this time, an opening for external connection is not required on the substrate on which the memory chip is mounted.
- the semiconductor memory device may further include a second insulating layer formed on the circuit surface of the memory chip, and the first surface electrode of the thin film capacitor may be formed on the second insulating layer, One insulating layer is formed on the second surface electrode excluding the second power input part and the second power output part, and a first connection bump is formed on the first power input part and the second power input part.
- the signal input unit is formed with a second connection bump having a height lower than the first connection bump by the thickness of the first insulating layer, and the first power output unit and the second power output.
- the signal output unit and the plurality of center pads may be connected by wire bonding.
- a semiconductor memory device that improves the effect of reducing power supply noise in the high-frequency interface and does not require an external connection opening on the substrate on which the memory chip is mounted is provided as a BGA (Ball Grid Array). It can be configured as a CSP (Chip Scale Package).
- the first power input unit, the second power input unit, the signal input unit, and the plurality of connection pads are connected by wire bonding, and include the first power output unit, the second power source An output section, and the signal output And the plurality of center pads are connected by wire bonding, and the substrate, the memory chip, the second insulating layer, the thin film capacitor, the first insulating layer, and the protective layer are stacked in this order.
- a storage unit is formed, and the semiconductor storage device includes at least two layers of the stacked storage units, and a heat dissipation member thermally connected to each metal plate is provided on a protective layer of the uppermost storage unit. It may be arranged.
- a semiconductor storage device configured by stacking a plurality of storage units including a memory chip
- an effect of reducing power supply noise in a high-frequency interface is improved and an external connection to a substrate on which the memory chip is mounted
- the metal plate has a length shorter than the length of the memory chip in a direction along the wire laying direction of the wire bonding in a plan view, and in the direction orthogonal to the wire laying direction,
- a metal plate having a rectangular shape having a length longer than the length of the memory chip and disposed on the lowermost substrate is disposed at an end portion in the longitudinal direction thereof, and is disposed on the upper substrate from the lowermost layer.
- an opening or a thin portion for arranging the metal plate may be formed in the substrate. According to this configuration, the metal plate can be easily arranged on the substrate.
- the first surface electrode of the thin film capacitor is formed on the second insulating layer, and the first insulating layer has a first power output unit and a second power output unit on the center pad side.
- the first power output unit, the second power output unit, the signal output unit, and the plurality of center pads are connected by wire bonding and formed on the circuit surface of the memory chip.
- the layer, the thin film capacitor, the first insulating layer, the transmission line, and the protective layer are mounted on the substrate by turning upside down so that the memory chip is at the top and the protective layer is at the bottom.
- the substrate includes a plurality of connection pads connected to the first power input unit, the second power input unit, and the signal input unit;
- the first power input unit, the second power input unit, the signal input unit, and the plurality of connection pads may be connected by wire bonding.
- the substrate, the first insulating layer formed on the substrate, the second insulating layer formed on the first insulating layer, and the protection formed on the thin film capacitor is mounted face down on the protective film, and the second insulating layer is formed on the first insulating layer excluding the signal input portion of the transmission line,
- the first surface electrode of the thin film capacitor is formed on the second insulating layer, and the first power output portion includes a first power output wiring formed on the second insulating layer, and the second power output portion.
- the pads may be connected by wire bonding, and the first power output wiring, the second power output wiring, the signal output wiring, and the plurality of center pads may be connected by bumps.
- the semiconductor memory device may include at least a pair of the thin film capacitors formed on both sides of the center pad region. According to this configuration, in the semiconductor memory device having a structure in which the memory area is separated by the center pad area, a thin film capacitor can be provided corresponding to each memory area.
- the second surface electrode may be divided into a plurality of parts in a region corresponding to the first surface electrode in plan view. According to this configuration, it is possible to configure a plurality of thin film capacitors for one common first surface electrode. Thereby, it is possible to deal with memory chips having a plurality of different power supply voltages.
- the semiconductor memory device of the present invention in the semiconductor memory device including the memory chip having the center pad, the effect of reducing the power supply noise in the high frequency interface is improved, and the external connection opening is provided on the memory chip mounting substrate. It is possible to provide a semiconductor memory device that does not require a part.
- FIG. 1 is a schematic cross-sectional view of a semiconductor memory device according to a first embodiment.
- Schematic partial plan view of the semiconductor memory device of Embodiment 1 Schematic sectional view showing the structure of a thin film capacitor
- Schematic partial enlarged view showing the connection on the board side Schematic partial enlarged view showing connection on the center pad side
- Schematic plan view showing another configuration example of the thin film capacitor Schematic cross-sectional view of the semiconductor memory device of Embodiment 2
- Schematic partial plan view of the semiconductor memory device of Embodiment 2 Schematic cross-sectional view of the semiconductor memory device of Embodiment 3
- Another schematic cross-sectional view of the semiconductor memory device of Embodiment 3 Schematic partial plan view of the semiconductor memory device of Embodiment 3
- Schematic cross-sectional view of the semiconductor memory device of Embodiment 4 Schematic partial enlarged view showing connections according to the substrate side of Embodiment 4 Partial sectional view for explaining etch back in
- the semiconductor memory device 1 As shown in FIG. 1, the semiconductor memory device 1 according to the first embodiment generally includes a memory chip 10, a thin film capacitor 30, and an intermediate substrate (an example of a “substrate”) 40.
- the memory chip 10 has a circuit surface 11 (see FIG. 2) including a center pad region 14 in which a plurality of center pads 13 are formed, and a back surface 12 which is a surface opposite to the circuit surface 11. As shown in FIG. 1, the memory chip 10 is mounted face up on the intermediate board 40 with the circuit surface 11 opposite to the intermediate board 40.
- the memory chip 10 is, for example, a DDR3-SDRAM.
- the memory chip 10 is not limited to the DDR3-SDRAM, and may be a memory chip having the circuit surface 11 including the center pad region 14.
- the thin film capacitor 30 is provided at a position facing the circuit surface 11 of the memory chip 10 except for the center pad region 14, as shown in FIG.
- a pair of thin film capacitors 30 are formed on both sides of the center pad region 14. Therefore, in the semiconductor memory device having a structure in which the memory area is separated by the center pad area 14, the thin film capacitor 30 can be provided corresponding to each memory area.
- Each thin film capacitor 30 is formed at a position separated from the center pad 13 provided in the center pad region 14 by, for example, about 100 ⁇ m (micrometer). As shown in FIG. 3, the thin film capacitor 30 includes a first surface electrode 31, a thin film dielectric layer 33, and a second surface electrode 32.
- the first surface electrode 31 includes a first power supply input unit 31Gin to which a ground voltage (zero potential) Gnd to the memory chip 10 is provided, and a first power supply output unit 31Gout for applying the ground voltage Gnd to the center pad 13G. including.
- the 1st surface electrode 31 is formed by sputtering, for example, and is comprised with the copper thin film which has a film thickness of 2 micrometers or more.
- the thin film dielectric layer 33 is made of, for example, a paraelectric material (for example, SrTiO) or a ferroelectric material (for example, BST) having a film thickness of 1 ⁇ m or less.
- a paraelectric material for example, SrTiO
- a ferroelectric material for example, BST
- the second surface electrode 32 is formed on the thin film dielectric layer 33, and is formed by, for example, sputtering and a copper thin film having a thickness of 2 ⁇ m or more, like the first surface electrode 31.
- the second surface electrode 32 includes a second power input part 32Vin to which a predetermined positive voltage Vdd of 10 is supplied to the memory chip, and a second power output part 32Vout for applying the predetermined positive voltage Vdd to the center pad 13V. including.
- the ground voltage Gnd corresponds to the power supply voltage of one polarity applied to the memory chip 10
- the positive voltage corresponds to the power supply voltage of the other polarity applied to the memory chip 10.
- the power supply voltage with one polarity may be the positive voltage Vdd
- the power supply voltage with the other polarity may be the ground voltage Gnd.
- the letter “V” is attached to the reference numeral of the member related to the positive voltage Vdd
- the letter “G” is attached to the reference numeral of the member related to the ground voltage Gnd.
- a letter “S” is attached to a member related to a signal other than the power source. Further, unless it is particularly necessary to distinguish, “V”, “G”, and “S” are not attached to the reference numerals.
- the intermediate substrate 40 has a mounting surface 41 on which the memory chip 10 is mounted face up, and an external connection surface 42 that is a surface opposite to the mounting surface 41.
- a plurality of connection pads 43 (see FIG. 4) and wiring (not shown) connected to the memory chip 10 are formed.
- the external connection surface 42 is provided with a plurality of solder balls 44 and wiring (not shown) for connecting the semiconductor memory device 1 to a mother board or the like. That is, the external connection surface 42 is provided with a BGA.
- a via hole (not shown) for connecting the mounting surface 41 and the external connection surface 42 is provided inside the intermediate substrate 40.
- the intermediate substrate 40 is, for example, an organic substrate.
- the external connection surface 42 is not limited to the BGA but may be provided with an LGA.
- the semiconductor memory device 1 includes a first insulating layer 21 and a second insulating layer 22.
- the first insulating layer 21 is formed on the side opposite to the memory chip 10 with respect to the thin film capacitor 30.
- the first insulating layer 21 is formed on the second surface electrode 32 excluding the second power input part 32Vin and the second power output part 32Vout.
- a transmission path 23 is formed on the first insulating layer 21.
- the first insulating layer 21 is made of a thermosetting resin such as BT resin for bonding the transmission path 23 in parallel.
- the layer thickness of the first insulating layer 21 is preferably 50 ⁇ m or more.
- the transmission path 23 includes a signal input unit 23Sin for supplying a signal to the memory chip 10 and a signal output unit 23Sout for supplying a signal to the center pad 13G.
- the transmission path 23 existing on the first insulating layer 21 is a transmission path for all signals except for the power supply system (Vdd and Gnd) among signals corresponding to all pads of the memory chip 10.
- the characteristic impedance of the transmission line 23 is set to a value recommended by the memory chip 10.
- the characteristic impedance of the transmission line 23 includes the relative dielectric constant of the material of the first insulating layer 21, the width of the transmission line 23, and the distance between the transmission line 23 and the second surface electrode 32 of the thin film capacitor 30 (the first insulating layer 21.
- the layer thickness is determined by.
- the transmission path 23 has a width of 25 ⁇ m, a thickness of 10 ⁇ m, and a characteristic impedance of 100 ⁇ is recommended
- the thickness of the first insulating layer (BT resin) 21 is preferably about 120 ⁇ m
- the wiring pitch of the transmission line 23 is preferably about 100 ⁇ m.
- the second insulating layer 22 is formed on the circuit surface 11 of the memory chip 10, and the first surface electrode 31 of the thin film capacitor 30 is formed on the second insulating layer 22. Similar to the first insulating layer 21, the second insulating layer 22 is made of a thermosetting resin such as BT resin. The layer thickness of the second insulating layer 22 is preferably 50 ⁇ m or more.
- the first power supply input unit 31Gin, the second power supply input unit 32Vin, the signal input unit 23Sin, and the plurality of connection pads 43 are connected by wire bonding using wires 24. Further, as shown in FIG. 5, the first power output unit 31Gout, the second power output unit 32Vout, the signal output unit 23Sout, and the plurality of center pads 13 are similarly connected by wire bonding using wires 25. Has been.
- the wire 25 is an Au (gold) wire, an Al (aluminum) wire, a Cu (copper) wire or the like. In wire bonding, ultrasonic bonding using a wire bonder is performed. In the present embodiment, the wire 25 is an Au wire.
- the memory chip 10 usually has a common ground GND, and has different power supply (positive voltage) Vdd systems (for internal circuits, DQ (data), etc.). Therefore, when the first surface electrode 31 of the thin film capacitor 30 is used for the ground voltage Gnd, in order to separate the corresponding positive voltages (Vdd1, Vdd2, etc.), as shown in FIG.
- the surface electrode 32 and the thin film dielectric layer 33 may be separated.
- FIG. 6 shows a thin film capacitor group 30 ⁇ / b> G separated into three thin film capacitors 30. In this case, a plurality of thin film capacitors can be configured for one common first surface electrode 31. Thereby, it is possible to deal with memory chips having a plurality of different power supply voltages.
- the first surface electrode 31 may be divided and configured as shown in FIG. That is, FIG. 7 shows a configuration example of a thin film capacitor in which four thin film capacitor groups 30G shown in FIG. 6 are provided and the first surface electrode 31 is divided into four.
- the first surface electrode 31 of the thin film capacitor 30 is formed on the second insulating layer 22, and the thin film dielectric layer 33 is formed on the first surface electrode 31. Then, the second surface electrode 32 is formed on the thin film dielectric layer 33. Next, the first insulating layer 21 is formed on the second surface electrode 32, and the transmission line 23 is formed on the first insulating layer 21.
- the intermediate product shown in FIG. 3 is arranged on both sides of the center pad region 14 of the circuit surface 11 of the memory chip 10.
- the memory chip 10 is die-bonded face up on the intermediate substrate 40 on which the solder balls 44 and the like are formed by a known method.
- the first power input unit 31Gin, the second power input unit 32Vin, and the signal input unit 23Sin are connected to the plurality of connection pads 43 by wire bonding using Au wires 24. Further, the first power supply output unit 31Gout, the second power supply output unit 32Vout, the signal output unit 23Sout, and the plurality of center pads 13 are connected by wire bonding using Au wires 25.
- the thin film capacitor 30 is provided at a position facing the circuit surface 11 of the memory chip 10 except for the center pad region 14.
- the thin film capacitor 30 is formed on the second insulating layer 22 formed on the circuit surface 11 of the memory chip 10, whereby the thin film capacitor 30, the intermediate substrate 40, and the center of the memory chip 10 are formed.
- the connection distance with the pad 13 can be minimized. That is, the length of the Au wires 24 and 25 can be minimized. Therefore, in the semiconductor memory device 1 including the memory chip 10 having the center pad 13, the effect of reducing power supply noise can be improved by the thin film capacitor 30 or the like.
- a thin film dielectric layer 33 having a high capacitance density using a paraelectric material or a high dielectric material is formed at a short distance from the center pad 13, and a sufficient charge can be given to the power supply system in a high frequency region of several GHz or more. It provides an environment and can reduce the power supply impedance at high frequencies. Accordingly, it is possible to provide the semiconductor memory device 1 that improves the effect of reducing power supply noise in the high-frequency interface and does not require an external connection opening on the memory chip mounting substrate.
- first surface electrode 31 and the second surface electrode 32 of the thin film capacitor 30 are provided with power supply output units (31Gout, 32Vout) for applying a power supply voltage (Gnd, Vdd) to the center pad 13.
- the transmission line 23 is provided with a signal output unit 23Sout for applying a signal such as an address signal to the center pad 13.
- Embodiment 2 will be described with reference to FIGS.
- symbol is attached
- the semiconductor memory device 1 ⁇ / b> A of the second embodiment is largely different from the semiconductor memory device 1 of the first embodiment in that it does not have the intermediate substrate 40. That is, the semiconductor memory device 1A of the second embodiment is formed as a CSP.
- connection between the thin film capacitor 30 and the transmission path 23 and the outside is performed by the solder ball 26, and the connection between the thin film capacitor 30 and the transmission path 23 and the center pad 13 is performed by wire bonding using the Au wire 25.
- the first surface electrode 31 is provided with regions where the thin film dielectric layer 33 and the second surface electrode 32 do not overlap in four directions, and a connection portion with the center pad 13 is provided. In the other three directions, regions where solder balls 26G can be mounted are provided. Similarly, the second surface electrode 32 is provided with regions in which the solder balls 26V can be mounted in three directions.
- a solder ball (an example of a “first connection bump”) 26G is formed on the first power input portion 31Gin of the first surface electrode 31, and a solder ball (an example of “first connection bump”) is formed on the second power input portion 32Vin of the second surface electrode 32.
- An example of “first connection bump”) The height (diameter) of the solder ball 26G on which 26V is formed and the solder ball 26V is a value obtained by adding the film thicknesses of the thin film dielectric layer 33 and the second surface electrode 32 (3 ⁇ m). There is a difference in degree), but they are almost equal.
- solder ball 26S (“second connection bump”) having a height (diameter) lower than the solder balls 26G and 26V by the thickness of the first insulating layer 21 (about 50 ⁇ m) is provided to the signal input portion 23Sin of the transmission line 23. Example) is formed.
- the diameter of the solder balls 26G and 26V is about 200 ⁇ m
- the diameter of the solder ball 26S is about 150 ⁇ m.
- the first power input unit 31Gin and the second power input unit 32Vin are gold-plated lands having a diameter of 150 ⁇ m to 200 ⁇ m
- the signal input unit 23Sin is a gold-plated land having a diameter of 100 ⁇ m to 150 ⁇ m.
- the second connection bumps are not limited to the solder balls 26S, and may be gold stud bumps, for example.
- the thin film capacitor 30 or the like improves the effect of reducing power supply noise in the high-frequency interface, and an opening for external connection is required on the intermediate substrate 40 on which the memory chip 10 is mounted.
- the semiconductor memory device 1A not to be configured can be configured as a CSP.
- Embodiment 3 will be described with reference to FIGS.
- symbol is attached
- the storage unit is stacked in this order by the intermediate substrate 40, the memory chip 10, the second insulating layer 22, the thin film capacitor 30, the first insulating layer 21, and the protective layer 27. 50 is formed.
- the semiconductor memory device 1B includes at least two stages (two stages in the third embodiment) of stacked storage units 50A and 50B.
- Each intermediate substrate 40 includes a heat radiating metal plate (an example of a “metal plate”) 46 on which the memory chip 10 is mounted face up.
- Each intermediate substrate 40 is formed with a thin portion 48 for disposing the heat radiating metal plate 46.
- the thin metal portion 48 allows the heat radiating metal plate 46 to be easily arranged on the substrate.
- the method of disposing the heat radiating metal plate 46 on the intermediate substrate 40 is not limited to the method using the thin portion 48.
- the heat radiating metal plate 46 may be disposed by providing an opening in the intermediate substrate 40.
- the heat radiating metal plate 46 has a length shorter than the length of the memory chip 10 in a direction (in the direction of the arrow X in FIG. 12) along the laying direction of the wires 24 and 25 for wire bonding. And has a rectangular shape having a length longer than the length of the memory chip 10 in a direction (arrow Y direction) perpendicular to the wire laying direction.
- the heat radiating metal plate 46 is, for example, a copper plate having a planar shape of 1 mm ⁇ 2 mm and a thickness of 2-3 mm.
- a heat spreader (an example of a “heat radiating member”) 45 that is thermally connected to each of the heat radiating metal plates 46 and 46A is arranged on the protective layer 27 of the uppermost storage unit 50B.
- a heat spreader 45 that is thermally connected to each of the heat radiating metal plates 46 and 46A is arranged on the protective layer 27 of the uppermost storage unit 50B.
- FIG. 12 the top view except the heat spreader 45 is shown.
- the heat radiating metal plate 46A disposed on the lowermost intermediate substrate 40 is disposed at an end portion in the longitudinal direction (the direction of arrow Y in FIG. 12), and is intermediate between the uppermost stage and the lowermost stage.
- the heat transfer part 47 thermally connected to the heat radiating metal plate 46 and the heat spreader 45 disposed on the substrate 40 is provided.
- the heat transfer part 47 is integrally formed with the heat radiating metal plate 46A. Note that the heat transfer section 47 is not limited to this, and may be formed separately from the heat radiating metal plate 46A.
- the heat of the heat radiating metal plates 46 and 46A is transmitted to the heat spreader 45 by the heat transfer portion 47. That is, heat generated from the storage units 50 at each stage can be transmitted to the heat spreader 45 via the heat transfer unit 47 and escaped from the heat spreader 45.
- the heat radiating metal plate 46 and the heat transfer portion 47 are bonded with Ag (silver) paste, silicon grease or the like in order to obtain suitable heat conduction.
- the semiconductor memory device 1B configured by stacking the storage units 50 including the memory chip 10 in a plurality of stages (here, two stages), the effect of reducing the power supply noise is improved by the thin film capacitor 30 or the like.
- the heat generated by each memory chip 10 of the storage unit 50 can be suitably radiated. Thereby, the reliability of the operation of the semiconductor memory device 1B can be improved.
- Embodiment 4 will be described with reference to FIGS.
- symbol is attached
- the memory chip 10 is mounted on the intermediate substrate 40 in a face-down manner. That is, in the semiconductor memory device 1C, as shown in FIG. 13, the second insulating layer 22, the thin film capacitor 30, the first insulating layer 21, the transmission line 23, and the transmission path 23 provided on the circuit surface 11 of the memory chip 10.
- the protective layer 27 is mounted on the intermediate substrate 40 so as to be turned upside down so that the memory chip 10 is at the top and the protective layer 27 is at the bottom.
- connection between the thin film capacitor 30 and the transmission line 23 and the memory chip 10 is the same as that of the first embodiment in terms of the connection by wire bonding, but the arrangement location of each input unit is different from that of the first embodiment. That is, as shown in FIG. 14, the first power input part 31Gin and the second power input part 32Vin are arranged on the first insulating layer 21, and the signal input part 23Sin is arranged on the protective layer 27. ing. The first power input unit 31Gin, the second power input unit 32Vin, and the signal input unit 23Sin are connected to the plurality of connection pads 43 on the intermediate substrate 40 by wire bonding using the wires 24 as in the first embodiment. Has been.
- FIG. 14 First, for example, using a metal base material or the like, the second insulating layer 22, the thin film capacitor 30, the first insulating layer 21, the transmission line 23, and the portion including the portion to be etched back (see FIG. 15) indicated by a two-dot chain line, A multilayer thin film body in which the protective layer 27 is laminated in this order is formed.
- the carbon dioxide is formed at the end opposite to the end where the first power output part 31 Gout and the like are formed with respect to the second insulating layer 22.
- the gas (CO2) laser beam L1 is irradiated, and the end portion of the second insulating layer 22 indicated by the two-dot chain line is etched back and removed.
- carbon dioxide laser light L1 having a long wavelength is used which decomposes only the second insulating layer 22 which is an organic material and reflects the first surface electrode 31 of the thin film capacitor 30 made of metal such as copper. Thereby, the first surface electrode 31 can be exposed on the first insulating layer 21.
- the exposed first surface electrode 31 is irradiated with ultraviolet (UV) laser light L2 having a short wavelength for a predetermined time except for a portion that becomes the first power input portion 31Gin. Then, the first surface electrode 31 is etched to expose the thin film dielectric layer 33 made of a paraelectric material such as SrTiO. Further, the thin film dielectric layer 33 is etched by irradiating the exposed thin film dielectric layer 33 with the ultraviolet laser light L2 for a predetermined time except in the vicinity of the first surface electrode 31, so that the second surface electrode is etched. 32 is exposed.
- UV ultraviolet
- the exposed second surface electrode 32 is subjected to etching by removing the second surface electrode 32 by irradiating with ultraviolet laser light L2 for a predetermined time except for the portion serving as the second power input portion 32Vin. .
- the end of the first insulating layer 21 is exposed.
- the exposed end portion of the first insulating layer 21 that is an organic material is irradiated with a carbon dioxide laser beam L1, and the end portion of the first insulating layer 21 is removed by etching back.
- the portion that becomes the signal input portion 23Sin of the transmission line 23 is exposed on the protective layer 27 on the protective layer 27.
- the multilayer thin film body that has been subjected to the etch-back process related to the input unit in this manner is attached onto the circuit surface 11 of the memory chip 10.
- wire bonding processing between the multilayer thin film body and the memory chip 10 is performed, and wire bonding processing between the multilayer thin film body and the intermediate substrate 40 is performed with the memory chip 10 face down.
- connection method between the thin film capacitor 30 and the memory chip 10 and the arrangement of the output units are both the same as in the first embodiment. That is, the first power output unit 31Gout, the second power output unit 32Vout, the signal output unit 23Sout, and the plurality of center pads 13 are in the same manner as in the first embodiment shown in FIG. Connected by.
- the first insulating layer 21 is formed on the thin film capacitor 30 by exposing the first power output part 31Gout and the second power output part 32Vout on the center pad side.
- the signal input portion 23Sin is etched back so as to be exposed on the protective layer 27.
- the second power supply portion 31Gin and the second power supply input portion 32Vin are exposed on the first insulation layer 21 on the opposite side to the center pad side, that is, on the intermediate substrate 40 side. , Has been etched back.
- the protective layer 27 is formed so that the signal output portion 23Sout is exposed on the second insulating layer 22 on the center pad side, and the signal input portion 23Sin is exposed on the opposite side to the center pad side.
- connection by wire bonding is possible on the center pad side and the intermediate substrate 40 side of the multilayer thin film body.
- the thin film capacitor 30 or the like improves the effect of reducing power supply noise at the high-frequency interface.
- a semiconductor memory device that does not require an opening for external connection in the intermediate substrate 40 can be provided.
- a heat radiating member such as the heat spreader 45 can be provided on the back surface 12 of the memory chip.
- the problem can be easily solved by the configuration in which the heat spreader 45 is arranged on the back surface 12 of the memory chip 10 while improving the power noise reduction effect in the high frequency interface.
- the etch back method is not limited to the one using laser light. For example, a method using an etching solution using a normal resist or a method using gas may be used.
- Embodiment 5 will be described with reference to FIGS. 17 to 19.
- the memory chip 10 is mounted on the intermediate substrate 40 in a face-down manner.
- symbol is attached
- the fifth embodiment differs from the fourth embodiment in that the first power output unit 31Gout, the second power output unit 32Vout, the signal output unit 23Sout, and the plurality of center pads 13 are formed by bumps 15 formed on the center pad 13. The connection is different.
- the first power output part 31Gout includes a first power output line 31W formed on the second insulating layer 22.
- the second power output unit 32Vout includes a second power output line 32W formed on the second insulating layer 22.
- the signal output unit 23Sout of the transmission line 23 includes a via 22H formed in the second insulating layer 22 and a signal output wiring 23W connected to the via 22H and formed on the second insulating layer 22.
- Lands 23L, 31L, and 32L connected to the bumps 15 formed on the center pad 13 of the memory chip 10 are formed on the output wirings 23W, 31W, and 32W.
- the bump 15 is, for example, an Au stud bump or a micro solder bump.
- the first insulating layer 21 is formed on the intermediate substrate 40, and the second insulating layer 22 is formed on the first insulating layer 21. .
- the thin film capacitor 30 is formed on the second insulating layer 22, and the protective layer 27 is formed on the thin film capacitor 30.
- the memory chip 10 is mounted face down on the protective layer 27.
- the first power input unit 31Gin, the second power input unit 32Vin, the signal input unit 23Sin, and the plurality of connection pads 43 are Au as in the first embodiment.
- the wires 24 are connected by wire bonding.
- the effect of reducing power supply noise is improved by the thin film capacitor 30 or the like.
- the semiconductor memory device 1D that does not require an opening for external connection in the intermediate substrate 40 on which the memory chip 10 is mounted. In this configuration, since the back surface of the memory chip can be exposed, a heat radiating member such as a heat spreader can be provided on the back surface of the memory chip.
- the pair of thin film capacitors 30 are formed to face both sides of the center pad region 14
- the present invention is not limited to this.
- the thin film capacitor 30 may be formed to face only one side of the center pad region 14.
- two pairs may be formed to face both sides of the center pad region 14.
- the formation mode (division mode) of the thin film capacitor group 30G is not limited to that shown in FIGS. 6 and 7, and may be appropriately divided according to the required form of the thin film capacitor.
- the heat spreader 45 may be omitted.
- a heat radiating member such as the heat spreader 45 may be provided on the back surface 12 of the memory chip 10.
- SYMBOLS 1 Semiconductor memory device, 10 ... Memory chip, 11 ... Circuit surface, 13 ... Center pad, 14 ... Center pad area
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Abstract
Description
そのため、センターパッドを有するメモリチップを備えた半導体記憶装置において、センターパッドに至近距離で、常誘電体或いは高誘電体を用いた容量密度の高い絶縁層を形成し電源系に数GHz以上の高周波領域で充分な電荷を与え得る環境を提供し、高周波に於ける電源インピーダンスを下げ、電源ノイズの低減効果を向上させるとともに、メモリチップが搭載される基板に外部接続用の開口部を必要としない半導体記憶装置を提供できる。
本構成によれば、周知のワイヤボンディングによって、薄膜キャパシタおよび伝送路と基板とを、また、薄膜キャパシタおよび伝送路とメモリチップのセンターパッドとを接続することができる。その際、メモリチップが搭載される基板に外部接続用の開口部は、必要とされない。
本構成によれば、高周波インターフェイスに於ける電源ノイズの低減効果を向上させるとともに、メモリチップが搭載される基板に外部接続用の開口部を必要としない半導体記憶装置を、BGA(Ball Grid Array)を有するCSP(Chip Scale Package)として構成できる。
本構成によれば、メモリチップを含む記憶ユニットを複数段重ねて構成される半導体記憶装置において、高周波インターフェイスに於ける電源ノイズの低減効果を向上させるとともに、メモリチップが搭載される基板に外部接続用の開口部を必要としない半導体記憶装置を提供できることに加え、さらに、各メモリチップによって発生する熱を好適に放熱することができる。それによって半導体記憶装置の動作の信頼性を向上させることができる。
本構成によれば、各段の記憶ユニットからの発熱を、熱伝達部を介して放熱部材に伝達し、放熱部材から逃がすことができる。
本構成によれば、金属板を基板に簡易に配置できる。
前記第1電源入力部、前記第2電源入力部、および前記信号入力部と、前記複数の接続パッドとはワイヤボンディングによって接続されているようにしてもよい。
本構成によれば、メモリチップがフェイスダウンの態様で基板に搭載される構成の半導体記憶装置において、高周波インターフェイスに於ける電源ノイズの低減効果を向上させるとともに、基板に外部接続用の開口部を必要としない半導体記憶装置を提供できる。また、この構成では、メモリチップの裏面を露出させることができるため、メモリチップの裏面に、ヒートスプレッダ等の放熱部材を設けることができる。
本構成によれば、メモリチップがフェイスダウンの態様で基板に搭載される構成の半導体記憶装置において、電源ノイズの低減効果を向上させるとともに、メモリチップが搭載される基板に外部接続用の開口部を必要としない半導体記憶装置を提供できる。この構成では、メモリチップの裏面を露出させることができるため、メモリチップの裏面に、ヒートスプレッダ等の放熱部材を設けることができる。
本構成によれば、メモリチップの発熱を放熱部材によって抑制することができ、それによって半導体記憶装置の動作の信頼性を向上させることができる。
本構成によれば、センターパッド領域によってメモリ領域が分離された構造の半導体記憶装置において、各メモリ領域に対応して薄膜キャパシタを設けることができる。
本構成によれば、1個の共通の第1面電極に対して複数個の薄膜キャパシタを構成することができる。それによって、複数の異なる電源電圧を備えたメモリチップにも対応できる。
本発明に係る実施形態1を、図1から図7を参照して説明する。
1.半導体記憶装置の構成
本実施形態1の半導体記憶装置1は、図1に示されるように、大きくは、メモリチップ10、薄膜キャパシタ30、および中間基板(「基板」の一例)40を備える。
図3に示されるように、第2絶縁層22上に薄膜キャパシタ30の第1面電極31を形成し、第1面電極31上に薄膜誘電体層33を形成し、薄膜誘電体層33上に第2面電極32を形成する。次いで、第2面電極32上に第1絶縁層21を形成し、第1絶縁層21上に伝送路23を形成する。
3.実施形態1の効果
実施形態1においては、薄膜キャパシタ30は、センターパッド領域14を除いて、メモリチップ10の回路面11に対向した位置に設けられる。実施形態1では、メモリチップ10の回路面11上に形成された第2絶縁層22上に薄膜キャパシタ30が形成されている、それによって、薄膜キャパシタ30と、中間基板40およびメモリチップ10のセンターパッド13との接続距離を最短化できる。すなわち、Auワイヤ24,25の長さを最短化できる。そのため、センターパッド13を有するメモリチップ10を備えた半導体記憶装置1において、薄膜キャパシタ30等によって電源ノイズの低減効果を向上させることができる。
次に、図8、図9を参照して、実施形態2を説明する。なお、実施形態1と同一の部材には、同一の符号を付しその説明を省略する。そのため、実施形態1との相違点のみ説明する。
次に、図10から図12を参照して、実施形態3を説明する。なお、実施形態1と同一の部材には、同一の符号を付しその説明を省略する。そのため、実施形態1との相違点のみ説明する。
次に、図13から図16を参照して、実施形態4を説明する。なお、実施形態1と同一の部材には、同一の符号を付しその説明を省略する。そのため、実施形態1との相違点のみ説明する。
すなわち、図14に示されるように、第1電源入力部31Ginおよび第2電源入力部32Vinは、第1絶縁層21上に配置されており、信号入力部23Sinは、保護層27上に配置されている。そして、第1電源入力部31Gin、第2電源入力部32Vin、および信号入力部23Sinと、中間基板40上の複数の接続パッド43とは、実施形態1と同様に、ワイヤ24によるワイヤボンディングによって接続されている。
その際、有機材である第2絶縁層22のみを分解し、銅等の金属製である薄膜キャパシタ30の第1面電極31を反射する波長の長い炭酸ガスレーザ光L1が使用される。それによって、第1絶縁層21上に第1面電極31を露出させることができる。
次に、図17から図19を参照して、実施形態5を説明する。実施形態5の半導体記憶装置1Dでは、実施形態4と同様に、メモリチップ10がフェイスダウンの態様で中間基板40に搭載される。なお、実施形態1と同一の部材には、同一の符号を付しその説明を省略する。そのため、実施形態1との相違点のみ説明する。
本発明は上記記述及び図面によって説明した実施形態に限定されるものではなく、例えば次のような種々の態様も本発明の技術的範囲に含まれる。
Claims (11)
- 複数のセンターパッドが形成されたセンターパッド領域を含む回路面と、前記回路面と反対側の面である裏面とを有するメモリチップを備えた半導体記憶装置であって、
前記センターパッド領域を除いて、前記回路面に対向した位置に設けられた薄膜キャパシタと、
前記薄膜キャパシタに対して、前記メモリチップと反対側に形成された第1絶縁層であって、その上に伝送路が形成された第1絶縁層と、
を備え、
前記薄膜キャパシタは、
前記メモリチップへの一方の極性の電源電圧が供給される第1電源入力部と、供給された前記一方の極性の電源電圧を前記センターパッドに出力するために前記センターパッド領域の近傍に設けられた第1電源出力部とを含む第1面電極と、
前記第1電源入力部および第1電源出力部を除く前記第1面電極上に形成された、常誘電体あるいは強誘電体の薄膜誘電体層と、
前記薄膜誘電体層上に形成された第2面電極であって、前記メモリチップへの他方の極性の電源電圧が供給される第2電源入力部と、供給された前記他方の極性の電源電圧を前記センターパッドに印加するために前記センターパッド領域の近傍に設けられた第2電源出力部とを含む第2面電極と、を含み、
前記伝送路は、前記メモリチップへの信号が供給される信号入力部と、供給された前記信号を前記センターパッドに供給するために前記センターパッド領域の近傍に設けられた信号出力部とを含む、半導体記憶装置。 - 請求項1に記載された半導体記憶装置において、
前記メモリチップがフェイスアップで搭載される基板と、
前記メモリチップの前記回路面上に形成された第2絶縁層と、
を備え、
前記薄膜キャパシタの前記第1面電極は、前記第2絶縁層上に形成され、
前記第1絶縁層は、前記第2電源入力部および第2電源出力部を除く前記第2面電極上に形成され、
前記基板は、前記第1電源入力部、前記第2電源入力部、および前記信号入力部と接続される、複数の接続パッドを含み、
前記第1電源入力部、前記第2電源入力部、および前記信号入力部と、前記複数の接続パッドとはワイヤボンディングによって接続され、
前記第1電源出力部、前記第2電源出力部、および前記信号出力部と、前記複数のセンターパッドとはワイヤボンディングによって接続される、半導体記憶装置。 - 請求項1に記載された半導体記憶装置において、
前記メモリチップの前記回路面上に形成された第2絶縁層を備え、
前記薄膜キャパシタの前記第1面電極は、前記第2絶縁層上に形成され、
前記第1絶縁層は、前記第2電源入力部および第2電源出力部を除く前記第2面電極上に形成され、
前記第1電源入力部および前記第2電源入力部には、第1接続バンプが形成され、
前記信号入力部には、前記第1接続バンプより高さが前記第1絶縁層の厚さ分だけ低い第2接続バンプが形成され、
前記第1電源出力部、前記第2電源出力部、および前記信号出力部と、前記複数のセンターパッドとはワイヤボンディングによって接続される、半導体記憶装置。 - 請求項1に記載された半導体記憶装置において、
前記メモリチップがフェイスアップで載置される金属板と、
前記金属板が配置される基板と、
前記メモリチップの前記回路面上に形成された第2絶縁層と、
前記第1絶縁層上に形成された保護層と、
を備え、
前記薄膜キャパシタの前記第1面電極は、前記第2絶縁層上に形成され、
前記第1絶縁層は、前記第2電源入力部および第2電源出力部を除く前記第2面電極上に形成され、
前記基板は、前記第1電源入力部、前記第2電源入力部、および前記信号入力部と接続される、複数の接続パッドを含み、
前記第1電源入力部、前記第2電源入力部、および前記信号入力部と、前記複数の接続パッドとはワイヤボンディングによって接続され、
前記第1電源出力部、前記第2電源出力部、および前記信号出力部と、前記複数のセンターパッドとはワイヤボンディングによって接続され、
前記基板、前記メモリチップ、前記第2絶縁層、前記薄膜キャパシタ、前記第1絶縁層、および前記保護層は、この順に積層された記憶ユニットを形成し、
当該半導体記憶装置は、積層された少なくとも二段の前記記憶ユニットを備え、
最上段の記憶ユニットの保護層の上に、各金属板と熱的に接続される放熱部材が配置されている、半導体記憶装置。 - 請求項4に記載された半導体記憶装置において、
前記金属板は、平面視において、前記ワイヤボンディングのワイヤの敷設方向に沿った方向において前記メモリチップの長さより短い長さを有し、前記ワイヤの敷設方向と直交する方向において、前記メモリチップの長さより長い長さを有する矩形の形状を有し、
最下段の基板に配置される金属板は、その長手方向の端部に配置され、最下段より上段の基板に配置される金属板と、前記放熱部材とに熱的に接続される熱伝達部を有する、半導体記憶装置。 - 請求項5に記載された半導体記憶装置において、
前記基板には、前記金属板を配置するための開口あるいは肉薄部が形成されている、半導体記憶装置。 - 請求項1に記載された半導体記憶装置において、
前記メモリチップがフェイスダウンの態様で搭載される基板と、
前記伝送路上に形成された保護層と、
前記メモリチップの前記回路面上に設けられた第2絶縁層と、を備え、
前記薄膜キャパシタの前記第1面電極は、前記第2絶縁層上に形成され、
前記第1絶縁層は、
センターパッド側においては、第1電源出力部および第2電源出力部を露出して前記薄膜キャパシタ上に形成されており、
センターパッド側と反対側においては、前記信号入力部が前記保護層上において露出するように、エッチバックされており、
前記第2絶縁層は、
センターパッド側と反対側においては、前記第1電源入力部および前記第2電源入力部が前記第1絶縁層上において露出するように、エッチバックされており、
前記保護層は、
センターパッド側においては、前記第2絶縁層上に前記信号出力部を露出し、センターパッド側と反対側においては、前記信号入力部をその上に露出するように形成されており、
前記第1電源出力部、前記第2電源出力部、および前記信号出力部と、前記複数のセンターパッドとはワイヤボンディングによって接続され、
前記メモリチップの前記回路面上に形成された、前記第2絶縁層、前記薄膜キャパシタ、前記第1絶縁層、前記伝送路、および前記保護層は、前記メモリチップが最上段となり、前記保護層が最下段となるように上下を反転して前記基板上に搭載されており、
前記基板は、前記第1電源入力部、前記第2電源入力部、および前記信号入力部と接続される、複数の接続パッドを含み、
前記第1電源入力部、前記第2電源入力部、および前記信号入力部と、前記複数の接続パッドとはワイヤボンディングによって接続されている、半導体記憶装置。 - 請求項1に記載された半導体記憶装置において、
基板と
前記基板上に形成された前記第1絶縁層と、
前記第1絶縁層上に形成された第2絶縁層と、
前記薄膜キャパシタ上に形成された保護膜と、を備え、
前記メモリチップは、前記保護膜上にフェイスダウンで搭載され、
前記第2絶縁層は、前記伝送路の前記信号入力部を除く前記第1絶縁層上に形成され、
前記薄膜キャパシタの前記第1面電極は、前記第2絶縁層上に形成され、
前記第1電源出力部は、第2絶縁層上に形成された第1電源出力配線を含み、
前記第2電源出力部は、第2絶縁層上に形成された第2電源出力配線を含み、
前記伝送路の信号出力部は、前記第2絶縁層内に形成されたビアと、前記ビアと接続され第2絶縁層上に形成された信号出力配線を含み、
前記基板は、前記第1電源入力部、前記第2電源入力部、および前記信号入力部と接続される、複数の接続パッドを含み、
前記第1電源入力部、前記第2電源入力部、および前記信号入力部と、前記複数の接続パッドとはワイヤボンディングによって接続され、
前記第1電源出力配線、前記第2電源出力配線、および前記信号出力配線と、前記複数のセンターパッドとはバンプによって接続される、半導体記憶装置。 - 請求項7または請求項8に記載された半導体記憶装置において、
前記メモリチップの前記裏面上に配置された放熱部材を備える、半導体記憶装置。 - 請求項1から請求項9のいずれか一項に記載された半導体記憶装置において、
前記センターパッド領域の両側に形成されている少なくとも一対の前記薄膜キャパシタを備える、半導体記憶装置。 - 請求項1から請求項10のいずれか一項に記載された半導体記憶装置において、
前記第2面電極は、平面視において、前記第1面電極に対応した領域内において、複数に分割されている、半導体記憶装置。
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