WO2016090807A1 - 阵列基板及其制作方法、显示装置 - Google Patents
阵列基板及其制作方法、显示装置 Download PDFInfo
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- WO2016090807A1 WO2016090807A1 PCT/CN2015/076954 CN2015076954W WO2016090807A1 WO 2016090807 A1 WO2016090807 A1 WO 2016090807A1 CN 2015076954 W CN2015076954 W CN 2015076954W WO 2016090807 A1 WO2016090807 A1 WO 2016090807A1
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- 239000000758 substrate Substances 0.000 title claims abstract description 64
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 238000002161 passivation Methods 0.000 claims abstract description 77
- 239000010409 thin film Substances 0.000 claims abstract description 69
- 239000010408 film Substances 0.000 claims description 172
- 238000000034 method Methods 0.000 claims description 46
- 239000004065 semiconductor Substances 0.000 claims description 26
- 239000000463 material Substances 0.000 claims description 17
- 238000000059 patterning Methods 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 13
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 38
- 229910004205 SiNX Inorganic materials 0.000 description 15
- 229910052814 silicon oxide Inorganic materials 0.000 description 15
- 239000007789 gas Substances 0.000 description 12
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 9
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 7
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 6
- 230000003071 parasitic effect Effects 0.000 description 5
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 4
- CXKCTMHTOKXKQT-UHFFFAOYSA-N cadmium oxide Inorganic materials [Cd]=O CXKCTMHTOKXKQT-UHFFFAOYSA-N 0.000 description 4
- CFEAAQFZALKQPA-UHFFFAOYSA-N cadmium(2+);oxygen(2-) Chemical compound [O-2].[Cd+2] CFEAAQFZALKQPA-UHFFFAOYSA-N 0.000 description 4
- 229910052733 gallium Inorganic materials 0.000 description 4
- 229910052738 indium Inorganic materials 0.000 description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 239000011787 zinc oxide Substances 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
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- 238000007254 oxidation reaction Methods 0.000 description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 238000010292 electrical insulation Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 101100489577 Solanum lycopersicum TFT10 gene Proteins 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device.
- TFT-LCD Thin Film Transistor Liquid Crystal Display
- the ground is used in the field of high performance display.
- the TFT 10 includes a gate electrode 100, a gate insulating layer 101 sequentially on the gate surface, a semiconductor active layer 102, and a source 103 and a drain 104 on both sides of the semiconductor active layer 102.
- the semiconductor active layer 102 forms a channel such that the source 103 and the drain 104 are turned on to achieve conduction of the TFT 10.
- the surface of the semiconductor active layer 102 In order to prevent the electrical performance of the TFT 10 from being affected, it is necessary to protect the surface of the semiconductor active layer 102. Since the SiO 2 (silicon dioxide) film has excellent electrical insulating properties and process feasibility, it can be in the semiconductor active layer 102. the surface of the SiO 2 passivation layer 105 is formed is composed of SiO 2.
- the oxidation is accelerated by the influence of temperature, so that the formed SiO 2 film structure is relatively loose. Therefore, the surface of the SiO 2 film has many small holes, resulting in a decrease in the adhesion of the surface of the SiO 2 film.
- the process of forming the pixel electrode layer 106 on the surface of the passivation layer 105 composed of SiO 2 by a patterning process after the photoresist covering the pixel electrode layer pattern is peeled off after the etching process, the pixel is caused. The detachment of the electrode layer 106 seriously affects the quality of the product.
- an array substrate includes a thin film transistor on a surface of the base substrate, a first passivation layer disposed over the thin film transistor, and a transparent electrode layer on a surface of the first passivation layer.
- the first passivation layer includes: a first sub-film layer, and a second sub-film layer on the surface of the first sub-film layer that is in contact with the transparent electrode layer. The film density of the second sub-film layer is greater than that of the first sub-film layer.
- a display device comprising the array substrate as described above.
- a method of fabricating an array substrate includes: forming a thin film transistor on a substrate by a patterning process; forming a first sub-film layer over the thin film transistor; forming a second sub-film layer on a surface of the first sub-film layer;
- the first sub-film layer and the second sub-film layer constitute a first passivation layer, and the second sub-film layer has a film density greater than the first sub-film layer;
- the surface of the layer is formed into a transparent electrode layer by a patterning process.
- FIG. 1 is a schematic structural view of an array substrate provided by the prior art
- FIG. 2a is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
- 2b is a schematic structural diagram of another array substrate according to an embodiment of the present invention.
- FIG. 3 is a schematic structural diagram of still another array substrate according to an embodiment of the present invention.
- FIG. 4 is a flowchart of a method for fabricating an array substrate according to an embodiment of the present invention.
- FIG. 5 is a flowchart of another method for fabricating an array substrate according to an embodiment of the present invention.
- An embodiment of the present invention provides an array substrate, as shown in FIG. 2a or 2b, which may include a TFT 10 on the surface of the base substrate 01, a first passivation layer 200 disposed over the TFT 10, and a first passivation layer 200.
- the upper side of the TFT 10 refers to a direction in which the TFT 10 is away from the base substrate 01.
- the first passivation layer 200 may include a first sub-thin film layer 210 and a second sub-thin film layer 211 on the surface of the first sub-thin film layer 210 in contact with the transparent electrode layer 300.
- the film density of the second sub-film layer 211 is greater than the film density of the first sub-film layer 210.
- Embodiments of the present invention provide an array substrate including a thin film transistor on a surface of a substrate; in order to prevent the electrical properties of the thin film transistor or other conductive film layer located on the surface of the thin film transistor from being affected, a thin film is disposed above the thin film transistor a passivation layer; a transparent electrode layer is disposed on the surface of the first passivation layer.
- the first passivation layer includes a first sub-film layer, and a second sub-film layer on the surface of the first sub-film layer that is in contact with the transparent electrode layer; wherein the second sub-film layer has a film density greater than the first sub-film layer Film layer.
- the second sub-film layer having a higher film density is brought into contact with the transparent electrode layer, and the bonding force between the transparent electrode layer and the second sub-film layer can be improved.
- the transparent electrode layer in the patterning process for fabricating the transparent electrode layer, when the photoresist on the surface of the transparent electrode layer is peeled off, the transparent electrode layer can be prevented from falling off the surface of the second sub-film layer. Thereby improving the quality of the product.
- the functions of the transparent electrode layer 300 are different, and the positions of the first passivation layer 200 in the array substrate are also different, which will be described in detail below.
- TN Transist Nematic
- the transparent electrode layer 300 is a pixel electrode layer 106, as shown in FIG. 2a.
- the surface of the first passivation layer 200 disposed over the TFT 10 is in contact with the TFT 10.
- the transparent electrode layer located in the upper layer has a slit shape, and the transparent electrode layer located in the lower layer has a planar shape.
- the structure of the array substrate may be as shown in FIG. 2b.
- the first passivation layer 200 disposed above the TFT 10 is not in direct contact with the surface of the TFT 10, and the pixel electrode layer 106 and the second passivation layer 201 are further disposed between the TFT 10 and the first passivation layer 200. .
- the common electrode layer 107 is a slit-shaped electrode, its contact area with the first passivation layer 200 is small and it is easier to fall off. Therefore, when the first passivation layer 200 is composed of the first sub-film layer 210 and the second sub-layer When the film layer 211 is formed, since the film density of the second sub film layer 211 is larger than that of the first sub film layer 210, the bonding force between the common electrode layer 107 and the second sub film layer 211 can be improved, thereby preventing the narrowness more effectively. Separation of the slit electrode during the manufacturing process.
- two transparent electrode layers are also disposed on the array substrate.
- the two transparent electrode layers are all slit-shaped, and their slit positions are alternately arranged.
- the transparent electrode layer (pixel electrode 106) that the second passivation layer 201 contacts is also a slit-shaped electrode, and the contact area with the second passivation layer 201 is small, so in order to avoid the fabrication of the pixel electrode 106.
- the peeling phenomenon occurs during the process, and the second passivation layer 201 may be disposed in the same manner as the first passivation layer 200, and is composed of two layers of sub-film layers.
- the thin film layer of the sub-film layer in contact with the pixel electrode 106 in the second passivation layer 201 has a large density. Therefore, the bonding force between the pixel electrode 106 and the second passivation layer 201 can be improved, and the detachment phenomenon of the slit electrode during the manufacturing process can be more effectively prevented.
- SiO 2 (silicon dioxide) film has superior electrical insulation and process feasibility; for LTPS (Low Temperature Poly-silicon) or semiconductor oxide, such as IGZO (indium gallium zinc oxide) , indium gallium zinc oxide) is used as the semiconductor active layer 102 of the TFT10, the use of the SiO 2 film as the passivation layer, the SiO 2 film is deposited using PECVD (plasma enhanced chemical vapor deposition, plasma enhanced chemical vapor deposition) In the process, the film formation atmosphere has less influence on the semiconductor active layer 102. Therefore, SiO 2 may be an ideal material constituting a passivation layer such as the first passivation layer 200.
- PECVD plasma enhanced chemical vapor deposition
- the formed SiO 2 film structure is relatively loose. Therefore, the surface of the SiO 2 film has many small holes, resulting in a decrease in the adhesion of the surface of the SiO 2 film.
- the transparent electrode layer 300 formed on the surface of the SiO 2 film is liable to fall off.
- a film formed using SiNx (silicon nitride) or SiON (silicon oxynitride) has a higher density, a thin film structure, and a higher bonding strength with the transparent conductive layer 300.
- the film formation atmosphere affects the semiconductor active layer 102 composed of LTPS or a semiconductor oxide, and the electrical performance of the TFT 10 is lowered.
- SiO 2 may be used as the material constituting the first sub-thin film layer 210; at least one of SiNx or SiON is used as the material constituting the second sub-thin film layer 211.
- the thickness of the first sub-thin film layer 210 composed of SiO 2 may be 2000 ⁇ or less; and the thickness of the second sub-thin film layer 211 composed of at least one of SiNx or SiON may be 100 to 500 ⁇ .
- the thickness of the second sub-film layer 211 is less than 100 angstroms, the thickness of the film layer is too thin, so that a good film forming effect cannot be ensured.
- the thickness of the second sub-thin film layer 211 is greater than 500 angstroms, since the thickness of the second sub-thin film layer 211 is large and the film forming time is long, the influence time of the film forming atmosphere on the TFT is increased, which is disadvantageous to the electrical properties of the TFT. .
- the thickness of the first sub-film layer 210 is greater than the thickness of the second sub-film layer 211, and the first passivation can be deposited while avoiding the separation of the transparent electrode layer 300 from the first passivation layer 200. During the process of layer 200, the effect of the film forming atmosphere on the electrical properties of the TFT is avoided.
- a transparent organic insulating layer 108 may be formed between the pixel electrode layer 106 and the second passivation layer 201.
- the thickness of the organic insulating layer 108 is generally greater than the thickness of the second passivation layer 201.
- the distance between the data line and the pixel electrode layer 106 can be increased by the organic insulating layer 108, and the relative dielectric constant of the organic insulating layer 108 is low, thereby reducing the above parasitic capacitance.
- the organic insulating layer 108 is also provided above the TFT region, so that a part of the light incident on the inside of the organic insulating layer 108 can be emitted from above the TFT region, thereby increasing the aperture ratio of the real panel.
- the array substrate may further include a second passivation layer 201 between the TFT 10 and the first passivation layer 200, an organic insulating layer 108 sequentially located on the surface of the second passivation layer 201, and a pixel electrode layer 106.
- the parasitic capacitance between the data line and the pixel electrode layer 106 can be reduced by the organic insulating layer 108, and the aperture ratio of the display panel can be improved.
- the first passivation layer 200 may further include a third sub-thin film layer 212 in contact with the organic insulating layer 108 and the pixel electrode layer 106.
- the material constituting the third sub-thin film layer 212 is at least one of SiNx or SiON.
- SiO 2 can be used as the material constituting the first sub-thin film layer 210.
- a large amount of N 2 O gas is used, and the N 2 O gas reacts with the organic insulating layer 108.
- a third sub-thin film layer 212 is disposed between the first sub-thin film layer 210 and the organic insulating layer 108.
- N 2 O nitrogen oxide
- the third sub-film layer 212 composed of SiNx or SiON is deposited by PECVD on the surface of the organic thin film layer 108
- N 2 O nitrogen oxide
- the probability of reaction between the N 2 O gas and the organic insulating layer 108 is lowered, the surface of the organic insulating layer 108 located at the boundary of the pixel electrode 106 is avoided, and the hole which occurs due to the reaction of the N 2 O gas with the organic insulating layer 108 phenomenon.
- the signal resistance of the array substrate is improved, and the phenomenon that the product quality is degraded due to low letter resistance in the high temperature or high voltage test is avoided.
- the third sub-film layer 212 may have a thickness of 100 to 500 angstroms. When the thickness of the third sub-film layer 212 is less than 100 angstroms, the thickness of the film layer is too thin, so that a good film forming effect cannot be ensured. When the thickness of the third sub-film layer 212 is greater than 500 angstroms, since the thickness of the third sub-film layer 212 is large and the film formation time is long, the reaction of the N 2 O gas and the organic insulating layer 108 in the film forming atmosphere is increased. There is a chance that the probability of creating a hole in the surface of the organic insulating layer 108 at the boundary of the pixel electrode 106 is also increased, which is disadvantageous for improving the signal resistance of the array substrate.
- the TFT 10 can be made to have a higher mobility.
- the mobility of the carrier of the TFT 10 may be 20 to 30 times that of the TFT 10 composed of amorphous silicon (a-Si).
- the semiconductor active layer 102 in this embodiment can be formed using a semiconductor oxide.
- a semiconductor oxide for example: zinc oxide (ZnO), cadmium oxide (CdO), aluminum oxide (Al 2 O 3 ) or indium gallium zinc oxide (IGZO), and the like.
- Embodiments of the present invention provide a display device including any of the array substrates described above. It has the same structure and advantageous effects as the array substrate provided by the foregoing embodiments. Since the beneficial effects of the array substrate have been described in detail in the foregoing embodiments, they are not described herein again.
- the display device may include, for example, a liquid crystal display device.
- the display device may be any product or component having a display function, such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, or a tablet computer.
- the embodiment of the invention provides a method for fabricating an array substrate, as shown in FIG. 4, which may include:
- the TFT 10 is formed by a patterning process.
- the first sub-thin film layer 210 is formed by chemical vapor deposition, such as PECVD.
- the first sub-film layer 210 and the second sub-film layer 211 constitute a first passivation layer 200; the film density of the second sub-film layer 211 is greater than the film density of the first sub-film layer 210.
- the transparent electrode layer 300 is formed by a patterning process.
- Embodiments of the present invention provide a method for fabricating an array substrate, comprising first forming a thin film transistor on a substrate by a patterning process; in order to avoid affecting electrical properties of the thin film transistor or other conductive film layer on the surface of the thin film transistor Forming a first sub-film layer by chemical vapor deposition on the thin film transistor; then, forming a second sub-film layer by chemical vapor deposition on the surface of the first sub-film layer; wherein, the first sub-film layer and The second sub-film layer constitutes a first passivation layer, and the second sub-film layer has a film density greater than that of the first sub-film layer; finally, a transparent electrode layer is formed on the surface of the first passivation layer by a patterning process.
- the film density of the second sub-film layer is larger than that of the first sub-film layer, the film density is high, the structure of the formed film layer is tight, and the number of small holes on the surface of the film layer is small. Therefore, when the transparent electrode layer is formed on the surface of the second sub-film layer, the bonding force between the transparent electrode layer and the second sub-film layer can be improved. In this way, in the patterning process for fabricating the transparent electrode layer, when the photoresist on the surface of the transparent electrode layer is peeled off, the transparent electrode layer can be prevented from falling off the surface of the second sub-film layer. Thereby improving the quality of the product.
- the patterning process may include a photolithography process, and may also include other processes for forming a predetermined pattern, such as printing, inkjet, etc.; the photolithography process includes film formation and exposure.
- the corresponding patterning process can be selected in accordance with the structure formed in the present invention.
- the transparent electrode layer 300 has different functions. In the process of fabricating the array substrate, the steps of forming the first passivation layer 200 are also different, which will be described in detail below.
- the transparent electrode layer 300 is the pixel electrode layer 106
- the first passivation layer 200 in contact with the surface of the TFT 10 is formed in step S102.
- Step S102 includes, before forming the first passivation layer 200, further forming with the TFT 10
- the second passivation layer 201 is in contact with the surface, and then the pixel electrode layer 106 is formed on the surface of the second passivation layer 201.
- the common electrode layer 107 is a slit-shaped electrode, its contact area with the first passivation layer 200 is small and it is easier to fall off. Therefore, when the first passivation layer 200 is composed of the first sub-thin film layer 210 and the second sub-thin film layer 211, since the film density of the second sub-thin film layer 211 is larger than that of the first sub-thin film layer 210, the common electrode layer can be improved. The bonding force with the second sub-film layer 211 is more effective in preventing the detachment of the slit-like electrode during the manufacturing process.
- the transparent electrode layer (pixel electrode 106) that the second passivation layer 201 contacts is also a slit-shaped electrode, the contact area with the second passivation layer 201 is small, so the process of fabricating the pixel electrode 106 is avoided.
- the second passivation layer 201 may be disposed in the same manner as the first passivation layer 200, and may be composed of two layers of thin film layers.
- the thin film layer of the sub-film layer in contact with the pixel electrode 106 in the second passivation layer 201 has a large density. Therefore, the bonding force between the pixel electrode 106 and the second passivation layer 201 can be improved, and the detachment phenomenon of the slit electrode during the manufacturing process can be more effectively prevented.
- SiO 2 (silica) film has superior electrical insulation and process feasibility; for TFTs using LTPS or semiconductor oxide such as IGZO as the semiconductor active layer 102, SiO 2 film is used.
- the passivation layer the film formation atmosphere has little influence on the semiconductor active layer 102 in the process of depositing the SiO 2 film by PECVD. Therefore, SiO 2 may be an ideal material constituting a passivation layer such as the first passivation layer 200.
- the formed SiO 2 film structure is relatively loose. Therefore, the surface of the SiO 2 film has many small holes, resulting in a decrease in the adhesion of the surface of the SiO 2 film.
- the transparent electrode layer 300 formed on the surface of the SiO 2 film is liable to fall off.
- a film formed using SiNx (silicon nitride) or SiON (silicon oxynitride) has a higher density, a thin film structure, and a higher bonding strength with the transparent conductive layer 300.
- the film formation atmosphere affects the semiconductor active layer 102 composed of LTPS or a semiconductor oxide, and the electrical performance of the TFT 10 is lowered.
- SiO 2 may be used as the material constituting the first sub-thin film layer 210; at least one of SiNx or SiON is used as the material constituting the second sub-thin film layer 211.
- the thickness of the first sub-thin film layer 210 composed of SiO 2 may be 2000 ⁇ or less; and the thickness of the second sub-thin film layer 211 composed of at least one of SiNx or SiON may be 100 to 500 ⁇ .
- the thickness of the second sub-film layer 211 is less than 100 angstroms, the thickness of the film layer is too thin, so that a good film forming effect cannot be ensured.
- the thickness of the second sub-thin film layer 211 is greater than 500 angstroms, since the thickness of the second sub-thin film layer 211 is large and the film forming time is long, the influence time of the film forming atmosphere on the TFT is increased, which is disadvantageous to the electrical properties of the TFT. .
- the thickness of the first sub-film layer 210 is greater than the thickness of the second sub-film layer 211, and the first passivation can be deposited while avoiding the separation of the transparent electrode layer 300 from the first passivation layer 200. During the process of layer 200, the effect of the film forming atmosphere on the electrical properties of the TFT is avoided.
- a transparent organic insulating layer 108 may be formed between the pixel electrode layer 106 and the second passivation layer 201.
- the manufacturing method may include:
- the parasitic capacitance between the data line and the pixel electrode layer 106 can be reduced by the organic insulating layer 108, and the aperture ratio of the display panel can be improved.
- a via hole at a position corresponding to the drain 104 of the TFT 10 is formed by a patterning process.
- a pixel electrode layer 106 is formed on the surface of the organic insulating layer 108, and the pixel electrode layer 106 is connected to the drain 104 of the TFT 10 through a via.
- the material constituting the third sub-thin film layer 212 is at least one of silicon nitride or silicon oxynitride.
- N 2 O nitrogen oxide
- the third sub-film layer 212 composed of SiNx or SiON is deposited by PECVD on the surface of the organic thin film layer 108
- N 2 O (nitrogen oxide) gas may be used in the film formation atmosphere, or only a small amount of N 2 O may be used. gas.
- the probability of reaction between the N 2 O gas and the organic insulating layer 108 is lowered, the surface of the organic insulating layer 108 located at the boundary of the pixel electrode 106 is avoided, and the hole which occurs due to the reaction of the N 2 O gas with the organic insulating layer 108 phenomenon.
- the reliability of the array substrate is improved, and the deterioration of product quality due to low letter resistance is avoided in the high temperature or high voltage test.
- the third sub-film layer 212 may have a thickness of 100 to 500 angstroms. When the thickness of the third sub-film layer 212 is less than 100 angstroms, the thickness of the film layer is too thin, so that a good film forming effect cannot be ensured. When the thickness of the third sub-film layer 212 is greater than 500 angstroms, since the thickness of the third sub-film layer 212 is large and the film formation time is long, the reaction of the N 2 O gas and the organic insulating layer 108 in the film forming atmosphere is increased. There is a chance that the probability of creating a hole in the surface of the organic insulating layer 108 at the boundary of the pixel electrode 106 is also increased, which is disadvantageous for improving the signal resistance of the array substrate.
- the semiconductor active layer 102 may be composed of a semiconductor oxide.
- a semiconductor oxide For example: zinc oxide (ZnO), cadmium oxide (CdO), aluminum oxide (Al2O3) or indium gallium zinc oxide (IGZO) and the like.
- ZnO zinc oxide
- CdO cadmium oxide
- Al2O3 aluminum oxide
- IGZO indium gallium zinc oxide
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Abstract
Description
Claims (11)
- 一种阵列基板,包括位于衬底基板表面的薄膜晶体管、设置于所述薄膜晶体管上方的第一钝化层,以及位于所述第一钝化层表面的透明电极层,其中所述第一钝化层包括:第一子薄膜层,以及位于所述第一子薄膜层表面与所述透明电极层相接触的第二子薄膜层;所述第二子薄膜层的薄膜致密度大于所述第一子薄膜层。
- 根据权利要求1所述的阵列基板,其中,构成所述第一子薄膜层的材料为二氧化硅;构成所述第二子薄膜层的材料为氮化硅或氮氧化硅中的至少一种。
- 根据权利要求1所述的阵列基板,其中,在所述透明电极层为公共电极层的情况下,所述阵列基板还包括,位于所述薄膜晶体管与所述第一钝化层之间的第二钝化层、依次位于所述第二钝化层表面的有机绝缘层、像素电极层;所述第一钝化层还包括,与所述有机绝缘层和所述像素电极层相接触的第三子薄膜层;构成所述第三子薄膜层的材料为氮化硅或氮氧化硅中的至少一种。
- 根据权利要求2或3所述的阵列基板,其中,所述第一子薄膜层的厚度为2000埃以下;所述第二子薄膜层或所述第三子薄膜层的厚度为100~500埃。
- 根据权利要求1所述的阵列基板,其中,所述薄膜晶体管的半导体有源层由氧化物半导体材料构成。
- 一种显示装置,包括如权利要求1-5任一项所述的阵列基板。
- 一种阵列基板的制作方法,包括:在衬底基板上,通过构图工艺形成薄膜晶体管;在所述薄膜晶体管上方,形成第一子薄膜层;在所述第一子薄膜层的表面,形成第二子薄膜层;其中,所述第一子薄膜层与所述第二子薄膜层构成第一钝化层,所述第二子薄膜层的薄膜致密度大于所述第一子薄膜层;在所述第一钝化层的表面,通过构图工艺形成透明电极层。
- 根据权利要求7所述的阵列基板的制作方法,其中,构成所述第一子薄膜层的材料为二氧化硅;构成所述第二子薄膜层的材料为氮化硅或氮氧化硅。
- 根据权利要求7所述的阵列基板的制作方法,其中,在所述透明电极层为公共电极层的情况下,在形成薄膜晶体管的步骤之后,形成所述第一子薄膜层的步骤之前,所述方法包括:在所述薄膜晶体管远离所述衬底基板一侧的表面,沉积第二钝化层;在所述第二钝化层的表面形成有机绝缘层;在所述有机绝缘层中,通过构图工艺形成对应所述薄膜晶体管的漏极位置处的过孔;在所述有机绝缘层的表面形成像素电极层,所述像素电极层通过所述过孔与所述薄膜晶体管的漏极相连接;在所述像素电极层以及所述有机绝缘层的表面形成第三子薄膜层;构成所述第三子薄膜层的材料为氮化硅或氮氧化硅中的至少一种。
- 根据权利要求8或9所述的阵列基板的制作方法,其中,所述第一子薄膜层的厚度为2000埃以下;所述第二子薄膜层或所述第三子薄膜层的厚度为100~500埃。
- 根据权利要求8所述的阵列基板的制作方法,其中所述薄膜晶体管的半导体有源层由氧化物半导体材料构成。
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