CN109148491B - 一种阵列基板及其制备方法、显示装置 - Google Patents

一种阵列基板及其制备方法、显示装置 Download PDF

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CN109148491B
CN109148491B CN201811294729.9A CN201811294729A CN109148491B CN 109148491 B CN109148491 B CN 109148491B CN 201811294729 A CN201811294729 A CN 201811294729A CN 109148491 B CN109148491 B CN 109148491B
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polycrystalline silicon
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张永强
樊君
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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Ordos Yuansheng Optoelectronics Co Ltd
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Abstract

本发明公开了一种阵列基板及其制备方法、显示装置，阵列基板包括位于***区的至少一个低温多晶硅TFT和位于显示区的至少一个氧化物TFT，该阵列基板的制备方法包括在***区形成低温多晶硅TFT有源层，在低温多晶硅TFT有源层上方形成低温多晶硅TFT栅极，并形成与低温多晶硅TFT有源层电连接的低温多晶硅TFT源极和漏极；在显示区形成氧化物TFT有源层以及与低温多晶硅TFT源极和漏极同层设置的氧化物TFT栅极，并形成与氧化物TFT有源层电绝缘的氧化物膜层；在氧化物膜层上采用湿刻法形成氧化物TFT源极和漏极，其中，氧化物TFT源极与氧化物TFT有源层电连接，该方法能够减少氧化物膜层的损伤，提高产品良率。

Description

一种阵列基板及其制备方法、显示装置
技术领域
本发明涉及显示技术领域，尤指一种阵列基板及其制备方法、显示装置。
背景技术
在显示技术领域，薄膜晶体管液晶显示器(Thin Film Transistor LiquidCrystal Display，TFT-LCD)以其具有轻、薄、功耗低、亮度高以及画质高等优点，在平板显示领域占据重要的地位。尤其是大尺寸、高分辨率以及高画质的平板显示装置，如液晶电视，在当前的平板显示器市场已经占据了主导地位。
随着TFT-LCD技术的发展，人们对显示装置的低功耗性能要求越来越高，能实现较低能耗的LTPS(低温多晶硅)显示技术逐渐成为主流，与多晶硅显示技术相比，LTPS电子迁移率大，但也存在漏电流大的问题，所以采用氧化物膜层代替多晶硅作为有源层的氧化物薄膜晶体管以其开态电流大、迁移率高、均一性好、透明度高以及制备工艺简单被广泛应用于液晶显示器中。
虽然现有技术中的氧化物薄膜晶体管的漏电流一般较小，能使像素刷新频率降低，从而降低功耗，但LTPS工艺中源漏极金属层主要采用干刻工艺制备，在制备过程中会对氧化物膜层造成损伤，从而造成氧化物薄膜晶体管不良。
因此，如何减少氧化物膜层的损伤是本领域技术人员亟需解决的技术问题。
发明内容
有鉴于此，本发明实施例提供了一种阵列基板及其制备方法、显示装置，该阵列基板的制备方法能够减少氧化物膜层的损伤，提高产品良率。
本发明实施例提供一种阵列基板的制备方法，所述阵列基板包括位于***区的至少一个低温多晶硅TFT和位于显示区的至少一个氧化物TFT，阵列基板的制备过程包括：
在***区形成低温多晶硅TFT有源层，在低温多晶硅TFT有源层上方形成低温多晶硅TFT栅极，并形成与所述低温多晶硅TFT有源层电连接的低温多晶硅TFT源极和漏极；
在显示区形成氧化物TFT有源层以及与低温多晶硅TFT源极和漏极同层设置的氧化物TFT栅极，并形成与氧化物TFT有源层电绝缘的氧化物膜层；
在氧化物膜层上采用湿刻法形成氧化物TFT源极和漏极，其中，氧化物TFT源极与氧化物TFT有源层电连接。
在上述阵列基板的制备方法中，通过将现有技术中的源漏极金属层分离成低温多晶硅TFT源极和漏极和与氧化物TFT源极和漏极，并且氧化物TFT源极和漏极采用湿刻法制备，以避免制备氧化物TFT源极和漏极时对氧化物膜层造成侵蚀，进而提高阵列基板的产品良率；具体过程为：首先，在***区形成低温多晶硅TFT有源层，在低温多晶硅TFT有源层上方形成低温多晶硅TFT栅极，并采用干刻法形成与低温多晶硅TFT有源层电连接的低温多晶硅TFT源极和漏极，接着，在显示区形成氧化物TFT有源层以及与低温多晶硅TFT源极和漏极同层设置的氧化物TFT栅极，并形成与氧化物TFT有源层电绝缘的氧化物膜层，最后，采用湿刻法在氧化物膜层上形成氧化物TFT源极和漏极，其中，氧化物TFT源极与氧化物TFT有源层电连接，通过不同的步骤制备低温多晶硅TFT源极和漏极和与氧化物TFT源极和漏极，即将现有技术中的源漏极金属层采用不同的制备方法进行分离，而与氧化物膜层同层设置的氧化物TFT源极和漏极采用湿刻法制备的方式避免对氧化物膜层造成侵蚀，而氧化物TFT源极和漏极与氧化物膜层同层设置、且三者只设置于显示区，并且将氧化物TFT源极与位于其下方的氧化物TFT有源层电连接，能够精确管控阵列基板的像素开口，提高湿刻法制备时的刻蚀均一性以及刻蚀精度。
因此，上述阵列基板的制备方法能够减少氧化物膜层的损伤，提高产品良率。
优选地，所述在低温多晶硅TFT有源层上方形成低温多晶硅TFT栅极，并形成与所述低温多晶硅TFT有源层电连接的低温多晶硅TFT源极和漏极，具体包括：
在低温多晶硅TFT有源层上制备第一绝缘层，并在第一绝缘层上制备栅极金属层，对***区的栅极金属层进行图形化处理形成低温多晶硅TFT栅极；
在栅极金属层上制备层间介质层，并在层间介质层上制备第一金属层，对***区的第一金属层进行图形化处理形成所述低温多晶硅TFT源极和漏极；
所述低温多晶硅TFT源极和漏极与低温多晶硅TFT有源层通过过孔连接。
优选地，所述在显示区形成氧化物TFT有源层以及与低温多晶硅TFT源极和漏极同层设置的氧化物TFT栅极，具体包括：
对显示区的第一金属层进行图形化处理形成所述氧化物TFT有源层；
对显示区的栅极金属层和第一金属层分别进行图形化处理且通过过孔连接，以形成所述氧化物TFT栅极。
优选地，所述形成与氧化物TFT有源层电绝缘的氧化物膜层，具体包括：
在氧化物TFT有源层上制备第二绝缘层，并在显示区的第二绝缘层上采用等离子体增强化学气相沉积方法沉积氧化物膜层，所述氧化物膜层材料为金属氧化物或金属氮氧化物。
优选地，所述在氧化物膜层上采用湿刻法形成氧化物TFT源极和漏极，具体包括：
在显示区的第二绝缘层上制备第二金属层，采用湿刻法对第二金属层进行图形化处理形成所述氧化物TFT源极和漏极，所述氧化物TFT源极和漏极搭接在所述氧化物膜层上，所述氧化物TFT源极通过过孔跳接到所述氧化物TFT有源层上。
优选地，阵列基板的制备方法还包括在所述氧化物TFT源极和漏极上依次形成第一保护层、第一平坦层、公共电极层、第二保护层和氧化物TFT像素电极，其中，所述氧化物TFT像素电极与所述氧化物TFT漏极电连接。
优选地，在形成第一金属层之后，在形成所述第二绝缘层之前，还包括在位于显示区的层间介质层上形成氧化物TFT触控走线，所述氧化物TFT触控走线与公共电极层电连接。
优选地，在形成所述第一平坦层之后、在形成所述第二保护层之前，还包括在位于显示区的第一平坦层上依次形成第三保护层、氧化物TFT触控走线和第二平坦层，其中，所述氧化物TFT触控走线与所述公共电极层电连接。
另外，本发明还提供一种阵列基板，包括位于***区的至少一个低温多晶硅TFT和位于显示区的至少一个氧化物TFT，其中：
所述低温多晶硅TFT包括低温多晶硅TFT有源层，形成于低温多晶硅TFT有源层上方的低温多晶硅TFT栅极，以及与所述低温多晶硅TFT有源层电连接的低温多晶硅TFT源极和漏极；
所述氧化物TFT包括氧化物TFT有源层、与低温多晶硅TFT源极和漏极同层设置的氧化物TFT栅极，以及与氧化物TFT有源层电绝缘的氧化物膜层；
在氧化物膜层上采用湿刻法形成有氧化物TFT源极和漏极，其中，所述氧化物TFT源极与氧化物TFT有源层电连接。
优选地，所述低温多晶硅TFT有源层包括多晶硅，所述氧化物TFT有源层包括金属氧化物或金属氮氧化物。
另外，本发明还提供一种显示装置，包括上述任意技术方案所述的阵列基板。
附图说明
图1为本发明实施例提供的阵列基板的制备方法的流程示意图；
图2a至图2e分别为本发明实施例提供的阵列基板的制备方法至执行各步骤后的结构示意图；
图3为图2e中阵列基板的一种结构示意图；
图4a至图4f分别为本发明实施例提供的阵列基板的制备方法至执行各步骤后的结构示意图；
图5为图4f中阵列基板的一种结构示意图。
具体实施方式
下面结合附图，对本发明实施例提供的薄膜晶体管的制备方法、薄膜晶体管、阵列基板及显示装置的具体实施方式进行详细地说明。
其中，附图中各膜层厚度和形状不反映阵列基板的真实比例，目的只是示意说明本发明内容。
请参考图1、图2a-图2e以及图4a-图4f，本发明实施例提供了一种阵列基板的制备方法，其中，阵列基板包括位于***区的至少一个低温多晶硅TFT和位于显示区的至少一个氧化物TFT，阵列基板的制备过程包括：
步骤S101，如图2a以及图4a所示，在***区形成低温多晶硅TFT有源层3，在低温多晶硅TFT有源层3上方形成低温多晶硅TFT栅极5，并形成与低温多晶硅TFT有源层3电连接的低温多晶硅TFT源极和漏极；
步骤S102，如图2b-图2c以及图4b-图4c所示，在显示区形成氧化物TFT有源层7以及与低温多晶硅TFT源极和漏极同层设置的氧化物TFT栅极20，并形成与氧化物TFT有源层7电绝缘的氧化物膜层11；
步骤S103，如图2d以及图4d所示，在氧化物膜层11上采用湿刻法形成氧化物TFT源极9和氧化物TFT漏极10，其中，氧化物TFT源极9与氧化物TFT有源层7电连接。
在上述阵列基板的制备方法中，通过将现有技术中的源漏极金属层分离成低温多晶硅TFT源极和漏极和与氧化物膜层11同层设置的氧化物TFT源极9和氧化物TFT漏极10，并且氧化物TFT源极9和氧化物TFT漏极10采用湿刻法制备，以避免制备氧化物TFT源极9和氧化物TFT漏极10时对氧化物膜层11造成侵蚀，进而提高阵列基板的产品良率；具体过程为：根据步骤S101，在***区形成低温多晶硅TFT有源层3，在低温多晶硅TFT有源层3上方形成低温多晶硅TFT栅极5，并采用干刻法形成与低温多晶硅TFT有源层3电连接的低温多晶硅TFT源极和漏极，并且低温多晶硅TFT栅极5数据走线的宽度精准，根据步骤S102，在显示区形成氧化物TFT有源层7以及与低温多晶硅TFT源极和漏极同层设置的氧化物TFT栅极20，并形成与氧化物TFT有源层7电绝缘的氧化物膜层11，根据步骤S103，在氧化物膜层11上采用湿刻法形成氧化物TFT源极9和氧化物TFT漏极10，其中，氧化物TFT源极9与氧化物TFT有源层7电连接，通过不同的步骤制备低温多晶硅TFT源极和漏极和氧化物TFT源极9和氧化物TFT漏极10，即将现有技术中的源漏极金属层采用不同的制备方法进行分离，而与氧化物膜层11同层设置的氧化物TFT源极9和氧化物TFT漏极10采用湿刻法制备的方式避免对氧化物膜层11造成侵蚀，而氧化物TFT源极9和氧化物TFT漏极10与氧化物膜层11同层设置、且三者只设置于显示区，并且将氧化物TFT源极9与位于其下方的氧化物TFT有源层7电连接，能够精确管控阵列基板的像素开口，提高湿刻法制备时的刻蚀均一性以及刻蚀精度。
因此，上述阵列基板的制备方法能够减少氧化物膜层11的损伤，提高产品良率。
一种优选实施方式中，如图2a以及图4a所示，在低温多晶硅TFT有源层3上方形成低温多晶硅TFT栅极5，并形成与低温多晶硅TFT有源层3电连接的低温多晶硅TFT源极和漏极，具体包括：
在低温多晶硅TFT有源层3上制备第一绝缘层4，并在第一绝缘层4上制备栅极金属层，对***区的栅极金属层进行图形化处理形成低温多晶硅TFT栅极5；
在栅极金属层上制备层间介质层6，并在层间介质层6上制备第一金属层，对***区的第一金属层进行图形化处理形成低温多晶硅TFT源极和漏极；
低温多晶硅TFT源极和漏极与低温多晶硅TFT有源层3通过过孔连接。
在上述阵列基板的制备方法中，采用干刻法制备低温多晶硅TFT源极和漏极，首先在衬底基板1的整个区域上形成缓冲层2，接着在***区形成低温多晶硅TFT有源层3，其中低温多晶硅TFT有源层3包括多晶硅材料，继续在整个区域上依次制备第一绝缘层4和栅极金属层，并对栅极金属层进行图案化，图形化后的***区的栅极金属层形成低温多晶硅TFT栅极5，然后在整个区域上依次制备层间介质层6和第一金属层，并对第一金属层进行图案化，图形化后的***区的第一金属层形成低温多晶硅TFT源极和漏极，其中，低温多晶硅TFT源极和漏极与低温多晶硅TFT有源层3通过过孔连接，通过上述方法能够方便快捷地制备低温多晶硅TFT源极和漏极。
具体地，在显示区形成氧化物TFT有源层7以及与低温多晶硅TFT源极和漏极同层设置的氧化物TFT栅极20，如图2b以及图4b所示，具体包括：
对显示区的第一金属层进行图形化处理形成氧化物TFT有源层7；
对显示区的栅极金属层和第一金属层分别进行图形化处理且通过过孔连接，以形成氧化物TFT栅极20。
在上述阵列基板的制备方法中，图形化后的显示区的第一金属层形成氧化物TFT有源层7，其中，氧化物TFT有源层7包括金属材料，图形化后的显示区的栅极金属层和第一金属层通过过孔连接形成氧化物TFT栅极20，通过上述方法能够方便快捷地制备氧化物TFT栅极20。
具体地，形成与氧化物TFT有源层7电绝缘的氧化物膜层11，具体包括：
如图2c以及图4c所示，在氧化物TFT有源层7上制备第二绝缘层8，并在显示区的第二绝缘层8上采用等离子体增强化学气相沉积方法在位于显示区的第二绝缘层8上沉积氧化物膜层11，氧化物膜层11可以材料为金属氧化物或金属氮氧化物。
具体地，在氧化物膜层11上采用湿刻法形成氧化物TFT源极9和氧化物TFT漏极10，具体包括：
如图2d以及图4c所示，在显示区的第二绝缘层8上制备第二金属层，采用湿刻法对第二金属层进行图形化处理形成氧化物TFT源极9和氧化物TFT漏极10，氧化物TFT源极9和氧化物TFT漏极10搭接在氧化物膜层11上，氧化物TFT源极9通过过孔跳接到氧化物TFT有源层7上。
在上述阵列基板的制备方法中，为了形成同层设置的氧化物TFT源极9、氧化物TFT漏极10以及氧化物膜层11，首先采用等离子体增强化学气相沉积方法或其他能够满足功能的方法在位于显示区的第二绝缘层8上沉积氧化物膜层11，此时氧化物膜层11可以材料为金属氧化物或金属氮氧化物，也可以为金属氧化物和金属氮氧化物的复合，还可以为其他能够满足功能的材料；接着在位于显示区的第二绝缘层8上采用湿刻法制备氧化物TFT源极9和氧化物TFT漏极10，此时氧化物TFT源极9和氧化物TFT漏极10搭接在氧化物膜层11上，而由于氧化物TFT源极9和氧化物TFT漏极10采用湿刻法制备的方式能够避免对氧化物膜层11造成侵蚀，而由于氧化物TFT源极9通过位于其下方的第二绝缘层8的过孔跳接到氧化物TFT有源层7上，能够精确管控阵列基板的像素开口，提高刻蚀均一性以及刻蚀精度，提高产品良率。
具体地，阵列基板的制备方法还包括在氧化物TFT源极9和氧化物TFT漏极10上依次形成第一保护层12、第一平坦层13、公共电极层18、第二保护层16和氧化物TFT像素电极19，其中，氧化物TFT像素电极19与漏电极10电连接。
在上述阵列基板的制备方法中，与传统的9掩模版制备工艺相比，减少了制备遮光层所需的掩模版，增加了制备第二绝缘层8、氧化物膜层11、氧化物TFT源极9、氧化物TFT漏极10以及第二保护层16所需的掩模版，能够较为简单快速的制备阵列基板。
在上述阵列基板的制备方法的基础上，为了实现触控功能，需要在阵列基板中增加氧化物TFT触控走线17。
更具体地，如图2a以及图3所示，在形成第一金属层之后，在形成第二绝缘层8之前，还包括在位于***区的层间介质层6上形成氧化物TFT触控走线17。
在上述阵列基板的制备方法中，氧化物TFT触控走线17设置在层间介质层6上，在制备时，可以采用同一掩模版在层间介质层6上形成第一源漏极金属层7以及在显示区形成氧化物TFT触控走线17。
更具体地，如图2e所示，在形成第一平坦层13之后、在形成第二保护层16之前，还包括在位于***区的层间介质层6上形成公共电极层18，公共电极层18与氧化物TFT触控走线17电连接。
具体地，如图4c、图4d、图4e、图4f以及图5所示，在形成第一平坦层13之后、在形成第二保护层16之前，还包括在位于***区的第一平坦层13上依次形成第三保护层14、氧化物TFT触控走线17、第二平坦层15和公共电极层18，其中，公共电极层18与氧化物TFT触控走线17电连接。
在上述阵列基板的制备方法中，氧化物TFT触控走线17设置在第三保护层14和第二平坦层15之间，在制备时，第一金属层和氧化物TFT触控走线17采用两个掩模版，可使工艺上不必考虑同层金属刻蚀条件的工艺极限，不存在工艺间隔过小无法对应的情况。同时，将氧化物TFT触控走线17尽可能的做到氧化物TFT源极9被黑矩阵遮挡层范围内，氧化物TFT触控走线17所占用开口面积较小，能够大大提高产品的开口率。
另外，本发明还提供一种阵列基板，包括位于***区的至少一个低温多晶硅TFT和位于显示区的至少一个氧化物TFT，其中：
低温多晶硅TFT包括低温多晶硅TFT有源层3，形成于低温多晶硅TFT有源层3上方的低温多晶硅TFT栅极5，以及与低温多晶硅TFT有源层3电连接的低温多晶硅TFT源极和漏极；
氧化物TFT包括氧化物TFT有源层7、与低温多晶硅TFT源极和漏极同层设置的氧化物TFT栅极20，以及与氧化物TFT有源层7电绝缘的氧化物膜层11；
在氧化物膜层11上采用湿刻法形成有氧化物TFT源极9和氧化物TFT漏极10，其中，氧化物TFT源极9与氧化物TFT有源层7电连接。
在上述阵列基板中，由于氧化物TFT源极9和氧化物TFT漏极10采用湿刻法制备，避免制备氧化物TFT源极9和氧化物TFT漏极10时对氧化物膜层11造成侵蚀，使得氧化物膜层11的产品良率较高，而氧化物TFT源极9和氧化物TFT漏极10与氧化物膜层11同层设置、且三者只设置于显示区，并且将氧化物TFT源极9与位于其下方的氧化物TFT有源层7电连接，能够精确管控阵列基板的像素开口，提高湿刻法制备时的刻蚀均一性以及刻蚀精度，使得阵列基板的像素开口较为精确，阵列基板的精度较好，产品良率较高。
如图2e以及图4f所示，一种优选实施方式中，低温多晶硅TFT有源层3包括多晶硅，氧化物TFT有源层7包括金属氧化物或金属氮氧化物。
在上述阵列基板中，通过氧化物TFT有源层7包括金属氧化物或金属氮氧化物能够使得氧化物TFT的漏电流一般较小，能使像素刷新频率降低，从而降低功耗，提高产品良率。
另外，本发明还提供一种显示装置，包括上述任意技术方案的阵列基板，由于该阵列基板的像素开口较为精确，阵列基板的精度较好，产品良率较高，因此，具有该阵列基板的显示装置的产品良率较高。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (10)

1.一种阵列基板的制备方法，所述阵列基板包括位于***区的至少一个低温多晶硅TFT和位于显示区的至少一个氧化物TFT，其特征在于，阵列基板的制备过程包括：
在***区形成低温多晶硅TFT有源层，在低温多晶硅TFT有源层上方形成低温多晶硅TFT栅极，并形成与所述低温多晶硅TFT有源层电连接的低温多晶硅TFT源极和漏极；
在显示区形成氧化物TFT有源层以及与低温多晶硅TFT源极和漏极同层设置的氧化物TFT栅极，并形成与氧化物TFT有源层电绝缘的氧化物膜层；
在氧化物膜层上采用湿刻法形成氧化物TFT源极和漏极，其中，氧化物TFT源极与氧化物TFT有源层电连接；
所述在显示区形成氧化物TFT有源层以及与低温多晶硅TFT源极和漏极同层设置的氧化物TFT栅极，具体包括：
对显示区的第一金属层进行图形化处理形成所述氧化物TFT有源层；
对显示区的栅极金属层和第一金属层分别进行图形化处理且通过过孔连接，以形成所述氧化物TFT栅极。
2.如权利要求1所述的阵列基板的制备方法，其特征在于，所述在低温多晶硅TFT有源层上方形成低温多晶硅TFT栅极，并形成与所述低温多晶硅TFT有源层电连接的低温多晶硅TFT源极和漏极，具体包括：
在低温多晶硅TFT有源层上制备第一绝缘层，并在第一绝缘层上制备栅极金属层，对***区的栅极金属层进行图形化处理形成低温多晶硅TFT栅极；
在栅极金属层上制备层间介质层，并在层间介质层上制备第一金属层，对***区的第一金属层进行图形化处理形成所述低温多晶硅TFT源极和漏极；
所述低温多晶硅TFT源极和漏极与低温多晶硅TFT有源层通过过孔连接。
3.如权利要求1所述的阵列基板的制备方法，其特征在于，所述形成与氧化物TFT有源层电绝缘的氧化物膜层，具体包括：
在氧化物TFT有源层上制备第二绝缘层，并在显示区的第二绝缘层上采用等离子体增强化学气相沉积方法沉积氧化物膜层，所述氧化物膜层材料为金属氧化物或金属氮氧化物。
4.如权利要求3所述的阵列基板的制备方法，其特征在于，所述在氧化物膜层上采用湿刻法形成氧化物TFT源极和漏极，具体包括：
在显示区的第二绝缘层上制备第二金属层，采用湿刻法对第二金属层进行图形化处理形成所述氧化物TFT源极和漏极，所述氧化物TFT源极和漏极搭接在所述氧化物膜层上，所述氧化物TFT源极通过过孔跳接到所述氧化物TFT有源层上。
5.如权利要求4所述的阵列基板的制备方法，其特征在于，还包括在所述氧化物TFT源极和漏极上依次形成第一保护层、第一平坦层、公共电极层、第二保护层和氧化物TFT像素电极，其中，所述氧化物TFT像素电极与所述氧化物TFT漏极电连接。
6.如权利要求5所述的阵列基板的制备方法，其特征在于，在形成第一金属层之后，在形成所述第二绝缘层之前，还包括在位于显示区的层间介质层上形成氧化物TFT触控走线，所述氧化物TFT触控走线与所述公共电极层电连接。
7.如权利要求5所述的阵列基板的制备方法，其特征在于，在形成所述第一平坦层之后、在形成所述第二保护层之前，还包括在位于显示区的第一平坦层上依次形成第三保护层、氧化物TFT触控走线和第二平坦层，其中，所述氧化物TFT触控走线与所述公共电极层电连接。
8.一种阵列基板，其特征在于，包括位于***区的至少一个低温多晶硅TFT和位于显示区的至少一个氧化物TFT，其中：
所述低温多晶硅TFT包括低温多晶硅TFT有源层，形成于低温多晶硅TFT有源层上方的低温多晶硅TFT栅极，以及与所述低温多晶硅TFT有源层电连接的低温多晶硅TFT源极和漏极；
所述氧化物TFT包括氧化物TFT有源层、与低温多晶硅TFT源极和漏极同层设置的氧化物TFT栅极，以及与氧化物TFT有源层电绝缘的氧化物膜层；
在氧化物膜层上采用湿刻法形成有氧化物TFT源极和漏极，其中，所述氧化物TFT源极与氧化物TFT有源层电连接。
9.如权利要求8所述的阵列基板，其特征在于，所述低温多晶硅TFT有源层包括多晶硅，所述氧化物TFT有源层包括金属氧化物或金属氮氧化物。
10.一种显示装置，其特征在于，包括权利要求8-9任一项所述的阵列基板。
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