CN106505033B - 阵列基板及其制备方法、显示装置 - Google Patents
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- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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Abstract
本发明公开了一种阵列基板的制备方法,其中,用于制备形成有源层、源电极和漏电极的第二道光罩工序具体包括:依次沉积形成半导体薄膜层、N+掺杂薄膜层、金属薄膜层以及光刻胶层;应用灰色调光罩工艺对光刻胶层进行处理获得第一光刻胶掩膜版;依次应用第一湿刻工艺和第一干刻工艺,刻蚀所述金属薄膜层中、半导体薄膜层和N+掺杂薄膜层;对所述第一光刻胶掩膜版进行等离子体灰化处理,获得第二光刻胶掩膜版;应用第二湿刻工艺,刻蚀所述金属薄膜层;剥离去除所述第二光刻胶掩膜版,应用第二干刻工艺,刻蚀所述N+掺杂薄膜层。本发明还公开了按照如上方法制备得到的阵列基板以及包含该阵列基板的显示装置。
Description
技术领域
本发明涉及显示器技术领域,尤其涉及一种阵列基板及其制备方法,还涉及包含该阵列基板的显示装置。
背景技术
薄膜晶体管(Thin Film Transistor,TFT)是平板显示装置的重要组成部分,可形成在玻璃基板或塑料基板上,通常作为开光装置和驱动装置用在诸如LCD、OLED。薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display,简称TFT-LCD)具有体积小、功耗低、无辐射等特点,在当前的平板显示器市场中占据了主导地位。
TFT-LCD中的阵列基板是通过多次光罩工序(构图工序)形成结构图形来完成,每一次光罩工序中又分别包括涂胶、曝光、显影、刻蚀和剥离等工艺,其中刻蚀工艺包括干法刻蚀和湿法刻蚀。光罩工序的次数可以衡量制造薄膜晶体管阵列基板的繁简程度,减少光罩工序的次数就意味着制造成本的降低。薄膜晶体管阵列基板的制造技术经历了从7道光罩工序(7Mask)到目前的5道光罩工序(5Mask)的发展过程,5Mask技术成为现在的TFT-LCD阵列基板制造的主流。5Mask技术包括5次光罩工序,它们分别是栅电极光罩(Gate Mask),有源层光罩(Active Mask),源/漏电极光罩(S/D Mask),过孔光罩(ViaHole Mask)和像素电极光罩(Pixel Mask)。
目前,为了进一步降低生产成本,部分厂商开始使用4Mask技术,4Mask技术是以5Mask技术为基准,利用灰色调光罩(Gray Tone Mask)工艺,将有源层光罩(Active Mask)与源/漏电极光罩(S/D Mask)合并成一个Mask,通过调整刻蚀(Etch)工艺,从而完成原来Active Mask和S/D Mask的功能,即通过一次Mask工艺达到两次Mask工艺的效果。
现有的4Mask技术,参阅图1a-1g,用于制备形成有源层、源电极和漏电极的第二道光罩工序主要包括以下步骤:
(一)、如图1a所示,在栅极绝缘层1上依次沉积形成半导体薄膜层2、N+掺杂薄膜层3、金属薄膜层4以及光刻胶层5。
(二)、如图1b所示,应用灰色调光罩工艺将光刻胶层5制备获得第一光刻胶掩膜版5a。
(三)、如图1c所示,在第一光刻胶掩膜版5a的保护下,应用第一湿刻工艺,刻蚀所述金属薄膜层4。
(四)、如图1d所示,在所述第一光刻胶掩膜版5a的保护下,应用第一干刻工艺,刻蚀所述半导体薄膜层2和所述N+掺杂薄膜层3,获得有源层2a。
(五)、如图1e所示,对所述第一光刻胶掩膜版5a进行等离子体灰化处理,获得第二光刻胶掩膜版5b,所述第二光刻胶掩膜版5b的中间区域暴露出所述金属薄膜层4。
(六)、如图1f所示,在所述第二光刻胶掩膜版5b的保护下,应用第二湿刻工艺,刻蚀所述金属薄膜层4,获得源电极4a和漏电极4b。
(七)、如图1g所示,在所述第二光刻胶掩膜版5b的保护下,应用第二干刻工艺,刻蚀所述N+掺杂薄膜层3,形成N+接触层3a、3b。
(八)、如图1h所示,去除所述第二光刻胶掩膜版5b。
如上的工艺步骤中,步骤(六)进行湿刻工艺时,由于湿法刻蚀各向同性的性质,金属薄膜层4的侧向刻蚀严重,导致获得的源电极4a和漏电极4b的边缘相对于第二光刻胶掩膜版5b的边缘内缩,如图1f所示。步骤(七)进行干刻工艺时,由于干法刻蚀各向异性,刻蚀的等离子体垂直轰击,刻蚀后形成的N+接触层3a、3b的边缘相对于第二光刻胶掩膜版5b的边缘是齐平的,如图1g所示。即,最终得到的薄膜晶体管结构中,参阅图1h,源电极4a和漏电极4b的边缘与各自对应的N+接触层3a、3b的边缘并不是平滑过渡,而是N+接触层3a、3b的边缘相对于源电极4a和漏电极4b的边缘具有凸出尾部(tail)6,这将会影响薄膜晶体管的实际沟道长度,不利于获得具有高性能的薄膜晶体管。
发明内容
有鉴于此,本发明提供了一种阵列基板及其制备方法,应用四道光罩工序制备获得所述阵列基板中的薄膜晶体管和像素电极,通过对第二道光罩工序的具体步骤进行改进,提高了薄膜晶体管的性能。
一种阵列基板的制备方法,应用四道光罩工序制备获得所述阵列基板中的薄膜晶体管和像素电极,其中,用于制备形成有源层、源电极和漏电极的第二道光罩工序具体包括:在栅极绝缘层上依次沉积形成半导体薄膜层、N+掺杂薄膜层、金属薄膜层以及光刻胶层;应用灰色调光罩工艺对所述光刻胶层进行曝光、显影,获得第一光刻胶掩膜版;在所述第一光刻胶掩膜版的保护下,应用第一湿刻工艺,刻蚀去除所述金属薄膜层中未被所述第一光刻胶掩膜版覆盖的部分;在所述第一光刻胶掩膜版的保护下,应用第一干刻工艺,刻蚀去除所述半导体薄膜层和所述N+掺杂薄膜层中未被所述第一光刻胶掩膜版覆盖的部分,获得所述有源层;对所述第一光刻胶掩膜版进行等离子体灰化处理,获得第二光刻胶掩膜版,所述第二光刻胶掩膜版的中间区域暴露出所述金属薄膜层;在所述第二光刻胶掩膜版的保护下,应用第二湿刻工艺,刻蚀去除所述金属薄膜层中未被所述第二光刻胶掩膜版覆盖的部分,获得所述源电极和漏电极;剥离去除所述第二光刻胶掩膜版,应用第二干刻工艺,刻蚀去除所述N+掺杂薄膜层中位于所述源电极和漏电极之间的部分,在所述源电极和所述所述有源层之间以及所述漏电极和所述有源层之间分别获得N+接触层。
进一步地,该方法具体包括步骤:S1、在玻璃基板上应用第一道光罩工序制备形成栅电极;S2、在所述玻璃基板上制备形成覆盖所述栅电极的栅极绝缘层;S3、应用第二道光罩工序,在所述栅极绝缘层上制备形成有源层、源电极和漏电极;S4、在所述玻璃基板上制备形成覆盖所述有源层、源电极和漏电极的钝化层;S5、应用第三道光罩工序,在所述钝化层中制备形成过孔;S6、应用第四道光罩工序,在所述钝化层上制备形成像素电极;其中,所述像素电极通过所述过孔电性连接到所述源电极和漏电极的其中之一。
其中,所述半导体薄膜层的材料为氢化非晶硅或多晶硅。
其中,所述半导体薄膜层通过化学气相沉积工艺制备形成。
其中,所述N+掺杂薄膜层的材料为N+非晶硅或N+掺杂多晶硅。
其中,所述N+掺杂薄膜层通过化学气相沉积工艺制备形成。
其中,所述金属薄膜层的材料为Cr、W、Ti、Ta、Mo、Al或Cu的单层金属层,或者是Cr、W、Ti、Ta、Mo、Al和Cu中的任意两种或两种以上的金属组合构成的复合金属层。
其中,所述金属薄膜层通过溅射沉积工艺制备形成。
本发明提供了一种阵列基板,采用如上所述的制备方法制备获得。
本发明还提供了一种显示装置,包括如上所述的阵列基板。
本发明实施例中提供的一种阵列基板及其制备方法,应用四道光罩工序制备获得所述阵列基板中的薄膜晶体管和像素电极,对于用于制备形成有源层、源电极和漏电极的第二道光罩工序,在进行第二次湿刻工艺获得获得源电极和漏电极之后,首先剥离去除光刻胶掩膜版再进行第二次干刻工艺,由此制备得到的N+接触层的边缘与源电极和漏电极的边缘相对平齐,边缘没有凸出尾部,基本上属于平滑过渡,相比于现有技术,其制备得到的阵列基板中的薄膜晶体管具有更加优良的性能。
附图说明
图1a-图1h是现有技术中用于制备形成有源层、源电极和漏电极的第二道光罩工序的各步骤的示例性图示;
图2是本发明实施例1提供的阵列基板的结构示意图;
图3是本发明实施例1提供的阵列基板的制备方法的工艺流程图;
图4是本发明实施例1中的第二道光罩工序的工艺流程图;
图5a-图5h是本发明实施例1中的第二道光罩工序的各步骤的示例性图示;
图6是本发明实施例2提供的显示装置的结构示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚,下面结合附图对本发明的具体实施方式进行详细说明。这些优选实施方式的示例在附图中进行了例示。附图中所示和根据附图描述的本发明的实施方式仅仅是示例性的,并且本发明并不限于这些实施方式。
在此,还需要说明的是,为了避免因不必要的细节而模糊了本发明,在附图中仅仅示出了与根据本发明的方案密切相关的结构和/或处理步骤,而省略了与本发明关系不大的其他细节。
实施例1
本实施例提供了一种阵列基板,是一种薄膜晶体管阵列基板,如图2所示,所述阵列基板包括阵列设置于玻璃基板10上的多个薄膜晶体管20(附图中仅示例性示出了其中的一个薄膜晶体管20)和像素电极30,像素电极30与薄膜晶体管20电性连接。
具体地,参阅图2,所述薄膜晶体管20包括栅电极21、栅极绝缘层22、有源层23、源电极251和漏电极252。其中,栅电极21形成于所述玻璃基板10上,栅极绝缘层22覆设于所述栅电极21上,有源层23形成于所述栅极绝缘层22上,源电极251和漏电极252位于同一结构层中,形成于所述有源层23上。进一步的,所述源电极251和所述有源层23之间通过N+接触层241连接,所述源电极252和所述有源层23之间通过N+接触层242连接。其中,所述薄膜晶体管20上设置有钝化层40,所述像素电极30通过设置在所述钝化层40中的过孔电性连接到所述薄膜晶体管20中的漏电极252。
如上所提供的阵列基板,其中的薄膜晶体管20中,N+接触层241、242的边缘与源电极251和漏电极252的边缘相对平齐,边缘没有凸出尾部,基本上属于平滑过渡,N+接触层241、242的宽度不会影响到有源层23的沟道区长度,使得薄膜晶体管20具有更加优良的性能。
本实施例还提供了如上实施例所提供的阵列基板的制备方法,本实施例中,应用四道光罩工序制备获得所述阵列基板中的薄膜晶体管和像素电极。具体地,参阅图3,该方法具体包括步骤:
S1、在玻璃基板上应用第一道光罩工序制备形成栅电极。
此步骤可以采用任何可以通过一次光罩工序实现的现有技术来实现。其中,光罩工序包括沉积薄膜、涂胶、曝光、显影、刻蚀等形成图形的工艺。一次光罩工序,是指使用一张掩膜版Mask的构图工艺。例如,首先在玻璃基板10上沉积一层栅极金属薄膜并在栅极金属薄膜上涂覆光刻胶,然后使用栅极掩膜版对形成在栅极金属薄膜上的光刻胶层进行曝光显影后,需要保留的栅极金属薄膜上覆盖有光刻胶,而不需要保留的栅极金属薄膜上的光刻胶被去除;最后通过刻蚀步骤,将不需要的栅极金属薄膜刻蚀掉,剩余的栅极金属薄膜即为所需的图案化的栅极21。其中,栅极金属薄膜的材料为Cr、W、Ti、Ta、Mo、Al或Cu的单层金属层,或者是Cr、W、Ti、Ta、Mo、Al和Cu中的任意两种或两种以上的金属组合构成的复合金属层。形成栅极金属薄膜的工艺可以为溅射工艺,也可以为本领域技术人员所知的其它工艺。
S2、在所述玻璃基板上制备形成覆盖所述栅电极的栅极绝缘层。
具体地,所述栅极绝缘层22的材料可以为SiOx或SiNx,形成栅极绝缘层22的工艺可以为化学气相沉积工艺,也可以是本领域技术人员所知的其它工艺。
S3、应用第二道光罩工序,在所述栅极绝缘层上制备形成有源层、源电极和漏电极。
具体地,参阅图4以及图5a-图5h,第二道光罩工序主要包括以下步骤:
S31、如图5a所示,在栅极绝缘层22上依次沉积形成半导体薄膜层23a、N+掺杂薄膜层24a、金属薄膜层25a以及光刻胶层26。其中,所述半导体薄膜层23a的材料为氢化非晶硅或多晶硅,形成所述半导体薄膜层23a的工艺可以为化学气相沉积工艺,也可以是本领域技术人员所知的其它工艺。所述N+掺杂薄膜层24a的材料为N+非晶硅或N+掺杂多晶硅。形成所述N+掺杂薄膜层24a的工艺可以为化学气相沉积工艺,也可以是本领域技术人员所知的其它工艺。所述金属薄膜层25a的材料为Cr、W、Ti、Ta、Mo、Al或Cu的单层金属层,或者是Cr、W、Ti、Ta、Mo、Al和Cu中的任意两种或两种以上的金属组合构成的复合金属层;形成金属薄膜层25a的工艺可以为溅射工艺,也可以为本领域技术人员所知的其它工艺。
S32、如图5b所示,应用灰色调光罩工艺对光刻胶层26进行曝光、显影,获得第一光刻胶掩膜版26a。具体地,第一光刻胶掩膜版26a包括两侧的具有较大厚度的区域以及位于中间的具有厚度较小的区域。
S33、如图5c所示,在第一光刻胶掩膜版26a的保护下,应用第一湿刻工艺刻蚀金属薄膜层25a。该步骤中主要刻蚀去除所述金属薄膜层25a中未被所述第一光刻胶掩膜版26a覆盖的部分。
S34、如图5d所示,在第一光刻胶掩膜版26a的保护下,应用第一干刻工艺,刻蚀半导体薄膜层23a和N+掺杂薄膜层24a。该步骤中主要刻蚀去除所述导体薄膜层23a和所述N+掺杂薄膜层24a中未被所述第一光刻胶掩膜版覆盖的部分。其中,所述导体薄膜层23a经过刻蚀后保留的部分形成薄膜晶体管20的有源层23。
S35、如图5e所示,对第一光刻胶掩膜版26a进行等离子体灰化处理,获得第二光刻胶掩膜版26b。具体地,对第一光刻胶掩膜版26a进行等离子体灰化处理时,第一光刻胶掩膜版26a位于两侧的具有较大厚度的区域的厚度变小,而位于中间的具有厚度较小的区域则完全被去除,最终形成第二光刻胶掩膜版26b,即,所述第二光刻胶掩膜版26b的中间区域暴露出所述金属薄膜层25a。
S36、如图5f所示,在第二光刻胶掩膜版26b的保护下,应用第二湿刻工艺刻蚀金属薄膜层25a。该步骤中,主要刻蚀去除所述金属薄膜层25a中未被所述第二光刻胶掩膜版26b覆盖的部分,即,所述金属薄膜层25a从所述第二光刻胶掩膜版26b的中间区域暴露出的部分被刻蚀去除,对应于第二光刻胶掩膜版26b覆盖的部分则分别形成源电极251和漏电极252。由于湿法刻蚀各向同性的性质,获得的源电极251和漏电极252的边缘相对于第二光刻胶掩膜版26b的边缘内缩。
S37、如图5g所示,剥离去除所述第二光刻胶掩膜版26b。
S38、如图5h所示,应用第二干刻工艺刻蚀N+掺杂薄膜层24a。该步骤中,主要是刻蚀去除所述N+掺杂薄膜层24a中位于所述源电极251和漏电极252之间的部分,在所述源电极251和所述所述有源层23之间以及所述漏电极252和所述有源层23之间分别获得N+接触层241、242。其中,该步骤中,由于已经去除第二光刻胶掩膜版26b,此时对所述N+掺杂薄膜层24a的刻蚀是以源电极251和漏电极252为掩膜版,由于干法刻蚀各向异性,刻蚀的等离子体垂直轰击,刻蚀后得到的N+接触层241、242的边缘与源电极251和漏电极252的边缘相对平齐,边缘没有凸出尾部,基本上属于平滑过渡,N+接触层241、242的宽度不会影响到有源层23的沟道区长度,使得薄膜晶体管20具有更加优良的性能。
S4、在所述玻璃基板上制备形成覆盖所述薄膜晶体管的钝化层。
具体地,所述钝化层40的材料可以为SiOx或SiNx,形成钝化层40的工艺可以为化学气相沉积工艺,也可以是本领域技术人员所知的其它工艺。
S5、应用第三道光罩工序,在所述钝化层中制备形成过孔。
具体地,通过在钝化层40涂覆光刻胶,然后使用过孔掩膜版对形成光刻胶层进行曝光显影后,去除对应于需要形成过孔的位置的光刻胶;最后通过刻蚀步骤在所述钝化层40中制备形成过孔41。
S6、应用第四道光罩工序,在所述钝化层上制备形成像素电极。
具体地,首先在钝化层40上沉积一层像素电极薄膜并在像素电极薄膜上涂覆光刻胶,像素电极薄膜至少要填充在过孔41中;然后使用像素电极掩膜版对形成在光刻胶层进行曝光显影后,需要保留的像素电极薄膜上覆盖有光刻胶,而不需要保留的像素电极薄膜上的光刻胶被去除;最后通过刻蚀步骤,将不需要的像素电极薄膜刻蚀掉,剩余的像素电极薄膜即为所需的图案化的像素电极30。其中,所述像素电极30通过过孔41电性连接到所述漏电极252。其中,像素电极薄膜的材料可以是氧化铟锡(ITO),其形成工艺可以为溅射工艺,或是本领域技术人员所知的其它工艺。
实施例2
本实施例提供了一种显示装置,其中采用了如实施例1提供的薄膜晶体管阵列基板。该显示装置例如可以是薄膜晶体管液晶显示装置(TFT-LCD)或有机电致发光显示装置(OLED),采用了如实施例1提供的薄膜晶体管阵列基板,可以使得显示装置相比于现有技术具有更优越的性能,同时还降低了成本。具体地,以薄膜晶体管液晶显示装置为例,参阅图6,该液晶显示装置包括液晶面板100及背光模组200,所述液晶面板100与所述背光模组200相对设置,所述背光模组200提供显示光源给所述液晶面板100,以使所述液晶面板100显示影像。其中,液晶面板100包括相对设置的阵列基板101和滤光基板102,还包括位于阵列基板101和滤光基板102之间的液晶层103。其中,阵列基板101即采用了如实施例1提供的薄膜晶体管阵列基板。
需要说明的是,在本文中,诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来,而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且,术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含,从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素,而且还包括没有明确列出的其他要素,或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下,由语句“包括一个……”限定的要素,并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
以上所述仅是本申请的具体实施方式,应当指出,对于本技术领域的普通技术人员来说,在不脱离本申请原理的前提下,还可以做出若干改进和润饰,这些改进和润饰也应视为本申请的保护范围。
Claims (10)
1.一种阵列基板的制备方法,应用四道光罩工序制备获得所述阵列基板中的薄膜晶体管和像素电极,其特征在于,用于制备形成有源层、源电极和漏电极的第二道光罩工序具体包括:
在栅极绝缘层上依次沉积形成半导体薄膜层、N+掺杂薄膜层、金属薄膜层以及光刻胶层;
应用灰色调光罩工艺对所述光刻胶层进行曝光、显影,获得第一光刻胶掩膜版;
在所述第一光刻胶掩膜版的保护下,应用第一湿刻工艺,刻蚀去除所述金属薄膜层中未被所述第一光刻胶掩膜版覆盖的部分;
在所述第一光刻胶掩膜版的保护下,应用第一干刻工艺,刻蚀去除所述半导体薄膜层和所述N+掺杂薄膜层中未被所述第一光刻胶掩膜版覆盖的部分,获得所述有源层;
对所述第一光刻胶掩膜版进行等离子体灰化处理,获得第二光刻胶掩膜版,所述第二光刻胶掩膜版的中间区域暴露出所述金属薄膜层;
在所述第二光刻胶掩膜版的保护下,应用第二湿刻工艺,刻蚀去除所述金属薄膜层中未被所述第二光刻胶掩膜版覆盖的部分,获得所述源电极和漏电极;
剥离去除所述第二光刻胶掩膜版,应用第二干刻工艺,刻蚀去除所述N+掺杂薄膜层中位于所述源电极和漏电极之间的部分,在所述源电极和所述所述有源层之间以及所述漏电极和所述有源层之间分别获得N+接触层。
2.根据权利要求1所述的阵列基板的制备方法,其特征在于,该方法具体包括步骤:
S1、在玻璃基板上应用第一道光罩工序制备形成栅电极;
S2、在所述玻璃基板上制备形成覆盖所述栅电极的栅极绝缘层;
S3、应用第二道光罩工序,在所述栅极绝缘层上制备形成有源层、源电极和漏电极;
S4、在所述玻璃基板上制备形成覆盖所述有源层、源电极和漏电极的钝化层;
S5、应用第三道光罩工序,在所述钝化层中制备形成过孔;
S6、应用第四道光罩工序,在所述钝化层上制备形成像素电极;其中,所述像素电极通过所述过孔电性连接到所述源电极和漏电极的其中之一。
3.根据权利要求1或2所述的阵列基板的制备方法,其特征在于,所述半导体薄膜层的材料为氢化非晶硅或多晶硅。
4.根据权利要求3所述的阵列基板的制备方法,其特征在于,所述半导体薄膜层通过化学气相沉积工艺制备形成。
5.根据权利要求1或2所述的阵列基板的制备方法,其特征在于,所述N+掺杂薄膜层的材料为N+非晶硅或N+掺杂多晶硅。
6.根据权利要求5所述的阵列基板的制备方法,其特征在于,所述N+掺杂薄膜层通过化学气相沉积工艺制备形成。
7.根据权利要求1或2所述的阵列基板的制备方法,其特征在于,所述金属薄膜层的材料为Cr、W、Ti、Ta、Mo、Al或Cu的单层金属层,或者是Cr、W、Ti、Ta、Mo、Al和Cu中的任意两种或两种以上的金属组合构成的复合金属层。
8.根据权利要求7所述的阵列基板的制备方法,其特征在于,所述金属薄膜层通过溅射沉积工艺制备形成。
9.一种阵列基板,采用如权利要求1-8任一所述的阵列基板的制备方法制备获得。
10.一种显示装置,包括权利要求9所述的阵列基板。
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CN107591416B (zh) * | 2017-08-29 | 2020-04-14 | 惠科股份有限公司 | 一种阵列基板的制造方法和阵列基板 |
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US10224349B1 (en) * | 2017-12-05 | 2019-03-05 | Shenzhen China Star Optoelecronics Semiconductor Display Technology Co., Ltd. | Method of manufacturing TFT array substrate and display device |
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