WO2016070512A1 - 低温多晶硅薄膜晶体管goa电路 - Google Patents
低温多晶硅薄膜晶体管goa电路 Download PDFInfo
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- WO2016070512A1 WO2016070512A1 PCT/CN2015/072357 CN2015072357W WO2016070512A1 WO 2016070512 A1 WO2016070512 A1 WO 2016070512A1 CN 2015072357 W CN2015072357 W CN 2015072357W WO 2016070512 A1 WO2016070512 A1 WO 2016070512A1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0404—Matrix technologies
- G09G2300/0408—Integration of the drivers onto the display substrate
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0404—Matrix technologies
- G09G2300/0417—Special arrangements specific to the use of low carrier mobility technology
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0871—Several active elements per pixel in active matrix panels with level shifting
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0243—Details of the generation of driving signals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
- G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels
Definitions
- the present invention relates to the field of display technologies, and in particular, to a low temperature polysilicon thin film transistor GOA circuit.
- GOA Gate Drive On Array
- TFT thin film transistor
- Array liquid crystal display array
- the GOA circuit is mainly composed of a pull-up part, a pull-up control part, a transfer part, a pull-down part, and a pull-down sustain circuit part (
- the pull-down holding part and the boost part responsible for the potential rise are generally composed of a bootstrap capacitor.
- the pull-up portion is mainly responsible for outputting an input clock signal (Clock) to the gate of the thin film transistor as a driving signal of the liquid crystal display.
- the pull-up control part is mainly responsible for controlling the opening of the pull-up part, which is generally a signal transmitted by the upper-level GOA circuit.
- the pull-down portion is mainly responsible for quickly pulling the scan signal (that is, the potential of the gate of the thin film transistor) to a low level after outputting the scan signal.
- the pull-down sustain circuit portion is mainly responsible for keeping the scan signal and the signal of the pull-up portion in a closed state (ie, a set negative potential).
- the rising portion is mainly responsible for the secondary rise of the potential of the pull-up portion to ensure the normal output of the pull-up portion.
- LTPS-TFT liquid crystal displays have attracted more and more attention.
- LTPS-TFT liquid crystal displays have high resolution and response. Fast speed, high brightness, high aperture ratio, etc.
- the low temperature polysilicon has an order of arrangement of amorphous silicon (a-Si)
- the low temperature polysilicon semiconductor itself has an ultrahigh electron mobility, which is 100 times higher than that of an amorphous silicon semiconductor.
- the gate driver can be fabricated on the thin film transistor array substrate by using GOA technology to achieve the goal of system integration, space saving and cost of driving the IC.
- a single type (single N-type or single P-type) GOA circuit has a complicated structure, poor circuit characteristics, and particularly a problem of large power consumption, especially in small and medium sizes, and power consumption becomes An important indicator of its performance research, therefore, how to effectively reduce power consumption, while enhancing the overall stability of circuit structure and performance has become an important issue in the current low temperature polysilicon semiconductor thin film transistor GOA circuit.
- the object of the present invention is to provide a low-temperature polysilicon semiconductor thin film transistor GOA circuit, which can solve the problem that the device circuit stability of the LTPS single TFT is poor and the power consumption is large; and solve the problem of current TFT leakage of a single type GOA circuit, and optimize The performance of the circuit; and can be designed with ultra-narrow bezel or borderless.
- the present invention provides a low temperature polysilicon semiconductor thin film transistor GOA circuit for forward scan transmission, including a plurality of cascaded GOA units, wherein N is a positive integer, and the Nth stage GOA unit uses a plurality of N And a plurality of P-type transistors, the N-th stage GOA unit includes: a transmission portion, a transmission control portion, a data storage portion, a data clearing portion, an output control portion, and an output buffer portion;
- the transmission portion is electrically connected to the first low frequency signal, the second low frequency signal, the driving output end of the N-1th GOA unit of the previous stage of the Nth stage GOA unit, and the data storage portion;
- the transmission The control portion is electrically connected to the driving output of the N+1th GOA unit of the subsequent stage of the Nth stage GOA unit, and the driving output of the N-1th GOA unit of the previous stage of the Nth stage GOA unit
- the data storage part is electrically connected to the transmission part, the transmission control part, the data clearing part, the power supply high potential and the low power supply
- the data clearing portion is electrically connected to the data storage portion, the output control portion, the power supply high potential and the reset signal end;
- the output control portion is electrically connected to the data clearing portion, the output buffer portion, and the driving output
- the first low frequency signal corresponds to a DC high potential
- the second low frequency signal corresponds to a DC low potential
- the transmission part includes:
- the gate of the first P-type transistor is electrically connected to the second low-frequency signal, and the source is electrically connected to the first-stage N-1th GOA unit of the N-th stage GOA unit a driving output end, the drain is electrically connected to the first node;
- the gate of the second N-type transistor is electrically connected to the first low-frequency signal, and the source is electrically connected to the first-stage N-1th GOA unit of the N-th stage GOA unit a driving output end, the drain is electrically connected to the first node;
- the transmission control portion includes:
- the gate of the fifth P-type transistor is electrically connected to a driving output end of the N-1th GOA unit of the previous stage of the Nth stage GOA unit, and the source is electrically connected The power source is high, and the drain is electrically connected to the source of the sixth P-type transistor;
- the gate of the sixth P-type transistor is electrically connected to a driving output end of the N+1th GOA unit of the subsequent stage of the Nth stage GOA unit, and the source is electrically connected a drain of the fifth P-type transistor, the drain is electrically connected to the source of the seventh N-type transistor;
- the gate of the seventh N-type transistor is electrically connected to a driving output end of the N-1th GOA unit of the previous stage of the Nth stage GOA unit, and the source is electrically connected a drain of the sixth P-type transistor, the drain is electrically connected to the low potential of the power source;
- An eighth N-type transistor the gate of the eighth N-type transistor is electrically connected to a driving output end of the N+1th GOA unit of the subsequent stage of the Nth stage GOA unit, and the source is electrically connected a drain of the sixth P-type transistor, the drain is electrically connected to the low potential of the power source;
- the gate of the ninth P-type transistor is electrically connected to the drain of the sixth P-type transistor, the source is electrically connected to the high potential of the power source, and the drain is electrically connected to the tenth N-type The source of the transistor;
- the gate of the tenth N-type transistor is electrically connected to the drain of the sixth P-type transistor, the source is electrically connected to the drain of the ninth P-type transistor, and the drain is electrically connected At low power supply;
- An eleventh P-type transistor the gate of the eleventh P-type transistor is electrically connected to the drain of the sixth P-type transistor, and the source is electrically connected to the source and drain of the twelfth N-type transistor Electrically connected to the M-2th timing signal;
- the gate of the twelfth N-type transistor is electrically connected to the drain of the ninth P-type transistor, and the source is electrically connected to the source and drain of the eleventh P-type transistor Electrically connected to the M-2th timing signal;
- the data storage part includes:
- the gate of the thirteenth N-type transistor is electrically connected to the source of the eleventh P-type transistor, and the source is electrically connected to the drain of the fourteenth P-type transistor, and the drain Very electrically connected to the low potential of the power supply;
- the gate of the fourteenth P-type transistor is electrically connected to the source of the eleventh P-type transistor, the source is electrically connected to the power supply high potential, and the drain is electrically connected to the first The source of the thirteen N-type transistor;
- the gate of the fifteenth P-type transistor is electrically connected to the source of the thirteenth N-type transistor, the source is electrically connected to the high potential of the power source, and the drain is electrically connected to the first The source of a sixteen P-type transistor;
- the gate of the sixteenth P-type transistor is electrically connected to the first node, the source is electrically connected to the drain of the fifteenth P-type transistor, and the drain is electrically connected to the first Seventeen The source of the N-type transistor;
- the gate of the seventeenth N-type transistor is electrically connected to the first node, the source is electrically connected to the drain of the sixteenth P-type transistor, and the drain is electrically connected to the first The source of the eighteen N-type transistor;
- An eighteenth N-type transistor the gate of the eighteenth N-type transistor is electrically connected to the source of the eleventh P-type transistor, and the source is electrically connected to the drain of the seventeenth N-type transistor, and the drain Very electrically connected to the low potential of the power supply;
- the data clearing part includes:
- the gate of the twenty-third P-type transistor is electrically connected to the reset signal terminal, the source is electrically connected to the power supply high potential, and the drain is electrically connected to the sixteenth P-type The drain of the transistor;
- the output control portion (500) includes
- the gate of the twenty-fourth P-type transistor is electrically connected to the drain of the sixteenth P-type transistor, the source is electrically connected to the power supply high potential, and the drain is electrically connected At the drive output;
- the gate of the twenty-fifth N-type transistor is electrically connected to the drain of the sixteenth P-type transistor, the source is electrically connected to the driving output end, and the drain is electrically connected At low power supply;
- the gate of the second sixteen P-type transistor is electrically connected to the driving output end, the source is electrically connected to the high potential of the power source, and the drain is electrically connected to the twenty-ninth N The source of the transistor;
- the gate of the twenty-seventh N-type transistor is electrically connected to the driving output end, and the source is electrically connected to the drain of the twenty-ninth N-type transistor, and the drain is electrically Connected to the low potential of the power supply;
- the gate of the twenty-eighth P-type transistor is electrically connected to the timing signal, the source is electrically connected to the power supply high potential, and the drain is electrically connected to the twenty-ninth N-type The source of the transistor;
- the gate of the twenty-ninth N-type transistor is electrically connected to the timing signal, the source is electrically connected to the drain of the twenty-six P-type transistor, and the drain is electrically connected The source of the twenty-seventh N-type transistor;
- the output buffer portion includes:
- the gate of the thirtieth P-type transistor is electrically connected to the source of the twenty-ninth N-type transistor, the source is electrically connected to the high potential of the power source, and the drain is electrically connected to the drain The source of the thirty-first N-type transistor;
- the gate of the 31st N-type transistor is electrically connected to the source of the ninth N-type transistor, and the source is electrically connected to the drain of the thirtieth P-type transistor The drain is electrically connected to the low potential of the power source;
- the gate of the thirty-second P-type transistor is electrically connected to the drain of the thirtieth P-type transistor, the source is electrically connected to the power supply high potential, and the drain is electrically connected The source of the thirty-third N-type transistor;
- the gate of the thirty-third N-type transistor is electrically connected to the drain of the thirtieth P-type transistor, and the source is electrically connected to the drain of the thirty-second P-type transistor The drain is electrically connected to the low potential of the power source;
- the gate of the thirty-fourth P-type transistor is electrically connected to the drain of the thirty-second P-type transistor, and the source is electrically connected to the high potential of the power source, and the drain is electrically Connected to the output;
- the gate of the thirty-fifth N-type transistor is electrically connected to the drain of the thirty-second P-type transistor, the source is electrically connected to the output end, and the drain is electrically connected The power supply is low.
- the GOA circuit further includes a second output control portion and a second output buffer portion;
- the second output control portion is electrically connected to the output control portion, the driving output terminal, the M+1th timing signal, the power supply high potential and the power supply low potential;
- the second output buffer portion is electrically connected to the second Output control part, output end of the N+1th GOA unit, power supply high potential and power supply low potential;
- the second output control portion includes:
- the gate of the thirty-six P-type transistor is electrically connected to the driving output end, the source is electrically connected to the power supply high potential, and the drain is electrically connected to the thirty-ninth N The source of the transistor;
- the gate of the thirty-seventh N-type transistor is electrically connected to the driving output end, and the source is electrically connected to the drain of the thirty-ninth N-type transistor, and the drain is electrically Connected to the low potential of the power supply;
- the gate of the thirty-eighth P-type transistor is electrically connected to the M+1th timing signal, the source is electrically connected to the power supply high potential, and the drain is electrically connected to the first The source of the thirty-nine N-type transistor;
- the gate of the thirty-ninth N-type transistor is electrically connected to the M+1th timing signal, and the source is electrically connected to the drain of the thirty-sixth P-type transistor.
- the drain is electrically connected to the source of the thirty-seventh N-type transistor;
- the second output buffering portion includes:
- the gate of the fortieth P-type transistor is electrically connected to the source of the thirty-ninth N-type transistor, the source is electrically connected to the high potential of the power source, and the drain is electrically connected to the drain The source of the forty-first N-type transistor;
- the gate of the forty-first N-type transistor is electrically connected to the source of the thirty-ninth N-type transistor, and the source is electrically connected to the drain of the fortieth P-type transistor The drain is electrically connected to the low potential of the power source;
- the gate of the forty-second P-type transistor is electrically connected to the drain of the fortieth P-type transistor, the source is electrically connected to the power supply high potential, and the drain is electrically connected The source of the forty-third N-type transistor;
- the gate of the forty-third N-type transistor is electrically connected to the drain of the fortieth P-type transistor, and the source is electrically connected to the drain of the forty-second P-type transistor The drain is electrically connected to the low potential of the power source;
- the gate of the forty-fourth P-type transistor is electrically connected to the drain of the forty-second P-type transistor, and the source is electrically connected to the high potential of the power source, and the drain is electrically Connected to the output of the N+1th GOA unit;
- the gate of the forty-fifth N-type transistor is electrically connected to the drain of the forty-second P-type transistor, and the source is electrically connected to the N+1th GOA unit At the output end, the drain is electrically connected to the low potential of the power supply.
- a source of the first P-type transistor, a source of the second N-type transistor, a gate of the fifth P-type transistor, and a gate of the seventh N-type transistor are both Electrically connected to the start signal end of the circuit.
- the gate of the sixth P-type transistor and the gate of the eighth N-type transistor are electrically connected to the start signal end of the circuit.
- the first P-type transistor and the second N-type transistor in the transfer portion constitute a transfer gate for forwardly transmitting the drive output signal of the N-1th stage GOA unit to the data storage portion.
- the fifth P-type transistor, the sixth P-type transistor, the seventh N-type transistor, and the eighth N-type transistor form a NAND gate logic unit in the transmission control portion;
- the ninth P-type transistor and the tenth N-type transistor form an inversion
- the eleventh P-type transistor and the twelfth N-type transistor constitute a transfer gate;
- the transfer control portion is configured to control the M-2th timing signal and transmit it to the data storage portion.
- the fifteenth P-type transistor, the sixteenth P-type transistor, the seventeenth N-type transistor, and the eighteenth N-type transistor in the data storage portion constitute a timing inverter; the thirteenth N-type transistor, the fourteenth P The type transistor constitutes an inverter; the data storage portion is configured to store and transmit signals transmitted by the driving output terminal of the N-1th stage GOA unit and the M-2th timing signal.
- the data clearing portion is used to timely clear the potential of the drive output of the circuit.
- a twenty-six P-type transistor, a twenty-seventh N-type transistor, a twenty-eighth P-type transistor, and a twenty-ninth N-type transistor in the output control portion constitute a NAND gate logic unit;
- the transistor and the twenty-fifth N-type transistor constitute an inverter;
- the output control portion is configured to control the scan signal outputted by the output terminal, and output a scan signal that conforms to the timing.
- the transistors form three inverters, respectively, which are used to adjust the timing-adjusted scan signal while enhancing the load carrying capability.
- a third hexadecimal P-type transistor, a thirty-seventh N-type transistor, a thirty-eighth P-type transistor, and a thirty-ninth N-type transistor in the second output control portion constitute a NAND gate logic unit, for The scan signal outputted from the output end of the N+1 stage GOA unit is controlled to output a timing-aligned scan signal;
- the fourth output buffer portion is a fortieth P-type transistor and a forty-first N-type transistor, and the forty-second
- the P-type transistor and the forty-third N-type transistor, the forty-fourth P-type transistor, and the forty-fifth N-type transistor respectively constitute three inverters for adjusting the timing-adjusted scan signal while enhancing the band Load capacity;
- the second output control portion and the second output buffer portion are outputted by the output end of the N+1th GOA unit according to the output signal of the driving output terminal and the M+1th timing signal, thereby realizing
- the timing signal includes four sets of timing signals: a first timing signal, a second timing signal, a third timing signal, and a fourth timing signal.
- the timing signal is a first timing signal
- the M-2th timing The signal is a third timing signal.
- the timing signal is a second timing signal
- the M-2th timing signal is a fourth timing signal
- the M+ The level 1 timing signal is the first timing signal.
- the present invention provides a low temperature polysilicon semiconductor thin film transistor GOA circuit for forward scan transmission, and the Nth stage GOA unit employs a plurality of N-type transistors and a plurality of P-type transistors, including a transmission portion and a transmission.
- the transmission portion has a transfer gate; the transfer control portion has a NOR gate logic unit, an inverter, and a transfer gate; the data storage portion has a timing inverter and an inverter; and the output control portion has a non-gate logic unit, an inverter; the output buffer portion has an inverter; a transmission gate is used to transmit signals to the upper and lower stages, and a signal is converted by a NOR gate logic unit and a NAND gate logic unit, and a timing inverter is used. And the inverter stores and transmits the signal, which solves the problem that the device circuit stability of the LTPS single TFT is poor, the power consumption is large, and the TFT leakage of the single type GOA circuit is optimized.
- the performance of the circuit is achieved by setting the second output control portion and the second output buffer portion to realize the common drive output terminal, so that the single-stage GOA unit controls the forward scan output of the two-stage circuit, thereby reducing the number of TFTs and achieving an ultra-narrow bezel or no The design of the border.
- FIG. 1 is a circuit diagram of a first embodiment of a low temperature polysilicon semiconductor thin film transistor GOA circuit of the present invention
- FIG. 2 is a circuit diagram showing a first-stage connection relationship of a first embodiment of a low-temperature polysilicon semiconductor thin film transistor GOA circuit of the present invention
- FIG. 3 is a circuit diagram showing the final connection relationship of the first embodiment of the low temperature polysilicon semiconductor thin film transistor GOA circuit of the present invention
- FIG. 4 is a circuit diagram of a second embodiment of a low temperature polysilicon semiconductor thin film transistor GOA circuit of the present invention.
- Figure 5 is a waveform diagram of key nodes of the low temperature polysilicon semiconductor thin film transistor GOA circuit of the present invention.
- FIG. 1 is a circuit diagram of a first embodiment of the present invention.
- the present invention provides a low temperature polysilicon thin film transistor GOA circuit for forward scan transmission, including a plurality of cascaded GOA units, wherein N is a positive integer, and the Nth stage GOA unit uses a plurality of N
- the transistor and the plurality of P-type transistors, the N-th stage GOA unit includes: a transmission portion 100, a transmission control portion 200, a data storage portion 300, a data clearing portion 400, an output control portion 500, and an output buffer portion 600;
- the transmitting portion 100 is electrically connected to the first low frequency signal UD, the second low frequency signal DU, and the driving output terminal ST(N-1) of the N-1th GOA unit of the previous stage of the Nth stage GOA unit and The data storage portion 300;
- the transmission control portion 200 is electrically connected to the driving output terminal ST(N+1) of the N+1th GOA unit of the subsequent stage of the Nth stage GOA unit, the Nth Drive output terminal ST(N-1), M-2 timing signal CK(M-2), power supply high potential H, power supply low potential L and data of the first stage N-1 GOA unit of the stage GOA unit Storage portion 300;
- the data storage portion 300 is electrically connected to the transmission portion 100, the transmission control portion 200, the data clearing portion 400, the power supply high potential H and the power supply low potential L;
- the data clearing portion 400 is electrically connected to the data storage The portion 300, the output control portion 500, the power supply high potential H and the reset signal terminal Reset; the output control portion 500 is electrically connected to the data clearing portion
- the first low frequency signal UD is equivalent to a DC high potential
- the second low frequency signal DU is equivalent to a DC low potential
- the transmitting portion 100 includes a first P-type transistor T1, the gate of the first P-type transistor T1 is electrically connected to the second low-frequency signal DU, and the source is electrically connected to the front of the N-th stage GOA unit.
- a second N-type transistor T2, the second N-type transistor T2 The gate is electrically connected to the first low frequency signal UD, and the source is electrically connected to the driving output terminal ST(N-1) of the N-1th GOA unit of the previous stage of the Nth stage GOA unit, and the drain Electrically connected to the first node P (N);
- the first P-type transistor T1 and the second N-type transistor T2 constitute a transfer gate for forwardly transmitting the drive output signal ST(N-1) of the N-1th stage GOA unit to the data storage portion 300.
- the transmission control portion 200 includes a fifth P-type transistor T5, and the gate of the fifth P-type transistor T5 is electrically connected to the driving of the N-1th GOA unit of the previous stage of the Nth stage GOA unit.
- the output terminal ST(N-1) has a source electrically connected to the power supply high potential H, a drain electrically connected to the source of the sixth P-type transistor T6, and a sixth P-type transistor T6, the sixth P-type
- the gate of the transistor T6 is electrically connected to the driving output terminal ST(N+1) of the N+1th GOA unit of the subsequent stage of the Nth stage GOA unit, and the source is electrically connected to the fifth P-type transistor T5.
- a drain a drain electrically connected to the source of the seventh N-type transistor T7; a seventh N-type transistor T7, the gate of the seventh N-type transistor T7 is electrically connected to the Nth-level GOA unit
- the driving output terminal ST(N-1) of the first-stage N-1th GOA unit is electrically connected to the drain of the sixth P-type transistor T6, and the drain is electrically connected to the power supply low potential L;
- the eighth N-type transistor T8, the gate of the eighth N-type transistor T8 is electrically connected to the driving output terminal ST(N+1) of the N+1th GOA unit of the subsequent stage of the Nth stage GOA unit
- the source is electrically connected to the sixth P-type crystal
- the drain of T6 is electrically connected to the power supply low potential L; a ninth P-type transistor T9, the gate of the ninth P-type transistor T9 is electrically connected to the drain of the sixth P-type transistor T6, the source
- the pole is electrically connected to the power supply high potential H, the
- the fifth P-type transistor T5, the sixth P-type transistor T6, the seventh N-type transistor T7, and the eighth N-type transistor T8 constitute a NAND gate logic unit; the ninth P-type transistor T9, the tenth N-type The transistor T10 constitutes an inverter; the eleventh P-type transistor T11 and the twelfth N-type transistor T12 constitute a transmission gate; and the transmission control portion 200 is for controlling the M-2th timing signal CK(M-2) And transfer it to the material storage section 300.
- the data storage portion 300 includes a thirteenth N-type transistor T13.
- the gate of the thirteenth N-type transistor T13 is electrically connected to the source of the eleventh P-type transistor T11, and the source is electrically connected to the first
- the drain of the fourteen P-type transistor T14 is electrically connected to the power supply low potential L; a fourteenth P-type transistor T14, and the gate of the fourteenth P-type transistor T14 is electrically connected to the eleventh P
- the source of the transistor T11 is electrically connected to the power supply high potential H, and the drain is electrically connected to the source of the thirteenth N-type transistor T13; a fifteenth P-type transistor T15, the fifteenth P
- the gate of the transistor T15 is electrically connected to the source of the thirteenth N-type transistor T13, the source is electrically connected to the power supply high potential H, and the drain is electrically connected to the source of the sixteenth P-type transistor T16;
- the fifteenth P-type transistor T15, the sixteenth P-type transistor T16, the seventeenth N-type transistor T17, and the eighteenth N-type transistor T18 constitute a timing inverter; the thirteenth N-type transistor T13, The fourteenth P-type transistor T14 constitutes an inverter; the data storage portion 300 is used for the driving output terminal ST(N-1) and the M-2th timing signal CK of the N-1th stage GOA unit ( M-2) The incoming signal is stored and transmitted.
- the data clearing portion 400 includes a twenty-third P-type transistor T23.
- the gate of the twenty-third P-type transistor T23 is electrically connected to the reset signal end Reset, and the source is electrically connected to the power.
- the source high potential H, the drain is electrically connected to the drain of the sixteenth P-type transistor T16; the data clearing portion 400 is used for timely clearing the potential of the driving output terminal ST(N) of the circuit, mainly at each At the beginning of the frame, the reset signal terminal Reset receives a pulse reset signal, and discharges the drive output terminal ST(N), thereby clearing the potential of the drive output terminal ST(N).
- the output control portion 500 includes a second fourteen P-type transistor T24.
- the gate of the twenty-fourth P-type transistor T24 is electrically connected to the drain of the sixteenth P-type transistor T16, and the source is electrically connected.
- the power supply is at a high potential H, the drain is electrically connected to the driving output terminal ST(N); a twenty-fifth N-type transistor T25, and the gate of the twenty-fifth N-type transistor T25 is electrically connected to the sixteenth
- the drain of the P-type transistor T16 is electrically connected to the driving output terminal ST(N), and the drain is electrically connected to the power supply low potential L; a second sixteen P-type transistor T26, the second sixteen P
- the gate of the transistor T26 is electrically connected to the driving output terminal ST(N), the source is electrically connected to the power supply high potential H, and the drain is electrically connected to the source of the ninth N-type transistor T29; a seventeen N-type transistor T27, the gate of the twenty-seven
- the drain is electrically connected to the power supply low potential L; a twenty-eighth P-type transistor T28, the gate of the twenty-eighth P-type transistor T28 is electrically connected to the timing signal CK(M)
- the source is electrically connected to the power supply high potential H, and the drain is electrically connected to the source of the ninth N-type transistor T29; a ninth N-type transistor T29, the ninth N-type transistor T29
- the gate is electrically connected to the timing signal CK (M)
- the source is electrically connected to the drain of the twenty-six P-type transistor T26, and the drain is electrically connected to the source of the twenty-seventh N-type transistor T27;
- the second sixteen P-type transistor T26, the twenty-seventh N-type transistor T27, the twenty-eighth P-type transistor T28, and the twenty-ninth N-type transistor T29 form a NAND gate logic unit;
- the four P-type transistor T24 and the twenty-fifth N-type transistor T25 constitute an inverter; the output control portion 500 is configured to control the scan signal outputted from the output terminal G(N) to output a scan signal conforming to the timing.
- the output buffer portion 600 includes a thirtieth P-type transistor T30.
- the gate of the thirtieth P-type transistor T30 is electrically connected to the source of the twenty-ninth N-type transistor T29, and the source is electrically connected to the source.
- the power supply high potential H the drain is electrically connected to the source of the 31st N-type transistor T31; a 31st N-type transistor T31, the gate of the 31st N-type transistor T31 is electrically connected to a source of the twenty-ninth N-type transistor T29, the source is electrically connected to the drain of the thirtieth P-type transistor T30, the drain is electrically connected to the power supply low potential L; a thirty-second P-type transistor T32, The gate of the thirty-second P-type transistor T32 is electrically connected to the drain of the thirtieth P-type transistor T30, the source is electrically connected to the power supply high potential H, and the drain is electrically connected to the thirty-third N a source of the transistor T33; a thirty-third N-type transistor T33, the thirty-third N-type transistor T33 The gate is electrically connected to the drain of the thirtieth P-type transistor T30, the source is electrically connected to the drain of the thirty-second P-type transistor T
- the five N-type transistors T35 respectively constitute three inverters; they are used to adjust the timing-adjusted scan signals while enhancing the load carrying capability.
- the source of the first P-type transistor T1, the source of the second N-type transistor T2, and the fifth P The gate of the transistor T5 and the gate of the seventh N-type transistor T7 are electrically connected to the start signal terminal STV of the circuit; in the last-stage connection relationship, the gate of the sixth P-type transistor T6, the eighth N The gate of the transistor T8 is electrically connected to the enable signal terminal STV of the circuit.
- FIG. 5 is a waveform diagram of key nodes of the low temperature polysilicon semiconductor thin film transistor GOA circuit of the present invention.
- the waveforms of the key nodes meet the design requirements, wherein the first low frequency signal UD and the second low frequency signal DU are The forward scan is equivalent to a high-low potential of DC;
- the timing signal CK(M) includes four sets of timing signals, which are a first timing signal CK(1), a second timing signal CK(2), and a third timing signal, respectively.
- the M-2th timing signal CK(M-2) is The third timing signal CK(3), when the timing signal CK(M) is the second timing signal CK(2), the M-2th timing signal CK(M-2) is the fourth timing signal CK (4)
- the timing signal CK(M) is the fourth timing signal CK(4)
- the M+1th timing signal CK(M+1) is the first timing signal CK(1).
- the pulse signals of the timing signal CK(M) sequentially arrive in the order of CK(1)-CK(4), and the third timing signal CK(3) corresponds to the output signal of the first stage output terminal G(1), and the fourth The timing signal CK(4) corresponds to the output signal of the second stage output terminal G(2), the first timing signal CK(1) corresponds to the output signal of the third stage output terminal G(3), and the second timing signal CK(2) Corresponding to the output signal of the fourth stage output terminal G(4), and so on.
- FIG. 4 is a circuit diagram of a second embodiment of a low temperature polysilicon semiconductor thin film transistor GOA circuit of the present invention.
- the second embodiment is different from the first embodiment in that it further includes a second output control.
- the second output control portion 501 is electrically connected to the output control portion 500, the drive output terminal ST(N), and the M+1th stage.
- the second output buffering portion 601 is electrically connected to the second output control portion 501, the output end of the (N+1)th GOA unit G(N+1), power supply high potential H and power supply low potential L.
- the second output control portion 501 includes a thirty-six P-type transistor T36.
- the gate of the third sixteen P-type transistor T36 is electrically connected to the driving output terminal ST(N), and the source is electrically connected to the source.
- the power supply high potential H the drain is electrically connected to the source of the thirty-ninth N-type transistor T39; a thirty-seventh N-type transistor T37, the gate of the thirty-seventh N-type transistor T37 is electrically connected to Driving output ST (N), the source is electrically connected to the drain of the thirty-ninth N-type transistor T39, the drain is electrically connected to the power supply low potential L; a thirty-eighth P-type transistor T38, the The gate of the thirty-eight P-type transistor T38 is electrically connected to the M+1th timing signal CK(M+1), the source is electrically connected to the power supply high potential H, and the drain is electrically connected to the thirty-ninth N.
- the second output buffering portion 601 includes a fortieth P-type transistor T40, and the gate of the fortieth P-type transistor T40 is electrically connected to the source of the thirty-ninth N-type transistor T39, and the source is electrically Connected to the power supply high potential H, the drain is electrically connected to the source of the forty-first N-type transistor T41; a forty-first N-type transistor T41, the gate electrical property of the forty-first N-type transistor T41 Connected to the source of the thirty-ninth N-type transistor T39, the source is electrically connected to the drain of the fortieth P-type transistor T40, and the drain is electrically connected to the power supply low potential L; a forty-second P-type transistor T42, the gate of the forty-second P-type transistor T42 is electrically connected to the drain of the fortieth P-type transistor T40, the source is electrically connected to the power supply high potential H, and the drain is electrically connected to the fort
- the third sixteen P-type transistor T36, the thirty-seventh N-type transistor T37, the thirty-eighth P-type transistor T38, and the thirty-ninth N-type transistor T39 in the second output control portion 501 constitute a NAND gate logic unit For scanning the output G(N+1) output of the N+1th GOA unit The signal is controlled to output a timing-aligned scan signal;
- the fourth output buffer portion 601 is a fortieth P-type transistor T40 and a forty-first N-type transistor T41, a forty-second P-type transistor T42, and a forty-third The N-type transistor T43, the forty-fourth P-type transistor T44, and the forty-fifth N-type transistor T45 respectively constitute three inverters for adjusting the timing-adjusted scan signal while enhancing the load carrying capability;
- the second output control portion 501 and the second output buffer portion 601 are output from the N+1th stage GOA unit according to the output signal of the driving output terminal ST(N
- the effect of the single-stage GOA unit controlling the forward scan output of the two-stage circuit can be achieved by adding the second output control portion 501 and the second output buffer portion 601, and the second output control portion 501 shares a drive output with the output control portion 500.
- the terminal ST(N) can reduce the number of TFTs by sharing the output terminal ST(N), and realizes an ultra-narrow bezel or a borderless design.
- the low temperature polysilicon semiconductor thin film transistor GOA circuit of the present invention is used for forward scan transmission, and the Nth stage GOA unit uses a plurality of N type transistors and a plurality of P type transistors, including a transmission part and a transmission control part. , data storage part, data clearing part, output control part, and output buffer part.
- the transmission portion has a transfer gate; the transfer control portion has a NOR gate logic unit, an inverter, and a transfer gate; the data storage portion has a timing inverter and an inverter; and the output control portion has a non-gate logic unit, an inverter; the output buffer portion has an inverter; a transmission gate is used to transmit signals to the upper and lower stages, and a signal is converted by a NOR gate logic unit and a NAND gate logic unit, and a timing inverter is used.
- the inverter stores and transmits the signal, which solves the problem that the device circuit stability of the LTPS single TFT is poor, the power consumption is large, and the TFT leakage of the single type GOA circuit is optimized, and the performance of the circuit is optimized;
- the second output control portion and the second output buffer portion implement a common drive output end, so that the single-stage GOA unit controls the forward scan output of the two-stage circuit, which can reduce the number of TFTs and realize an ultra-narrow bezel or a borderless design.
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Abstract
Description
Claims (13)
- 一种低温多晶硅薄膜晶体管GOA电路,用于正向扫描传输,包括级联的多个GOA单元,设N为正整数,第N级GOA单元采用多个N型晶体管与多个P型晶体管,所述第N级GOA单元包括:传输部分、传输控制部分、资料存储部分、数据清除部分、输出控制部分及输出缓冲部分;所述传输部分电性连接于第一低频信号、第二低频信号、所述第N级GOA单元的前一级第N-1级GOA单元的驱动输出端与所述资料存储部分;所述传输控制部分电性连接于所述第N级GOA单元的后一级第N+1级GOA单元的驱动输出端、所述第N级GOA单元的前一级第N-1级GOA单元的驱动输出端、第M-2级时序信号、电源高电位、电源低电位与资料存储部分;所述资料存储部分电性连接于所述传输部分、传输控制部分、数据清除部分、电源高电位与电源低电位;所述数据清除部分电性连接于所述资料存储部分、输出控制部分、电源高电位与复位信号端;所述输出控制部分电性连接于所述数据清除部分、输出缓冲部分、驱动输出端、时序信号、电源高电位与电源低电位;所述输出缓冲部分电性连于所述输出控制部分、输出端、电源高电位与电源低电位;所述第一低频信号相当于直流高电位,所述第二低频信号相当于直流低电位;所述传输部分包括一第一P型晶体管,所述第一P型晶体管的栅极电性连接于第二低频信号,源极电性连接于所述第N级GOA单元的前一级第N-1级GOA单元的驱动输出端,漏极电性连接于第一节点;一第二N型晶体管,所述第二N型晶体管的栅极电性连接于第一低频信号,源极电性连接于所述第N级GOA单元的前一级第N-1级GOA单元的驱动输出端,漏极电性连接于第一节点;所述传输控制部分包括:一第五P型晶体管,所述第五P型晶体管的栅极电性连接于所述第N级GOA单元的前一级第N-1级GOA单元的驱动输出端,源极电性连接于电源高电位,漏极电性连接于第六P型晶体管的源极;一第六P型晶体管,所述第六P型晶体管的栅极电性连接于所述第N级GOA单元的后一级第N+1级GOA单元的驱动输出端,源极电性连接于第五P型晶体管的漏极,漏极电性连接于第七N型晶体管的源极;一第七N型晶体管,所述第七N型晶体管的栅极电性连接于所述第N 级GOA单元的前一级第N-1级GOA单元的驱动输出端,源极电性连接于第六P型晶体管的漏极,漏极电性连接于电源低电位;一第八N型晶体管,所述第八N型晶体管的栅极电性连接于所述第N级GOA单元的后一级第N+1级GOA单元的驱动输出端,源极电性连接于第六P型晶体管的漏极,漏极电性连接于电源低电位;一第九P型晶体管,所述第九P型晶体管的栅极电性连接于第六P型晶体管的漏极,源极电性连接于电源高电位,漏极电性连接于第十N型晶体管的源极;一第十N型晶体管,所述第十N型晶体管的栅极电性连接于第六P型晶体管的漏极,源极电性连接于第九P型晶体管的漏极,漏极电性连接于电源低电位;一第十一P型晶体管,所述第十一P型晶体管的栅极电性连接于第六P型晶体管的漏极,源极电性连接于第十二N型晶体管的源极,漏极电性连接于第M-2级时序信号;一第十二N型晶体管,所述第十二N型晶体管的栅极电性连接于第九P型晶体管的漏极,源极电性连接于第十一P型晶体管的源极,漏极电性连接于第M-2级时序信号;所述资料存储部分包括:一第十三N型晶体管,所述第十三N型晶体管的栅极电性连接于第十一P型晶体管的源极,源极电性连接于第十四P型晶体管的漏极,漏极电性连接于电源低电位;一第十四P型晶体管,所述第十四P型晶体管的栅极电性连接于第十一P型晶体管的源极,源极电性连接于电源高电位,漏极电性连接于第十三N型晶体管的源极;一第十五P型晶体管,所述第十五P型晶体管的栅极电性连接于第十三N型晶体管的源极,源极电性连接于电源高电位,漏极电性连接于第十六P型晶体管的源极;一第十六P型晶体管,所述第十六P型晶体管的栅极电性连接于第一节点,源极电性连接于第十五P型晶体管的漏极,漏极电性连接于第十七N型晶体管的源极;一第十七N型晶体管,所述第十七N型晶体管的栅极电性连接于第一节点,源极电性连接于第十六P型晶体管的漏极,漏极电性连接于第十八N型晶体管的源极;一第十八N型晶体管,所述第十八N型晶体管的栅极电性连接于第十 一P型晶体管的源极,源极电性连接于第十七N型晶体管的漏极,漏极电性连接于电源低电位;所述数据清除部分包括:一第二十三P型晶体管,所述第二十三P型晶体管的栅极电性连接于复位信号端,源极电性连接于电源高电位,漏极电性连接于第十六P型晶体管的漏极;所述输出控制部分包括:一第二十四P型晶体管,所述第二十四P型晶体管的栅极电性连接于第十六P型晶体管的漏极,源极电性连接于电源高电位,漏极电性连接于驱动输出端;一第二十五N型晶体管,所述第二十五N型晶体管的栅极电性连接于第十六P型晶体管的漏极,源极电性连接于驱动输出端,漏极电性连接于电源低电位;一第二十六P型晶体管,所述第二十六P型晶体管的栅极电性连接于驱动输出端,源极电性连接于电源高电位,漏极电性连接于第二十九N型晶体管的源极;一第二十七N型晶体管,所述第二十七N型晶体管的栅极电性连接于驱动输出端,源极电性连接于第二十九N型晶体管的漏极,漏极电性连接于电源低电位;一第二十八P型晶体管,所述第二十八P型晶体管的栅极电性连接于时序信号,源极电性连接于电源高电位,漏极电性连接于第二十九N型晶体管的源极;一第二十九N型晶体管,所述第二十九N型晶体管的栅极电性连接于时序信号,源极电性连接于第二十六P型晶体管的漏极,漏极电性连接于第二十七N型晶体管的源极;所述输出缓冲部分包括:一第三十P型晶体管,所述第三十P型晶体管的栅极电性连接于第二十九N型晶体管的源极,源极电性连接于电源高电位,漏极电性连接于第三十一N型晶体管的源极;一第三十一N型晶体管,所述第三十一N型晶体管的栅极电性连接于第二十九N型晶体管的源极,源极电性连接于第三十P型晶体管的漏极,漏极电性连接于电源低电位;一第三十二P型晶体管,所述第三十二P型晶体管的栅极电性连接于第三十P型晶体管的漏极,源极电性连接于电源高电位,漏极电性连接于 第三十三N型晶体管的源极;一第三十三N型晶体管,所述第三十三N型晶体管的栅极电性连接于第三十P型晶体管的漏极,源极电性连接于第三十二P型晶体管的漏极,漏极电性连接于电源低电位;一第三十四P型晶体管,所述第三十四P型晶体管的栅极电性连接于第三十二P型晶体管的漏极,源极电性连接于电源高电位,漏极电性连接于输出端;一第三十五N型晶体管,所述第三十五N型晶体管的栅极电性连接于第三十二P型晶体管的漏极,源极电性连接于输出端,漏极电性连接于电源低电位。
- 如权利要求1所述的低温多晶硅薄膜晶体管GOA电路,其中,所述GOA电路还包括第二输出控制部分、第二输出缓冲部分;所述第二输出控制部分电性连接于输出控制部分、驱动输出端、第M+1级时序信号、电源高电位与电源低电位;所述第二输出缓冲部分电性连接于所述第二输出控制部分、第N+1级GOA单元的输出端、电源高电位与电源低电位;所述第二输出控制部分包括:一第三十六P型晶体管,所述第三十六P型晶体管的栅极电性连接于驱动输出端,源极电性连接于电源高电位,漏极电性连接于第三十九N型晶体管的源极;一第三十七N型晶体管,所述第三十七N型晶体管的栅极电性连接于驱动输出端,源极电性连接于第三十九N型晶体管的漏极,漏极电性连接于电源低电位;一第三十八P型晶体管,所述第三十八P型晶体管的栅极电性连接于第M+1级时序信号,源极电性连接于电源高电位,漏极电性连接于第三十九N型晶体管的源极;一第三十九N型晶体管,所述第三十九N型晶体管的栅极电性连接于第M+1级时序信号,源极电性连接于第三十六P型晶体管的漏极,漏极电性连接于第三十七N型晶体管的源极;所述第二输出缓冲部分包括:一第四十P型晶体管,所述第四十P型晶体管的栅极电性连接于第三十九N型晶体管的源极,源极电性连接于电源高电位,漏极电性连接于第四十一N型晶体管的源极;一第四十一N型晶体管,所述第四十一N型晶体管的栅极电性连接于 第三十九N型晶体管的源极,源极电性连接于第四十P型晶体管的漏极,漏极电性连接于电源低电位;一第四十二P型晶体管,所述第四十二P型晶体管的栅极电性连接于第四十P型晶体管的漏极,源极电性连接于电源高电位,漏极电性连接于第四十三N型晶体管的源极;一第四十三N型晶体管,所述第四十三N型晶体管的栅极电性连接于第四十P型晶体管的漏极,源极电性连接于第四十二P型晶体管的漏极,漏极电性连接于电源低电位;一第四十四P型晶体管,所述第四十四P型晶体管的栅极电性连接于第四十二P型晶体管的漏极,源极电性连接于电源高电位,漏极电性连接于第N+1级GOA单元的输出端;一第四十五N型晶体管,所述第四十五N型晶体管的栅极电性连接于第四十二P型晶体管的漏极,源极电性连接于第N+1级GOA单元的输出端,漏极电性连接于电源低电位。
- 如权利要求1所述的低温多晶硅薄膜晶体管GOA电路,其中,所述GOA电路的第一级连接关系中,所述第一P型晶体管的源极、第二N型晶体管的源极、第五P型晶体管的栅极、第七N型晶体管的栅极均电性连接于电路的启动信号端。
- 如权利要求1所述的低温多晶硅薄膜晶体管GOA电路,其中,所述GOA电路的最后一级连接关系中,所述第六P型晶体管的栅极、第八N型晶体管的栅极均电性连接于电路的启动信号端。
- 如权利要求1所述的低温多晶硅薄膜晶体管GOA电路,其中,所述传输部分中第一P型晶体管和第二N型晶体管构成一传输闸,用于将第N-1级GOA单元的驱动输出信号正向传输至资料存储部分。
- 如权利要求1所述的低温多晶硅薄膜晶体管GOA电路,其中,所述传输控制部分中第五P型晶体管、第六P型晶体管、第七N型晶体管、第八N型晶体管构成或非门逻辑单元;第九P型晶体管、第十N型晶体管构成反相器;第十一P型晶体管和第十二N型晶体管构成传输闸;所述传输控制部分用于控制第M-2级时序信号,并将其传输到资料存储部分。
- 如权利要求1所述的低温多晶硅薄膜晶体管GOA电路,其中,所述资料存储部分中第十五P型晶体管、第十六P型晶体管、第十七N型晶体管、第十八N型晶体管构成时序反向器;第十三N型晶体管、第十四P型晶体管构成反向器;所述资料存储部分用于对由第N-1级GOA单元的驱动输出端和第M-2级时序信号传入的信号进行存储和传输。
- 如权利要求1所述的低温多晶硅薄膜晶体管GOA电路,其中,所述数据清除部分用于对电路的驱动输出端电位的适时清除。
- 如权利要求1所述的低温多晶硅薄膜晶体管GOA电路,其中,所述输出控制部分中第二十六P型晶体管、第二十七N型晶体管、第二十八P型晶体管、第二十九N型晶体管构成与非门逻辑单元;第二十四P型晶体管、第二十五N型晶体管构成反向器;所述输出控制部分用于对输出端输出的扫描信号进行控制,输出符合时序的扫描信号。
- 如权利要求1所述的低温多晶硅薄膜晶体管GOA电路,其中,所述输出缓冲部分中第三十P型晶体管和第三十一N型晶体管、第三十二P型晶体管和第三十三N型晶体管、第三十四P型晶体管和第三十五N型晶体管分别构成三个反向器,用于对经过时序调整的扫描信号进行调整,同时增强带负载能力。
- 如权利要求2所述的低温多晶硅薄膜晶体管GOA电路,其中,所述第二输出控制部分中第三十六P型晶体管,第三十七N型晶体管,第三十八P型晶体管、第三十九N型晶体管构成与非门逻辑单元,用于对第N+1级GOA单元的输出端输出的扫描信号进行控制,输出符合时序的扫描信号;所述第二输出缓冲部分中第四十P型晶体管和第四十一N型晶体管、第四十二P型晶体管和第四十三N型晶体管、第四十四P型晶体管和第四十五N型晶体管分别构成三个反向器,用于对经过时序调整的扫描信号进行调整,同时增强带负载能力;所述第二输出控制部分和第二输出缓冲部分依据驱动输出端的输出信号与第M+1级时序信号,由第N+1级GOA单元的输出端输出后一级扫描信号,实现单级GOA单元控制两级电路正向扫描输出。
- 如权利要求2所述的低温多晶硅薄膜晶体管GOA电路,其中,所述时序信号包括四组时序信号:第一时序信号、第二时序信号、第三时序信号、第四时序信号,当所述时序信号为第一时序信号时,所述第M-2级时序信号为第三时序信号,当所述时序信号为第二时序信号时,所述第M-2级时序信号为第四时序信号,当所述时序信号为第四时序信号,所述第M+1级时序信号为第一时序信号。
- 一种低温多晶硅薄膜晶体管GOA电路,用于正向扫描传输,包括级联的多个GOA单元,设N为正整数,第N级GOA单元采用多个N型晶体管与多个P型晶体管,所述第N级GOA单元包括:传输部分、传输控制部分、资料存储部分、数据清除部分、输出控制部分及输出缓冲部分;所述传输部分电性连接于第一低频信号、第二低频信号、所述第N级 GOA单元的前一级第N-1级GOA单元的驱动输出端与所述资料存储部分;所述传输控制部分电性连接于所述第N级GOA单元的后一级第N+1级GOA单元的驱动输出端、所述第N级GOA单元的前一级第N-1级GOA单元的驱动输出端、第M-2级时序信号、电源高电位、电源低电位与资料存储部分;所述资料存储部分电性连接于所述传输部分、传输控制部分、数据清除部分、电源高电位与电源低电位;所述数据清除部分电性连接于所述资料存储部分、输出控制部分、电源高电位与复位信号端;所述输出控制部分电性连接于所述数据清除部分、输出缓冲部分、驱动输出端、时序信号、电源高电位与电源低电位;所述输出缓冲部分电性连于所述输出控制部分、输出端、电源高电位与电源低电位;所述第一低频信号相当于直流高电位,所述第二低频信号相当于直流低电位;所述传输部分包括一第一P型晶体管,所述第一P型晶体管的栅极电性连接于第二低频信号,源极电性连接于所述第N级GOA单元的前一级第N-1级GOA单元的驱动输出端,漏极电性连接于第一节点;一第二N型晶体管,所述第二N型晶体管的栅极电性连接于第一低频信号,源极电性连接于所述第N级GOA单元的前一级第N-1级GOA单元的驱动输出端,漏极电性连接于第一节点;所述传输控制部分包括:一第五P型晶体管,所述第五P型晶体管的栅极电性连接于所述第N级GOA单元的前一级第N-1级GOA单元的驱动输出端,源极电性连接于电源高电位,漏极电性连接于第六P型晶体管的源极;一第六P型晶体管,所述第六P型晶体管的栅极电性连接于所述第N级GOA单元的后一级第N+1级GOA单元的驱动输出端,源极电性连接于第五P型晶体管的漏极,漏极电性连接于第七N型晶体管的源极;一第七N型晶体管,所述第七N型晶体管的栅极电性连接于所述第N级GOA单元的前一级第N-1级GOA单元的驱动输出端,源极电性连接于第六P型晶体管的漏极,漏极电性连接于电源低电位;一第八N型晶体管,所述第八N型晶体管的栅极电性连接于所述第N级GOA单元的后一级第N+1级GOA单元的驱动输出端,源极电性连接于第六P型晶体管的漏极,漏极电性连接于电源低电位;一第九P型晶体管,所述第九P型晶体管的栅极电性连接于第六P型晶体管的漏极,源极电性连接于电源高电位,漏极电性连接于第十N型晶体管的源极;一第十N型晶体管,所述第十N型晶体管的栅极电性连接于第六P型晶体管的漏极,源极电性连接于第九P型晶体管的漏极,漏极电性连接于电源低电位;一第十一P型晶体管,所述第十一P型晶体管的栅极电性连接于第六P型晶体管的漏极,源极电性连接于第十二N型晶体管的源极,漏极电性连接于第M-2级时序信号;一第十二N型晶体管,所述第十二N型晶体管的栅极电性连接于第九P型晶体管的漏极,源极电性连接于第十一P型晶体管的源极,漏极电性连接于第M-2级时序信号;所述资料存储部分包括:一第十三N型晶体管,所述第十三N型晶体管的栅极电性连接于第十一P型晶体管的源极,源极电性连接于第十四P型晶体管的漏极,漏极电性连接于电源低电位;一第十四P型晶体管,所述第十四P型晶体管的栅极电性连接于第十一P型晶体管的源极,源极电性连接于电源高电位,漏极电性连接于第十三N型晶体管的源极;一第十五P型晶体管,所述第十五P型晶体管的栅极电性连接于第十三N型晶体管的源极,源极电性连接于电源高电位,漏极电性连接于第十六P型晶体管的源极;一第十六P型晶体管,所述第十六P型晶体管的栅极电性连接于第一节点,源极电性连接于第十五P型晶体管的漏极,漏极电性连接于第十七N型晶体管的源极;一第十七N型晶体管,所述第十七N型晶体管的栅极电性连接于第一节点,源极电性连接于第十六P型晶体管的漏极,漏极电性连接于第十八N型晶体管的源极;一第十八N型晶体管,所述第十八N型晶体管的栅极电性连接于第十一P型晶体管的源极,源极电性连接于第十七N型晶体管的漏极,漏极电性连接于电源低电位;所述数据清除部分包括:一第二十三P型晶体管,所述第二十三P型晶体管的栅极电性连接于复位信号端,源极电性连接于电源高电位,漏极电性连接于第十六P型晶体管的漏极;所述输出控制部分包括:一第二十四P型晶体管,所述第二十四P型晶体管的栅极电性连接于 第十六P型晶体管的漏极,源极电性连接于电源高电位,漏极电性连接于驱动输出端;一第二十五N型晶体管,所述第二十五N型晶体管的栅极电性连接于第十六P型晶体管的漏极,源极电性连接于驱动输出端,漏极电性连接于电源低电位;一第二十六P型晶体管,所述第二十六P型晶体管的栅极电性连接于驱动输出端,源极电性连接于电源高电位,漏极电性连接于第二十九N型晶体管的源极;一第二十七N型晶体管,所述第二十七N型晶体管的栅极电性连接于驱动输出端,源极电性连接于第二十九N型晶体管的漏极,漏极电性连接于电源低电位;一第二十八P型晶体管,所述第二十八P型晶体管的栅极电性连接于时序信号,源极电性连接于电源高电位,漏极电性连接于第二十九N型晶体管的源极;一第二十九N型晶体管,所述第二十九N型晶体管的栅极电性连接于时序信号,源极电性连接于第二十六P型晶体管的漏极,漏极电性连接于第二十七N型晶体管的源极;所述输出缓冲部分包括:一第三十P型晶体管,所述第三十P型晶体管的栅极电性连接于第二十九N型晶体管的源极,源极电性连接于电源高电位,漏极电性连接于第三十一N型晶体管的源极;一第三十一N型晶体管,所述第三十一N型晶体管的栅极电性连接于第二十九N型晶体管的源极,源极电性连接于第三十P型晶体管的漏极,漏极电性连接于电源低电位;一第三十二P型晶体管,所述第三十二P型晶体管的栅极电性连接于第三十P型晶体管的漏极,源极电性连接于电源高电位,漏极电性连接于第三十三N型晶体管的源极;一第三十三N型晶体管,所述第三十三N型晶体管的栅极电性连接于第三十P型晶体管的漏极,源极电性连接于第三十二P型晶体管的漏极,漏极电性连接于电源低电位;一第三十四P型晶体管,所述第三十四P型晶体管的栅极电性连接于第三十二P型晶体管的漏极,源极电性连接于电源高电位,漏极电性连接于输出端;一第三十五N型晶体管,所述第三十五N型晶体管的栅极电性连接于 第三十二P型晶体管的漏极,源极电性连接于输出端,漏极电性连接于电源低电位;其中,所述传输部分中第一P型晶体管和第二N型晶体管构成一传输闸,用于将第N-1级GOA单元的驱动输出信号正向传输至资料存储部分;其中,所述传输控制部分中第五P型晶体管、第六P型晶体管、第七N型晶体管、第八N型晶体管构成或非门逻辑单元;第九P型晶体管、第十N型晶体管构成反相器;第十一P型晶体管和第十二N型晶体管构成传输闸;所述传输控制部分用于控制第M-2级时序信号,并将其传输到资料存储部分;其中,所述资料存储部分中第十五P型晶体管、第十六P型晶体管、第十七N型晶体管、第十八N型晶体管构成时序反向器;第十三N型晶体管、第十四P型晶体管构成反向器;所述资料存储部分用于对由第N-1级GOA单元的驱动输出端和第M-2级时序信号传入的信号进行存储和传输;其中,所述数据清除部分用于对电路的驱动输出端电位的适时清除;其中,所述输出控制部分中第二十六P型晶体管、第二十七N型晶体管、第二十八P型晶体管、第二十九N型晶体管构成与非门逻辑单元;第二十四P型晶体管、第二十五N型晶体管构成反向器;所述输出控制部分用于对输出端输出的扫描信号进行控制,输出符合时序的扫描信号;其中,所述输出缓冲部分中第三十P型晶体管和第三十一N型晶体管、第三十二P型晶体管和第三十三N型晶体管、第三十四P型晶体管和第三十五N型晶体管分别构成三个反向器,用于对经过时序调整的扫描信号进行调整,同时增强带负载能力。
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