WO2016070505A1 - Amoled背板的制作方法 - Google Patents

Amoled背板的制作方法 Download PDF

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Publication number
WO2016070505A1
WO2016070505A1 PCT/CN2015/072350 CN2015072350W WO2016070505A1 WO 2016070505 A1 WO2016070505 A1 WO 2016070505A1 CN 2015072350 W CN2015072350 W CN 2015072350W WO 2016070505 A1 WO2016070505 A1 WO 2016070505A1
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layer
polysilicon
gate
patterned
segment
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PCT/CN2015/072350
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English (en)
French (fr)
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徐源竣
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深圳市华星光电技术有限公司
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Priority to GB1703514.8A priority Critical patent/GB2545360B/en
Priority to JP2017522825A priority patent/JP6460582B2/ja
Priority to US14/424,107 priority patent/US9553169B2/en
Priority to KR1020177007166A priority patent/KR101944644B1/ko
Publication of WO2016070505A1 publication Critical patent/WO2016070505A1/zh

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    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
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    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating an AMOLED backplane.
  • OLED organic light emitting diodes
  • OLEDs can be classified into passive OLEDs (PMOLEDs) and active OLEDs (AMOLEDs) according to the type of driving.
  • the AMOLED is usually composed of a low temperature poly-Silicon (LTPS) driven backplane and an electroluminescent layer to form a self-illuminating component.
  • LTPS low temperature poly-Silicon
  • electroluminescent layer to form a self-illuminating component.
  • Low-temperature polysilicon has high electron mobility.
  • low-temperature polysilicon material has the advantages of high resolution, fast reaction speed, high brightness, high aperture ratio, and low energy consumption.
  • FIG. 1 The structure of an AMOLED backplane that is common in the prior art is shown in FIG.
  • the manufacturing process of the AMOLED backplane is generally as follows:
  • Step 1 depositing a buffer layer 200 on the substrate 100;
  • Step 2 depositing an amorphous silicon (a-Si) layer on the buffer layer 200, and crystallizing the amorphous silicon layer into a polysilicon (Poly-Si) layer by laser treatment; then passing the yellow light and etching process
  • the polysilicon layer is patterned to form a first polysilicon segment 301, a second polysilicon segment 303, and a third polysilicon segment 305;
  • Step 3 depositing a gate insulating layer 400
  • Step 4 forming a first layer of photoresist pattern on the gate insulating layer 400 by a yellow light process
  • Step 5 P-type heavily doped the patterned polysilicon layer with the first photoresist pattern as a shielding layer, and form a P-type weight on both sides of the second polysilicon segment 303 and the third polysilicon segment 305.
  • Step 6 first removing the first layer of photoresist pattern, and then forming a second layer of photoresist pattern on the gate insulating layer by a yellow light process;
  • Step 7 using a second layer of photoresist pattern as a shielding layer, N-type heavily doping the patterned polysilicon layer, forming an N-type heavily doped region N+ on both sides of the first polysilicon segment 301;
  • Step 8 removing the second layer of photoresist pattern, depositing and patterning the first metal layer on the gate insulating layer 400, forming a first gate 601, a second gate 605, and an electrode plate 603;
  • Step 9 Perform ion-alignment on the patterned polysilicon layer with the patterned first metal layer as a shielding layer, and form a lightly doped drain region on both sides of the first polysilicon segment 301 (Light Doping Drain) N-.
  • Step 10 sequentially forming an interlayer insulating layer 700, first and second source/drain electrodes 810, 830, a flat layer 900, an anode 1000, a pixel defining layer 1100, and a photoresist spacer 1200 on the gate insulating layer 400.
  • the first source/drain 810 is electrically connected to the N-type heavily doped region N+ of the first polysilicon segment 301, and the second source/drain 830 is electrically connected to the P-type heavily doped of the second polysilicon segment 303.
  • the impurity region P+; the anode 1000 is electrically connected to the second source/drain 830.
  • the first polysilicon segment 301, the first gate 601 and the first source/drain 810 constitute a switching TFT;
  • the second polysilicon segment 303, the second gate 603 and the second source/drain 830 constitute a driving The TFT;
  • the third polysilicon segment 305 and the electrode plate 605 constitute a storage capacitor.
  • the object of the present invention is to provide a method for fabricating an AMOLED backplane, which can make the lightly doped drain regions on both sides of the channel region of the switching TFT symmetrical, increase the on current, reduce the photocurrent, and save a mask and reduce cost.
  • the present invention provides a method for fabricating an AMOLED backplane: sequentially depositing a buffer layer and an amorphous silicon layer on the substrate, crystallizing the amorphous silicon layer, converting into a polysilicon layer, and patterning the polysilicon layer to deposit a gate electrode.
  • the photoresist pattern prepared by the yellow light process is used as a shielding layer, and the patterned polysilicon layer is heavily doped by P-type; then the first metal layer is deposited and patterned on the gate insulating layer to form a gate.
  • the patterned first metal layer is used as a shielding layer to perform N-type light doping on the patterned polysilicon layer; then an insulating layer is deposited, and the insulating layer is anisotropically etched to form a barrier, and then The patterned first metal layer and the barrier are the shielding layer, and the patterned polysilicon layer is heavily doped N-type to form a symmetric lightly doped drain region.
  • the manufacturing method of the AMOLED backplane specifically includes the following steps:
  • Step 1 providing a substrate, depositing a buffer layer on the substrate;
  • Step 2 depositing an amorphous silicon layer on the buffer layer, and performing an excimer laser annealing treatment on the amorphous silicon layer, so that the amorphous silicon layer is crystallized and converted into a polysilicon layer; and then the polysilicon layer is patterned. Processing, forming mutually spaced first polysilicon segments, second polysilicon segments, and third polysilicon segments;
  • the third polysilicon segment is located between the first polysilicon segment and the second polysilicon segment;
  • Step 3 depositing a gate insulating layer on the buffer layer and the first, second, and third polysilicon segments;
  • Step 4 forming a photoresist pattern on the gate insulating layer by a yellow light process, the photoresist pattern completely shielding the first polysilicon segment, shielding the middle portion of the second polysilicon segment, and completely obscuring the third polycrystal Silicon segment
  • Step 5 using the photoresist pattern as a shielding layer, performing P-type heavily doping on the patterned polysilicon layer, thereby forming a P-type weight on both sides of the second polysilicon segment and the third polysilicon segment. Doped region
  • Step 6 removing the photoresist pattern, depositing and patterning a first metal layer on the gate insulating layer to form a first gate, a second gate, and an electrode plate;
  • the first gate is located above a middle portion of the first polysilicon segment
  • Step 7 Perform N-type light doping on the patterned polysilicon layer with the patterned first metal layer as a shielding layer, thereby forming an N-type light on both sides of the first polysilicon segment not shielded by the first gate. Doped region
  • Step 8 Deposit an insulating layer on the gate insulating layer and the first gate, the second gate and the electrode plate, and then anisotropically etch the insulating layer to form a barrier;
  • the barriers on both sides of the first gate are symmetrical;
  • Step 9 The patterned polysilicon layer is heavily doped with N by using the patterned first metal layer and the barrier as a shielding layer, so as to form a symmetric light blend directly under the barrier on both sides of the first gate. Miscellaneous drain region;
  • Step 10 forming an interlayer insulating layer, first and second source/drain, a flat layer, an anode, a pixel defining layer, and a photoresist spacer by sequentially depositing, yellowing, and etching processes on the gate insulating layer;
  • the first source/drain is electrically connected to the N-type heavily doped region of the first polysilicon segment, and the second source/drain is electrically connected to the P-type heavily doped region of the second polysilicon segment a region; the anode is electrically connected to the second source/drain;
  • the first polysilicon segment, the first gate and the first source/drain constitute a switching TFT; the second polysilicon segment, the second gate and the second source/drain constitute a driving TFT;
  • the third polysilicon segment and the electrode plate constitute a storage capacitor.
  • the insulating layer is a silicon oxide rich layer or a silicon nitride rich layer.
  • the insulating layer has a thickness of 0.2 to 0.5 um.
  • the concentration of the P-type heavily doped is higher than the concentration of the N-type heavily doped.
  • the buffer layer is a silicon oxide layer, a silicon nitride layer, or a combination of the two.
  • the interlayer insulating layer is a silicon oxide layer, a silicon nitride layer, or a combination of the two.
  • the material of the first gate, the second gate and the electrode plate is Mo.
  • the materials of the first and second source/drain electrodes are Ti/Al/Ti.
  • the material of the anode is ITO/Ag/ITO.
  • the present invention provides a method for fabricating an AMOLED backplane. After the first metal layer is patterned to form the first gate electrode, the second gate electrode, and the electrode plate, the patterned first metal layer is The shielding layer performs N-type light doping on the patterned polysilicon layer; the insulating layer is further deposited, and the insulating layer is anisotropically etched to form a barrier, and the patterned first metal layer and the barrier are used as the shielding layer pair pattern.
  • the polysilicon layer is heavily doped with N-type, so that a lightly doped drain region is formed directly under the barrier on both sides of the first gate, and on the one hand, lightly doped drain on both sides of the channel region of the switching TFT can be made.
  • the polar region is symmetrical, which can shorten the length of the lightly doped drain region and increase the on-current.
  • the material of the barrier is silicon-rich or silicon-rich silicon which can absorb light, the photocurrent can be effectively reduced and saved.
  • a reticle that forms an N-type heavily doped region reduces cost.
  • FIG. 1 is a schematic structural view of a conventional AMOLED backplane
  • FIG. 2 is a flow chart of a method for fabricating an AMOLED backplane according to the present invention
  • step 2 is a schematic diagram of step 2 of a method for fabricating an AMOLED backplane according to the present invention
  • step 3 is a schematic diagram of step 3 of a method for fabricating an AMOLED backplane according to the present invention.
  • step 4 is a schematic diagram of step 4 of a method for fabricating an AMOLED backplane according to the present invention.
  • step 5 is a schematic diagram of step 5 of a method for fabricating an AMOLED backplane according to the present invention.
  • step 6 is a schematic diagram of step 6 of a method for fabricating an AMOLED backplane according to the present invention.
  • step 7 is a schematic diagram of step 7 of a method for fabricating an AMOLED backplane according to the present invention.
  • step 8 is a schematic view showing deposition of an insulating layer in step 8 of the method for fabricating an AMOLED backplane according to the present invention.
  • FIG. 10 is a schematic view showing the formation of a barrier in step 8 of the method for fabricating an AMOLED backplane according to the present invention.
  • step 9 is a schematic diagram of step 9 of a method for fabricating an AMOLED backplane according to the present invention.
  • FIG. 12 is a schematic diagram of step 10 of a method for fabricating an AMOLED backplane according to the present invention.
  • the present invention provides a method for fabricating an AMOLED backplane, which specifically includes the following steps:
  • Step 1 A substrate 1 is provided, and a buffer layer 2 is deposited on the substrate 1.
  • the substrate 1 is a transparent substrate.
  • the substrate 1 is a glass substrate or a plastic substrate.
  • the buffer layer 2 is an SiOx silicon oxide layer, a SiNx silicon nitride layer, or a combination of the two.
  • Step 2 depositing an amorphous silicon layer on the buffer layer 2, and performing an excimer laser annealing treatment on the amorphous silicon layer, so that the amorphous silicon layer is crystallized and converted into a polysilicon layer; Patterning is performed to form first polysilicon segments 31, second polysilicon segments 33, and third polysilicon segments 35 that are spaced apart from one another.
  • the third polysilicon segment 35 is located between the first polysilicon segment 31 and the second polysilicon segment 33.
  • Step 3 As shown in FIG. 4, a gate insulating layer 4 is deposited on the buffer layer 2 and the first, second, and third polysilicon segments 31, 33, and 35.
  • Step 4 As shown in FIG. 5, a photoresist pattern 5 is formed on the gate insulating layer 4 by a yellow light process.
  • the photoresist pattern 5 completely shields the first polysilicon segment 31, shielding the middle portion of the second polysilicon segment 33, and does not shield the third polysilicon segment 35 at all.
  • Step 5 using the photoresist pattern 5 as a shielding layer, performing P-type heavily doping on the patterned polysilicon layer, so as to be on both sides of the second polysilicon segment 33, and third.
  • the polysilicon segment 35 forms a P-type heavily doped region P+.
  • the conductivity of the third polysilicon segment 35 is greatly improved after being heavily doped by the P-type.
  • Step 6 as shown in FIG. 7, the photoresist pattern 5 is removed, and a first metal layer is deposited and patterned on the gate insulating layer 4 to form a first gate 61, a second gate 63, and an electrode plate 65. .
  • the first gate 61 is located above the middle of the first polysilicon segment 31, and the second gate 63 is located above the middle of the second polysilicon segment 33, and the electrode plate 65 is the third largest The crystalline silicon segment 35 corresponds.
  • the material of the first gate 61, the second gate 63 and the electrode plate 65 is molybdenum Mo.
  • Step 7 as shown in FIG. 8 , the patterned first silicon layer, the first gate 61 , the second gate 63 , and the electrode plate 65 are used as a shielding layer to perform N-type light doping on the patterned polysilicon layer, thereby An N-type lightly doped region N- is formed on both sides of the first polysilicon segment 31 that is not shielded by the first gate 61.
  • Step 8 as shown in FIG. 9 and FIG. 10, firstly depositing an insulating layer 7 on the gate insulating layer 4 and the first gate 61, the second gate 63 and the electrode plate 65, the insulating layer 7
  • the thickness is 0.2 ⁇ 0.5 um
  • the material is silicon rich oxide (SRO) or silicon rich nitride (SRN); and the insulating layer 7 is subjected to non-isotropic etching (Non-Isotropic etch), A barrier 71 is formed, and the barrier 71 is located on both sides of the first gate 61, the second gate 63, and the electrode plate 65, respectively.
  • the barriers 71 located on both sides of the first gate 61 are symmetrical.
  • Step 9 As shown in FIG. 11 , the patterned polysilicon layer is heavily doped N-type with the patterned first metal layer and the barrier 71 as a shielding layer, so that the barrier is on both sides of the first gate 61.
  • a lightly doped drain region N- is formed directly under the 71, and an N-type heavily doped region N+ is formed outside the lightly doped drain region N-.
  • the lightly doped drain region N- formed directly under the barrier 71 on both sides of the first gate 61 is also symmetrical.
  • the concentration of the N-type heavily doped in the step 9 is smaller than the concentration of the P-type heavily doped in the step 5, and the P-type heavily doped on the two sides of the second polysilicon segment 33 by the N-type heavily doped.
  • the influence of the conductivity of the region P+ is small.
  • Step 10 as shown in FIG. 12, an interlayer insulating layer 8, first and second source/drain electrodes 91, 93, a flat layer 10, and an anode are sequentially formed on the gate insulating layer 4 by a deposition, a yellow light, and an etching process.
  • a pixel defining layer 12 and a photoresist spacer 13 are sequentially formed on the gate insulating layer 4 by a deposition, a yellow light, and an etching process. 11.
  • the first source/drain 91 is electrically connected to the N-type heavily doped region N+ of the first polysilicon segment 31, and the second source/drain 93 is electrically connected to the second polysilicon segment 33.
  • the P-type heavily doped region P+; the anode 11 is electrically connected to the second source/drain 93.
  • the first polysilicon segment 31, the first gate 61 and the first source/drain 91 constitute a switching TFT; the second polysilicon segment 33, the second gate 63 and the second source/drain 93
  • the driving TFT is configured;
  • the third polysilicon segment 35 and the electrode plate 65 constitute a storage capacitor.
  • the storage capacitor is located between the switching TFT and the driving TFT.
  • the interlayer insulating layer 8 is an SiOx silicon oxide layer, a SiNx silicon nitride layer, or a combination of the two.
  • the materials of the first and second source/drain electrodes 91, 93 are titanium/aluminum/titanium Ti/Al/Ti.
  • the material of the anode is indium tin oxide/silver/indium tin oxide ITO/Ag/ITO.
  • the lightly doped drain region on both sides of the channel region of the switching TFT is N-symmetric, the length of the lightly doped drain region N- can be shortened, and the on current can be increased;
  • the silicon-rich or silicon-rich silicon nitride of 71 can absorb light and can effectively reduce the photocurrent; and the N-type heavily doped region N+ has the patterned first metal layer and the barrier 71 as a shielding layer, compared with the existing method.
  • the photoresist pattern formed by the yellow light process is used as a shielding layer, which saves a mask and can reduce the cost.
  • the patterned first metal layer is used as the shielding layer pair pattern.
  • the polysilicon layer is lightly doped with N-type; the insulating layer is further deposited, and the insulating layer is anisotropically etched to form a barrier, and the patterned first metal layer and the barrier are used as the shielding layer to pattern the polysilicon layer.
  • N-type heavily doping to form a lightly doped drain region directly under the barrier on both sides of the first gate on the one hand, making the lightly doped drain regions on both sides of the channel region of the switching TFT symmetrical, The length of the lightly doped drain region can be shortened, and the on-current can be increased.
  • the material of the barrier is silicon-rich or silicon-rich silicon which can absorb light, the photocurrent can be effectively reduced, and a N-type is saved. Photomasks in heavily doped areas reduce cost.

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Abstract

提供一种AMOLED背板的制作方法，在图案化第一金属层形成第一栅极(61)、第二栅极(63)及电极板(65)后，以图案化的第一金属层为遮蔽层对图案化的多晶硅层进行N型轻掺杂；再沉积绝缘层(7)，对绝缘层(7)进行非等向性蚀刻，形成阻隔物(71)，以图案化的第一金属层与阻隔物(71)为遮蔽层对图案化的多晶硅层进行N型重掺杂，从而在第一栅极(61)的两侧于阻隔物(71)的正下方形成轻掺杂漏极区域(N-)，能够使得开关TFT沟道区域两侧的轻掺杂漏极区域(N-)对称，可缩短轻掺杂漏极区域(N-)的长度，增大导通电流，有效降低光电流，且节省一道光罩，降低成本。

Description

AMOLED背板的制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种AMOLED背板的制作方法。
背景技术
在显示技术领域，液晶显示器(Liquid Crystal Display，LCD)与有机发光二极管显示器(Organic Light Emitting Diode，OLED)等平板显示技术已经逐步取代CRT显示器。其中，OLED具有自发光、驱动电压低、发光效率高、响应时间短、清晰度与对比度高、近180°视角、使用温度范围宽，可实现柔性显示与大面积全色显示等诸多优点，被业界公认为是最有发展潜力的显示装置。
OLED按照驱动类型可分为无源OLED(PMOLED)和有源OLED(AMOLED)。其中，AMOLED通常是由低温多晶硅(Low Temperature Poly-Silicon，LTPS)驱动背板和电激发光层组成自发光组件。低温多晶硅具有较高的电子迁移率，对AMOLED而言，采用低温多晶硅材料具有高分辨率、反应速度快、高亮度、高开口率、低能耗等优点。
现有技术中常见的AMOLED背板的结构如图1所示。该AMOLED背板的制作过程大体为：
步骤1、在基板100上沉积缓冲层200；
步骤2、在缓冲层200上沉积非晶硅(a-Si)层，经激光(Laser)处理使非晶硅层结晶、转变为多晶硅(Poly-Si)层；接着通过黄光、蚀刻制程对多晶硅层进行图案化处理，形成间隔排列的第一多晶硅段301、第二多晶硅段303、及第三多晶硅段305；
步骤3、沉积栅极绝缘层400；
步骤4、通过黄光制程在栅极绝缘层400上制作第一层光刻胶图案；
步骤5、以第一光刻胶图案为遮蔽层对图案化的多晶硅层进行P型重掺杂，在第二多晶硅段303的两侧、及第三多晶硅段305形成P型重掺杂区域P+；
步骤6、先清除第一层光刻胶图案，再通过黄光制程在栅极绝缘层上制作第二层光刻胶图案；
步骤7、以第二层光刻胶图案为遮蔽层，对图案化的多晶硅层进行N型重掺杂，在第一多晶硅段301的两侧形成N型重掺杂区域N+；
步骤8、清除第二层光刻胶图案，在栅极绝缘层400上沉积并图案化第一金属层，形成第一栅极601、第二栅极605、及电极板603；
步骤9、以图案化的第一金属层作为遮蔽层对图案化的多晶硅层进行离子植入(Self-align)，在第一多晶硅段301的两侧形成轻掺杂漏极区域(Light Doping Drain)N-。
步骤10、在栅极绝缘层400上依次形成层间绝缘层700、第一与第二源/漏极810、830、平坦层900、阳极1000、像素定义层1100、及光阻间隙物1200。
第一源/漏极810电性连接于第一多晶硅段301的N型重掺杂区域N+，第二源/漏极830电性连接于第二多晶硅段303的P型重掺杂区域P+；阳极1000电性连接于第二源/漏极830。
所述第一多晶硅段301、第一栅极601与第一源/漏极810构成开关TFT；第二多晶硅段303、第二栅极603与第二源/漏极830构成驱动TFT；第三多晶硅段305与电极板605构成存储电容。
通过上述方法制作AMOLED的背板存在一定的问题，若进行N型重掺杂之前的步骤6中的黄光制程偏移，容易造成位于开关TFT沟道区域两侧的轻掺杂漏极区域不对称。
发明内容
本发明的目的在于提供一种AMOLED背板的制作方法，能够使得开关TFT沟道区域两侧的轻掺杂漏极区域对称，增大导通电流，降低光电流，且节省一道光罩，降低成本。
为实现上述目的，本发明提供一种AMOLED背板的制作方法：依次在基板上沉积缓冲层、非晶硅层，使非晶硅层结晶、转变为多晶硅层并图案化多晶硅层，沉积栅极绝缘层后，先利用黄光制程制作的光刻胶图案为遮蔽层，对图案化的多晶硅层进行P型重掺杂；再在栅极绝缘层上沉积并图案化第一金属层，形成栅极，以图案化的第一金属层为遮蔽层对图案化的多晶硅层进行N型轻掺杂；然后沉积一层绝缘层，对该绝缘层进行非等向性蚀刻，形成阻隔物，再以图案化的第一金属层与阻隔物为遮蔽层对图案化的多晶硅层进行N型重掺杂，形成对称的轻掺杂漏极区域。
所述的AMOLED背板的制作方法具体包括如下步骤：
步骤1、提供一基板，在该基板上沉积缓冲层；
步骤2、在缓冲层上沉积非晶硅层，并对非晶硅层进行准分子激光退火处理，使得该非晶硅层结晶、转变为多晶硅层；再对多晶硅层进行图案化 处理，形成相互间隔的第一多晶硅段、第二多晶硅段、及第三多晶硅段；
所述第三多晶硅段位于第一多晶硅段与第二多晶硅段之间；
步骤3、在所述缓冲层与第一、第二、第三多晶硅段上沉积栅极绝缘层；
步骤4、通过黄光制程在栅极绝缘层上制作光刻胶图案，该光刻胶图案完全遮蔽第一多晶硅段，遮蔽第二多晶硅段的中部，完全不遮蔽第三多晶硅段；
步骤5、以所述光刻胶图案为遮蔽层，对图案化的多晶硅层进行P型重掺杂，从而在第二多晶硅段的两侧、及第三多晶硅段形成P型重掺杂区域；
步骤6、清除所述光刻胶图案，在栅极绝缘层上沉积并图案化第一金属层，形成第一栅极、第二栅极及电极板；
所述第一栅极位于第一多晶硅段中部的上方；
步骤7、以图案化的第一金属层为遮蔽层对图案化的多晶硅层进行N型轻掺杂，从而在未被第一栅极遮蔽的第一多晶硅段的两侧形成N型轻掺杂区域；
步骤8、在所述栅极绝缘层与第一栅极、第二栅极及电极板上沉积一层绝缘层，再对该绝缘层进行非等向性蚀刻，形成阻隔物；
位于所述第一栅极两侧的阻隔物对称；
步骤9、以图案化的第一金属层与阻隔物为遮蔽层对图案化的多晶硅层进行N型重掺杂，从而在第一栅极的两侧于阻隔物的正下方形成对称的轻掺杂漏极区域；
步骤10、在栅极绝缘层上依次通过沉积、黄光、蚀刻制程形成层间绝缘层、第一与第二源/漏极、平坦层、阳极、像素定义层、及光阻间隙物；
所述第一源/漏极电性连接于第一多晶硅段的N型重掺杂区域，所述第二源/漏极电性连接于第二多晶硅段的P型重掺杂区域；所述阳极电性连接于第二源/漏极；
所述第一多晶硅段、第一栅极与第一源/漏极构成开关TFT；所述第二多晶硅段、第二栅极与第二源/漏极构成驱动TFT；所述第三多晶硅段与电极板构成存储电容。
所述绝缘层为富氧化硅层或富氮化硅层。
所述绝缘层的厚度为0.2～0.5um。
所述P型重掺杂的浓度高于N型重掺杂的浓度。
所述缓冲层为氧化硅层、氮化硅层、或二者的组合。
所述层间绝缘层为氧化硅层、氮化硅层、或二者的组合。
所述第一栅极、第二栅极及电极板的材料为Mo。
所述第一与第二源/漏极的材料为Ti/Al/Ti。
所述阳极的材料为ITO/Ag/ITO。
本发明的有益效果：本发明提供的一种AMOLED背板的制作方法，在图案化第一金属层形成第一栅极、第二栅极及电极板后，以图案化的第一金属层为遮蔽层对图案化的多晶硅层进行N型轻掺杂；再沉积绝缘层，对绝缘层进行非等向性蚀刻，形成阻隔物，以图案化的第一金属层与阻隔物为遮蔽层对图案化的多晶硅层进行N型重掺杂，从而在第一栅极的两侧于阻隔物的正下方形成轻掺杂漏极区域，一方面能够使得开关TFT沟道区域两侧的轻掺杂漏极区域对称，可缩短轻掺杂漏极区域的长度，增大导通电流，一方面由于阻隔物的材料为可以吸收光的富氧化硅或富氮化硅，能够有效降低光电流，且节省一道形成N型重掺杂区域的光罩，降低成本。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为现有AMOLED背板的结构示意图；
图2为本发明AMOLED背板的制作方法的流程图；
图3为本发明AMOLED背板的制作方法的步骤2的示意图；
图4为本发明AMOLED背板的制作方法的步骤3的示意图；
图5为本发明AMOLED背板的制作方法的步骤4的示意图；
图6为本发明AMOLED背板的制作方法的步骤5的示意图；
图7为本发明AMOLED背板的制作方法的步骤6的示意图；
图8为本发明AMOLED背板的制作方法的步骤7的示意图；
图9为本发明AMOLED背板的制作方法的步骤8中沉积绝缘层的示意图；
图10为本发明AMOLED背板的制作方法的步骤8中形成阻隔物的示意图；
图11为本发明AMOLED背板的制作方法的步骤9的示意图；
图12为本发明AMOLED背板的制作方法的步骤10的示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图2，本发明提供一种AMOLED背板的制作方法，具体包括如下步骤：
步骤1、提供一基板1，在该基板1上沉积缓冲层2。
所述基板1为透明基板，优选的，所述基板1为玻璃基板或塑料基板。
所述缓冲层2为SiOx氧化硅层、SiNx氮化硅层、或二者的组合。
步骤2、如图3所示，在缓冲层2上沉积非晶硅层，并对非晶硅层进行准分子激光退火处理，使得该非晶硅层结晶、转变为多晶硅层；再对多晶硅层进行图案化处理，形成相互间隔的第一多晶硅段31、第二多晶硅段33、及第三多晶硅段35。
所述第三多晶硅段35位于第一多晶硅段31与第二多晶硅段33之间。
步骤3、如图4所示，在所述缓冲层2与第一、第二、第三多晶硅段31、33、35上沉积栅极绝缘层4。
步骤4、如图5所示，通过黄光制程在栅极绝缘层4上制作光刻胶图案5。
该光刻胶图案5完全遮蔽第一多晶硅段31，遮蔽第二多晶硅段33的中部，完全不遮蔽第三多晶硅段35。
步骤5、如图6所示，以所述光刻胶图案5为遮蔽层，对图案化的多晶硅层进行P型重掺杂，从而在第二多晶硅段33的两侧、及第三多晶硅段35形成P型重掺杂区域P+。
由于光刻胶图案5完全不遮蔽第三多晶硅段35，经P型重掺杂后，该第三多晶硅段35的导电性能大幅提高。
步骤6、如图7所示，清除所述光刻胶图案5，在栅极绝缘层4上沉积并图案化第一金属层，形成第一栅极61、第二栅极63及电极板65。
具体的，所述第一栅极61位于第一多晶硅段31中部的上方，所述第二栅极63位于第二多晶硅段33中部的上方，所述电极板65与第三多晶硅段35相对应。所述第一栅极61、第二栅极63及电极板65的材料为钼Mo。
步骤7、如图8所示，以图案化的第一金属层即第一栅极61、第二栅极63及电极板65为遮蔽层对图案化的多晶硅层进行N型轻掺杂，从而在未被第一栅极61遮蔽的第一多晶硅段31的两侧形成N型轻掺杂区域N-。
步骤8、如图9、图10所示，首先在所述栅极绝缘层4与第一栅极61、第二栅极63及电极板65上沉积一层绝缘层7，所述绝缘层7的厚度为0.2 ～0.5um，其材料为富氧化硅(Silicon rich oxide，SRO)或富氮化硅(Silicon rich nitride，SRN)；再对所述绝缘层7进行非等向性蚀刻(Non-Isotropic etch)，形成阻隔物71，所述阻隔物71分别位于第一栅极61、第二栅极63、与电极板65的两侧。
位于所述第一栅极61两侧的阻隔物71对称。
步骤9、如图11所示，以图案化的第一金属层与阻隔物71为遮蔽层对图案化的多晶硅层进行N型重掺杂，从而在第一栅极61的两侧于阻隔物71的正下方形成轻掺杂漏极区域N-，在轻掺杂漏极区域N-的外侧形成N型重掺杂区域N+。
由于位于所述第一栅极61两侧的阻隔物71对称，从而在第一栅极61的两侧于阻隔物71的正下方形成的轻掺杂漏极区域N-也是对称的。
值得一提的是，该步骤9中N型重掺杂的浓度小于步骤5中P型重掺杂的浓度，N型重掺杂对第二多晶硅段33两侧的P型重掺杂区域P+的导电性能的影响较小。
步骤10、如图12所示，通过沉积、黄光、蚀刻制程在栅极绝缘层4上依次形成层间绝缘层8、第一与第二源/漏极91、93、平坦层10、阳极11、像素定义层12、及光阻间隙物13。
所述第一源/漏极91电性连接于第一多晶硅段31的N型重掺杂区域N+，所述第二源/漏极93电性连接于第二多晶硅段33的P型重掺杂区域P+；所述阳极11电性连接于第二源/漏极93。
所述第一多晶硅段31、第一栅极61与第一源/漏极91构成开关TFT；所述第二多晶硅段33、第二栅极63与第二源/漏极93构成驱动TFT；所述第三多晶硅段35与电极板65构成存储电容。所述存储电容位于开关TFT与驱动TFT之间。
具体的，所述层间绝缘层8为SiOx氧化硅层、SiNx氮化硅层、或二者的组合。
所述第一与第二源/漏极91、93的材料为钛/铝/钛Ti/Al/Ti。
所述阳极的材料为氧化铟锡/银/氧化铟锡ITO/Ag/ITO。
上述AMOLED背板的制作方法，由于开关TFT沟道区域两侧的轻掺杂漏极区域N-对称，可缩短轻掺杂漏极区域N-的长度，增大导通电流；由于构成阻隔物71的富氧化硅或富氮化硅可以吸收光，能够有效降低光电流；且N型重掺杂区域N+以图案化的第一金属层与阻隔物71为遮蔽层，相比现有方法中采用黄光制程形成的光刻胶图案为遮蔽层，节省了一道光罩，能够降低成本。
综上所述，本发明的AMOLED背板的制作方法，在图案化第一金属层形成第一栅极、第二栅极及电极板后，以图案化的第一金属层为遮蔽层对图案化的多晶硅层进行N型轻掺杂；再沉积绝缘层，对绝缘层进行非等向性蚀刻，形成阻隔物，以图案化的第一金属层与阻隔物为遮蔽层对图案化的多晶硅层进行N型重掺杂，从而在第一栅极的两侧于阻隔物的正下方形成轻掺杂漏极区域，一方面能够使得开关TFT沟道区域两侧的轻掺杂漏极区域对称，可缩短轻掺杂漏极区域的长度，增大导通电流，一方面由于阻隔物的材料为可以吸收光的富氧化硅或富氮化硅，能够有效降低光电流，且节省一道形成N型重掺杂区域的光罩，降低成本。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (11)

  1. 一种AMOLED背板的制作方法，依次在基板上沉积缓冲层、非晶硅层，使非晶硅层结晶、转变为多晶硅层并图案化多晶硅层，沉积栅极绝缘层后，先利用黄光制程制作的光刻胶图案为遮蔽层，对图案化的多晶硅层进行P型重掺杂；再在栅极绝缘层上沉积并图案化第一金属层，形成栅极，以图案化的第一金属层为遮蔽层对图案化的多晶硅层进行N型轻掺杂；然后沉积一层绝缘层对该绝缘层进行非等向性蚀刻，形成阻隔物，再以图案化的第一金属层与阻隔物为遮蔽层对图案化的多晶硅层进行N型重掺杂，形成对称的轻掺杂漏极区域。
  2. 如权利要求1所述的AMOLED背板的制作方法，其中，包括如下步骤：
    步骤1、提供一基板，在该基板上沉积缓冲层；
    步骤2、在缓冲层上沉积非晶硅层，并对非晶硅层进行准分子激光退火处理，使得该非晶硅层结晶、转变为多晶硅层；再对多晶硅层进行图案化处理，形成相互间隔的第一多晶硅段、第二多晶硅段、及第三多晶硅段；
    所述第三多晶硅段位于第一多晶硅段与第二多晶硅段之间；
    步骤3、在所述缓冲层与第一、第二、第三多晶硅段上沉积栅极绝缘层；
    步骤4、通过黄光制程在栅极绝缘层上制作光刻胶图案，该光刻胶图案完全遮蔽第一多晶硅段，遮蔽第二多晶硅段的中部，完全不遮蔽第三多晶硅段；
    步骤5、以所述光刻胶图案为遮蔽层，对图案化的多晶硅层进行P型重掺杂，从而在第二多晶硅段的两侧、及第三多晶硅段形成P型重掺杂区域；
    步骤6、清除所述光刻胶图案，在栅极绝缘层上沉积并图案化第一金属层，形成第一栅极、第二栅极及电极板；
    所述第一栅极位于第一多晶硅段中部的上方；
    步骤7、以图案化的第一金属层为遮蔽层对图案化的多晶硅层进行N型轻掺杂，从而在未被第一栅极遮蔽的第一多晶硅段的两侧形成N型轻掺杂区域；
    步骤8、在所述栅极绝缘层与第一栅极、第二栅极及电极板上沉积一层绝缘层，再对该绝缘层进行非等向性蚀刻，形成阻隔物；
    位于所述第一栅极两侧的阻隔物对称；
    步骤9、以图案化的第一金属层与阻隔物为遮蔽层对图案化的多晶硅层 进行N型重掺杂，从而在第一栅极的两侧于阻隔物的正下方形成对称的轻掺杂漏极区域；
    步骤10、在栅极绝缘层上依次通过沉积、黄光、蚀刻制程形成层间绝缘层、第一与第二源/漏极、平坦层、阳极、像素定义层、及光阻间隙物；
    所述第一源/漏极电性连接于第一多晶硅段的N型重掺杂区域，所述第二源/漏极电性连接于第二多晶硅段的P型重掺杂区域；所述阳极电性连接于第二源/漏极；
    所述第一多晶硅段、第一栅极与第一源/漏极构成开关TFT；所述第二多晶硅段、第二栅极与第二源/漏极构成驱动TFT；所述第三多晶硅段与电极板构成存储电容。
  3. 如权利要求2所述的AMOLED背板的制作方法，其中，所述绝缘层为富氧化硅层或富氮化硅层。
  4. 如权利要求2所述的AMOLED背板的制作方法，其中，所述绝缘层的厚度为0.2～0.5um。
  5. 如权利要求2所述的AMOLED背板的制作方法，其中，所述P型重掺杂的浓度高于N型重掺杂的浓度。
  6. 如权利要求2所述的AMOLED背板的制作方法，其中，所述缓冲层为氧化硅层、氮化硅层、或二者的组合。
  7. 如权利要求2所述的AMOLED背板的制作方法，其中，所述层间绝缘层为氧化硅层、氮化硅层、或二者的组合。
  8. 如权利要求2所述的AMOLED背板的制作方法，其中，所述第一栅极、第二栅极及电极板的材料为Mo。
  9. 如权利要求2所述的AMOLED背板的制作方法，其中，所述第一与第二源/漏极的材料为Ti/Al/Ti。
  10. 如权利要求2所述的AMOLED背板的制作方法，其中，所述阳极的材料为ITO/Ag/ITO。
  11. 一种AMOLED背板的制作方法，依次在基板上沉积缓冲层、非晶硅层，使非晶硅层结晶、转变为多晶硅层并图案化多晶硅层，沉积栅极绝缘层后，先利用黄光制程制作的光刻胶图案为遮蔽层，对图案化的多晶硅层进行P型重掺杂；再在栅极绝缘层上沉积并图案化第一金属层，形成栅极，以图案化的第一金属层为遮蔽层对图案化的多晶硅层进行N型轻掺杂；然后沉积一层绝缘层对该绝缘层进行非等向性蚀刻，形成阻隔物，再以图案化的第一金属层与阻隔物为遮蔽层对图案化的多晶硅层进行N型重掺杂，形成对称的轻掺杂漏极区域；
    其中，包括如下步骤：
    步骤1、提供一基板，在该基板上沉积缓冲层；
    步骤2、在缓冲层上沉积非晶硅层，并对非晶硅层进行准分子激光退火处理，使得该非晶硅层结晶、转变为多晶硅层；再对多晶硅层进行图案化处理，形成相互间隔的第一多晶硅段、第二多晶硅段、及第三多晶硅段；
    所述第三多晶硅段位于第一多晶硅段与第二多晶硅段之间；
    步骤3、在所述缓冲层与第一、第二、第三多晶硅段上沉积栅极绝缘层；
    步骤4、通过黄光制程在栅极绝缘层上制作光刻胶图案，该光刻胶图案完全遮蔽第一多晶硅段，遮蔽第二多晶硅段的中部，完全不遮蔽第三多晶硅段；
    步骤5、以所述光刻胶图案为遮蔽层，对图案化的多晶硅层进行P型重掺杂，从而在第二多晶硅段的两侧、及第三多晶硅段形成P型重掺杂区域；
    步骤6、清除所述光刻胶图案，在栅极绝缘层上沉积并图案化第一金属层，形成第一栅极、第二栅极及电极板；
    所述第一栅极位于第一多晶硅段中部的上方；
    步骤7、以图案化的第一金属层为遮蔽层对图案化的多晶硅层进行N型轻掺杂，从而在未被第一栅极遮蔽的第一多晶硅段的两侧形成N型轻掺杂区域；
    步骤8、在所述栅极绝缘层与第一栅极、第二栅极及电极板上沉积一层绝缘层，再对该绝缘层进行非等向性蚀刻，形成阻隔物；
    位于所述第一栅极两侧的阻隔物对称；
    步骤9、以图案化的第一金属层与阻隔物为遮蔽层对图案化的多晶硅层进行N型重掺杂，从而在第一栅极的两侧于阻隔物的正下方形成对称的轻掺杂漏极区域；
    步骤10、在栅极绝缘层上依次通过沉积、黄光、蚀刻制程形成层间绝缘层、第一与第二源/漏极、平坦层、阳极、像素定义层、及光阻间隙物；
    所述第一源/漏极电性连接于第一多晶硅段的N型重掺杂区域，所述第二源/漏极电性连接于第二多晶硅段的P型重掺杂区域；所述阳极电性连接于第二源/漏极；
    所述第一多晶硅段、第一栅极与第一源/漏极构成开关TFT；所述第二多晶硅段、第二栅极与第二源/漏极构成驱动TFT；所述第三多晶硅段与电极板构成存储电容；
    其中，所述绝缘层为富氧化硅层或富氮化硅层；
    其中，所述P型重掺杂的浓度高于N型重掺杂的浓度；
    其中，所述缓冲层为氧化硅层、氮化硅层、或二者的组合。
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