WO2015174123A1 - 電力変換装置 - Google Patents
電力変換装置 Download PDFInfo
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- WO2015174123A1 WO2015174123A1 PCT/JP2015/056612 JP2015056612W WO2015174123A1 WO 2015174123 A1 WO2015174123 A1 WO 2015174123A1 JP 2015056612 W JP2015056612 W JP 2015056612W WO 2015174123 A1 WO2015174123 A1 WO 2015174123A1
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- switching element
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- gate signal
- power
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
- H02M1/4208—Arrangements for improving power factor of AC input
- H02M1/4225—Arrangements for improving power factor of AC input using a non-isolated boost converter
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
- H02M1/4208—Arrangements for improving power factor of AC input
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
- H02M1/4208—Arrangements for improving power factor of AC input
- H02M1/4258—Arrangements for improving power factor of AC input using a single converter stage both for correction of AC input power factor and generation of a regulated and galvanically isolated DC output voltage
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33538—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only of the forward type
- H02M3/33546—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only of the forward type with automatic control of the output voltage or current
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0009—Devices or circuits for detecting current in a converter
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Definitions
- the present invention relates to a power conversion device that converts input power from an AC power source and supplies desired power to the secondary side of the insulation transformer.
- a converter circuit for a charger includes a half bridge rectifier circuit composed of two diodes, a capacitor connected in parallel to both ends of the half bridge rectifier circuit, and a first half composed of two switch elements (1) and (2), respectively.
- a full bridge circuit comprising four switch elements configured by connecting both ends of a second half bridge circuit comprising a bridge circuit and two switch elements (3) and (4) in parallel to both ends of the capacitor;
- a reactor provided between the other end of the AC power source having one end connected to the connection point between the switch elements in the half bridge circuit and the connection point between the diodes in the half bridge rectifier circuit, and the first and second half bridges A primary coil of a high-frequency transformer connected between connection points of switch elements in the circuit, and the four switches.
- the control circuit performs on / off control alternately for the group composed of the switch elements (1) and (4) and the group composed of the switch elements (2) and (3) in the full bridge circuit composed of four switch elements.
- a full-bridge rectifier circuit connected in parallel to the secondary coil of the high-frequency transformer and a capacitor connected in parallel to both ends of the full-bridge rectifier circuit constitute a secondary circuit of the converter, which is generated in the primary circuit.
- the battery is charged by rectifying the high-frequency power (see, for example, Patent Document 1).
- the two half-bridge circuits of the full-bridge circuit are controlled synchronously with the same duty ratio. For this reason, when high power factor control of the input current is performed, the DC capacitor voltage of the full bridge circuit may be out of the operating range, an overvoltage is applied to the power converter, or the ripple component of the output current is further expanded. There was a problem.
- the present invention has been made to solve the above-described problems, and provides a power converter that can simultaneously realize high power factor control of input current and output power control with high reliability. Objective.
- a power converter includes a rectifier circuit in which a plurality of diodes are configured in a full bridge, rectifies an input from an AC power supply, a reactor connected to a DC terminal of the rectifier circuit, an inverter circuit, and an insulation transformer. And a control circuit for controlling the output of the inverter circuit.
- the inverter circuit the first switching element and the second switching element are connected in series, the first leg having the connection point as the first AC terminal, the third switching element and the fourth switching element are connected in series, and the connection A second leg having a second AC terminal as a point and a DC capacitor are connected in parallel between the DC buses, the first AC terminal is connected to the positive DC terminal of the rectifier circuit, and the negative DC bus is connected.
- the insulation transformer has a primary winding and a secondary winding, and the first AC terminal and the second AC terminal of the inverter circuit are connected to both ends of the primary winding.
- the control circuit performs high power factor control of the circuit current flowing from the AC power source through the rectifier circuit by PWM control of the first leg, and uses a duty ratio equal to or lower than the duty ratio of the first leg.
- the power output to the secondary side of the isolation transformer is controlled by controlling the voltage of the DC capacitor by PWM control of the second leg.
- FIG. 1 is a schematic configuration diagram of a power conversion device according to Embodiment 1 of the present invention.
- the power conversion apparatus includes a main circuit and a control circuit 11 for converting AC power of an AC power source 1 into DC power and outputting the DC power to a battery 10 that is a DC circuit.
- the main circuit includes a rectifier circuit 2 that rectifies an input from the AC power source 1, a reactor 3 as a current limiting circuit, an inverter circuit 4, an insulating transformer 6, a second rectifier circuit 7, and a smoothing as a second reactor.
- a reactor 8 and a smoothing capacitor 9 are provided.
- the rectifier circuit 2 is a diode rectifier circuit in which four diodes 201 to 204 are configured as a full bridge.
- the inverter circuit 4 includes a first leg A in which a first switching element 401 and a second switching element 402 are connected in series, and the connection point is a first AC terminal 4a, and a third switching element 403 and a fourth switching element 404.
- This is a full-bridge inverter circuit that is connected in series, and the second leg B having the connection point as the second AC terminal 4b and the DC capacitor 5 are connected in parallel between the DC buses (between the PN buses).
- the second rectifier circuit 7 is a diode rectifier circuit in which the four diodes 701 to 704 are configured as a full bridge, but may be a rectifier system using other diodes or a rectifier system using active elements.
- the insulating transformer 6 has a primary winding 6a and a secondary winding 6b.
- the first AC terminal 4a and the second AC terminal 4b of the inverter circuit 4 are connected to both ends of the primary winding 6a, and the secondary winding 6b.
- the output of the AC power source 1 is connected to the AC terminal of the rectifier circuit 2, and the positive side DC terminal 2 a of the rectifier circuit 2 is connected to the first AC terminal 4 a of the inverter circuit 4 via the reactor 3.
- the negative side DC terminal 2b of the rectifier circuit 2 is connected to the negative side DC bus (hereinafter referred to as N bus) of the inverter circuit 4.
- the smoothing capacitor 9 is connected in parallel to the battery 10, the first DC output terminal of the second rectifier circuit 7 is connected to the first terminal of the smoothing capacitor 9 via the smoothing reactor 8, The second DC output terminal of the two rectifier circuit 7 is connected to the second terminal of the smoothing capacitor 9.
- the first to fourth switching elements 401 to 404 are constituted by IGBTs (Insulated Gate Bipolar Transistors) in which diodes 401a to 404a are connected in antiparallel.
- the first to fourth switching elements 401 to 404 may be semiconductor switching elements such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a diode built in between the source and the drain other than the IGBT. In the case where a MOSFET is used, a built-in diode may be used for the diodes 401a to 404a.
- MOSFET Metal Oxide Semiconductor Field Effect Transistor
- the reactor 3 is connected to the positive side DC terminal 2a of the rectifier circuit 2, but may be connected to the negative side DC terminal 2b, and the positive side DC terminal 2a and negative side DC terminal of the rectifier circuit 2 may be used. 2b may be distributed and connected. Further, the DC circuit may be a DC load that needs to be insulated from the input from the AC power source 1 in addition to the battery 10, and may be composed of, for example, an electric double layer capacitor.
- a current sensor for detecting a charging current (DC current) ibat In this case, a current flowing through reactor 3 is detected as current iac.
- the detected DC capacitor voltage Vdc, smoothing capacitor voltage Vbat, AC power supply voltage (AC voltage) Vac, current iac, and charging current ibat are input to the control circuit 11, and the control circuit 11 performs high frequency based on these values.
- the PWM control gate signals G1 to G4 to the first to fourth switching elements 401 to 404 are generated, and the output of the inverter circuit 4 is controlled.
- the control circuit 11 causes the gate signal GA (G1, G2) to the first leg A so that the input power factor from the AC power supply 1 becomes approximately 1, that is, the current iac is controlled at a high power factor.
- the inverter circuit 4 is output-controlled by turning on and off.
- FIG. 2 is a diagram showing gate signals G1 to G4 to the first to fourth switching elements 401 to 404, a current iac, and a voltage Vdc of the DC capacitor 5.
- the voltage Vdc of the DC capacitor 5 is controlled to be higher than the peak voltage Vp by setting the target voltage Vdc * higher than the peak voltage Vp of the voltage Vac of the AC power supply 1. Since the voltage Vac from the AC power supply 1 is full-wave rectified by the rectifier circuit 2, the voltage Vac operates at a cycle twice the AC cycle.
- the first and second switching elements 401 and 402 of the first leg A operated by the gate signals G1 and G2 are PWM controlled so that the amount of input current from the AC power supply 1 is constant and the input power factor is approximately 1.
- the third and fourth switching elements 403 and 404 of the second leg B operated by the gate signals G3 and G4 adjust the amount of power supplied to the battery 10 and the charge / discharge amount of the DC capacitor 5 to adjust the voltage of the DC capacitor 5. Control is performed so that Vdc becomes a constant target voltage Vdc * .
- controlling the current iac so that the input power factor from the AC power supply 1 is approximately 1 is simply referred to as current control.
- the driving cycle T is 4 of t0 to t1, t1 to t2, t2 to t3, t3 to t4 (t0).
- the operation mode in each period can be set to the first to fourth modes.
- the first switching element 401 operating with the gate signal G1 is turned on and the second switching element 402 operating with the gate signal G2 is turned off.
- the fourth switching element 404 operated by the gate signal G4 is also turned on at the same time.
- the fourth switching element 404 is turned off.
- the first switching element 401 is turned off and the second switching element 402 is turned on.
- the third switching element 403 operated by the gate signal G3 is also turned on simultaneously.
- t3 the third switching element 403 is turned off.
- FIGS. Current path diagrams for explaining the operation of each period in each operation mode are shown in FIGS.
- the current path diagram shows a current path in the inverter circuit 4.
- the current iac flowing through the reactor 3 flows from the AC power source 1 through the rectifier circuit 2 to the reactor 3 and is input to the first AC terminal 4 a of the inverter circuit 4.
- the first and fourth switching elements 401 and 404 are both turned on, and a current flows through the current path shown in FIG. That is, the current iac flowing through the reactor 3 flows through the primary winding 6 a of the insulating transformer 6 and returns to the input side via the fourth switching element 404.
- a current flows from the DC capacitor 5 to the primary winding 6 a via the first switching element 401, and the current returns to the DC capacitor 5 via the fourth switching element 404.
- the first switching element 401 since the first switching element 401 is on, the potential on the inverter circuit 4 side of the reactor 3 is fixed to the voltage Vdc.
- the voltage Vdc of the DC capacitor 5 is controlled to be higher than the peak voltage Vp of the voltage Vac of the AC power supply 1, and the current iac flowing through the reactor 3 decreases.
- the DC capacitor 5 discharges current, the voltage Vdc decreases.
- the second and third switching elements 402 and 403 are both turned on, and a current flows through the current path shown in FIG. That is, the current iac flowing through the reactor 3 flows back to the input side via the second switching element 402. Further, a current flows from the DC capacitor 5 to the primary winding 6 a via the third switching element 403, and the current returns to the DC capacitor 5 via the second switching element 402.
- the second switching element 402 since the second switching element 402 is in the ON state, the potential on the inverter circuit 4 side of the reactor 3 is fixed at the potential 0 of the N bus, and the current iac flowing through the reactor 3 increases.
- the DC capacitor 5 discharges current, the voltage Vdc decreases.
- a current flows through the insulating transformer 6, and the polarity of the current flowing through the primary winding 6a is reversed between the first mode and the third mode. That is, AC current is input to the insulating transformer 6, AC power is converted to DC power by the second rectifier circuit connected to the secondary winding 6 b, and DC power is smoothed by the smoothing reactor 8 and the smoothing capacitor 9. Power is supplied to the battery 10. Thus, DC power is supplied to the battery 10 in the first mode and the third mode.
- the periods of the first mode and the third mode are set to be equal in order to suppress the magnetization of the isolation transformer 6. That is, the ON period of the fourth switching element 404 is equal to the ON period of the third switching element 403, and the duty ratio is controlled to be equal.
- the first switching element 401 and the second switching element 402 are controlled to be turned on and off, and the current iac decreases during the on period of the first switching element 401, so that the second switching element 402 is turned on.
- the current iac increases during the period.
- the fourth switching element 404 has an on period only within the on period of the first switching element 401, and the third switching element 403 has an on period only within the on period of the second switching element 402.
- the voltage Vdc decreases during the on period of the third and fourth switching elements 403 and 404, and the voltage Vdc increases during the period when only the first switching element 401 is on. 2 is adjusted, that is, by adjusting the duty ratio of the third and fourth switching elements 403 and 404, the increase / decrease in the voltage Vdc of the DC capacitor 5 is adjusted and maintained at the target voltage Vdc * . .
- the current control of the current iac using the first and second switching elements 401 and 402 of the first leg A and the voltage Vdc using the third and fourth switching elements 403 and 404 of the second leg B are performed.
- DC power is supplied to the battery 10 while simultaneously performing current control and voltage control. Details of the current control and voltage control will be described in detail below.
- t2 is a timing determined by current control, and a duty ratio D1 that is an ON period (t0-t2) per drive cycle T in the first switching element 401 is expressed by (Expression 1). Further, the duty ratio D2 that is the ON period (t2-t4) per drive cycle T in the second switching element 402 is expressed by (Expression 2). However, vac is a voltage waveform of the AC power source 1, and Vdc is a voltage of the DC capacitor 5.
- the first and second switching elements 401 and 402 are driven at a duty ratio based on the above (Formula 1) and (Formula 2).
- the fourth switching element 404 is turned on simultaneously with the first switching element 401, the third switching element 403 is turned on simultaneously with the second switching element 402, and the fourth switching element 404 is turned on during the third period (t0-t1).
- the ON period (t2-t3) of the switching element 403 is equal.
- Duty ratios D3 and D4, which are ON periods per drive cycle T in the third and fourth switching elements 403 and 404, are expressed by (Equation 3). Where Vbat is the voltage of the smoothing capacitor 9, N1 is the number of turns of the primary winding 6a of the insulating transformer 6, and N2 is the number of turns of the secondary winding 6b of the insulating transformer 6.
- the fourth switching element 404 has an on period only within the on period of the first switching element 401, and the third switching element 403 has an on period only within the on period of the second switching element 402. Therefore, the duty ratios D3 and D4 are always smaller than the duty ratios D1 and D2, and the relationship between t0 to t4 is t0 ⁇ t1 ⁇ t2, t2 ⁇ t3 ⁇ t4 It becomes.
- FIG. 7 shows a schematic duty locus diagram of the duty ratios D1 and D2 of the first leg A and Dlim which is the upper limit of the duty ratio D3 (D4) of the second leg B.
- Dlim is min (D1, D2) in that phase, that is, Dlim is the duty ratio of the smaller of D1 and D2.
- D3 (D4) By making the duty ratio D3 (D4) smaller than Dlim, it is possible to control the voltage Vdc by adjusting the period of the first mode and the third mode, which are the current flow periods to the isolation transformer 6.
- a condition that enables control of the voltage Vdc that is, a controllable condition is represented by the following expression.
- FIG. 8 is a diagram showing the duty ratio D3 (D4) of the second leg B.
- D3 (D4) D3a
- D3 (D4) Dlim
- Dlim is set to the value of Dlim in a phase range in which the calculated value of D3 (D4) is equal to or greater than Dlim.
- D3 (D4) is smaller than Dlim due to the controllable condition.
- the duty ratio D3 (D4) of the third and fourth switching elements 403 and 404 of the second leg B is set to the duty ratio of the first and second switching elements 401 and 402 of the first leg A regardless of the phase. It can be made smaller than the ratios D1 and D2, and the voltage Vdc can be controlled to a constant target voltage Vdc * .
- This voltage control is output power control for controlling the voltage Vdc by controlling the amount of output power.
- current control is performed by duty control of the first leg A
- output power control is performed by duty control of the second leg B. That is, current control and output power control are performed by one inverter circuit 4 having a full bridge configuration. Can be realized.
- a voltage pulsation having a frequency twice as high as the AC frequency is generated in the DC section.
- the generated voltage pulsation is based on the driving cycle T, and is particularly defined by the charging period in the second mode. .
- the capacity of the DC capacitor 5 can be greatly reduced, and the DC capacitor 5 can be downsized.
- the voltage vac and current iac with a power factor of 1 are defined by (Equation 6) and (Equation 7).
- the electric power Pac of the AC power supply 1 is (Equation 8).
- all the electric power Pac shown in (Equation 8) is transmitted to the battery 10.
- the current ibat supplied to the battery 10 is (Equation 9), and has a pulsating component having a frequency twice the AC frequency.
- Vac and Iac are the effective voltage value and effective current value of the AC power supply 1, respectively.
- FIG. 9 is a control block diagram illustrating generation of the duty command of the first leg A by the control circuit 11.
- D1 * and D2 * are duty commands for PWM control of the first and second switching elements 401 and 402.
- the amount of current from the AC power supply 1 is controlled by the duty commands D1 * and D2 * , and the current iac is controlled so that the input power factor from the AC power supply 1 is approximately 1.
- a PI-controlled output 21 is obtained by using a difference 20 between a sine wave current command (target sine wave current) iac * synchronized with the voltage Vac of the AC power supply 1 and the detected current iac as a feedback amount.
- the reference duty command 22 of the second switching element 402 is obtained.
- the feedforward term 23 is added to the reference duty command 22 to obtain the duty command D2 * of the second switching element 402.
- the feedforward term 23 is (Vdc ⁇ vac) / Vdc shown in the above (Equation 2), and is determined for each drive cycle of the inverter circuit 4 according to the phase of the AC power supply 1.
- a value obtained by subtracting the duty command D2 * from 1 is set as the duty command D1 * of the first switching element 401.
- FIG. 10 is a control block diagram illustrating the generation of Dlim which is the duty command upper limit of the second leg B.
- D1 * and D2 * are input to the selector 24 and also to the comparator 25. Based on the comparison signal 25a from the comparator 25, the selector 24 outputs one of D1 * and D2 * as Dlim.
- the comparison signal 25a from the comparator 25 becomes H, and the selector 24 outputs D1 * as Dlim.
- the comparison signal 25a from the comparator 25 becomes L, and the selector 24 outputs D2 * as Dlim.
- FIG. 11 is a control block diagram illustrating generation of the basic duty command of the second leg B.
- D3a * is a command value of the basic duty ratio D3a shown in FIG. 8, that is, a basic duty command.
- This basic duty command D3a * is calculated so as to maintain the voltage Vdc at the target voltage Vdc * by controlling the output electric energy.
- the PI-controlled output is set as an output current command value 31 to the battery 10 with a difference 30 between the target voltage Vdc * of the DC capacitor 5 and the detected voltage Vdc as a feedback amount.
- the gain 33 adjusts the output 33 that is PI-controlled using the difference 32 between the output current command value 31 and the detected current ibat as a feedback amount to generate a basic duty command D3a * .
- FIG. 12 is a control block diagram showing generation of the duty command of the second leg B.
- the basic duty command D3a * and Dlim are input to the selector 35 and also to the comparator 36.
- the selector 35 outputs one of D3a * and Dlim as D3 * based on the comparison signal 36a from the comparator 36.
- D3a * is equal to or greater than the value of Dlim
- the comparison signal 36a from the comparator 36 becomes H, and the selector 35 outputs Dlim as D3 * .
- D3a * is less than the value of Dlim
- the comparison signal 36a from the comparator 36 becomes L, and the selector 35 outputs D3a * as D3 * .
- FIG. 13 is a waveform diagram for explaining generation of the gate signals G1 to G4
- FIG. 14 is a control block diagram showing generation of the gate signals G1 and G2 of the first leg A
- FIG. 15 is a diagram of the second leg B. It is a control block diagram showing generation of gate signals G3 and G4.
- the gate signals G1 to G4 are generated by PWM control using the duty commands of the first leg A and the second leg B and the carrier wave. In this case, the sawtooth wave 38 is used for the carrier wave. .
- D2 * is used as the duty command of the first leg A
- the sawtooth wave 38 used to generate the gate signals G1 to G4 has the same phase and the same value.
- the gate signal generator 39 of the first leg A includes two comparators 39a and 39b, and compares D2 * with the sawtooth wave 38 to generate gate signals G2 and G1, respectively.
- the gate signal G2 becomes H, and the second switching element 402 is turned on.
- the gate signal G1 becomes H, and the first switching element 401 is turned on.
- the gate signal generator 40 that generates the gate signal G3 of the second leg B includes one comparator 40a.
- the gate signal G4 is generated using a gate signal generator 41 including two comparators 41a and 41b and an AND circuit 43.
- the comparator 40a compares D3 * and the sawtooth wave 38 to generate the gate signal G3.
- the gate signal G3 becomes H, and the third switching element 403 is turned on.
- the gate signals G2 and G3 both rise at tt0, that is, the rise of the gate signal pulse is synchronized.
- the comparator 41a compares the sum 42 obtained by adding D2 * and D3 * with the sawtooth wave 38
- the comparator 41b compares the sawtooth wave 38 with D2 * .
- the comparison signals from the two comparators 41a and 41b are input to the AND circuit 43.
- the AND circuit 43 generates a logical product and outputs a gate signal G4.
- the gate signal G4 becomes H only for the pulse width W1 of the gate signal G3 based on D3 * from the timing (tt2) when the sawtooth wave 38 becomes equal to or greater than the value of D2 * , and the fourth switching element 404 is turned on in the period (tt2 to tt3). Turn on.
- the gate signals G1 and G4 both rise at tt2, that is, the rise of the gate signal pulse is synchronized.
- tt0, tt1, tt2, and tt3 in FIG. 13 correspond to t2, t3, t4 (t0), and t1 in FIG. That is, the operation modes in the periods tt0 to tt1, tt1 to tt2, tt2 to tt3, and tt3 to tt4 (t0) are the third mode, the fourth mode, the first mode, and the second mode in order.
- the first leg A is PWM-controlled by adjusting the duty ratios D1 and D2, so that the high power factor control of the current iac flowing from the AC power supply 1 through the rectifier circuit 2 is performed.
- the second leg B is PWM-controlled by adjusting the duty ratio D3 (D4) to a value less than or equal to the duty ratio D1, D2, thereby controlling the voltage Vdc of the DC capacitor 5 to the secondary side of the insulation transformer 6. Controls the output power.
- control circuit 11 performs PWM control on the first leg A and the second leg B with the same synchronized driving cycle T, and the first leg A so that the current iac becomes the current command iac * which is the target sine wave current.
- high power factor control of the current iac and output power control for maintaining the voltage Vdc at the target voltage Vdc * can be realized with high reliability.
- the duty ratios D3 and D4 for controlling the third and fourth switching elements 403 and 404 of the second leg B are controlled to be equal, the magnetic bias of the insulating transformer 6 is suppressed. Furthermore, the duty ratios D3 and D4 are limited to the smaller one of the duty ratios D1 and D2 of the first and second switching elements 401 and 402 as the upper limit Dlim. For this reason, the fourth switching element 404 has an ON period only within the ON period of the first switching element 401, and the third switching element 403 has an ON period only within the ON period of the second switching element 402. Can be controlled to have. For this reason, the period between charging and discharging of the DC capacitor 5 can be reliably controlled, and the voltage Vdc can be reliably controlled to the target voltage Vdc * .
- the sawtooth wave 38 is used as the carrier wave for PWM control of the first leg A and the second leg B, and the rising of the gate signal pulse to the first switching element 401 and the rising of the gate signal pulse to the fourth switching element 404 are performed.
- the gate signals G1 to G4 are generated so as to synchronize the rising edge of the gate signal pulse to the second switching element 402 and the rising edge of the gate signal pulse to the third switching element 403. For this reason, it becomes possible to freely adjust the duty ratio D3 (D4) of the second leg B within the constraints imposed by the high power factor control, and the high power factor control and the output power control can be reliably and independently performed.
- the transmission power quality can be improved, and the output control of the power conversion device with higher reliability can be realized.
- the DC capacitor 5 since the DC capacitor 5 is charged and discharged within the drive cycle T of the inverter circuit 4, the generated voltage pulsation is based on the drive cycle T. For this reason, all of the power pulsation pulsating at a frequency twice that of the AC power supply cycle generated in the AC power supply 1 is transmitted to the secondary battery 10 of the insulation transformer 6, and the power pulsation having a frequency twice that of the AC power supply cycle There is no need to secure it with the DC capacitor 5.
- the DC capacitor 5 only needs to secure charging / discharging due to the drive cycle T of the inverter circuit 4, and can be reduced in size due to a significant capacity reduction.
- the rising edges of the gate signal pulses to the first and fourth switching elements 401 and 404 are synchronized, and the rising edges of the gate signal pulses to the second and third switching elements 402 and 403 are synchronized. Although shown, both may be configured to synchronize the falling edge of the gate signal pulse.
- a dead time for preventing a short circuit may be provided in the switching of the first and second switching elements 401 and 402 of the first leg A.
- a dead time for preventing a short circuit may be provided for the switching of the third and fourth switching elements 403 and 404 of the second leg B.
- the reactor 3 when the reactor 3 is connected to the negative side DC terminal 2b, or when connected to both the positive side DC terminal 2a and the negative side DC terminal 2b of the rectifier circuit 2, the reactor 3 is connected as in the above embodiment.
- the current control is performed by PWM control of the first leg A, and the voltage Vdc of the DC capacitor 5 is controlled by PWM control of the second leg B, thereby obtaining the same effect as the above embodiment. .
- the power conversion device is configured to include the secondary side configuration of the insulating transformer 6, that is, the second rectifier circuit 7, the smoothing reactor 8, and the smoothing capacitor 9.
- the side circuit is not limited to this, and may be omitted in the power conversion device and connected to another device.
- FIG. 16 is a waveform diagram for explaining generation of the gate signals G1 to G4
- FIG. 17 is a control block diagram showing generation of the gate signals G1 and G2 of the first leg A
- FIG. 18 is a diagram of the second leg B. It is a control block diagram showing generation of gate signals G3 and G4.
- the gate signals G1 to G4 are generated by PWM control using the duty commands of the first leg A and the second leg B and the carrier wave.
- the triangular wave 50 is used as the carrier wave.
- D2 * is used as the duty command of the first leg A
- the triangular wave 50 used to generate the gate signals G1 to G4 is the same.
- the gate signal generator 51 of the first leg A includes two comparators 51a and 51b, and compares D2 * and the triangular wave 50, respectively, to generate gate signals G2 and G1.
- the gate signal G2 becomes H, and the second switching element 402 is turned on.
- the gate signal G1 becomes H, and the first switching element 401 is turned on.
- the gate signal generator 52 of the second leg B includes two comparators 52a and 52b.
- the comparator 52a compares D3 * and the triangular wave 50 to generate the gate signal G3.
- the gate signal G3 becomes H, and the third switching element 403 is turned on.
- the center of the gate signal pulse by the gate signals G2 and G3 is synchronized with the peak phase below the triangular wave 50.
- the comparator 52b compares the triangular wave 50 with a duty command (1-D3 * ) that is a value obtained by subtracting D3 * from 1, and generates a gate signal G4.
- the gate signal G4 becomes H, and the fourth switching element 404 is turned on.
- the pulse widths W2 of the gate signal pulses by the gate signals G3 and G4 are equal, and the lengths of the ON periods of the third and fourth switching elements 403 and 404 are the same.
- the center of the gate signal pulse by the gate signals G1 and G4 is synchronized with the peak phase on the triangular wave 50.
- the power conversion apparatus also operates in the four operation modes shown in the first embodiment.
- t0 to t1 is the third mode
- t1 to t2 is the fourth mode
- t2 to t3 is the second mode
- t3 to t4 is the first mode
- t4 to t5 is the second mode
- t5 to t6 is the fourth mode
- t6 to t7 (t0) operates in the third mode.
- the first leg A is PWM-controlled by adjusting the duty ratios D1 and D2, so that the high power factor of the current iac flowing from the AC power supply 1 through the rectifier circuit 2 is increased.
- the second leg B is PWM-controlled by adjusting the duty ratio D3 (D4) to a value equal to or less than the duty ratio D1 and D2, thereby controlling the voltage Vdc of the DC capacitor 5 and the secondary of the isolation transformer 6
- the power output to the side is controlled.
- the triangular wave 50 is used as the carrier wave for PWM control of the first leg A and the second leg B, and the center of the gate signal pulse to the first switching element 401 and the center of the gate signal pulse to the fourth switching element 404 are Are synchronized with the peak phase above the triangular wave 50, and the center of the gate signal pulse to the second switching element 402 and the center of the gate signal pulse to the third switching element 403 are synchronized with the peak phase below the triangular wave 50.
- the gate signals G1 to G4 are generated. For this reason, it becomes possible to freely adjust the duty ratio D3 (D4) of the second leg B within the constraints imposed by the high power factor control, and the high power factor control and the output power control can be reliably and independently performed.
- the transmission power quality can be improved, and the output control of the power conversion device with higher reliability can be realized.
- the total period of the second mode and the fourth mode that is, the period in which power is not transmitted to the insulating transformer 6 is centered on the peak phase of the triangular wave 50 in the driving period T. It becomes symmetric. For this reason, when current flows through the insulating transformer 6 in the first mode and then decreases in the second mode, the amount of current flowing through the fourth switching element 404 and the insulating transformer 6 in the third mode are reduced. When the transformer current decreases in the fourth mode after passing the current, the amount of current flowing through the third switching element 403 becomes equal. Thereby, the loss of the 3rd, 4th switching elements 403 and 404 becomes uniform, a heat dissipation structure can be simplified, and size reduction of a power converter device can be promoted.
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Abstract
Description
充電器用のコンバータ回路は、2つのダイオードより成るハーフブリッジ整流回路と、前記ハーフブリッジ整流回路の両端に並列接続したコンデンサと、夫々2つのスイッチ素子(1)と(2)より成る第1のハーフブリッジ回路および2つのスイッチ素子(3)と(4)より成る第2のハーフブリッジ回路の両端を前記コンデンサの両端に並列接続して構成した4つのスイッチ素子より成るフルブリッジ回路と、上記第1のハーフブリッジ回路におけるスイッチ素子同士の接続点に一端を接続した交流電源の他端とハーフブリッジ整流回路におけるダイオード同士の接続点との間に設けたリアクタと、前記第1と第2のハーフブリッジ回路におけるスイッチ素子同士の接続点との間を接続した高周波トランスの1次コイルと、前記4つのスイッチ素子に接続した4つの駆動回路と制御回路とによってコンバータの1次回路を構成する。制御回路は、4つのスイッチ素子より成るフルブリッジ回路におけるスイッチ素子(1)と(4)より成るグループ、およびスイッチ素子(2)と(3)より成るグループを交互にオン・オフ制御する。
そして、前記高周波トランスの2次コイルに並列接続したフルブリッジ整流回路と、前記フルブリッジ整流回路の両端に並列接続したコンデンサとによってコンバータの2次回路を構成し、前記1次回路において生成された高周波電力を整流してバッテリーを充電させる(例えば、特許文献1参照)。
そして上記制御回路は、上記第1レグのPWM制御により、上記交流電源から上記整流回路を介して流れる回路電流の高力率制御を行い、上記第1レグのduty比以下のduty比を用いた上記第2レグのPWM制御により、上記直流コンデンサの電圧を制御して上記絶縁トランスの二次側に出力する電力を制御する。
以下、この発明の実施の形態1による電力変換装置について説明する。図1はこの発明の実施の形態1による電力変換装置の概略構成図である。
図1に示すように、電力変換装置は、交流電源1の交流電力を直流電力に変換して直流回路であるバッテリ10に出力するための主回路と制御回路11とを備える。
主回路は、交流電源1からの入力を整流する整流回路2と、限流回路としてのリアクトル3と、インバータ回路4と、絶縁トランス6と、第2整流回路7と、第2リアクトルとしての平滑リアクトル8と、平滑コンデンサ9とを備える。
第2整流回路7は、この場合、4つのダイオード701~704をフルブリッジ構成したダイオード整流回路であるが、その他のダイオードを用いた整流方式や能動素子を用いた整流方式でも良い。
また絶縁トランス6の一次側では、交流電源1の出力は整流回路2の交流端子に接続され、整流回路2の正極側直流端子2aはリアクトル3を介してインバータ回路4の第1交流端4aに接続される。整流回路2の負極側直流端子2bは、インバータ回路4の負極側直流母線(以下、N母線)に接続される。
絶縁トランス6の二次側では、平滑コンデンサ9がバッテリ10に並列接続され、第2整流回路7の第1直流出力端子が平滑リアクトル8を介して平滑コンデンサ9の第1端子に接続され、第2整流回路7の第2直流出力端子が平滑コンデンサ9の第2端子に接続される。
なお、第1~第4スイッチング素子401~404は、IGBT以外でも、ソース・ドレイン間にダイオードが内蔵されたMOSFET(Metal Oxide Semiconductor Field Effect Transistor)等の半導体スイッチング素子でもよい。またMOSFETを用いる場合は、内蔵ダイオードをダイオード401a~404aに用いても良い。
さらに、直流回路は、バッテリ10の他、交流電源1からの入力と絶縁を必要とする直流負荷であれば良く、例えば電気2重層キャパシタなどで構成してもよい。
図2は、第1~第4スイッチング素子401~404へのゲート信号G1~G4と、電流iacと、直流コンデンサ5の電圧Vdcとを示す図である。なお、直流コンデンサ5の電圧Vdcは、目標電圧Vdc*を、交流電源1の電圧Vacのピーク電圧Vpより高く設定し、ピーク電圧Vpより高く制御されている。
交流電源1からの電圧Vacは整流回路2で全波整流されるため、交流周期の2倍周期で動作する。ゲート信号G1、G2により動作する第1レグAの第1、第2スイッチング素子401、402は、交流電源1からの入力電流量を一定に、かつ入力力率が概1になるようにPWM制御により電流iacを制御する。またゲート信号G3、G4により動作する第2レグBの第3、第4スイッチング素子403、404は、バッテリ10に供給する電力量と直流コンデンサ5の充放電量を調整して直流コンデンサ5の電圧Vdcが一定の目標電圧Vdc*になるように制御する。以下、交流電源1からの入力力率が概1になるように電流iacを制御することを、単に電流制御と称す。
t0(=t4)の時、ゲート信号G1で動作する第1スイッチング素子401がオンしてゲート信号G2で動作する第2スイッチング素子402がオフする。この時、ゲート信号G4で動作する第4スイッチング素子404も同時にオンする。
t1の時、第4スイッチング素子404がオフする。
t2の時、第1スイッチング素子401がオフして第2スイッチング素子402がオンする。この時、ゲート信号G3で動作する第3スイッチング素子403も同時にオンする。
t3の時、第3スイッチング素子403がオフする。
t0~t1における第1モードでは、第1、第4スイッチング素子401、404が共にオン状態で、図3に示す電流経路で電流が流れる。即ち、リアクトル3に流れる電流iacは、絶縁トランス6の一次巻線6aに流れ、第4スイッチング素子404を介して入力側へ戻る。また直流コンデンサ5から第1スイッチング素子401を介して一次巻線6aへ電流が流れ、第4スイッチング素子404を介して直流コンデンサ5へと電流が戻る。
この第1モードでは、第1スイッチング素子401がオン状態であるため、リアクトル3のインバータ回路4側の電位は電圧Vdcに固定される。直流コンデンサ5の電圧Vdcは、交流電源1の電圧Vacのピーク電圧Vpより高く制御され、リアクトル3に流れる電流iacは減少する。また直流コンデンサ5では電流を放電しているため電圧Vdcは減少する。
この第2モードでは、第1スイッチング素子401がオン状態であるため、リアクトル3のインバータ回路4側の電位は電圧Vdcに固定される。直流コンデンサ5の電圧Vdcは、交流電源1の電圧Vacのピーク電圧Vpより高く制御され、リアクトル3に流れる電流iacは減少する。また直流コンデンサ5では電流を充電しているため電圧Vdcは増加する。
この第3モードでは、第2スイッチング素子402がオン状態であるため、リアクトル3のインバータ回路4側の電位はN母線の電位0に固定され、リアクトル3に流れる電流iacは増加する。また直流コンデンサ5では電流を放電しているため電圧Vdcは減少する。
この第4モードでは、第2スイッチング素子402がオン状態であるため、リアクトル3のインバータ回路4側の電位はN母線の電位0に固定され、リアクトル3に流れる電流iacは増加する。また直流コンデンサ5では電流の充放電がなく電圧Vdcは変化しない。
なお、第1モードと第3モードとで絶縁トランス6に逆極性に電流が流れるため、絶縁トランス6の偏磁を抑制するために、第1モードと第3モードとの期間は等しく設定する。即ち、第4スイッチング素子404のオン期間と第3スイッチング素子403のオン期間とは等しく、duty比は等しく制御される。
D2=(Vdc-vac)/Vdc ・・・(式2)
t0≦t1≦t2、t2≦t3≦t4
となる。
図7に示すように、D1は交流電圧のゼロクロス位相0、πで0となり、位相π/2ではピーク値となる。このため、位相0、πの付近ではDlim=D1となる。この場合、位相π/2付近では、D2<D1であり、Dlim=D2となる。
また、位相π/2の時のDlimの値Dαは、(式4)で表される。但し、Vpは交流電圧Vacのピーク電圧である。
D3(D4)<Dα
即ち、
(1/2)・(Vbat/Vdc)・(N2/N1)
<min(Vp/Vdc,(Vdc-Vp)/Vdc) ・・・(式5)
D3a<Dlimのとき、D3(D4)=D3a
D3a≧Dlimのとき、D3(D4)=Dlim
とする。
交流電圧のゼロクロス位相0、πの付近ではDlimが原理上限りなく0に近い。このため、D3(D4)の演算値がDlim以上となる位相範囲でD3(D4)をDlimの値に設定する。それ以外の位相範囲では、上記可制御条件から、D3(D4)はDlimより小さい。これにより、全位相においてduty比D3(D4)をDlimより小さくでき、電圧Vdcを制御できる。
これにより、第1レグAのduty制御により電流制御を行い、第2レグBのduty制御により出力電力制御を行い、即ち、電流制御と出力電力制御とをフルブリッジ構成の1つのインバータ回路4で実現することができる。
iac=(√2)Iac・sin(ωt) ・・・(式7)
Pac=Vac・Iac(1-cos(2ωt)) ・・・(式8)
ibat=(Vac/Vbat)・Iac(1-cos(2ωt)) ・・・(式9)
図9は、制御回路11による第1レグAのduty指令の生成を示す制御ブロック図である。D1*、D2*は、第1、第2スイッチング素子401、402をPWM制御する為のduty指令である。このduty指令D1*、D2*により、交流電源1からの電流量を制御し、交流電源1からの入力力率が概1になるように電流iacを制御する。
D2*がD1*の値以上である時、比較器25からの比較信号25aはHとなり、選択器24はD1*をDlimとして出力する。D2*がD1*の値未満である時、比較器25からの比較信号25aはLとなり、選択器24はD2*をDlimとして出力する。
図11に示すように、直流コンデンサ5の目標電圧Vdc*と検出された電圧Vdcとの差30をフィードバック量として、PI制御した出力をバッテリ10への出力電流指令値31とする。この出力電流指令値31と検出された電流ibatとの差分32をフィードバック量としてPI制御した出力33を、ゲイン調整器34にて調整して、基本duty指令D3a*を生成する。
図12に示すように、基本duty指令D3a*とDlimとは、選択器35に入力されると共に、比較器36にも入力される。選択器35は、比較器36からの比較信号36aに基づいてD3a*、Dlimのいずれか一方をD3*として出力する。
D3a*がDlimの値以上である時、比較器36からの比較信号36aはHとなり、選択器35はDlimをD3*として出力する。D3a*がDlimの値未満である時、比較器36からの比較信号36aはLとなり、選択器35はD3a*をD3*として出力する。
図13に示すように、ゲート信号G1~G4は、第1レグA、第2レグBのduty指令とキャリア波とを用いたPWM制御により生成され、この場合、キャリア波に鋸波38を用いる。第1レグAのduty指令としてD2*を用い、第2レグBのduty指令はD3*(=D4*)を用いる。なお、各ゲート信号G1~G4の生成に用いる鋸波38は、同位相、同じ値の波形である。
D2*が鋸波38の値以上の期間(tt0~tt2)で、ゲート信号G2はHとなり、第2スイッチング素子402をオン状態にする。また、鋸波38の値がD2*以上の期間(tt2~tt4(=tt0))で、ゲート信号G1はHとなり、第1スイッチング素子401をオン状態にする。
ゲート信号G3を生成するゲート信号生成器40では、比較器40aがD3*と鋸波38とを比較してゲート信号G3を生成する。D3*が鋸波38の値以上の期間(tt0~tt1)で、ゲート信号G3はHとなり、第3スイッチング素子403をオン状態にする。また、ゲート信号G2、G3は共にtt0で立ち上がり、即ち、ゲート信号パルスの立ち上がりが同期する。
以下、この発明の実施の形態2による電力変換装置について説明する。上記実施の形態1では、インバータ回路4のPWM制御のキャリア波に鋸波38を用いたが、この実施の形態2では、キャリア波に三角波を用いる。この実施の形態2による電力変換装置は、主回路構成および各duty指令D1*~D4*の生成については、上記実施の形態1と同様である。
この実施の形態2におけるインバータ回路4の第1~第4スイッチング素子401~404を制御するゲート信号G1~G4の生成について、図16~図18に基づいて以下に説明する。図16は、ゲート信号G1~G4の生成を説明する波形図であり、図17は、第1レグAのゲート信号G1、G2の生成を示す制御ブロック図、図18は、第2レグBのゲート信号G3、G4の生成を示す制御ブロック図である。
D2*が三角波50の値以上の期間(t0~t2、t5~t7(t0))で、ゲート信号G2はHとなり、第2スイッチング素子402をオン状態にする。また、三角波50の値がD2*以上の期間(t2~t5)で、ゲート信号G1はHとなり、第1スイッチング素子401をオン状態にする。
比較器52bは、三角波50と、1からD3*を減算した値であるduty指令(1-D3*)とを比較してゲート信号G4を生成する。三角波50が(1-D3*)以上の期間(t3~t4)で、ゲート信号G4はHとなり、第4スイッチング素子404をオン状態にする。ゲート信号G3、G4によるゲート信号パルスのパルス幅W2は等しく、第3、第4スイッチング素子403、404のオン期間の長さは同じである。また、ゲート信号G1、G4によるゲート信号パルスの中心は、三角波50の上のピーク位相で同期する。
Claims (8)
- 複数のダイオードがフルブリッジ構成され、交流電源からの入力を整流する整流回路と、
上記整流回路の直流端子に接続されるリアクトルと、
第1スイッチング素子および第2スイッチング素子が直列接続され、その接続点を第1交流端とする第1レグと、第3スイッチング素子および第4スイッチング素子が直列接続され、その接続点を第2交流端とする第2レグと、直流コンデンサとが直流母線間に並列接続されて構成され、上記第1交流端が上記整流回路の正極側直流端子に接続され、負極側直流母線が上記整流回路の負極側直流端子に接続されるインバータ回路と、
一次巻線、二次巻線を有し、該一次巻線の両端に上記インバータ回路の上記第1交流端、上記第2交流端が接続される絶縁トランスと、
上記インバータ回路を出力制御する制御回路とを備え、
上記制御回路は、上記第1レグのPWM制御により、上記交流電源から上記整流回路を介して流れる回路電流の高力率制御を行い、上記第1レグのduty比以下のduty比を用いた上記第2レグのPWM制御により、上記直流コンデンサの電圧を制御して上記絶縁トランスの二次側に出力する電力を制御する
電力変換装置。 - 上記絶縁トランスの上記二次巻線に接続される第2整流回路と、該第2整流回路の直流端子に接続される第2リアクトルとを備え、
上記制御回路は、上記第2レグをPWM制御することにより上記第2整流回路に接続される直流回路への出力電力を制御する
請求項1に記載の電力変換装置。 - 上記制御回路は、
上記第1レグおよび上記第2レグを、同期する等しい駆動周期でPWM制御し、
上記回路電流が目標正弦波電流になるように上記第1レグを制御し、
上記直流コンデンサの電圧が、上記交流電源のピーク電圧よりも高い目標電圧になるように上記第2レグを制御する
請求項1または請求項2に記載の電力変換装置。 - 上記制御回路は、上記第3スイッチング素子および上記第4スイッチング素子のduty比を等しくし、該duty比を、上記第1、第2スイッチング素子の2つのduty比内の小さい方を上限として制限する
請求項3に記載の電力変換装置。 - 上記制御回路は、
上記第1スイッチング素子とオンオフが反転するように上記第2スイッチング素子を制御し、
上記第1スイッチング素子と対角の関係にある上記第4スイッチング素子を、上記第1スイッチング素子のオン期間内のみにオン期間を有するように制御し、
上記第2スイッチング素子と対角の関係にある上記第3スイッチング素子を、上記第2スイッチング素子のオン期間内のみにオン期間を有するように制御する
請求項3または請求項4に記載の電力変換装置。 - 上記制御回路は、
上記第1レグ、上記第2レグのPWM制御のキャリア波に鋸波を用い、
上記第1スイッチング素子へのゲート信号パルスの立ち上がりと、上記第4スイッチング素子へのゲート信号パルスの立ち上がりとを同期させ、
上記第2スイッチング素子へのゲート信号パルスの立ち上がりと、上記第3スイッチング素子へのゲート信号パルスの立ち上がりとを同期させる
請求項5に記載の電力変換装置。 - 上記制御回路は、
上記第1レグ、上記第2レグのPWM制御のキャリア波に三角波を用い、
上記第1スイッチング素子へのゲート信号パルスの中心と、上記第4スイッチング素子へのゲート信号パルスの中心とを同期させ、
上記第2スイッチング素子へのゲート信号パルスの中心と、上記第3スイッチング素子へのゲート信号パルスの中心とを同期させる
請求項5に記載の電力変換装置。 - 上記制御回路は、
上記第3、第4スイッチング素子の一方の素子へのduty比の指令値を生成し、該duty比の指令値と上記三角波との比較により上記一方の素子への上記ゲート信号パルスを生成し、
上記duty比の指令値を1から差し引いた値と上記三角波との比較により、上記第3、第4スイッチング素子の他方の素子への上記ゲート信号パルスを生成する
請求項7に記載の電力変換装置。
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US15/129,945 US10044278B2 (en) | 2014-05-15 | 2015-03-06 | Power conversion device |
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