WO2015143980A1 - 电荷泵的实现电路 - Google Patents

电荷泵的实现电路 Download PDF

Info

Publication number
WO2015143980A1
WO2015143980A1 PCT/CN2015/073742 CN2015073742W WO2015143980A1 WO 2015143980 A1 WO2015143980 A1 WO 2015143980A1 CN 2015073742 W CN2015073742 W CN 2015073742W WO 2015143980 A1 WO2015143980 A1 WO 2015143980A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
current mirror
gain amplifier
voltage
unity gain
Prior art date
Application number
PCT/CN2015/073742
Other languages
English (en)
French (fr)
Inventor
宋利军
张玉龙
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Publication of WO2015143980A1 publication Critical patent/WO2015143980A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
    • H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers

Definitions

  • Embodiments of the present invention relate to communication technologies, and in particular, to an implementation circuit of a charge pump.
  • the working steps of the half-sampling phase-locked loop (PLL) shown in Figure 1 are as follows: First, enter the Frequency Locked Loop (FLL) mode in Figure 1 to lock the PLL in The required frequency point is then switched to the Core Loop, and a Sub Sampling Phase Detector (SSPD) is used to lock the PLL to the desired phase.
  • SSPD Sub Sampling Phase Detector
  • CP charge pump
  • the implementation structure of the existing CP can be as shown in FIG. 2, the input signal is collected through the reference clock (REF), and the acquired differential signal is acquired ( versus The voltage difference signal between them is converted into a current Icp by the CP.
  • Iup Idn
  • Idn The current signal mirrored by the corresponding current mirror.
  • LPF Low Pass Filter
  • Embodiments of the present invention provide a circuit for implementing a charge pump to avoid the problems of charge sharing and charge injection effects caused by the charge pump in the prior art.
  • the present invention provides a charge pump implementation circuit including: a first current mirror, a second current mirror, a first switch circuit, a second switch circuit, a connection circuit, a first unity gain amplifier, and a second unity gain An amplifier and a pulse generating circuit;
  • the output end of the first current mirror and the output end of the second current mirror are both connected to a source of the first switching circuit and a source of the second switching circuit;
  • the first unity gain amplifier a first end connected to the output end of the first current mirror and an output end of the second current mirror, the second end of the first unity gain amplifier being connected to the connection circuit;
  • the second unity gain amplifier The first end is connected to the input end of the low pass filter LPF, the second end of the second unit gain amplifier is connected to the connection circuit; the input end of the LPF is connected to the drain of the second switch circuit;
  • An output of the pulse generating circuit is connected to a gate of the first switching circuit and a gate of the second switching circuit;
  • connection circuit includes a first capacitor and a first switching transistor for connecting the first gain amplifier and the second gain amplifier;
  • the first current mirror is configured to mirror a first voltage outputted by the voltage controlled oscillator VCO as a first current
  • the second current mirror is configured to mirror the second voltage output by the VCO as a second current
  • the pulse generating circuit is configured to generate a pulse signal according to a reference clock signal, where the pulse signal is used to control a switching state of the first switching circuit and the second switching circuit;
  • the first unity gain amplifier and the second unity gain amplifier are configured to: when the reference clock signal is low, the voltage of the output end of the first current mirror and the output end of the second current mirror The voltage, the voltage at the LPF input, and the drain voltage of the first switch remain the same.
  • the first end of the first unit gain amplifier is connected to an output end of the first current mirror and an output end of the second current mirror
  • the second end of the first unity gain amplifier is connected to the connection circuit, and includes:
  • the first end of the first unity gain amplifier is connected to the first through a third switching circuit An output of a current mirror;
  • the first end of the first unity gain amplifier is connected to the output end of the second current mirror through a fourth switching circuit
  • the second end of the first unity gain amplifier is coupled to the drain of the first switching transistor.
  • the second end of the second unit gain amplifier is connected to the connecting circuit, including:
  • the second end of the second unity gain amplifier is coupled to the drain of the first switching transistor.
  • the drain of the first switching circuit is grounded through the second capacitor.
  • the pulse generating circuit includes a delay unit; a unit for generating a fixed delay time;
  • the pulse generating circuit is configured to delay the reference clock signal according to the fixed delay time generated by the delay unit, and delay the reference clock signal with a delay before The pulse signal is generated after a logical AND operation of the reference clock signal.
  • the delay unit includes a third current mirror, a second switch tube, a third switch tube, and a fourth a switch tube and a third capacitor;
  • An output end of the third current mirror is connected to a source of the second switch tube; a drain of the second switch tube is connected to a drain of the third switch tube, and one end of the third capacitor Connected to the drain of the second switch tube and the drain of the third switch tube, the other end of the third capacitor is connected to the source of the fourth switch tube; the second switch tube a gate and a gate of the third switching transistor are connected to an output end of the reference clock; a source of the third switching transistor is connected to a drain of the fourth switching transistor; a gate of the fourth opening transistor Connecting a bias voltage output terminal;
  • the third current mirror is configured to mirror a bias voltage of the system into a third current and output from an output end of the third current mirror.
  • the implementation of the charge pump provided by the embodiment of the present invention maintains the voltage of the output end of the first current mirror, the voltage of the output end of the second current mirror, and the voltage of the input end of the LPF by the first unity gain amplifier and the second unity gain amplifier. , making the pulse signal turn from low level
  • the second switch circuit is switched from the off state to the on state, no charge flows into the LPF, which avoids the charge injection effect and improves the performance of the PLL.
  • FIG. 1 is a schematic structural view of a half sampling type phase locked loop provided by the present invention.
  • FIG. 2 is a circuit diagram of an implementation of a charge pump in the prior art
  • Embodiment 3 is a schematic structural view of Embodiment 1 of an implementation circuit of a charge pump according to the present invention
  • FIG. 4 is a schematic structural diagram of a pulse generating circuit provided by the present invention.
  • FIG. 5 is a schematic structural diagram of a circuit of a delay unit provided by the present invention.
  • 16 second unity gain amplifier
  • 17 pulse generation circuit
  • 18 low pass filter
  • 152 a second end of the first unity gain amplifier
  • 181 an input end of the low pass filter
  • 132 a gate of the second switching circuit; 141: a first capacitor; 142: a first switching transistor;
  • 203 a third switch tube; 204: a third capacitor; 301: an output end of the third current mirror;
  • 312 a source of the fourth switching transistor; 313: a drain of the fourth switching transistor;
  • 314 the gate of the fourth light-emitting tube
  • 315 the bias voltage output terminal
  • FIG. 3 is a schematic structural diagram of Embodiment 1 of an implementation circuit of a charge pump according to the present invention. As shown in FIG. 3, the circuit includes: a first current mirror 10, a second current mirror 11, a first switch circuit 12, a second switch circuit 13, a connection circuit 14, a first unity gain amplifier 15, and a second unity gain amplifier. 16 and pulse generating circuit 17.
  • the output end 101 of the first current mirror 10 and the output end 111 of the second current mirror 11 are both connected to the source 122 of the first switch circuit 12 and the source 133 of the second switch circuit 13.
  • the first end 151 of the first unity gain amplifier 15 is connected to the first current mirror
  • An output terminal 101 of the 10 and an output end 111 of the second current mirror 11, a second end 152 of the first unity gain amplifier 15 is connected to the connection circuit 14;
  • a first end of the second unity gain amplifier 16 161 is connected to the input end 181 of the LPF 18, the second end 162 of the second unity gain amplifier 16 is connected to the connection circuit 14;
  • the input end 181 of the LPF 18 is connected to the drain 131 of the second switch circuit 13;
  • An output terminal 171 of the pulse generating circuit 17 is connected to the gate 121 of the first switching circuit 12 and the gate 132 of the second switching circuit 13;
  • the connecting circuit 14 includes a first capacitor 141 and a first switching transistor 142, configured to connect the first gain amplifier 15 and
  • the second voltage for outputting the VCO 19 is mirrored as a second current;
  • the pulse generating circuit 17 is configured to generate a pulse generating signal according to the reference clock signal, where the pulse signal is used to control the first switching circuit 12 and opening of the second switching circuit 13
  • the first unity gain amplifier 15 and the second unity gain amplifier 16 are configured to: when the reference clock signal is low, the voltage of the output end 101 of the first current mirror 10, the first The voltage of the output terminal 111 of the two current mirrors 11, the voltage of the input terminal 181 of the LPF 18, and the drain voltage of the first switching transistor 142 remain equal.
  • the embodiment of the present invention is only a simple illustration, as long as it is ensured that the two voltages outputted by the VCO 19 can be mirrored as Iup or Idn, respectively, and input to the first switching circuit 12 and the second switching circuit 13, and
  • the pulse signal generated by the pulse generating circuit 17 can control the switching states of the first switching circuit 12 and the second switching circuit 13.
  • the first switching circuit 12 and the second switching circuit are not shown in FIG. 3, and the first switching circuit and the second switching circuit indicated in FIG. 2 can be referred to.
  • the VCO 19 outputs a first voltage and a second voltage; the first voltage here may be Can also be The second voltage can be Can also be When the first voltage is When the second voltage is When the first voltage is When the second voltage is In the embodiment of the present invention, the first voltage is assumed to be The second voltage is The first current mirror 10 mirrors the first voltage as Iup, and the second current mirror 11 mirrors the second voltage as Idn.
  • the output terminal 101 of the first current mirror 10 is actually the drain of the first current mirror 10, that is, Iup is output from the drain of the first current mirror 10; correspondingly, Idn is output from the drain of the second current mirror 11 .
  • the pulse generating circuit 17 shown in Fig. 3 is only a logic circuit diagram, and its specific implementation can be seen in Fig. 4 (the delay unit 20 in Fig. 4 will be described later in this embodiment).
  • the pulse generating circuit 17 performs a logical AND operation according to the reference clock signal and the delayed reference clock signal to form a pulse signal (Pul), which can control the opening of the first switching circuit 12 and the second switching circuit 13 or Disabled.
  • Pul pulse signal
  • the connection manner of the two MOS transistors in the first switching circuit 12 and the second switching circuit 13 can be referred to the prior art.
  • the pulse signal is output to the gate 121 of the first switching circuit 12 and the gate 132 of the second switching circuit 13 via the output terminal 171 of the pulse generating circuit 17, and when the level of the pulse signal is low, the first switching circuit 12
  • the input signal of the entire CP is the oscillation signal of the VCO 19, that is, the voltage difference between the first voltage and the second voltage, and the voltage difference processes the changing state. That is, the first voltage and the second voltage are not equal and are not equal to the voltage at the input of the LPF 18. That is, the drain voltage of the first current mirror 10, the drain voltage of the second current mirror 11, and the voltage of the input terminal 181 of the LPF 18 are not equal to each other.
  • the output terminal 101 of the first current mirror 10 ie, the drain of the first current mirror 10
  • the output terminal 111 of the second current mirror 11 ie, the drain of the second current mirror 11
  • the connection circuit 14 the connection circuit 14.
  • the voltage at the first terminal 151 of the first unity gain amplifier 15 is equal to the voltage of the second terminal 152 of the first unity gain amplifier 15; again due to the first unity gain amplifier 15
  • the two ends 152 are connected to the connection circuit 14, so the second end 152 of the first unity gain amplifier 15
  • the voltage is equal to the drain voltage of the first switching transistor 142 in the connection circuit 14; that is, the voltage of the first terminal 151 of the first unity gain amplifier 15 is equal to the drain voltage of the first switching transistor 142, and
  • An output 101 of the current mirror 10 and an output 111 of the second current mirror 11 are connected to the first end 151 of the first unity gain amplifier 15, so that the voltage of the output 101 of the first current mirror 10 and the second current mirror
  • the voltage at the output 111 of 11 is also equal to the drain voltage of the first switching transistor 142.
  • the input terminal 181 of the LPF 18 (ie, the port where Icp is located) is connected to the first terminal 161 of the second unity gain amplifier 16, and the first unity gain amplifier 15 and the second unity gain amplifier 16 are connected by the connection circuit 14, The second end 162 of the second unity gain amplifier 16 is coupled to the connection circuit 14.
  • the voltage at the first terminal 161 of the second unity gain amplifier 16 is equal to the voltage of the second terminal 162 of the second unity gain amplifier 16; again due to the second unity gain amplifier 16
  • the second terminal 162 is connected to the connection circuit 14, so that the voltage of the second terminal 162 of the second unity gain amplifier 16 is equal to the drain voltage of the first switching transistor 142 in the connection circuit 14; that is, the second unity gain amplifier 16
  • the voltage of the first terminal 161 is equal to the drain voltage of the first switching transistor 142, and since the first terminal 161 of the second unity gain amplifier 16 is connected to the input terminal 181 of the LPF 18 (ie, the port where Icp is located), the LPF 18
  • the voltage of the input terminal 181 is also equal to the drain voltage of the first switching transistor 142.
  • the embodiment of the present invention can pass the voltage of the output terminal 101 of the first current mirror 10, the voltage of the output terminal 111 of the second current mirror 11 and the input end of the LPF 18 through the first unity gain amplifier 15 and the second unity gain amplifier 16.
  • the voltages of 181 are converted to be equal (ie, such that all three are equal to the drain voltage of the first switching transistor 142), that is, there is no voltage difference between the three, so that when the pulse signal is high, the second switch
  • no current flows into the LPF 18, that is, no charge is injected into the LPF 18, thereby ensuring the performance of the PLL.
  • the implementation of the charge pump provided by the embodiment of the present invention maintains the voltage of the output end of the first current mirror, the voltage of the output end of the second current mirror, and the voltage of the input end of the LPF by the first unity gain amplifier and the second unity gain amplifier. Therefore, the pulse signal is converted from a low level to a high level, and when the second switch circuit is switched from the off state to the on state, no charge flows into the LPF, thereby avoiding a charge injection effect and improving the performance of the PLL.
  • the first end 151 of the first unity gain amplifier 15 is connected to the output end 101 of the first current mirror 10 and the output end 111 of the second current mirror 11, which may be:
  • the first end 151 of the gain amplifier 15 can be connected to the output terminal 101 of the first current mirror 10 through the third switching circuit 30.
  • the first end 151 of the first unity gain amplifier 15 can pass through the fourth switching circuit 31 and the second current mirror.
  • the output terminal 111 of the 11 is connected, and the second terminal 152 of the first unity gain amplifier 15 is connected to the connection circuit 14.
  • the second end 152 of the first unity gain amplifier 15 and the second end 162 of the second unity gain amplifier 16 are connected to the connection circuit 14, specifically, the first unity gain amplifier 15
  • the second terminal 152 is connected to the drain of the first switching transistor 142 of the connection circuit 14, and the second terminal 162 of the second unity gain amplifier 16 is connected to the drain of the first switching transistor 142, thereby implementing the first unity gain amplifier 15 Connection to the second unity gain amplifier 16.
  • the drain 123 of the first switch circuit 12 is grounded through the second capacitor 143, and the second capacitor is not shown in FIG. 3, and the second capacitor shown in FIG. 2 can be referred to.
  • the implementation of the charge pump provided by the embodiment of the present invention maintains the voltage of the output end of the first current mirror, the voltage of the output end of the second current mirror, and the voltage of the input end of the LPF by the first unity gain amplifier and the second unity gain amplifier. Therefore, the pulse signal is converted from a low level to a high level, and when the second switch circuit is switched from the off state to the on state, no charge flows into the LPF, thereby avoiding a charge injection effect and improving the performance of the PLL.
  • the generation of the pulse signal requires the reference clock signal and the delayed reference clock signal to perform logical AND operation.
  • the pulse generating circuit 17 of the prior art also adopts the connection mode of FIG.
  • the pulse signal is generated, but the delay of the reference clock signal in the prior art is cascaded by a common inverter.
  • the delay of the inverter is easy to change under different processes, different voltages or different temperatures. Therefore, the width of the generated pulse signal varies greatly, which affects the stability of the system parameters of the entire PLL, thereby affecting the performance of the PLL.
  • the pulse generating circuit 17 can generate a fixed delay time, which does not change according to changes in the external environment, and the pulse generating circuit 17 generates according to the delay unit 20.
  • the fixed delay time delays the reference clock signal, and logically ANDes the delayed reference clock signal with the reference clock signal before the delay to generate a pulse signal.
  • the specific implementation circuit of the delay unit 20 can be referred to the following Figure 5.
  • the delay unit 20 includes: a third current mirror 201, a second switch tube 202, a third switch tube 203, a fourth switch tube 311, and a third capacitor 204; wherein the third current mirror
  • the output end 301 of the second switch tube 202 is connected to the source 302 of the second switch tube 202; the drain 303 of the second switch tube 202 is connected to the drain 304 of the third switch tube 203, the third capacitor
  • One end 305 of the second switch tube 202 is connected to the drain 303 of the second switch tube 202 and the drain 304 of the third switch tube 203.
  • the other end 306 of the third capacitor 204 and the fourth switch tube 311 are connected.
  • the source 312 is connected; the gate 307 of the second switch 202 and the gate 308 of the third switch 203 are connected to the output terminal 309 of the reference clock; the source 310 of the third switch 203 Connected to the drain 313 of the fourth switch 311; the gate 314 of the fourth open transistor 311 is connected to the bias voltage output 315; the third current mirror 201 is used to mirror the bias voltage of the system. Three currents are output from the output terminal 301 of the third current mirror 201.
  • the circuit system provides a fixed bias voltage that is mirrored by the third current mirror 201 as a third current from the output terminal 301 of the third current mirror 201 (ie, the drain of the third current mirror 201). ) Output.
  • the output terminal 309 of the reference clock outputs a reference clock signal (ie, an external reference clock).
  • the second switch transistor 202 is turned on (the second switch transistor 202 is a PMOS transistor).
  • the third current charges the third capacitor 204 via the second switch 202; when the reference clock signal is switched to the high level, the third switch 203 is turned on (the third switch 203 is an NMOS transistor), and the third capacitor 204 is The third switch tube 203 and the fourth switch tube 311 discharge (the fourth switch tube 311 provides a constant current when the third capacitor 204 is discharged).
  • the discharge time is the delay time of the delay unit 20.
  • the second switch tube 202 can also be an NMOS tube
  • the third switch tube 203 can also be a PMOS tube, but the level of the reference clock signal should also be switched accordingly, that is, the level of the reference clock signal should be first high. After the low. It should be noted that the case where the two delay units 20 shown in FIG. 5 are cascaded.
  • the third current is fixed, so that the amount of stored charge of the third capacitor 204 during charging is fixed; and the fourth switch tube 311 can provide a constant discharge current, and therefore, the third capacitor 204 performs
  • the time of discharge is also fixed, so that the delay time of the delay unit 20 is fixed, so that the variation range of the width of the pulse signal generated by the pulse generating circuit 17 is reduced, that is, the width variation of the pulse signal is reduced.
  • the implementation of the charge pump provided by the embodiment of the present invention maintains the voltage of the output end of the first current mirror, the voltage of the output end of the second current mirror, and the voltage of the input end of the LPF by the first unity gain amplifier and the second unity gain amplifier. Therefore, the pulse signal is converted from a low level to a high level, and when the second switching circuit is switched from the off state to the on state, no charge flows into the LPF to avoid the charge injection effect; in addition, the delay unit generates a fixed The delay time reduces the variation of the width of the pulse signal outputted by the pulse generating circuit, ensures the stability of the PLL system, and improves the performance of the PLL.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

一种电荷泵的实现电路，该电路包括：第一电流镜（10）、第二电流镜（11）、第一开关电路（12）、第二开关电路（13）、连接电路（14）、第一单位增益放大器（15）、第二单位增益放大器（16）和脉冲产生电路（17）。其中，第一电流镜（10），用于将VCO（19）输出的第一电压镜像为第一电流；第二电流镜（11），用于将VCO（19）输出的第二电压镜像为第二电流；脉冲产生电路（17），用于根据参考时钟信号生成脉冲信号，脉冲信号用于控制所述第一开关电路（12）和第二开关电路（13）的开关状态；第一单位增益放大器（15）和第二单位增益放大器（16），用于在参考时钟信号为低电平时，将第一电流镜（10）的输出端的电压、第二电流镜（11）的输出端的电压、LPF（18）输入端的电压以及第一开关管（142）的漏极电压保持相等，从而避免产生电荷注入效应，提高了PLL的性能。

Description

电荷泵的实现电路 技术领域
本发明实施例涉及通信技术，尤其涉及一种电荷泵的实现电路。
背景技术
如图1所示的半采样型锁相环(Phase Locked Loop，以下简称PLL)的工作步骤如下:首先进入图1中的锁频环(Frequency Locked Loop，以下简称FLL)模式，使PLL锁定在所需要的频率点，然后切换到核心环(Core Loop)，采用半采样型鉴相器(Sub Sampling Phase Detector，以下简称SSPD)，使PLL锁定在需要的相位上。为了使半采样型锁相环具有较好的性能，则需要有一个较好的电荷泵(Charge Pump，以下简称CP)来实现电压到电流的转换。
现有的CP的实现结构可以如图2所示的结构，通过参考时钟(REF)采集输入进来的信号，并将采集的差分信号(
Figure PCTCN2015073742-appb-000001
与
Figure PCTCN2015073742-appb-000002
间的电压差信号)通过CP转换成电流Icp。当采样的差分信号幅度为零时，Iup＝Idn，那么Icp的电流为零；其中，Iup为图2中
Figure PCTCN2015073742-appb-000003
通过对应的电流镜镜像过来的电流信号，Idn为图2中
Figure PCTCN2015073742-appb-000004
通过对应的电流镜镜像过来的电流信号。当Icp的电流为零时，LPF的电压保持不变，从而使压控振荡器(Voltage controlled Oscillator，以下简称VCO)的振荡频率不变，PLL处于锁定状态。当REF为低电平时，CP输入信号是VCO的振荡信号(即
Figure PCTCN2015073742-appb-000005
与
Figure PCTCN2015073742-appb-000006
间的电压差信号)，在一段时间内，脉冲信号Pul＝0，这样Icp左侧的开关电路中的第一路开关(左边)打开，第二路开关关闭；当REF＝1，且Pul＝1时，Icp左侧的开关电路中的第二路开关(右边)打开。
但是，现有技术中，当REF从低电平切换至高电平时，会有电荷经过Icp流入到低通滤波器(Low Pass Filter，以下简称LPF)，即会产生电荷共享和电荷注入效应，使LPF上的电压产生周期性的纹波，导致LPF电压变化，从而影响PLL的性能。
发明内容
本发明实施例提供一种电荷泵的实现电路，用以避免现有技术中的电荷泵带来的电荷共享和电荷注入效应的问题。
第一方面，本发明提供一种电荷泵的实现电路，包括：第一电流镜、第二电流镜、第一开关电路、第二开关电路、连接电路、第一单位增益放大器、第二单位增益放大器和脉冲产生电路；
其中，所述第一电流镜的输出端和所述第二电流镜的输出端均连接所述第一开关电路的源极和所述第二开关电路的源极；所述第一单位增益放大器的第一端连接所述第一电流镜的输出端和所述第二电流镜的输出端，所述第一单位增益放大器的第二端连接所述连接电路；所述第二单位增益放大器的第一端连接所述低通滤波器LPF的输入端，所述第二单位增益放大器的第二端连接所述连接电路；所述LPF的输入端连接至所述第二开关电路的漏极；所述脉冲产生电路的输出端连接至所述第一开关电路的栅极和所述第二开关电路的栅极；
所述连接电路包括第一电容和第一开关管，用于连接所述第一增益放大器和所述第二增益放大器；
所述第一电流镜，用于将压控振荡器VCO输出的第一电压镜像为第一电流；
所述第二电流镜，用于将所述VCO输出的第二电压镜像为第二电流；
所述脉冲产生电路，用于根据参考时钟信号生成脉冲信号，所述脉冲信号用于控制所述第一开关电路和所述第二开关电路的开关状态；
所述第一单位增益放大器和所述第二单位增益放大器，用于在所述参考时钟信号为低电平时，将所述第一电流镜的输出端的电压、所述第二电流镜的输出端的电压、所述LPF输入端的电压以及所述第一开关管的漏极电压保持相等。
结合第一方面，在第一方面的第一种可能的实施方式中，所述第一单位增益放大器的第一端连接所述第一电流镜的输出端和所述第二电流镜的输出端，所述第一单位增益放大器的第二端连接所述连接电路，包括：
所述第一单位增益放大器的第一端通过第三开关电路连接至所述第 一电流镜的输出端；
所述第一单位增益放大器的第一端通过第四开关电路连接至所述第二电流镜的输出端；
所述第一单位增益放大器的第二端连接至所述第一开关管的漏极。
结合第一方面，在第一方面的第二种可能的实施方式中，所述第二单位增益放大器的第二端连接所述连接电路，包括：
所述第二单位增益放大器的第二端连接至所述第一开关管的漏极。
结合第一方面，在第一方面的第三种可能的实施方式中，所述第一开关电路的漏极通过第二电容接地。
结合第一方面至第一方面的第三种可能的实施方式中的任一项，在第一方面的第四种可能的实施方式中，所述脉冲产生电路包括延时单元；所述延时单元，用于产生固定的延时时间；
则所述脉冲产生电路，具体用于根据所述延时单元所产生的所述固定的延时时间对所述参考时钟信号进行延时，并将延时后的参考时钟信号与延时前的参考时钟信号进行逻辑与运算后产生所述脉冲信号。
结合第一方面的第四种可能的实施方式，在第一方面的第五种可能的实施方式中，所述延时单元包括第三电流镜、第二开关管、第三开关管、第四开关管和第三电容；其中，
所述第三电流镜的输出端连接至所述第二开关管的源极；所述第二开关管的漏极与所述第三开关管的漏极相连接，所述第三电容的一端与所述第二开关管的漏极和所述第三开关管的漏极相连接，所述第三电容的另一端与所述第四开关管的源极连接；所述第二开关管的栅极和所述第三开关管的栅极连接至所述参考时钟的输出端；所述第三开关管的源极与第四开关管的漏极连接；所述第四开光管的栅极连接偏置电压输出端；
所述第三电流镜，用于将***的偏置电压镜像为第三电流，从所述第三电流镜的输出端输出。
本发明实施例提供的电荷泵的实现电路，通过第一单位增益放大器和第二单位增益放大器将第一电流镜的输出端的电压、第二电流镜的输出端的电压以及LPF的输入端的电压保持相等，使得脉冲信号由低电平转 换为高电平，第二开关电路由关闭状态切换为打开状态时，不会有电荷流入到LPF中，避免产生电荷注入效应，提高了PLL的性能。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本发明提供的半采样型锁相环的结构示意图；
图2为现有技术中的电荷泵的实现电路图；
图3为本发明提供的电荷泵的实现电路实施例一的结构示意图；
图4为本发明提供的脉冲产生电路的结构示意图；
图5为本发明提供的延时单元的电路结构示意图。
附图说明：
10：第一电流镜；  11：第二电流镜；  12：第一开关电路；
13：第二开关电路；  14：连接电路；  15：第一单位增益放大器；
16：第二单位增益放大器；  17：脉冲产生电路；  18：低通滤波器；
19：压控振荡器；  101：第一电流镜的输出端；
111：第二电流镜的输出端；  151：第一单位增益放大器的第一端；
152：第一单位增益放大器的第二端；  181：低通滤波器的输入端；
161：第二单位增益放大器的第一端；  131：第二开关电路的漏极；
162：第二单位增益放大器的第二端；
171：脉冲产生电路的输出端；  121：第一开关电路的栅极；
132：第二开关电路的栅极；  141：第一电容；  142：第一开关管；
30：第三开关电路；  31：第四开关电路；
122：第一开关电路的源极；  133：第二开关电路的源极；
123：第一开关电路的漏极；  143：第二电容；
20：延时单元；  201：第三电流镜；  202：第二开关管；
203：第三开关管；  204：第三电容；  301：第三电流镜的输出端；
302：第二开关管的源极；  303：第二开关管的漏极；
304：第三开关管的漏极；  305：第三电容的一端；
306：第三电容的另一端；  307：第二开关管的栅极；
308：第三开关管的栅极；  309：参考时钟的输出端；
310：第三开关管的源极；  311：第四开关管；
312：第四开关管的源极；  313：第四开关管的漏极；
314：第四开光管的栅极；  315：偏置电压输出端。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
图3为本发明提供的电荷泵的实现电路实施例一的结构示意图。如图3所示，该电路包括：第一电流镜10、第二电流镜11、第一开关电路12、第二开关电路13、连接电路14、第一单位增益放大器15、第二单位增益放大器16和脉冲产生电路17。
其中，所述第一电流镜10的输出端101和所述第二电流镜11的输出端111均连接所述第一开关电路12的源极122和所述第二开关电路13的源极133；所述第一单位增益放大器15的第一端151连接所述第一电流镜 10的输出端101和所述第二电流镜11的输出端111，所述第一单位增益放大器15的第二端152连接所述连接电路14；所述第二单位增益放大器16的第一端161连接LPF18的输入端181，所述第二单位增益放大器16的第二端162连接所述连接电路14；所述LPF18的输入端181连接至所述第二开关电路13的漏极131；所述脉冲产生电路17的输出端171连接至所述第一开关电路12的栅极121和所述第二开关电路13的栅极132；所述连接电路14包括第一电容141和第一开关管142，用于连接所述第一增益放大器15和所述第二增益放大器16；所述第一电流镜10，用于将VCO19输出的第一电压镜像为第一电流；所述第二电流镜11，用于将所述VCO19输出的第二电压镜像为第二电流；所述脉冲产生电路17，用于根据参考时钟信号生成产生脉冲信号，所述脉冲信号用于控制所述第一开关电路12和所述第二开关电路13的开关状态；所述第一单位增益放大器15和所述第二单位增益放大器16，用于在参考时钟信号为低电平时，将所述第一电流镜10的输出端101的电压、所述第二电流镜11的输出端111的电压、所述LPF18的输入端181的电压以及所述第一开关管142的漏极电压保持相等。
需要说明的是，图3中的第一电流镜10、第二电流镜11，第一开关电路12、第二开关电路13以及脉冲产生电路17的连接的方法可以有多种，例如可以参见图2所示的连接方式，本发明实施例只是一种简单示意，只要确保能够将VCO19输出的两路电压分别镜像为Iup或Idn，并输入到第一开关电路12和第二开关电路13，并且脉冲产生电路17产生的脉冲信号能够控制第一开关电路12和第二开关电路13的开关状态即可。另外，第一开关电路12和第二开关电路在图3中未示出，可以参照图2中所标出的第一开关电路和第二开关电路。
具体的，参见图3，VCO19输出第一电压和第二电压；这里的第一电压可以为
Figure PCTCN2015073742-appb-000007
也可以为
Figure PCTCN2015073742-appb-000008
第二电压可以为
Figure PCTCN2015073742-appb-000009
也可以为
Figure PCTCN2015073742-appb-000010
当第一电压为
Figure PCTCN2015073742-appb-000011
时，第二电压为
Figure PCTCN2015073742-appb-000012
当第一电压为
Figure PCTCN2015073742-appb-000013
时，第二电压为
Figure PCTCN2015073742-appb-000014
在本发明实施例中，假设第一电压为
Figure PCTCN2015073742-appb-000015
第二电压为
Figure PCTCN2015073742-appb-000016
第一电流镜10将第一电压镜像为Iup，第二电流镜11将第二电压镜像为Idn。这里的第一电流镜10的输出端101实际上为第一电流镜10的漏极，即Iup 从第一电流镜10的漏极输出；相应的，Idn从第二电流镜11的漏极输出。
图3中所示的脉冲产生电路17仅是逻辑电路图，其具体实现方式可以参见图4所示(图4中的延时单元20在该实施例的后面会有描述)。脉冲产生电路17会根据参考时钟信号以及延时后的参考时钟信号进行逻辑与的操作后，形成脉冲信号(Pul)，该脉冲信号可以控制第一开关电路12和第二开关电路13的打开或关闭状态。这里的第一开关电路12和第二开关电路13中的两个MOS管的连接方式可以参照现有技术。脉冲信号经脉冲产生电路17的输出端171输出至第一开关电路12的栅极121和第二开关电路13的栅极132，当该脉冲信号的电平为低电平时，第一开关电路12打开，第二开关电路13处于关闭状态，这时整个CP的输入信号即为VCO19的振荡信号，即第一电压和第二电压之间的电压差，并且该电压差处理不断变化的状态。即，第一电压和第二电压不相等，也不等于LPF18输入端的电压。也就是说，第一电流镜10的漏极电压、第二电流镜11的漏极电压以及LPF18的输入端181的电压三者互不相等。
现有技术中，因为第一电流镜10的漏极电压、第二电流镜11的漏极电压以及LPF18的输入端181的电压三者互不相等，在脉冲信号的电平为高电平时，第二开关电路13会由原来的关闭状态切换为打开状态。在第二开关电路13切换的瞬间，由于第一开关电路12打开时，第一电流镜10的漏极电压、第二电流镜11的漏极电压以及LPF18的输入端181的电压由于之前所存在电压差，因此，会有电荷流入到LPF18中，引起电荷共享或电荷注入效应，从而使得LPF18上产生周期性的纹波，影响PLL的性能。
但是，在本发明实施例中，由于第一电流镜10的输出端101(即第一电流镜10的漏极)和第二电流镜11的输出端111(即第二电流镜11的漏极)与第一单位增益放大器15的第一端151连接；第一单位增益放大器15的第二端152与连接电路14连接。由于第一单位增益放大器15的作用，使得第一单位增益放大器15的第一端151上的电压等于第一单位增益放大器15的第二端152的电压；又由于第一单位增益放大器15的第二端152与连接电路14连接，所以第一单位增益放大器15的第二端152的 电压等于连接电路14中的第一开关管142的漏极电压；也就是说，第一单位增益放大器15的第一端151的电压与第一开关管142的漏极电压相等，并且，由于第一电流镜10的输出端101和第二电流镜11的输出端111与第一单位增益放大器15的第一端151连接，因此，第一电流镜10的输出端101的电压和第二电流镜11的输出端111的电压也就等于第一开关管142的漏极电压。
另一方面，LPF18的输入端181(即Icp所在的端口)与第二单位增益放大器16的第一端161连接，且第一单位增益放大器15和第二单位增益放大器16通过连接电路14相连，第二单位增益放大器16的第二端162与连接电路14连接。由于第二单位增益放大器16的作用，使得第二单位增益放大器16的第一端161上的电压等于第二单位增益放大器16的第二端162的电压；又由于第二单位增益放大器16的第二端162与连接电路14连接，所以第二单位增益放大器16的第二端162的电压等于连接电路14中的第一开关管142的漏极电压；也就是说，第二单位增益放大器16的第一端161的电压与第一开关管142的漏极电压相等，并且，由于第二单位增益放大器16的第一端161与LPF18的输入端181(即Icp所在的端口)连接，因此，LPF18的输入端181的电压也就等于第一开关管142的漏极电压
故，本发明实施例可以通过第一单位增益放大器15和第二单位增益放大器16将第一电流镜10的输出端101的电压、第二电流镜11的输出端111的电压和LPF18的输入端181的电压转换为相等的(即，使得这三者均等于第一开关管142的漏极电压)，即这三者之间不存在电压差，从而在脉冲信号为高电平时，第二开关电路13由关闭状态切换为打开状态的瞬间，不会有电流流进LPF18，即不会有电荷注入到LPF18里面，因而保证了PLL的性能。
本发明实施例提供的电荷泵的实现电路，通过第一单位增益放大器和第二单位增益放大器将第一电流镜的输出端的电压、第二电流镜的输出端的电压以及LPF的输入端的电压保持相等，使得脉冲信号由低电平转换为高电平，第二开关电路由关闭状态切换为打开状态时，不会有电荷流入到LPF中，避免产生电荷注入效应，提高了PLL的性能。
进一步地，继续参照图3，上述第一单位增益放大器15的第一端151连接所述第一电流镜10的输出端101和第二电流镜11的输出端111，具体可以为：第一单位增益放大器15的第一端151可以通过第三开关电路30与第一电流镜10的输出端101连接，第一单位增益放大器15的第一端151可以通过第四开关电路31与第二电流镜11的输出端111连接，第一单位增益放大器15的第二端152连接所述连接电路14。
更进一步地，继续参照图3，上述第一单位增益放大器15的第二端152以及第二单位增益放大器16的第二端162均与连接电路14相连，具体可以为：第一单位增益放大器15的第二端152与连接电路14中第一开关管142的漏极连接，第二单位增益放大器16的第二端162连接至第一开关管142的漏极，从而实现第一单位增益放大器15与第二单位增益放大器16的连接。另外，上述第一开关电路12的漏极123通过第二电容143接地，第二电容在图3中未示出，可以参见图2所示的第二电容。
本发明实施例提供的电荷泵的实现电路，通过第一单位增益放大器和第二单位增益放大器将第一电流镜的输出端的电压、第二电流镜的输出端的电压以及LPF的输入端的电压保持相等，使得脉冲信号由低电平转换为高电平，第二开关电路由关闭状态切换为打开状态时，不会有电荷流入到LPF中，避免产生电荷注入效应，提高了PLL的性能。
上述图4所示的脉冲产生电路17中，脉冲信号的生成需要参考时钟信号与延时后的参考时钟信号进行逻辑与操作，现有技术中的脉冲产生电路17虽然也是采用图4的连接方式生成脉冲信号，但现有技术中参考时钟信号的延时是通过普通的反相器级联而成，在不同的工艺、不同的电压或不同的温度下，反相器的延时容易产生变化，因而使得产生的脉冲信号的宽度变化很大，从而会影响整个PLL的***参数的稳定性，进而影响PLL的性能。但是，在本发明实施例中，图4所示的延时单元20可以产生固定的延时时间，其并不随外界环境的变化而变化，则上述脉冲产生电路17，根据该延时单元20产生的固定的延时时间对参考时钟信号进行延时，并将延时后的参考时钟信号与延时前的参考时钟信号进行逻辑与运算后产生脉冲信号。该延时单元20的具体实现电路可以参见下述 图5。
如图5所示，该延时单元20包括：第三电流镜201、第二开关管202、第三开关管203、第四开关管311和第三电容204；其中，所述第三电流镜201的输出端301连接至所述第二开关管202的源极302；所述第二开关管202的漏极303与所述第三开关管203的漏极304相连接，所述第三电容204的一端305与所述第二开关管202的漏极303和所述第三开关管203的漏极304相连接，所述第三电容204的另一端306与所述第四开关管311的源极312连接；所述第二开关管202的栅极307和所述第三开关管203的栅极308连接至所述参考时钟的输出端309；所述第三开关管203的源极310与第四开关管311的漏极313连接；所述第四开光管311的栅极314连接偏置电压输出端315；所述第三电流镜201，用于将***的偏置电压镜像为第三电流，从所述第三电流镜201的输出端301输出。
具体的，电路***会提供一固定的偏置电压，该偏置电压经第三电流镜201镜像为第三电流，从第三电流镜201的输出端301(即第三电流镜201的漏极)输出。此时，参考时钟的输出端309输出一参考时钟信号(即外部参考时钟)，当该参考时钟信号为低电平时，第二开关管202打开(该第二开关管202为一PMOS管)，第三电流经由第二开关管202为第三电容204充电；当参考时钟信号切换为高电平时，第三开关管203打开(该第三开关管203为一NMOS管)，第三电容204为第三开关管203与第四开关管311进行放电(第四开关管311为第三电容204放电时提供恒定的电流)。该放电时间即为该延时单元20的延时时间。可选的，第二开关管202也可以为NMOS管，第三开关管203也可以PMOS管，只是参考时钟信号的电平也应进行相应的切换，即参考时钟信号的电平应该是先高后低。需要说明的是，图5中所示的两个延时单元20进行级联的情况。
由于上述偏置电压固定，因此，第三电流固定，故第三电容204在充电时的所保存的电荷量固定；又第四开关管311可以提供恒定的放电电流，因此，第三电容204进行放电的时间也就固定，从而该延时单元20的延时时间固定，进而使得脉冲产生电路17所产生的脉冲信号的宽度的变动范围减小，即减小了脉冲信号的宽度变化。
本发明实施例提供的电荷泵的实现电路，通过第一单位增益放大器和第二单位增益放大器将第一电流镜的输出端的电压、第二电流镜的输出端的电压以及LPF的输入端的电压保持相等，使得脉冲信号由低电平转换为高电平，第二开关电路由关闭状态切换为打开状态时，不会有电荷流入到LPF中，避免产生电荷注入效应；另外，通过延时单元产生固定的延时时间，使得脉冲产生电路输出的脉冲信号的宽度的变化减小，保证了PLL***的稳定，提升了PLL的性能。最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (6)

  1. 一种电荷泵的实现电路，其特征在于，包括：第一电流镜、第二电流镜、第一开关电路、第二开关电路、连接电路、第一单位增益放大器、第二单位增益放大器和脉冲产生电路；
    其中，所述第一电流镜的输出端和所述第二电流镜的输出端均连接所述第一开关电路的源极和所述第二开关电路的源极；所述第一单位增益放大器的第一端连接所述第一电流镜的输出端和所述第二电流镜的输出端，所述第一单位增益放大器的第二端连接所述连接电路；所述第二单位增益放大器的第一端连接所述低通滤波器LPF的输入端，所述第二单位增益放大器的第二端连接所述连接电路；所述LPF的输入端连接至所述第二开关电路的漏极；所述脉冲产生电路的输出端连接至所述第一开关电路的栅极和所述第二开关电路的栅极；
    所述连接电路包括第一电容和第一开关管，用于连接所述第一增益放大器和所述第二增益放大器；
    所述第一电流镜，用于将压控振荡器VCO输出的第一电压镜像为第一电流；
    所述第二电流镜，用于将所述VCO输出的第二电压镜像为第二电流；
    所述脉冲产生电路，用于根据参考时钟信号生成脉冲信号，所述脉冲信号用于控制所述第一开关电路和所述第二开关电路的开关状态；
    所述第一单位增益放大器和所述第二单位增益放大器，用于在所述参考时钟信号为低电平时，将所述第一电流镜的输出端的电压、所述第二电流镜的输出端的电压、所述LPF输入端的电压以及所述第一开关管的漏极电压保持相等。
  2. 根据权利要求1所述的电路，其特征在于，所述第一单位增益放大器的第一端连接所述第一电流镜的输出端和所述第二电流镜的输出端，所述第一单位增益放大器的第二端连接所述连接电路，包括：
    所述第一单位增益放大器的第一端通过第三开关电路连接至所述第一电流镜的输出端；
    所述第一单位增益放大器的第一端通过第四开关电路连接至所述第二电流镜的输出端；
    所述第一单位增益放大器的第二端连接至所述第一开关管的漏极。
  3. 根据权利要求1所述的电路，其特征在于，所述第二单位增益放大器的第二端连接所述连接电路，包括：
    所述第二单位增益放大器的第二端连接至所述第一开关管的漏极。
  4. 根据权利要求1所述的电路，其特征在于，所述第一开关电路的漏极通过第二电容接地。
  5. 根据权利要求1-4任一项所述的电路，其特征在于，所述脉冲产生电路包括延时单元；所述延时单元，用于产生固定的延时时间；
    则所述脉冲产生电路，具体用于根据所述延时单元所产生的所述固定的延时时间对所述参考时钟信号进行延时，并将延时后的参考时钟信号与延时前的参考时钟信号进行逻辑与运算后产生所述脉冲信号。
  6. 根据权利要求5所述的电路，其特征在于，所述延时单元包括第三电流镜、第二开关管、第三开关管、第四开关管和第三电容；其中，
    所述第三电流镜的输出端连接至所述第二开关管的源极；所述第二开关管的漏极与所述第三开关管的漏极相连接，所述第三电容的一端与所述第二开关管的漏极和所述第三开关管的漏极相连接，所述第三电容的另一端与所述第四开关管的源极连接；所述第二开关管的栅极和所述第三开关管的栅极连接至所述参考时钟的输出端；所述第三开关管的源极与第四开关管的漏极连接；所述第四开光管的栅极连接偏置电压输出端；
    所述第三电流镜，用于将***的偏置电压镜像为第三电流，从所述第三电流镜的输出端输出。
PCT/CN2015/073742 2014-03-24 2015-03-06 电荷泵的实现电路 WO2015143980A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410112015.7 2014-03-24
CN201410112015.7A CN103887966B (zh) 2014-03-24 2014-03-24 电荷泵的实现电路

Publications (1)

Publication Number Publication Date
WO2015143980A1 true WO2015143980A1 (zh) 2015-10-01

Family

ID=50956718

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/073742 WO2015143980A1 (zh) 2014-03-24 2015-03-06 电荷泵的实现电路

Country Status (2)

Country Link
CN (1) CN103887966B (zh)
WO (1) WO2015143980A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112073065A (zh) * 2020-08-12 2020-12-11 西安电子科技大学 一种新型毫米波亚采样dds混频小数分频锁相环结构

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103887966B (zh) * 2014-03-24 2017-06-20 华为技术有限公司 电荷泵的实现电路
US9184623B1 (en) * 2015-04-23 2015-11-10 Xilinx, Inc. Circuits for and methods of implementing a charge/discharge switch in an integrated circuit

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1236225A (zh) * 1998-03-26 1999-11-24 日本电气株式会社 锁相环的电荷泵电路
JP2000286700A (ja) * 1999-03-30 2000-10-13 Hitachi Ltd 位相同期回路
US6611161B1 (en) * 2001-11-06 2003-08-26 National Semiconductor Corporation Charge pump circuit for a high speed phase locked loop
US6794911B2 (en) * 2002-05-23 2004-09-21 Industrial Technology Research Institute Charge-pump circuit for charge-share suppression
CN103887966A (zh) * 2014-03-24 2014-06-25 华为技术有限公司 电荷泵的实现电路

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5963025A (en) * 1997-12-19 1999-10-05 Stmicroelectronics, Inc. Switching voltage regulator having a charge pump circuit
FR2834396B1 (fr) * 2002-01-03 2004-02-27 Cit Alcatel Pompe a charge a tres large plage de tension de sortie
CN101488710B (zh) * 2008-10-22 2012-06-13 成都国腾电子技术股份有限公司 一种电荷泵电路
CN202167988U (zh) * 2011-06-10 2012-03-14 安凯(广州)微电子技术有限公司 一种用于锁相环的电荷泵电路
CN202111620U (zh) * 2011-06-30 2012-01-11 四川和芯微电子股份有限公司 电荷泵电路

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1236225A (zh) * 1998-03-26 1999-11-24 日本电气株式会社 锁相环的电荷泵电路
JP2000286700A (ja) * 1999-03-30 2000-10-13 Hitachi Ltd 位相同期回路
US6611161B1 (en) * 2001-11-06 2003-08-26 National Semiconductor Corporation Charge pump circuit for a high speed phase locked loop
US6794911B2 (en) * 2002-05-23 2004-09-21 Industrial Technology Research Institute Charge-pump circuit for charge-share suppression
CN103887966A (zh) * 2014-03-24 2014-06-25 华为技术有限公司 电荷泵的实现电路

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
LIU, WEIJIAN: "Design and Research of a ?-DELTA Modulator for Fractional-N Frequency Synthesis", DOC88, 2 March 2014 (2014-03-02), pages 44 - 45 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112073065A (zh) * 2020-08-12 2020-12-11 西安电子科技大学 一种新型毫米波亚采样dds混频小数分频锁相环结构
CN112073065B (zh) * 2020-08-12 2023-03-14 西安电子科技大学 一种毫米波亚采样dds混频小数分频锁相环结构

Also Published As

Publication number Publication date
CN103887966B (zh) 2017-06-20
CN103887966A (zh) 2014-06-25

Similar Documents

Publication Publication Date Title
US7212051B1 (en) Control signal generation for a low jitter switched-capacitor frequency synthesizer
US8063678B2 (en) Charge pump for phase locked loop
JP2009165109A (ja) 半導体素子、クロック同期化回路、及び、クロック同期化回路の駆動方法
US8890626B2 (en) Divider-less phase locked loop (PLL)
CN103297042A (zh) 一种可快速锁定的电荷泵锁相环电路
JP2000269808A (ja) Ｐｌｌ回路
US20050237092A1 (en) Charge pump circuit reducing noise and charge error and PLL circuit using the same
US20090189654A1 (en) Common-Mode Feedback Method Using a Current Starved Replica Biasing
CN101414784A (zh) 电荷泵
JPH03235512A (ja) 電圧制御発振回路
WO2015143980A1 (zh) 电荷泵的实现电路
WO2019169607A1 (zh) 抑制电流失配的电荷泵电路及其控制方法、锁相环电路
US8786334B2 (en) Lock detection circuit and phase-locked loop circuit including the same
TWI434168B (zh) 時脈資料回復電路
JP2011049736A (ja) チャージポンプ回路及びそれを用いるｐｌｌ回路
US20070164799A1 (en) Phase-locked loop systems and methods
JP2001274682A (ja) フェーズロックドループ回路
KR20120012386A (ko) 락 검출 회로 및 이를 포함하는 위상 동기 루프
US8368443B1 (en) Differential charge pump circuit
US7772897B2 (en) Switched-capacitor charge pump device for generation of output direct-current voltage with wide amplitude range
US7224213B2 (en) Switched capacitor ripple-smoothing filter
US8519746B2 (en) Voltage-to-current converter
JP2017079353A (ja) クロックリカバリ回路
US7777541B1 (en) Charge pump circuit and method for phase locked loop
US9337818B1 (en) Buffer circuit for voltage controlled oscillator

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15769239

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15769239

Country of ref document: EP

Kind code of ref document: A1