WO2015107849A1 - 半導体装置、及び撮像モジュール - Google Patents

半導体装置、及び撮像モジュール Download PDF

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Publication number
WO2015107849A1
WO2015107849A1 PCT/JP2014/084252 JP2014084252W WO2015107849A1 WO 2015107849 A1 WO2015107849 A1 WO 2015107849A1 JP 2014084252 W JP2014084252 W JP 2014084252W WO 2015107849 A1 WO2015107849 A1 WO 2015107849A1
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Prior art keywords
wiring
substrate
semiconductor device
terminal
dielectric layer
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PCT/JP2014/084252
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English (en)
French (fr)
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英之 和田
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株式会社フジクラ
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Publication of WO2015107849A1 publication Critical patent/WO2015107849A1/ja

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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections

Definitions

  • the present invention relates to a semiconductor device and an imaging module.
  • This application claims priority based on Japanese Patent Application No. 2014-004352 filed in Japan on January 14, 2014, the contents of which are incorporated herein by reference.
  • a semiconductor device such as a solid-state image sensor is manufactured as a chip size package (CSP), mounted on a wiring board, and used for various devices such as an imaging module.
  • CSP chip size package
  • Such a semiconductor device has a terminal surface such as a bump electrode and a terminal surface on which wiring is formed. The terminal surface is bonded to the wiring substrate with an adhesive or the like, and the semiconductor device is mounted on the wiring substrate (for example, , See Patent Documents 1 and 2 below).
  • an insulating overcoat layer is provided on a terminal surface of a semiconductor device in order to avoid a short circuit between the wiring on the surface of the semiconductor device and the wiring on the surface of the wiring board.
  • this overcoat layer for example, an insulating film covering the terminals and the wiring is formed over almost the entire surface of the terminal, and an opening exposing the terminal is formed in this insulating film.
  • This opening is formed so as to enclose the terminal in an annular shape so as to include a gap formed between the terminal and the inner edge of the opening so as to provide a margin for positional error and dimensional error between the opening and the terminal.
  • the semiconductor device when the semiconductor device is mounted using an adhesive or the like, bubbles (voids) tend to remain in the gap between the terminal and the inner edge of the opening of the overcoat layer. Such voids can cause problems such as breakage of electrical connection and breakage of a joint portion between a semiconductor device and a wiring board due to expansion and contraction accompanying temperature change.
  • the conventional semiconductor device may have a mounting defect.
  • the present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor device and an imaging module that can suppress the occurrence of mounting defects.
  • a semiconductor device is a semiconductor device mounted on a device, and includes a substrate having a first surface, a terminal formed on the first surface of the substrate and connected to the device, A first wiring formed on the first surface of the substrate and connected to the terminal; and a dielectric layer covering at least a part of the first wiring.
  • the first surface of the substrate has a non-formation region where the dielectric layer is not formed, and the non-formation region is continuous from the position of the terminal to the position of the edge of the substrate.
  • the substrate may have a rectangular shape, and the non-formation region may include at least a part of a side closest to the terminal among the four sides of the substrate.
  • the semiconductor device may include a conductive portion that penetrates the substrate and is electrically connected to the first wiring, and the dielectric layer may cover at least a part of the conductive portion.
  • a part of the dielectric layer may be formed as an alignment mark indicating an edge of the substrate.
  • the substrate has a rectangular shape including a first side and a second side orthogonal to each other, and the alignment mark includes a side parallel to the first side and the second side. You may have a side parallel to a side.
  • the semiconductor device includes a photoelectric conversion layer that converts incident light into electric power, and a plurality of terminals including the terminals are disposed on the first surface of the substrate, and the photoelectric conversion layer includes the photoelectric conversion layer, You may electrically connect with any terminal among several terminals.
  • An imaging module includes the semiconductor device according to the first aspect, an adhesive layer formed on the first surface of the semiconductor device, and the semiconductor device bonded via the adhesive layer.
  • the non-formation region of the semiconductor device includes a portion of the first surface of the substrate in plan view where the terminal of the semiconductor device is connected to the wiring substrate.
  • the first wiring of the semiconductor device may be arranged at a position where it does not overlap the second wiring of the wiring board in the first surface of the board in plan view.
  • FIG. 3 is a cross-sectional view of an image sensor and a wiring board along the line A-A ′ in FIG. 2. It is a figure which shows the semiconductor device of the 1st modification of this invention. It is explanatory drawing for demonstrating the usage example of an alignment mark. It is a figure which shows the semiconductor device of the 2nd modification of this invention. It is a figure which shows the semiconductor device of the 3rd modification of this invention. It is a figure which shows the semiconductor device of the 4th modification of this invention.
  • FIG. 1 is a diagram showing an optical device 1 equipped with a semiconductor device according to this embodiment.
  • the semiconductor device 2 is an image sensor (hereinafter also referred to as an image sensor) such as a CMOS sensor or a CCD sensor.
  • the optical device 1 (device) is at least a part of an imaging module that outputs image data acquired by the semiconductor device 2, and is used for an apparatus used in a narrow space such as an endoscope.
  • the optical device 1 includes an imaging module 3, a lens unit 4 provided on the light incident side with respect to the imaging module 3, a case 5 that houses the imaging module 3, and a cable 6 that outputs an imaging result of the imaging module 3.
  • the imaging module 3 includes a semiconductor device 2 (hereinafter also referred to as an imaging element 2) and a wiring board 7 on which the imaging element 2 is mounted.
  • the optical device 1 receives the light L obtained (reflected) from the imaging target by the imaging device 2 via the lens unit 4. In addition, the optical device 1 outputs image data indicating the result of imaging by the imaging device 2 to the outside via the wiring board 7 and the cable 6.
  • the cable 6 is connected to, for example, an image display device, a storage device, an image processing device, and the like. The user can display an image obtained by imaging an imaging target on an image display device, store the image in a storage device, or cause the image processing device to process the image.
  • the lens unit 4 includes, for example, one or more lenses and a lens barrel that holds the lenses.
  • the lens unit 4 forms an image of the imaging object on the light receiving surface 10 of the imaging device 2. In a state where the optical axis of the lens unit 4 is aligned with the light receiving surface 10 of the image sensor 2, the relative position between the lens unit 4 and the image sensor 2 is fixed.
  • the case 5 is, for example, a metal cylinder, and accommodates the imaging module 3 (an imaging module with a lens) to which the lens unit 4 is attached inside the metal cylinder.
  • the wiring board 7 is a flexible board such as a flexible printed board. One side of the wiring board 7 is a wiring surface 11 on which wiring is formed. The wiring substrate 7 is folded so that the wiring surface 11 faces outward and the both ends of the wiring substrate 7 are aligned.
  • the one end part (first end part) and the other end part (second end part) of the wiring board 7 constitute a joint part in which the opposite surfaces of the wiring surface 11 are joined to each other.
  • the joint extends in the axial direction of the case 5 and is fixed to the inner wall of the case 5 with an insulating resin or the like, for example.
  • the central portion of the wiring board 7 is a folded portion of the wiring board 7 and has a substantially triangular shape when viewed from the side of the wiring board 7 in FIG.
  • the portion of the wiring board 7 corresponding to the bottom of the triangle is formed in a substantially flat shape and is arranged toward the opening of the case 5 where light from the imaging target enters.
  • the imaging element 2 is mounted on the planar portion of the wiring board 7.
  • the image sensor 2 is, for example, a CMOS sensor manufactured using a chip size package technology.
  • the imaging element 2 faces the functional surface 12 (the surface of the protective substrate 26, the second surface) on which the light L from the imaging object is incident via the lens unit 4, and is opposite to the functional surface 12.
  • the imaging element 2 is arranged with the functional surface 12 facing the opening of the case 5 where light from the imaging target enters.
  • the imaging element 2 is mounted on the wiring board 7 with the terminal surface 14 of the imaging element 2 facing the wiring surface 11 of the wiring board 7.
  • Each of the plurality of terminals 13 is electrically connected to a wiring provided on the wiring surface 11 of the wiring board 7, and the plurality of terminals 13 are electrically connected to a conductor in the cable 6 through this wiring. Has been.
  • FIG. 2 is a diagram showing the terminal surface 14 of the image sensor 2.
  • the imaging device 2 includes a substrate 20, a terminal 13 formed on the terminal surface 14 of the substrate 20, a wiring 21 (first wiring) that conducts to the terminal 13, and at least a part of the wiring 21. And a dielectric layer 22 covering the substrate.
  • the terminal surface 14 is formed with a conductive portion 23 that communicates with the inside of the image sensor 2.
  • the conductive portion 23 is electrically connected to the wiring 21 and is electrically connected to the terminal 13 through the wiring 21.
  • FIG. 2 shows a plurality (four in this embodiment) of conductive portions 23 and a plurality (four in this embodiment) of terminals 13, and the terminals 13 are in one-to-one correspondence with the conductive portions 23. It corresponds. Further, one set, that is, one system (wiring system) is formed by one wiring 21, one conductive portion 23 corresponding to the wiring 21, and the terminal 13 corresponding to the wiring 21. Is formed.
  • FIG. 2 shows a plurality (four in this embodiment) of system wiring.
  • a part of the terminal surface 14 is a non-formation region 24 in which the dielectric layer 22 is not formed.
  • the non-formation region 24 is continuous from the position of the terminal 13 to the position of the edge 20a of the substrate 20. That is, in the imaging device 2 that is not mounted on the wiring substrate 7, when the terminal 13 is viewed from the end face (side) of the substrate 20, the terminal 13 is outside the substrate 20 via the non-formation region 24. In other words, it is exposed to the atmosphere (open to the atmosphere).
  • the substrate 20 has a rectangular plate shape including a first side and a second side orthogonal to each other.
  • the non-formation region 24 is continuous from the position of the terminal 13 to the side (edge 20a) closest to the terminal 13 among the four sides of the substrate 20.
  • the non-formation region 24 a structure such as a protrusion or a wall that blocks a space between the position of the terminal 13 and the position of the edge 20a of the substrate 20 is not formed. It can be said that the non-formation region 24 is a region that surrounds the terminal 13 and forms a space that leads from the terminal 13 to the outside of the substrate 20.
  • FIG. 3 is a cross-sectional view of the image sensor 2 and the wiring board 7 at a position along the line A-A ′ of FIG. 3 includes an element layer 25 provided on the substrate 20 and a protective substrate 26 provided on the element layer 25 and through which the light L passes.
  • the protective substrate 26 is, for example, a light-transmitting glass substrate, and is provided so as to face the surface of the substrate 20 opposite to the terminal surface 14.
  • the element layer 25 is sandwiched between the substrate 20 and the protective substrate 26.
  • the element layer 25 has a light receiving surface 10 that receives the light L that has passed through the protective substrate 26.
  • the image sensor 2 has a plurality of pixels, and the photoelectric conversion layer 50 is disposed on the light receiving surface 10 for each pixel.
  • the photoelectric conversion layer 50 has a function of converting incident light into electric power, and is electrically connected to any one of the plurality of terminals 13.
  • the photoelectric conversion layer 50 is formed of a semiconductor material, and charges are generated in the photoelectric conversion layer 50 due to the photoelectric effect of the incident light L. That is, the photoelectric conversion layer 50 converts the light L incident on the functional surface 12 opposite to the terminal surface 14 in the imaging device 2 into electric power.
  • the element layer 25 is provided with a readout circuit 27 that reads out charges generated in the photoelectric conversion layer 50 of each pixel.
  • the readout circuit 27 includes a switching element and a wiring provided in each pixel.
  • an interlayer insulating film, a planarizing film, a passivation film, and the like are provided in addition to the wiring and the switching element constituting the readout circuit 27.
  • the element layer 25 may be provided with an amplifier that amplifies an analog signal indicating the electric charge read from the photoelectric conversion layer 50 of each pixel, an AD converter that converts the analog signal into a digital signal, and the like.
  • the photoelectric conversion layer 50 is provided between the substrate 20 and the protective substrate 26, and is provided, for example, at a position close to the light receiving surface 10 of the image sensor 2.
  • the photoelectric conversion layer 50 may be provided inside the element layer 25.
  • Read circuit 27 is electrically connected to conductive portion 23. That is, the photoelectric conversion layer 50 of each pixel is electrically connected to the conductive portion 23 via the readout circuit 27.
  • the conductive portion 23 is a so-called through electrode (TSV; Through Silicon Via), and penetrates the substrate 20 and a part thereof is drawn on the terminal surface 14. At least a part of the conductive portion 23 may be formed in a lump (that is, with the same material) by the same process as the process for manufacturing the wiring 21 provided on the terminal surface 14, or formed separately from the wiring 21. May be.
  • the terminal 13 is a bump electrode such as a solder bump, a stud bump, or a plating bump, and has a convex shape (protrusion shape) that protrudes outward from the terminal surface 14 of the substrate 20.
  • the terminal 13 protrudes from the dielectric layer 22 in the normal direction of the terminal surface 14. That is, the distance from the terminal surface 14 to the upper surface (top) of the terminal 13 (the height of the terminal 13) is larger than the distance from the terminal surface 14 to the upper surface of the dielectric layer 22 (thickness of the dielectric layer 22).
  • the terminal 13 is formed in contact with the wiring 21 and is electrically connected to the wiring 21. Further, the terminal 13 is also in contact with the wiring 28 (second wiring) provided on the wiring surface 11 of the wiring board 7 and is electrically connected to the wiring 28.
  • the dielectric layer 22 is formed avoiding the electrical connection portion 29 between the wiring 21 and the wiring 28 via the terminal 13. Further, the dielectric layer 22 is formed between the wirings 21 corresponding to each other among the wiring 21 provided on the terminal surface 14 of the imaging element 2 and the wiring 28 provided on the wiring surface 11 of the wiring substrate 7. It is provided to prevent short circuit. This will be described in detail below.
  • one of the plurality of wirings 21 provided on the terminal surface 14 of the image sensor 2 is referred to as a first chip side wiring
  • the other system wiring is referred to as a second chip side wiring.
  • one system wiring is referred to as a first substrate side wiring
  • the other system wiring is referred to as a substrate side wiring.
  • the first chip side wiring is electrically connected to the first substrate side wiring through one of the plurality of terminals 13
  • the second chip side wiring is one of the plurality of terminals 13. A case where the second substrate side wiring is electrically connected via the wiring will be described.
  • the dielectric layer 22 is not formed in a region where the first chip-side wiring and the first substrate-side wiring overlap in the state where the terminal surface 14 is viewed in plan (for example, the connection portion 29 in FIG. 3). Further, the dielectric layer 22 is provided in a region where at least the first chip-side wiring and the second substrate-side wiring not corresponding to the first chip-side wiring overlap on the terminal surface 14 in plan view. . Similarly, when the second chip side wiring and the first substrate side wiring overlap in a state where the terminal surface 14 is viewed in plan, the dielectric layer 22 is also provided in the overlapping region.
  • the non-formation region 24 is located at a position where the terminal 13 of the terminal surface 14 of the substrate 20 in plan view overlaps with a location where the terminal 13 is connected to the wiring substrate 7 (location where the terminal 13 and the wiring 28 are connected). Has been placed.
  • the wiring 21 is disposed at a position that does not overlap the second wiring of the wiring substrate. That is, the non-formation region 24 in which the dielectric layer 22 is not formed as shown in FIG. 2 is the first wiring (specific wiring) of the wirings 21 of the image sensor 2 when the terminal surface 14 is viewed in plan view.
  • the first wiring (specific wiring) and the second wiring not corresponding to the first wiring (specific wiring) in the wiring 28 of the wiring board 7 are included (the first wiring and the first wiring not corresponding to the first wiring). Through the region where the two wirings do not overlap each other, the position from the terminal 13 to the position of the edge of the substrate 20 continues.
  • the image pickup device 2 has the first conductor (the wiring 21 and the terminal 13) to which an electric signal is supplied, and the wiring board 7 is the second conductor that is electrically connected to the first conductor. (One of the wirings 28) and a third conductor (another wiring 28) that is insulated from the first conductor.
  • a dielectric layer 22 is formed in a region of the terminal surface 14 in plan view where the first conductor and the third conductor overlap.
  • the non-forming region 24 is continuous from the region where the first conductor and the second conductor overlap to the edge 20a of the substrate 20.
  • the image pickup device 2 having the above configuration is mounted on the wiring board 7 by the following method.
  • a fluid insulating resin NCP: Non-conductive Paste
  • the protective substrate 26 of the image sensor 2 is held by a flip chip holder or the like, and the terminal surface 14 of the image sensor 2 is placed on the wiring substrate 7 while aligning the terminals 13 of the image sensor 2 and the wirings 28 of the wiring substrate 7.
  • the image sensor 2 is pressed against the wiring board 7 toward the wiring surface 11.
  • the NCP is cured while maintaining the state where the terminal 13 and the wiring 28 are in contact with each other, and the imaging element 2 is bonded to the wiring board 7.
  • the terminal 13 of the image pickup device 2 is electrically connected to the wiring 28 of the wiring board 7 and the image pickup device 2 is fixed to the wiring board 7.
  • the cured NPC becomes the adhesive layer 30 in FIG.
  • the overcoat layer covering the wiring provided on the terminal surface is formed in a partition shape surrounding the terminal in an annular shape, and the terminal is disposed inside the opening of the overcoat layer.
  • This opening is formed so as to have a gap between the inner edge of the opening and the outer edge of the terminal in consideration of a positional error between the opening and the terminal.
  • the imaging element 2 semiconductor device
  • the gas between the imaging element 2 and the wiring board 7 passes through the non-formation region 24 and the edge of the substrate 20. Almost discharged from 20a (see FIG. 3).
  • the generation of voids between the image pickup device 2 after mounting and the wiring board 7 is reduced, and the occurrence of breakage due to expansion and contraction of the voids is suppressed.
  • the imaging device 2 according to the present embodiment can suppress the occurrence of mounting defects.
  • the non-formation region 24 where the dielectric layer 22 is not formed includes at least a part of the four sides of the substrate 20 that are closest to the terminal 13. Therefore, when mounting the image pickup device 2 on the wiring board 7, the atmospheric gas easily escapes from between the image pickup device 2 and the wiring board 7, and the voids are significantly reduced.
  • the dielectric layer 22 covers at least a part of the conductive portion 23 that penetrates the substrate 20 and is electrically connected to the wiring 21. Therefore, it is possible to reduce the occurrence of voids between the image sensor 2 and the wiring board 7 while preventing a short circuit between the image sensor 2 and the wiring provided on the wiring board 7.
  • the imaging module 3 according to the present embodiment including the imaging element 2 as described above mounting defects of the imaging element 2 are suppressed, durability is improved, and the imaging element 2 is caused by mounting defects. Malfunctions can be suppressed.
  • FIG. 4 is a diagram illustrating the semiconductor device 2 according to the first modification.
  • the semiconductor device 2 of FIG. 4 includes an alignment mark 31 formed on the terminal surface 14.
  • the alignment mark 31 is a part of the dielectric layer 22 and is formed of the same material as the portion of the dielectric layer 22 that covers the wiring 21.
  • the alignment mark 31 indicates the edge of the substrate 20.
  • the substrate 20 has a rectangular shape, and the alignment mark 31 has a side 31 b parallel to the first side 20 b of the substrate 20 and a side 31 c parallel to the second side 20 c of the substrate 20.
  • Such a dielectric layer 22 is formed as follows, for example.
  • an insulating film covering the terminal 13 and the wiring 21 is formed on the entire surface of the terminal surface 14 in a state where the terminal 13 and the wiring 21 are formed on the terminal surface 14.
  • this insulating film is patterned so as to leave a portion covering the wiring 21 and a portion corresponding to the alignment mark 31 in the insulating film, and to remove a portion of the non-formation region 24.
  • the alignment mark 31 is collectively formed by the same process as that of the portion of the dielectric layer 22 that covers the wiring 21.
  • FIG. 5 is an explanatory diagram for explaining an example of use of the alignment mark 31.
  • FIG. 5 is a plan view (PART (a)) showing a wafer W used for manufacturing the semiconductor device 2 and an enlarged plan view (PART (b)) showing a part of the wafer W.
  • the conductor, semiconductor, and insulator constituting the semiconductor device 2 are formed in each of the plurality of chip regions W1 of the wafer W, and then the chip region W1 is diced (divided into individual pieces). With that, it is manufactured.
  • the alignment mark 31 functions as an identification mark indicating the edge of the semiconductor device 2 and is used for alignment between the dicing cutter and the wafer W.
  • the alignment mark 31 can be formed by a process of forming a portion of the dielectric layer 22 that covers the wiring 21, so that the productivity is higher than that of forming the alignment mark by another process.
  • FIG. 6A is a diagram illustrating a semiconductor device 2 according to a second modification.
  • the dielectric layer 22 includes a portion 22 a covering the four wires 21 corresponding to the four terminals 13, a portion 22 b covering the wires 21 corresponding to one terminal 13, and a wire 21 corresponding to the other one terminal 13. And a covering portion 22c.
  • the portion 22a, the portion 22b, and the portion 22c are each separated from other portions via the non-forming region 24.
  • the non-formation region 24 is continuous with three of the four sides of the substrate 20.
  • FIG. 6B is a diagram showing a semiconductor device 2 according to a third modification.
  • the dielectric layer 22 includes a portion 22 d that covers the four wirings 21 corresponding to the four terminals 13 and a portion 22 e that covers the wirings 21 corresponding to the other four terminals 13.
  • the portion 22e is separated from the portion 22d through the non-forming region 24.
  • the non-formation region 24 is continuous with two of the four sides of the substrate 20.
  • FIG. 6C is a diagram illustrating a semiconductor device 2 according to a fourth modification.
  • four terminals 13 are provided on the terminal surface 14.
  • Four dielectric layers 22 are formed in an island shape so as to correspond to the four terminals 13. These four portions (island-like dielectric layers) are separated from each other through the non-formation region 24.
  • the non-formation region 24 is continuous with the four sides of the substrate 20.
  • the number of terminals 13 is not limited, and the arrangement pattern of the plurality of terminals 13 is not limited.
  • region 24 should just continue from the position of the at least 1 terminal 13 among the some terminals 13 to the position of the edge 20a of the board
  • the dielectric layer 22 may be formed so as to surround the ring.
  • the dielectric layer 22 may include a part formed over two or more wirings 21 or may include a part that covers only one wiring 21.
  • the non-formation region 24 may be continuous with only one side of the substrate 20, or may be continuous with any of the two sides, the three sides, or the four sides.
  • the planar shape of each of the island-shaped portions when the terminal surface 14 is viewed in plan is not limited to a specific shape, and the shape of the island-shaped portions May be any of a polygon, an ellipse, a shape surrounded by a free curve, and a shape surrounded by a straight line and a curve.
  • the planar shapes of the plurality of island-shaped portions may be different from each other, and two or more of the plurality of island-shaped portions may have the same planar shape.
  • the semiconductor device 2 is an image sensor
  • the semiconductor device 2 may be a semiconductor device other than the image sensor, such as a solar power generation device.
  • the imaging module 3 can also be applied to various optical devices other than the endoscope.
  • the semiconductor device 2 may not include the conductive portion 23 that penetrates the substrate 20.
  • a circuit component using a semiconductor is formed at a predetermined position on the terminal surface 14 of the substrate 20, and the wiring 21 may electrically connect the processing unit including the circuit component and the terminal 13.
  • 1 optical device 2 imaging element (semiconductor device), 3 imaging module, 7 wiring board, 12 functional surface (protective substrate surface, second surface), 13 terminal, 14 terminal surface (one surface of substrate, first surface) ), 20 substrate, 20a edge, 20b first side, 20c second side, 21 wiring (first wiring), 22 dielectric layer, 23 conductive part, 24 non-formation region, 26 protective substrate, 28 wiring substrate wiring ( 2nd wiring), 31 alignment mark, 50 photoelectric conversion layer

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electromagnetism (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Wire Bonding (AREA)
  • Light Receiving Elements (AREA)

Abstract

　本発明の半導体装置は、デバイス（１）に実装される半導体装置（２）であって、第１面（１４）を有する基板（２０）と、前記基板（２０）の前記第１面（１４）に形成され、前記デバイス（１）に接続される端子（１３）と、前記基板（２０）の前記第１面（１４）に形成され、前記端子（１３）に導通する第１配線（２１）と、前記第１配線（２１）の少なくとも一部を覆う誘電体層（２２）とを備える。前記基板（２０）の第１面（１４）は、前記誘電体層（２２）が形成されていない非形成領域（２４）を有し、前記非形成領域（２４）は、前記端子（１３）の位置から前記基板（２０）のエッジ（２０ａ）の位置まで連続している。

Description

半導体装置、及び撮像モジュール
　本発明は、半導体装置、及び撮像モジュールに関する。
　本願は、２０１４年１月１４日に日本に出願された特願２０１４－００４３５２号に基づき優先権を主張し、その内容をここに援用する。
　従来から固体撮像素子などの半導体装置は、例えば、チップサイズパッケージ（ＣＳＰ）として製造され、配線基板に実装されて、撮像モジュールなどの各種デバイスに利用されている。このような半導体装置は、バンプ電極などの端子および配線が形成された端子面を有し、この端子面が接着剤などで配線基板に接着され、半導体装置は、配線基板に実装される（例えば、下記の特許文献１、２参照）。
　一般的に、半導体装置には端子面には、半導体装置の表面の配線と配線基板の表面の配線との短絡を避けるために、絶縁性のオーバーコート層が設けられる。このオーバーコート層を形成するには、例えば、端子および配線を覆う絶縁膜を端子面のほぼ全面にわたって形成し、この絶縁膜に端子を露出させる開口を形成する。この開口は、開口と端子との位置誤差、寸法誤差に対してマージンを取るように、端子と開口の内縁との間に形成されるギャップを含むように、端子を環状に囲むように形成される。
日本国特開２００９－２７７８８３号公報 日本国特開２００６－１９１１２６号公報
　上述のような半導体装置においては、接着剤などを利用して半導体装置を実装される際に、端子とオーバーコート層の開口の内縁との間のギャップに気泡（ボイド）が残りやすい。このようなボイドは、温度変化に伴う膨張収縮により、電気的接続の破断、半導体装置と配線基板との接合部の破壊などの不具合の原因になりうる。このように、従来の半導体装置は、実装不良が発生することがありえる。本発明は、上記の事情に鑑み成されたものであって、実装不良の発生を抑制できる半導体装置、及び撮像モジュールを提供することを目的とする。
　本発明の第１態様の半導体装置は、デバイスに実装される半導体装置であって、第１面を有する基板と、前記基板の前記第１面に形成され、前記デバイスに接続される端子と、前記基板の前記第１面に形成され、前記端子に導通する第１配線と、前記第１配線の少なくとも一部を覆う誘電体層と、を備える。前記基板の前記第１面は、前記誘電体層が形成されていない非形成領域を有し、前記非形成領域は、前記端子の位置から前記基板のエッジの位置まで連続している。
　本発明の第１態様の半導体装置においては、前記基板は矩形状であり、前記非形成領域は、前記基板の４辺のうち前記端子に最も近い辺の少なくとも一部を含んでもよい。
　本発明の第１態様の半導体装置は、前記基板を貫通して前記第１配線に導通する導電部を備え、前記誘電体層は、前記導電部の少なくとも一部を覆ってもよい。
　本発明の第１態様の半導体装置においては、前記誘電体層の一部は、前記基板のエッジを示すアライメントマークとして形成されてもよい。
　本発明の第１態様の半導体装置においては、前記基板は、互いに直交する第１辺および第２辺を含む矩形状であり、前記アライメントマークは、前記第１辺に平行な辺および前記第２辺に平行な辺を有してもよい。
　本発明の第１態様の半導体装置は、入射光を電力に変換する光電変換層を備え、前記基板の前記第１面に前記端子を含む複数の端子が配置され、前記光電変換層は、前記複数の端子のうちいずれかの端子と電気的に接続されてもよい。
　本発明の第２態様の撮像モジュールは、第１態様の半導体装置と、前記半導体装置の前記第１面に形成された接着層と、前記接着層を介して前記半導体装置が接着され、前記半導体装置の前記端子と接続された第２配線を有する配線基板とを備える。
　本発明の第２態様の撮像モジュールにおいては、前記半導体装置の前記非形成領域は、平面視した前記基板の前記第１面のうち前記半導体装置の前記端子が前記配線基板と接続される箇所と重なる位置、に配置されてもよく、平面視した前記基板の前記第１面のうち前記半導体装置の前記第１配線が前記配線基板の前記第２配線と重ならない位置に配置されてもよい。
　本発明の態様によれば、実装不良の発生を抑制できる半導体装置、及び撮像モジュールを提供することができる。
本発明の実施形態に係る半導体装置を搭載した光学装置を示す図である。 撮像素子（半導体装置）の端子面を示す図である。 図２のＡ－Ａ’線に沿う撮像素子及び配線基板の断面図である。 本発明の第１変形例の半導体装置を示す図である。 アライメントマークの利用例を説明するための説明図である。 本発明の第２変形例の半導体装置を示す図である。 本発明の第３変形例の半導体装置を示す図である。 本発明の第４変形例の半導体装置を示す図である。
　図１は、本実施形態に係る半導体装置を搭載した光学装置１を示す図である。本実施形態において、半導体装置２は、ＣＭＯＳセンサー、ＣＣＤセンサー等のイメージセンサー（以下、撮像素子ともいう）である。光学装置１（デバイス）は、半導体装置２が取得した画像データを出力する撮像モジュールの少なくとも一部であり、例えば、内視鏡などの狭い空間で使用される装置に利用される。
　光学装置１は、撮像モジュール３と、撮像モジュール３に対する光入射側に設けられたレンズユニット４と、撮像モジュール３を収容するケース５と、撮像モジュール３の撮像結果を出力するケーブル６と、を備える。撮像モジュール３は、半導体装置２（以下、撮像素子２ともいう）、及び撮像素子２が実装された配線基板７を備える。
　光学装置１は、撮像対象から得られた（反射された）光Ｌを、レンズユニット４を介して撮像素子２で受光する。また、光学装置１は、撮像素子２が撮像した結果を示す画像データを、配線基板７およびケーブル６を介して外部へ出力する。ケーブル６は、例えば、画像表示装置、記憶装置、画像処理装置などに接続されている。ユーザーは、撮像対象を撮像した画像を、画像表示装置に表示させること、記憶装置に記憶させること、画像処理装置に処理させること等ができる。
　レンズユニット４は、例えば、１又は２以上のレンズと、レンズを保持する鏡筒とを含む。レンズユニット４は、撮像対象物の像を撮像素子２の受光面１０に形成する。レンズユニット４の光軸を撮像素子２の受光面１０に対して位置合わせされた状態で、レンズユニット４と撮像素子２との相対位置が固定されている。ケース５は、例えば、金属製の筒状であり、金属筒の内部に、レンズユニット４が取り付けられた撮像モジュール３（レンズ付き撮像モジュール）を収容している。
　配線基板７は、例えば、フレキシブルプリント基板などのように、可撓性を有する基板である。配線基板７の片面は、配線が形成された配線面１１である。配線基板７は、配線面１１を外側に向けて、配線基板７の両端部を合せるように折り返されている。
　配線基板７の一端部（第一端部）および他端部（第二端部）は、配線面１１の反対側の面が互いに接合された接合部を構成する。この接合部は、ケース５の軸方向に延びており、例えば、ケース５の内壁に絶縁性の樹脂などで固定される。配線基板７の中央部は、配線基板７の折り返し部分であり、図１においては配線基板７の側方から見て略三角形状である。この三角形の底辺に相当する配線基板７の部分は、ほぼ平面状に形成されており、撮像対象からの光が入射するケース５の開口に向けて配置されている。このような配線基板７の平面状の部分には、撮像素子２が実装されている。
　撮像素子２は、例えば、チップサイズパッケージ技術を利用して製造されたＣＭＯＳセンサーである。撮像素子２は、撮像対象物からの光Ｌがレンズユニット４を介して入射する機能面１２（保護基板２６の面、第２面）と、機能面１２の反対を向いており複数の端子１３が配置された端子面１４（基板の一方の面、第１面）とを有する。撮像素子２は、撮像対象からの光が入射するケース５の開口に機能面１２を向けて、配置されている。撮像素子２は、撮像素子２の端子面１４を配線基板７の配線面１１に向けて、配線基板７に実装されている。複数の端子１３は、それぞれ、配線基板７の配線面１１に設けられた配線と電気的に接続されており、複数の端子１３は、この配線を介してケーブル６内の導体と電気的に接続されている。
　図２は撮像素子２の端子面１４を示す図である。図２に示すように、撮像素子２は、基板２０と、基板２０の端子面１４に形成された端子１３と、端子１３に導通する配線２１（第１配線）と、配線２１の少なくとも一部を覆う誘電体層２２とを備える。
　本実施形態において、端子面１４には、撮像素子２の内部に通じる導電部２３が形成されている。導電部２３は、配線２１に導通しており、配線２１を介して端子１３と電気的に接続されている。図２には、複数（本実施形態では４つ）の導電部２３、及び複数（本実施形態では４つ）の端子１３が図示されており、端子１３は、導電部２３と１対１で対応している。また、１つの配線２１と、この配線２１と対応関係にある１つの導電部２３と、この配線２１と対応関係にある端子１３とによって、一つの組、即ち、1つの系統（配線系統）が形成されている。図２には複数（本実施形態では４つ）の系統の配線が図示されている。
　端子面１４の一部は、誘電体層２２が形成されていない非形成領域２４である。
　非形成領域２４は、端子１３の位置から基板２０のエッジ２０ａの位置まで連続している。すなわち、配線基板７に実装されていない状態の撮像素子２においては、基板２０の端面（側方）から端子１３を見た場合に、端子１３は、非形成領域２４を介して基板２０の外側の雰囲気に曝されており、即ち、大気雰囲気に露出している（大気開放）。本実施形態において、基板２０は、互いに直交する第１辺および第２辺を含む矩形板状である。非形成領域２４は、端子１３の位置から、基板２０の４辺のうち端子１３に最も近い辺（エッジ２０ａ）まで連続している。
　換言すると、非形成領域２４においては、端子１３の位置から基板２０のエッジ２０ａの位置までの間の空間を遮るような突起物や壁等といった構造物が形成されていない。非形成領域２４は、端子１３を囲み、かつ、端子１３から基板２０の外側へ通じる空間を形成する領域であると言える。
　図３は、図２のＡ－Ａ’線に沿う位置における撮像素子２及び配線基板７の断面図である。図３の撮像素子２は、基板２０に設けられた素子層２５と、素子層２５上に設けられ光Ｌが通る保護基板２６とを含む。保護基板２６は、例えば、透光性を有するガラス基板であり、基板２０の端子面１４の反対側の面に対向するように設けられている。基板２０及び保護基板２６によって素子層２５は挟持されている。
　素子層２５は、保護基板２６を通った光Ｌを受光する受光面１０を有する。撮像素子２は、複数の画素を有し、受光面１０には画素ごとに光電変換層５０が配置されている。光電変換層５０は、入射光を電力に変換する機能を有し、複数の端子１３のうちいずれかの端子と電気的に接続されている。光電変換層５０は、半導体材料で形成されており、光電変換層５０には入射した光Ｌの光電効果により電荷が発生する。すなわち、光電変換層５０は、撮像素子２において端子面１４と反対側の機能面１２に入射する光Ｌを電力に変換する。
　素子層２５には、各画素の光電変換層５０に発生した電荷を読み出す読出回路２７が設けられている。読出回路２７は、各画素に設けられたスイッチング素子、及び配線などを含む。素子層２５には、読出回路２７を構成する配線およびスイッチング素子の他に、層間絶縁膜、平坦化膜、パッシベーション膜などが設けられる。また、素子層２５に、各画素の光電変換層５０から読み出された電荷を示すアナログ信号を増幅するアンプ、このアナログ信号をデジタル信号へ変換するＡＤ変換器などが設けられていてもよい。
　光電変換層５０は、基板２０及び保護基板２６の間に設けられ、例えば、撮像素子２の受光面１０に近い位置に設けられている。光電変換層５０は、素子層２５の内部に設けられてもよい。
　読出回路２７は、導電部２３と電気的に接続されている。すなわち、各画素の光電変換層５０は、読出回路２７を介して導電部２３と電気的に接続されている。導電部２３は、いわゆる貫通電極（ＴＳＶ；Ｔｈｒｏｕｇｈ　Ｓｉｌｉｃｏｎ　Ｖｉａ）であり、基板２０を貫通しているとともに一部が端子面１４上に引き出されている。導電部２３の少なくとも一部は、端子面１４上に設けられた配線２１を製造するプロセスと同じプロセスによって一括して（すなわち同一材料で）形成されていてもよいし、配線２１とは別に形成されていてもよい。
　端子１３は、はんだバンプ、スタッドバンプ、めっきバンプ等のバンプ電極であり、基板２０の端子面１４から外部に向かって突起する凸形状（突起形状）を有する。端子１３は、端子面１４の法線方向において、誘電体層２２よりも突出している。即ち、端子面１４から誘電体層２２の上面までの距離（誘電体層２２の厚さ）よりも、端子面１４から端子１３の上面（頂部）までの距離（端子１３の高さ）が大きい。端子１３は、配線２１に接して形成されており、配線２１と導通する。また、端子１３は、配線基板７の配線面１１に設けられた配線２８（第２配線）とも接しており、配線２８と導通する。
　誘電体層２２は、端子１３を介した配線２１と配線２８との電気的な接続部２９を避けて、形成されている。また、誘電体層２２は、撮像素子２の端子面１４上に設けられた配線２１と、配線基板７の配線面１１上に設けられた配線２８とのうち、互いに対応関係にある配線間の短絡を防止するように設けられている。以下、詳しく説明する。
　ここで、説明の便宜上、撮像素子２の端子面１４に設けられている複数の配線２１のうち１系統の配線を第１のチップ側配線、他の系統の配線を第２のチップ側配線という。同様に、配線基板７の配線面１１に設けられている複数の配線２８のうち１系統の配線を第１の基板側配線、他の系統の配線を基板側配線という。また、第１のチップ側配線が複数の端子１３のうちの１つを介して第１の基板側配線と電気的に接続され、第２のチップ側配線が複数の端子１３のうちの１つを介して第２の基板側配線と電気的に接続されている場合について説明する。
　誘電体層２２は、端子面１４を平面視した状態において、第１のチップ側配線と第１の基板側配線とが重なり合う領域（例えば、図３の接続部２９）には形成されていない。また、誘電体層２２は、平面視した端子面１４のうち少なくとも、第１のチップ側配線と、第１のチップ側配線の対応関係にない第２の基板側配線とが重なり合う領域に設けられる。同様に、端子面１４を平面視した状態において、第２のチップ側配線と第１の基板側配線とが重なり合う場合には、その重なり合う領域にも誘電体層２２が設けられる。
　換言すると、非形成領域２４は、平面視した基板２０の端子面１４のうち端子１３が配線基板７との接続される箇所（端子１３と配線２８とが接続される箇所）と重なる位置、に配置されている。平面視した基板２０の端子面１４のうち配線２１が配線基板の第２配線と重ならない位置に配置されている。
　即ち、図２に示した誘電体層２２が形成されていない非形成領域２４は、端子面１４を平面視した場合に、撮像素子２の配線２１のうちの第１配線（特定の配線）と、配線基板７の配線２８のうち第１配線（特定の配線）と対応関係にない第２配線とが重なり合わない領域を含むように（第１配線と、第１配線と対応関係にない第２配線とが重なり合わない領域を介して）、端子１３の位置から基板２０のエッジの位置まで連続している。
　このように、撮像素子２は、電気信号が供給される第１の導体（配線２１および端子１３）を有し、配線基板７は、第１の導体と電気的に接続される第２の導体（配線２８の１つ）と、第１の導体と絶縁とされる第３の導体（他の配線２８）とを有している。平面視した端子面１４のうち、第１の導体と第３の導体とが重なり合う領域には、誘電体層２２が形成されている。非形成領域２４は、第１の導体と第２の導体とが重なり合う領域から基板２０のエッジ２０ａまで連続している。
　以上のような構成の撮像素子２は、以下のような方法で配線基板７に実装される。まず、配線基板７の配線面１１上に、流動性を有する絶縁性の樹脂（ＮＣＰ；Ｎｏｎ－ｃｏｎｄｕｃｔｉｖｅ　Ｐａｓｔｅ）を塗布する。そして、撮像素子２の保護基板２６をフリップチップホルダー等で保持し、撮像素子２の端子１３と配線基板７の配線２８とを位置合わせしながら、撮像素子２の端子面１４を配線基板７の配線面１１に向けて、撮像素子２を配線基板７に押し付ける。そして、端子１３と配線２８とが接触した状態を維持しつつＮＣＰを硬化させて、撮像素子２を配線基板７と接着する。これにより、撮像素子２の端子１３が配線基板７の配線２８と電気的に接続されるとともに、撮像素子２が配線基板７に固定される。なお、硬化したＮＰＣは、図３の接着層３０になる。
　ところで、一般的な半導体装置において、端子面上に設けられた配線を覆うオーバーコート層は、端子を環状に囲む隔壁状に形成され、端子は、オーバーコート層の開口の内側に配置される。この開口は、開口と端子との位置誤差などを考慮して、開口の内縁と端子の外縁との間にギャップを有するように形成される。このような半導体装置を配線基板に接着剤で実装すると、開口の内縁と端子の外縁との間のギャップ内に、実装工程の雰囲気ガスが取り残され、ボイドが発生しやすい。このようなボイドは、温度変化に伴う膨張伸縮により、電気的接続の破断、半導体装置と配線基板との接合部の破壊などの不具合の原因になりうる。
　本実施形態に係る撮像素子２（半導体装置）は、配線基板７に実装される際に、撮像素子２と配線基板７との間のガスが、非形成領域２４を通って、基板２０のエッジ２０ａ（図３参照）から外部へ排出されやすい。その結果、実装後の撮像素子２と配線基板７との間におけるボイドの発生が低減され、ボイドの膨張収縮による破損等の発生が抑制される。また、ボイドの発生が低減されることにより、撮像素子２と配線基板７との接着面積が確保され、撮像素子２を配線基板７と接着力が高くなる。このように、本実施形態に係る撮像素子２は、実装不良の発生を抑制できる。
　本実施形態において、誘電体層２２が形成されていない非形成領域２４は、基板２０の４辺のうち端子１３に最も近い辺の少なくとも一部を含んでいる。そのため、撮像素子２を配線基板７に実装する際に、撮像素子２と配線基板７との間から雰囲気ガスが外部へ逃げやすく、ボイドが格段に低減される。
　本実施形態において、誘電体層２２は、基板２０を貫通して配線２１に導通する導電部２３の少なくとも一部を覆っている。そのため、撮像素子２と配線基板７に設けられた配線等との短絡を防止しながら、撮像素子２と配線基板７との間のボイドの発生を低減できる。
　また、上述のような撮像素子２を備えた本実施形態に係る撮像モジュール３によれば、撮像素子２の実装不良が抑制され、耐久性を向上するとともに、撮像素子２の実装不良に起因する動作不良を抑制できる。
＜変形例＞
　次に、変形例について説明する。変形例において上記の実施形態と共通する構成については、同じ符号を付してその説明を簡略化あるいは省略する。
　図４は、第１変形例に係る半導体装置２を示す図である。図４の半導体装置２は、端子面１４に形成されたアライメントマーク３１を備える。このアライメントマーク３１は、誘電体層２２の一部であり、誘電体層２２のうち配線２１を覆う部分と同じ材料で形成されている。アライメントマーク３１は、基板２０のエッジを示している。第１変形例では、基板２０が矩形状であり、アライメントマーク３１は、基板２０の第１辺２０ｂに平行な辺３１ｂと、基板２０の第２辺２０ｃに平行な辺３１ｃとを有する。
　このような誘電体層２２は、例えば、以下のように形成される。誘電体層２２を形成するには、端子面１４に端子１３および配線２１が形成された状態で、端子１３および配線２１を覆う絶縁膜を、端子面１４の全面に形成する。そして、この絶縁膜のうち、配線２１を覆う部分とアライメントマーク３１に相当する部分とを残し、かつ、非形成領域２４の部分を除去するように、この絶縁膜をパターニングする。このようにして、アライメントマーク３１は、誘電体層２２のうち配線２１を覆う部分と同じプロセスで一括して形成される。
　次に、アライメントマーク３１の利用例を説明する。図５は、アライメントマーク３１の利用例を説明するための説明図である。図５は、半導体装置２の製造に利用されるウエハーＷを示す平面図（ＰＡＲＴ（ａ））と、ウエハーＷの一部を示す拡大平面図（ＰＡＲＴ（ｂ））である。
　上述のような半導体装置２は、ウエハーＷの複数のチップ領域Ｗ１のそれぞれに、半導体装置２を構成する導体、半導体、及び絶縁体を形成した後、チップ領域Ｗ１をダイシング（個片化）することで、製造される。アライメントマーク３１は、例えば、ウエハーＷをダイシングする際に、半導体装置２のエッジを示す識別マークとして機能し、ダイシングカッターとウエハーＷとの位置合わせなどに利用される。このような半導体装置２は、誘電体層２２のうち配線２１を覆う部分を形成するプロセスでアライメントマーク３１を形成可能であるので、アライメントマークを別のプロセスで形成するよりも生産性が高い。
　図６Ａは、第２変形例に係る半導体装置２を示す図である。本変形例において、端子面１４には６つの端子１３が設けられている。誘電体層２２は、４つの端子１３に対応する４つの配線２１を覆う部分２２ａと、１つの端子１３に対応する配線２１を覆う部分２２ｂと、他の１つの端子１３に対応する配線２１を覆う部分２２ｃとを含む。部分２２ａ、部分２２ｂ、及び部分２２ｃは、それぞれ、非形成領域２４を介して他の部分から分離されている。ここでは、非形成領域２４は、基板２０の４辺のうちの３辺と連続している。
　図６Ｂは、第３変形例に係る半導体装置２を示す図である。本変形例において、端子面１４には８つの端子１３が設けられている。誘電体層２２は、４つの端子１３に対応する４つの配線２１を覆う部分２２ｄと、他の４つの端子１３に対応する配線２１を覆う部分２２ｅとを含む。部分２２ｅは、非形成領域２４を介して部分２２ｄから分離されている。ここでは、非形成領域２４は、基板２０の４辺のうちの２辺と連続している。
　図６Ｃは、第４変形例に係る半導体装置２を示す図である。本変形例において、端子面１４には４つの端子１３が設けられている。４つの端子１３に対応するように、４つの誘電体層２２が島状に形成されている。これら４つの部分（島状の誘電体層）は、非形成領域２４を介して互いに離れている。ここでは、非形成領域２４は、基板２０の４辺と連続している。
　図６Ａ～図６Ｃを参照して説明したように、本実施形態に係る半導体装置２において、端子１３の数に限定はなく、複数の端子１３の配置パターンについても限定はない。
　また、非形成領域２４は、複数の端子１３のうち少なくとも１つの端子１３の位置から基板２０のエッジ２０ａの位置まで連続してればよく、例えば、いずれかの端子１３については、その周囲を環状に囲むように誘電体層２２が形成されていてもよい。また、誘電体層２２は、２以上の配線２１にまたがって形成される部分を含んでいてもよいし、１つの配線２１のみを覆う部分を含んでいてもよい。基板２０が矩形状である場合に、非形成領域２４は、基板２０の１辺のみと連続していてもよいし、２辺、３辺、あるいは４辺のいずれと連続していてもよい。また、誘電体層２２が複数の島状の部分を含む場合に、端子面１４を平面視した島状の部分の各々の平面形状は、特定に形状に限定されず、島状の部分の形状は、多角形、楕円形、自由曲線に囲まれる形状、直線および曲線に囲まれる形状のいずれでもよい。また、複数の島状の部分の平面形状が互いに異なっていてもよいし、複数の島状の部分のうち２以上が同一の平面形状であってもよい。
　本発明の好ましい実施形態あるいは変形例を説明し、上記で説明してきたが、これらは本発明の例示的なものであり、限定するものとして考慮されるべきではないことを理解すべきである。追加、省略、置換、およびその他の変更は、本発明の範囲から逸脱することなく行うことができる。上記の実施形態あるいは変形例で説明した要素は、適宜組み合わせることができる。従って、本発明は、前述の説明によって限定されていると見なされるべきではなく、請求の範囲によって制限されている。
　上述の実施形態においては、半導体装置２が撮像素子である場合について説明したが、半導体装置２は撮像素子以外の半導体装置、例えば、太陽光発電装置などであってもよい。また、撮像モジュール３は、内視鏡以外の各種光学装置にも適用できる。また、半導体装置２は、基板２０を貫通する導電部２３が設けられていなくても構わない。例えば、基板２０の端子面１４の所定位置に半導体を利用した回路部品が形成されており、配線２１は、この回路部品を含む処理部と端子１３とを電気的に接続していてもよい。
１　光学装置、２　撮像素子（半導体装置）、３　撮像モジュール、７　配線基板、１２　機能面（保護基板の面、第２面）、１３　端子、１４　端子面（基板の一方の面、第１面）、２０　基板、２０ａ　エッジ、２０ｂ　第１辺、２０ｃ　第２辺、２１　配線（第１配線）、２２　誘電体層、２３　導電部、２４　非形成領域、２６　保護基板、２８　配線基板の配線（第２配線）、３１　アライメントマーク、５０　光電変換層

Claims (8)

  1. 　デバイスに実装される半導体装置であって、
    　第１面を有する基板と、
    　前記基板の前記第１面に形成され、前記デバイスに接続される端子と、
    　前記基板の前記第１面に形成され、前記端子に導通する第１配線と、
    　前記第１配線の少なくとも一部を覆う誘電体層と、を備え、
    　前記基板の前記第１面は、前記誘電体層が形成されていない非形成領域を有し、
    　前記非形成領域は、前記端子の位置から前記基板のエッジの位置まで連続している半導体装置。
  2. 　前記基板は矩形状であり、
    　前記非形成領域は、前記基板の４辺のうち前記端子に最も近い辺の少なくとも一部を含む
    　請求項１に記載の半導体装置。
  3. 　前記基板を貫通して前記第１配線に導通する導電部を備え、
    　前記誘電体層は、前記導電部の少なくとも一部を覆っている
    　請求項１又は請求項２に記載の半導体装置。
  4. 　前記誘電体層の一部は、前記基板のエッジを示すアライメントマークとして形成されている
    　請求項１から請求項３のいずれか一項に記載の半導体装置。
  5. 　前記基板は、互いに直交する第１辺および第２辺を含む矩形状であり、
    　前記アライメントマークは、前記第１辺に平行な辺および前記第２辺に平行な辺を有する
    　請求項４に記載の半導体装置。
  6. 　入射光を電力に変換する光電変換層を備え、
    　前記基板の前記第１面に前記端子を含む複数の端子が配置され、
    　前記光電変換層は、前記複数の端子のうちいずれかの端子と電気的に接続されている
    　請求項１から請求項５のいずれか一項に記載の半導体装置。
  7. 　請求項６に記載の半導体装置と、
    　前記半導体装置の前記第１面に形成された接着層と、
    　前記接着層を介して前記半導体装置が接着され、前記半導体装置の前記端子と接続された第２配線を有する配線基板と、を備える撮像モジュール。
  8. 　前記半導体装置の前記非形成領域は、平面視した前記基板の前記第１面のうち前記半導体装置の前記端子が前記配線基板と接続される箇所と重なる位置、に配置され、
    　平面視した前記基板の前記第１面のうち前記半導体装置の前記第１配線が前記配線基板の前記第２配線と重ならない位置に配置されている
    　請求項７に記載の撮像モジュール。
PCT/JP2014/084252 2014-01-14 2014-12-25 半導体装置、及び撮像モジュール WO2015107849A1 (ja)

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Publication number Priority date Publication date Assignee Title
JP2009158862A (ja) * 2007-12-27 2009-07-16 Toshiba Corp 半導体パッケージ
JP2009212481A (ja) * 2007-04-27 2009-09-17 Sharp Corp 半導体装置及び半導体装置の製造方法
JP2010278040A (ja) * 2009-05-26 2010-12-09 Renesas Electronics Corp 半導体装置の製造方法および半導体装置

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009212481A (ja) * 2007-04-27 2009-09-17 Sharp Corp 半導体装置及び半導体装置の製造方法
JP2009158862A (ja) * 2007-12-27 2009-07-16 Toshiba Corp 半導体パッケージ
JP2010278040A (ja) * 2009-05-26 2010-12-09 Renesas Electronics Corp 半導体装置の製造方法および半導体装置

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