WO2015085825A1 - 一种频率校准方法及装置 - Google Patents

一种频率校准方法及装置 Download PDF

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Publication number
WO2015085825A1
WO2015085825A1 PCT/CN2014/088791 CN2014088791W WO2015085825A1 WO 2015085825 A1 WO2015085825 A1 WO 2015085825A1 CN 2014088791 W CN2014088791 W CN 2014088791W WO 2015085825 A1 WO2015085825 A1 WO 2015085825A1
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control word
calibrated
clock
hopping
count value
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PCT/CN2014/088791
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English (en)
French (fr)
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许应新
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炬芯（珠海）科技有限公司
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Publication of WO2015085825A1 publication Critical patent/WO2015085825A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

Definitions

  • the present application relates to the field of integrated circuit technologies, and in particular, to a frequency calibration method and apparatus.
  • Automatic frequency control is an automatic control method that keeps the output signal frequency in a certain relationship with a given frequency. It is widely used in electronic equipment for frequency stabilization or phase locking. Specifically used in the Phase Locked Loop (PLL), the PLL output clock with little deviation from the reference clock is frequency-calibrated, so that the PLL outputs a more accurate clock.
  • PLL Phase Locked Loop
  • a common automatic frequency control method in PLL is to digitally control the oscillator capacitance to adjust the oscillation frequency of the oscillator.
  • a counter can be used to compare the clock frequency to be calibrated (ie, the oscillation frequency of the oscillator) with the reference clock frequency, and accordingly adjust the output control word for controlling the oscillator capacitance according to the comparison result, thereby adjusting the oscillation frequency.
  • the reference clock and the clock to be calibrated are counted simultaneously for a period of time.
  • the clock to be calibrated is considered to be slow, and the output control word is adjusted to decrement the control word by 1, thereby speeding up the calibration.
  • the frequency of the clock Conversely, if the clock counter to be calibrated reaches the preset value first, the clock to be calibrated is considered to be faster, and the output control word is adjusted to increase the control word by one. Repeat the calibration according to this method until the calibration clock is equal to the reference clock.
  • the existing automatic frequency control has the following problems:
  • the counting time of the counter is relatively long: the output control word is adjusted when one of the counters counts to a predetermined value, and the analysis from the circuit shows that the predetermined value is not well determined, because if the predetermined value is set too small, the accuracy of the frequency adjustment will be affected. degree. If the preset value is set too large, the frequency adjustment time is increased.
  • the control word can only be jumped by adding 1 or subtracting 1.
  • the jump mode is not flexible, and the frequency adjustment efficiency is low.
  • the purpose of the present application is to provide a frequency calibration method and apparatus to solve the problem that the counter has a long counting time.
  • a frequency calibration method comprising:
  • the method provided by the embodiment of the present application compares two count values in real time. As long as the count values of the two counters are different, the control word can be output to adjust the frequency of the clock to be calibrated without affecting the accuracy of the frequency adjustment. Improve the efficiency of frequency adjustment.
  • the count value of the clock counter to be calibrated is compared with the count value of the reference clock counter in real time in the reference clock domain.
  • the format of the count value of the clock counter to be calibrated is converted from a binary number to a Gray code; in the reference clock domain, the count value of the clock counter to be calibrated converted to the Gray code is performed.
  • the delay for canceling the metastable state is converted into a binary number; in the reference clock domain, after the delay value of the clock counter to be calibrated converted to a binary number is used to control the timing delay, the same delay is performed.
  • the count value of the reference clock counter is compared.
  • the same delay refers to the delay performed by the count value of the reference clock counter, and the delay for canceling the metastable state and the delay for controlling the timing are the same as the count value of the clock counter to be calibrated.
  • the specific implementation manner of outputting the control word for adjusting the clock frequency to be calibrated according to the comparison result may be, but is not limited to: When the count value of the reference clock counter is greater than the count value of the clock counter to be calibrated but less than the preset count threshold, outputting a control word for raising the clock frequency to be calibrated; when the count value of the clock counter to be calibrated is When the count value of the reference clock counter is greater than the preset count threshold, the control word for lowering the clock frequency to be calibrated is output.
  • condition for outputting the control word for increasing the clock frequency to be calibrated further comprises: the count value of the reference clock counter is greater than the count value +1 of the clock counter to be calibrated; and the output is used to lower the clock to be calibrated
  • condition of the frequency control word further includes: the count value of the clock counter to be calibrated is greater than the count value +1 of the reference clock counter.
  • control word for adjusting the clock frequency to be calibrated when the control word for adjusting the clock frequency to be calibrated is output according to the comparison result, the control word for adjusting the clock frequency to be calibrated may be output by using a binary method according to the comparison result; or According to the comparison result, the control word for adjusting the clock frequency to be calibrated is output by using the 1/4 hopping method; or, according to the comparison result, the control word for adjusting the clock frequency to be calibrated is output by adding 2 minus 1 hopping method.
  • a plurality of control word hopping modes are set in advance, preferably, before outputting the control word for adjusting the clock frequency to be calibrated according to the comparison result, the following operations may be included: when the cumulative number of hops of the control word does not reach the maximum When the number of transitions is changed, according to the difference between the clock frequency to be calibrated and the reference clock frequency, the control word hopping mode adopted by the output control word is selected from the preset N kinds of control word hopping modes, wherein the larger the difference is The longer the jump step of the selected control word hopping mode, N is not small An integer of 2; correspondingly, outputting a control word for adjusting a clock frequency to be calibrated according to the comparison result may be: outputting a control for adjusting a clock frequency to be calibrated by using a selected control word hopping manner according to the comparison result word.
  • the clock stability waiting time corresponding to the selected control word hopping mode may be determined according to the corresponding relationship between the preset control word hopping mode and the clock stability waiting time to be calibrated, as This output control word adjusts the clock to be calibrated and waits for the clock to be calibrated to stabilize.
  • the longer the hopping step of the selected control word hopping mode, the longer the waiting time of the corresponding clock to be calibrated, or the longer the hopping step of the selected control word hopping mode, the corresponding clock to be calibrated The shorter the stabilization wait time.
  • the embodiment of the present application further provides a frequency calibration apparatus, including:
  • the control word output module is configured to output a control word for adjusting a clock frequency to be calibrated according to the comparison result when the count value of the clock counter to be calibrated is different from the reference clock counter.
  • the device provided by the embodiment of the present application can output a control word to adjust the frequency of the clock to be calibrated as long as the count values of the two counters are different, and improve the efficiency of the frequency adjustment without affecting the accuracy of the frequency adjustment.
  • the counting real-time comparison module is specifically configured to: compare the count value of the clock counter to be calibrated with the count value of the reference clock counter in real time in a reference clock domain.
  • the counting real-time comparison module is specifically configured to:
  • the count value of the clock counter to be calibrated converted to Gray code is used to cancel the metastable delay and then convert to a binary number
  • the delay value of the clock counter to be calibrated converted to a binary number is used to control the timing delay, it is compared with the count value of the reference clock counter that has performed the same delay.
  • the same delay refers to the delay performed by the count value of the reference clock counter, and the delay for canceling the metastable state and the delay for controlling the timing are the same as the count value of the clock counter to be calibrated.
  • control word output module is specifically configured to:
  • condition for outputting the control word for increasing the clock frequency to be calibrated further comprises: the count value of the reference clock counter is greater than the count value +1 of the clock counter to be calibrated; and the output is used to lower the Describe the calibration clock
  • the condition of the frequency control word further includes: the count value of the clock counter to be calibrated is greater than the count value +1 of the reference clock counter.
  • control word output module is configured to: output a control word for adjusting a clock frequency to be calibrated by using a binary method according to the comparison result; or output a 1/4 hop method according to the comparison result.
  • a control word for adjusting the clock frequency to be calibrated; or, according to the comparison result, a control word for adjusting the clock frequency to be calibrated is output by adding 2 minus 1 hopping.
  • the control word output module may be further configured to: when the cumulative number of jumps of the control word is not When the maximum number of jumps is reached, the control word hopping mode used for outputting the control word is selected from the preset N kinds of control word hopping manners according to the difference between the clock frequency to be calibrated and the reference clock frequency, wherein The larger the difference is, the longer the hopping step of the selected control word hopping mode is, and the N is an integer not less than 2; correspondingly, when the control word for adjusting the clock frequency to be calibrated is output according to the comparison result, The control word output module is configured to: output a control word for adjusting a clock frequency to be calibrated by using a selected control word hopping manner according to the comparison result.
  • a waiting time determining module may be further included, after the control word output module selects the control word hopping mode, according to a preset control word hopping manner and a clock stability waiting time to be calibrated Determining the clock stabilization waiting time to be calibrated corresponding to the selected control word hopping mode, as the output control word adjusts the clock frequency to be calibrated and waits for the clock to be calibrated to be stable; wherein, the selected control word hopping mode jumps The longer the step size is, the longer the corresponding clock stabilization wait time is to be calibrated, or the longer the jump step size of the selected control word hopping mode, the shorter the waiting time for the corresponding clock to be calibrated.
  • Another object of the present application is to provide a frequency calibration method and apparatus to solve the problem that the control word hopping mode is inflexible and the frequency adjustment efficiency is low.
  • a frequency calibration method comprising:
  • a control word hopping mode is selected from the preset N control word hopping modes.
  • N is an integer not less than 2;
  • the control word for adjusting the clock frequency to be calibrated is outputted by using the selected control word hopping mode.
  • the method provided by the embodiment of the present application flexibly selects an appropriate control word hopping mode according to the difference between the clock frequency to be calibrated and the reference clock frequency.
  • the difference is larger, the longer the jump step of the selected control word hopping mode, the number of adjustments of the clock to be calibrated can be reduced, and the adjustment efficiency is improved.
  • the clock to be calibrated corresponding to the selected control word hopping mode is determined according to the corresponding relationship between the preset control word hopping mode and the clock stability waiting time to be calibrated. Waiting time As the output control word adjusts the clock frequency to be calibrated and waits for the clock to be calibrated to stabilize; wherein the longer the hopping step of the selected control word hopping mode, the longer the waiting time of the corresponding clock to be calibrated is. Alternatively, the longer the jump step of the selected control word hopping mode, the shorter the waiting time for the corresponding clock to be calibrated.
  • the embodiment of the present application further provides a frequency calibration apparatus, including:
  • a counting comparison module configured to compare a count value of the clock counter to be calibrated with a count value of the reference clock counter
  • the control word hopping mode selection module is configured to hop from the preset N kinds of control words according to the difference between the clock frequency to be calibrated and the reference clock frequency when the number of accumulated hops of the control word does not reach the maximum hopping number Selecting a control word hopping mode, wherein the larger the difference, the longer the hopping step of the selected control word hopping mode, and the N is an integer not less than 2;
  • the control word output module is configured to output a control word for adjusting the clock frequency to be calibrated by using a selected control word hopping manner according to a comparison result between the count value of the clock counter to be calibrated and the count value of the reference clock counter.
  • the device provided in the embodiment of the present application flexibly selects an appropriate control word hopping mode according to the difference between the clock frequency to be calibrated and the reference clock frequency.
  • the difference is larger, the longer the jump step of the selected control word hopping mode, the number of adjustments of the clock to be calibrated can be reduced, and the adjustment efficiency is improved.
  • the method further includes a waiting time determining module, configured to, after the control word hopping mode selection module selects the control word hopping mode, according to a preset control word hopping manner and a clock stability waiting time to be calibrated Relationship, determining the clock stabilization waiting time to be calibrated corresponding to the selected control word hopping mode, as the output control word adjusts the clock frequency to be calibrated and waits for the clock to be calibrated to be stable; wherein, the selected control word hopping mode The longer the hopping step is, the longer the waiting time for the clock to be calibrated is stable, or the longer the hopping step of the selected control word hopping mode, and the shorter the waiting time for the corresponding clock to be calibrated.
  • a waiting time determining module configured to, after the control word hopping mode selection module selects the control word hopping mode, according to a preset control word hopping manner and a clock stability waiting time to be calibrated Relationship, determining the clock stabilization waiting time to be calibrated corresponding to the selected control word hopping mode, as the
  • FIG. 1 is a schematic diagram of a frequency calibration method according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a real-time comparison processing process provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a dichotomy hopping provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a first frequency calibration apparatus according to an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a frequency calibration circuit according to an embodiment of the present application.
  • FIG. 6 is a schematic diagram of another frequency calibration method according to an embodiment of the present application.
  • FIG. 7 is a schematic diagram of another frequency calibration apparatus according to an embodiment of the present application.
  • a frequency calibration method provided by the embodiment of the present application is as shown in FIG. 1 , and specifically includes the following operations:
  • Step 100 Compare the count value of the clock counter to be calibrated with the count value of the reference clock counter in real time.
  • Step 110 When the count value of the clock counter to be calibrated is different from the reference clock counter, output a control word for adjusting the clock frequency to be calibrated according to the comparison result.
  • the control word can be output to adjust the frequency of the clock to be calibrated, and the efficiency of the frequency adjustment is improved without affecting the accuracy of the frequency adjustment.
  • the two clocks are asynchronous clocks.
  • asynchronous clocks need to be compared in real time in the same clock domain.
  • the two clocks are preferably compared in real time in the reference clock domain.
  • the two clocks can also be compared in real time in the clock domain to be calibrated.
  • the same delay refers to the delay performed by the count value of the reference clock counter, and the delay for canceling the metastable state and the delay for controlling the timing are the same as the count value of the clock counter to be calibrated.
  • the count value of the clock counter to be calibrated converted to the Gray code is subjected to two beat delays, and the count value of the clock counter to be calibrated converted to a binary number is subjected to one beat delay.
  • the processing of the above real-time comparison is as shown in FIG. 2.
  • the purpose of converting the binary number into the Gray code is to avoid a state error after converting the count value of the clock to be calibrated to the reference clock domain.
  • the delay is realized by the flip-flop. After the first-level flip-flop and the second-level flip-flop, the count value of the clock counter to be calibrated realizes two beat delays, and the purpose is to eliminate metastability.
  • the count value of the clock counter to be calibrated is converted to a binary number for comparison with the count value of the reference clock counter.
  • the purpose of implementing a beat delay via a three-level flip-flop is for timing considerations.
  • the count value of the reference clock counter is also subjected to three-shot delay processing.
  • the specific implementation manner of outputting the control word for adjusting the clock frequency to be calibrated according to the comparison result may be, but is not limited to, when the reference clock counter is used.
  • the count value is greater than the count value of the clock counter to be calibrated, but is smaller than the preset count threshold, and the output is used.
  • the embodiment of the present application introduces a counting threshold. When the counting threshold has not been determined, the real-time comparison will be terminated (ie, the frequency calibration is stopped).
  • the accuracy of the real-time comparison result is affected.
  • the control word is output according to the comparison result, the count value of the slow clock counter is incremented by one.
  • the condition for outputting the control word for increasing the clock frequency to be calibrated further includes: the count value of the reference clock counter is greater than the count value +1 of the clock counter to be calibrated; and the output is used to lower the clock frequency to be calibrated.
  • the condition of the control word further includes: the count value of the clock counter to be calibrated is greater than the count value +1 of the reference clock counter.
  • control word for adjusting the clock frequency to be calibrated when the control word for adjusting the clock frequency to be calibrated is output according to the comparison result, the control word for adjusting the clock frequency to be calibrated may be output by using a binary method according to the comparison result; or According to the comparison result, the control word for adjusting the clock frequency to be calibrated is output by using the 1/4 hopping method; or, according to the comparison result, the control word for adjusting the clock frequency to be calibrated is output by adding 2 minus 1 hopping method.
  • control word hopping mode when the cumulative number of hops of the control word does not reach the maximum When the number of hops is changed, according to the difference between the clock frequency to be calibrated and the reference clock frequency, the control word hopping mode adopted by the output control word is selected from the preset N kinds of control word hopping modes, wherein the difference is Large, the longer the hopping step of the selected control word hopping mode, N is an integer not less than 2; correspondingly, the specific implementation manner of outputting the control word for adjusting the clock frequency to be calibrated according to the comparison result may be:
  • the comparison result uses the selected control word hopping mode to output a control word for adjusting the clock frequency to be calibrated.
  • the control word hopping mode may be a dichotomy hop, a 1/4 hopping method, a plus 2 minus one hopping method, a hopping method with a fixed step size of 1, and the like.
  • the value range of the difference value may be divided, and each value range corresponds to a control word hopping manner.
  • the selection order of the control word hopping mode may be: dichotomy hopping -> 1/4 hopping method -> adding 2 minus 1 hopping method -> hopping method with step length fixed to 1 .
  • the reference clock frequency is fixed, for example, 24 megahertz (MHz). Since the sampling times of the two count values of the real-time comparison are the same, the total duration of the two clocks is the same from the initial sampling time to the current sampling time.
  • the clock frequency to be calibrated can be obtained by the following formula:
  • Clock frequency to be calibrated reference clock frequency ⁇ count value of reference clock counter ⁇ count value of clock counter to be calibrated
  • the so-called dichotomy means that the control word jump step size outputted each time is 1/2 of the control word jump step size of the previous output.
  • the initial value of the control word is 5'b10000, and the initial jump step size is 8. If it is required to output a control word for raising the clock frequency to be calibrated, the control word jumps to a large value. If it is necessary to output a control word for lowering the clock frequency to be calibrated, the control word jumps to a small value.
  • Figure 3 shows the control word hopping process for two frequency calibrations completed with 4 hops. The so-called one jump, that is, the control word is output once.
  • the 1/4 hopping method means that the control word hopping step size outputted each time is 1/4 of the control word hopping step size of the previous output.
  • the so-called plus 2 minus 1 hopping method means that the control word hopping step size of each output is 2. For example, if the current control word is word, the next control word will be word+2 or word-2. If the control word is incremented or decremented by 2 or more, the count value of the clock counter to be calibrated is greater than (or less than). The count value of the reference clock counter becomes less than (or greater than) the count value of the reference clock counter, then the control word is decremented by 1 (or incremented by 1).
  • the jump step size of the control word refers to the difference between the control word outputted this time and the control word outputted last time.
  • the relationship between the stable latency of the PLL and the output clock span is not considered. Take the PLL with a larger output clock span and a longer stable wait time as an example. For scenarios where the output clock span changes, the existing stable wait time setting is not flexible enough.
  • the control word hopping may be determined according to the corresponding relationship between the preset control word hopping mode and the clock stability waiting time to be calibrated.
  • the clock stabilization waiting time corresponding to the variable mode is used as the time when the output control word adjusts the clock frequency to be calibrated and waits for the clock to be calibrated to be stable.
  • the PLL output clock span is larger, the stable waiting time is longer. Then, the longer the hopping step of the selected control word hopping mode, the longer the waiting time for the corresponding clock to be calibrated is stable. Since the conventional PLL has the larger span and the longer the stable waiting time in the same adjustment gear position, the implementation can not only effectively reduce the number of transitions, but also adjust the stable waiting time for this characteristic of the PLL, further reducing Adjust the total time used by the clock to improve regulation efficiency.
  • the embodiment of the present application further provides a frequency calibration device, as shown in FIG. 4, specifically including:
  • the control word output module 402 is configured to output a control word for adjusting the clock frequency to be calibrated according to the comparison result when the clock counter to be calibrated is different from the count value of the reference clock counter.
  • the device provided in the embodiment of the present application can output a control word to adjust the waiting value as long as the count values of the two counters are different. Calibrating the frequency of the clock improves the efficiency of the frequency adjustment without affecting the accuracy of the frequency adjustment.
  • the counting real-time comparison module 401 is specifically configured to: compare the count value of the clock counter to be calibrated with the count value of the reference clock counter in real time in the reference clock domain.
  • the counting real-time comparison module 401 is specifically configured to:
  • the format of the count value of the clock counter to be calibrated is converted from a binary number to a Gray code; in the reference clock domain, the count value of the clock counter to be calibrated converted to Gray code is used. Converting to a binary number after canceling the metastable delay; in the reference clock domain, the count value of the clock counter to be calibrated converted to a binary number is used to control the timing delay, and is performed the same The count value of the delayed reference clock counter is compared.
  • the same delay refers to the delay performed by the count value of the reference clock counter, and the delay for canceling the metastable state and the delay for controlling the timing are the same as the count value of the clock counter to be calibrated.
  • control word output module 402 is specifically configured to:
  • condition for outputting the control word for increasing the clock frequency to be calibrated further comprises: the count value of the reference clock counter is greater than the count value +1 of the clock counter to be calibrated; and the output is used to lower the
  • the condition of the control word for calibrating the clock frequency further includes: the count value of the clock counter to be calibrated is greater than the count value +1 of the reference clock counter.
  • control word output module 402 is configured to: use a binary method to output a control word for adjusting a clock frequency to be calibrated according to the comparison result; or, according to the comparison result, adopt a 1/4 hopping method according to the comparison result.
  • the control word for adjusting the clock frequency to be calibrated is output; or, according to the comparison result, the control word for adjusting the clock frequency to be calibrated is output by adding 2 minus 1 hopping method.
  • the control word output module may be further configured to: when the cumulative number of jumps of the control word is not When the maximum number of jumps is reached, the control word hopping mode used for outputting the control word is selected from the preset N kinds of control word hopping manners according to the difference between the clock frequency to be calibrated and the reference clock frequency, wherein The larger the difference is, the longer the hopping step of the selected control word hopping mode is, and the N is an integer not less than 2; correspondingly, when the control word for adjusting the clock frequency to be calibrated is output according to the comparison result, The control word output module is configured to: output a control word for adjusting a clock frequency to be calibrated by using a selected control word hopping manner according to the comparison result.
  • a waiting time determining module may be further included, after the control word output module selects the control word hopping mode, according to a preset control word hopping manner and a clock stability waiting time to be calibrated Determining the clock stabilization waiting time to be calibrated corresponding to the selected control word hopping mode, as the output control word is adjusted Waiting for the clock to be calibrated to stabilize after the clock frequency is calibrated; wherein the longer the hopping step of the selected control word hopping mode, the longer the waiting time of the corresponding clock to be calibrated, or the selected control word hopping mode The longer the jump step, the shorter the waiting time for the corresponding clock to be calibrated.
  • FIG. 5 is a schematic structural diagram of a preferred frequency calibration circuit according to an embodiment of the present application.
  • T1 ⁇ T4 clock stabilization waiting times to be calibrated
  • T1 is the waiting time before the frequency calibration is performed to ensure that the clock to be calibrated is stable
  • T2 is the waiting time corresponding to the dichotomy hopping
  • T3 It is the waiting time corresponding to the 1/4 hopping method
  • T4 is the waiting time corresponding to the addition of 2 minus 1 hopping method. If the PLL output clock span is larger and the required settling time is longer, T2>T3>T4; if the PLL output clock span is larger, the required settling time is shorter, then T2 ⁇ T3 ⁇ T4.
  • the counter control circuit After waiting for the clock stabilization circuit to be calibrated to control the clock to be calibrated to be stable, the counter control circuit triggers the reference clock counter and the clock counter to be calibrated to start counting.
  • the reference clock counter and the clock counter to be calibrated transmit the count value to the count value real-time comparison circuit in real time, and the two count values of the input are compared by the count value real-time comparison circuit.
  • the control word hopping mode selection circuit determines the difference between the two clock frequencies according to the received two count values, and then selects one of the above three control word hopping modes according to the difference of the clock frequency, and selects the selected one.
  • the word hopping mode is notified to the control word output circuit.
  • the control word hopping mode selection circuit first determines whether the number of accumulated jumps of the control word reaches the maximum number of hops, and only when the mode is not reached, the control word hopping mode is performed. The selection, otherwise the counter control circuit stops counting and ends the frequency calibration process.
  • the corresponding state machine in the control word output circuit outputs the corresponding control word according to the indication of the real-time comparison circuit of the count value to adjust the oscillator capacitance, thereby adjusting the oscillation frequency of the oscillator (ie, the clock frequency to be calibrated); if the control word is output If a jump occurs, the number of accumulated jumps of the control word is incremented by one; if the control word jump mode selection circuit does not judge the number of accumulated jumps of the control word, the control word output circuit implements the determination, and only the number of jumps of the control word is accumulated. When the maximum number of jumps is not reached, the corresponding state machine is notified to work.
  • the correspondence between the difference between the clock frequency and the control word hopping manner is preset.
  • the value range x1 ⁇ x2 corresponds to the dichotomy hopping
  • the value range x2 ⁇ x3 corresponds to the 1/4 hopping method
  • the value range x3 ⁇ x4 corresponds to the plus 2 minus one hopping method.
  • control word hopping mode selection circuit selects the binary method hopping mode
  • the control word output The circuit notifies the dichotomy state machine to work. If the 1/4 hopping method is selected, the control word output circuit notifies the 1/4 state machine to operate. If the add 2 minus 1 hopping method is selected, the control word output circuit notifies the adding 2 minus 1 state machine. jobs.
  • control word hopping mode selection circuit selects the binary method hopping mode
  • the selected control word hopping mode is notified to the waiting clock stabilization circuit, and waits for the clock stabilization circuit to determine that the clock stabilization waiting time to be calibrated is T2
  • the word hopping mode selection circuit selects the 1/4 hopping method
  • the selected control word hopping mode is notified to the waiting clock stabilization circuit, waiting for the clock stabilization circuit to determine that the clock stabilization waiting time to be calibrated is T3
  • the control word hopping mode is selected The circuit selection plus 2 minus 1 hopping method notifies the waiting clock stabilization circuit of the selected control word hopping mode, and waits for the clock stabilization circuit to determine that the clock stabilization waiting time to be calibrated is T4.
  • the specific working principle of the binary method state machine is as follows: if the count value real-time comparison circuit instructs the control word output circuit to increase the value of the control word or reduce the value of the control word, the dichotomy state machine correspondingly increases or decreases The value of the control word, and the jump step of the control word output this time is 1/2 of the jump step of the control word of the previous jump, if the count value real-time comparison circuit indicates that the control word output circuit does not change the control word.
  • the value of the binary method state machine can either output the control word or output the control word without change.
  • the initial value of the control word is preset.
  • control word hopping mode selection circuit as shown in FIG. 5, the embodiment of the present application can still be implemented, that is, a fixed control word hopping mode is adopted.
  • control word output circuit can be implemented by a fixed control word state machine.
  • FIG. 6 Another frequency calibration method provided by the embodiment of the present application is as shown in FIG. 6 , and specifically includes the following operations:
  • Step 600 Compare the count value of the clock counter to be calibrated with the count value of the reference clock counter.
  • the real-time comparison mode provided by the foregoing embodiment of the present application can be used to compare the count values of the two counters. It can also be implemented by using an existing comparison method. For example, the calibration clock and the reference clock are counted simultaneously for a period of time, and the count values of the two counters are compared by determining which clock counter count value first reaches a predetermined value.
  • Step 610 When the cumulative number of jumps of the control word does not reach the maximum number of jumps, select a control word from the preset N control word hopping manner according to the difference between the clock frequency to be calibrated and the reference clock frequency.
  • the hopping mode wherein the larger the difference, the longer the hopping step of the selected control word hopping mode, and N is an integer not less than 2.
  • the clock frequency to be calibrated and the reference clock frequency can be compared in real time according to the method provided in the foregoing embodiment, or can be compared according to the existing manner. If the comparison is made in the existing manner, the difference between the two clock frequencies is further calculated when it is determined that the count value of the counter reaches the predetermined value first.
  • Step 620 Output a control word for adjusting a clock frequency to be calibrated by using a selected control word hopping manner according to a comparison result between the count value of the clock counter to be calibrated and the count value of the reference clock counter.
  • the method provided by the embodiment of the present application flexibly selects according to the difference between the clock frequency to be calibrated and the reference clock frequency. Appropriate control word jump mode. When the difference is larger, the longer the jump step of the selected control word hopping mode, the number of adjustments of the clock to be calibrated can be reduced, and the adjustment efficiency is improved.
  • the clock to be calibrated corresponding to the selected control word hopping mode is determined according to the corresponding relationship between the preset control word hopping mode and the clock stability waiting time to be calibrated. Waiting time, as the output control word adjusts the clock frequency to be calibrated and waits for the clock to be calibrated to stabilize; wherein the longer the hopping step of the selected control word hopping mode, the longer the waiting time of the corresponding clock to be calibrated Or, the longer the jump step of the selected control word hopping mode, the shorter the waiting time for the corresponding clock to be calibrated.
  • the embodiment of the present application further provides a frequency calibration device, as shown in FIG.
  • a counting comparison module 701 configured to compare a count value of the clock counter to be calibrated with a count value of the reference clock counter
  • the control word hopping mode selection module 702 is configured to: when the number of accumulated hops of the control word does not reach the maximum number of hops, according to the difference between the clock frequency to be calibrated and the reference clock frequency, jump from the preset N control words.
  • a control word hopping mode is selected in the variable mode, wherein the larger the difference is, the longer the hopping step of the selected control word hopping mode is, and the N is an integer not less than 2;
  • the control word output module 703 is configured to output a control word for adjusting the clock frequency to be calibrated by using a selected control word hopping manner according to a comparison result between the count value of the clock counter to be calibrated and the count value of the reference clock counter.
  • the device provided in the embodiment of the present application flexibly selects an appropriate control word hopping mode according to the difference between the clock frequency to be calibrated and the reference clock frequency.
  • the difference is larger, the longer the jump step of the selected control word hopping mode, the number of adjustments of the clock to be calibrated can be reduced, and the adjustment efficiency is improved.
  • the method further includes a waiting time determining module, configured to, after the control word hopping mode selection module selects the control word hopping mode, according to a preset control word hopping manner and a clock stability waiting time to be calibrated Relationship, determining the clock stabilization waiting time to be calibrated corresponding to the selected control word hopping mode, as the output control word adjusts the clock frequency to be calibrated and waits for the clock to be calibrated to be stable; wherein, the selected control word hopping mode The longer the hopping step is, the longer the waiting time for the clock to be calibrated is stable, or the longer the hopping step of the selected control word hopping mode, and the shorter the waiting time for the corresponding clock to be calibrated.
  • a waiting time determining module configured to, after the control word hopping mode selection module selects the control word hopping mode, according to a preset control word hopping manner and a clock stability waiting time to be calibrated Relationship, determining the clock stabilization waiting time to be calibrated corresponding to the selected control word hopping mode, as the
  • embodiments of the present application can be provided as a method, system, or computer program product.
  • the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment in combination of software and hardware.
  • the application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) including computer usable program code.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

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Abstract

本申请公开了一种频率校准方法及装置。其一种方法包括：将待校准时钟计数器的计数值与参考时钟计数器的计数值进行实时比较；当两个计数器的计数值不同时，根据比较结果输出用于调整待校准时钟频率的控制字。另一种方法包括：当控制字的累积跳变次数未达到最大可跳变次数时，根据待校准时钟计数器的计数值与参考时钟计数器的计数值的差值，从预设的N种控制字跳变方式中选择一种控制字跳变方式，其中，差值越大，选择的控制字跳变方式的跳变步长越长；采用选择的控制字跳变方式输出用于调整待校准时钟频率的控制字。本申请实施例提供的技术方案，较之现有的频率校准方案，提高了频率调节的效率。

Description

一种频率校准方法及装置
本申请要求在2013年12月10日提交中国专利局、申请号为201310671766.8、发明名称为“一种频率校准方法及装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及集成电路技术领域，尤其涉及一种频率校准方法及装置。
背景技术
自动频率控制是使输出信号频率与给定频率保持确定关系的自动控制方法，在电子设备中被广泛应用于稳频或锁相。具体用在锁相环(Phase Locked Loop，PLL)内部，对与参考时钟偏差不大的PLL输出时钟进行频率校准，使PLL输出一个较精确的时钟。
实现自动频率控制的频率校准电路多种多样，目前PLL内部一种较常见的自动频率控制方法是：数字控制振荡器电容，从而调节振荡器振荡频率。针对这种技术，具体可以使用计数器比较待校准时钟频率(即振荡器的振荡频率)与参考时钟频率的快慢，根据比较结果相应地调节输出用于控制振荡器电容的控制字，从而调节振荡频率。具体的，同时在一段时间内对参考时钟与待校准时钟进行计数，如果参考时钟计数器先到达预定数值，则认为待校准时钟较慢，调节输出控制字，使控制字减1，从而加快待校准时钟的频率。反之，如果待校准时钟计数器先到达预设定值，则认为待校准时钟较快，调节输出控制字，使控制字加1。按照这种方反复校准，直到校准时钟与参考时钟相等时停止校准。
现有的自动频率控制存在如下问题：
计数器的计数时间比较长：当其中一个计数器计数到预定数值时才调节输出控制字，并且从电路上分析可知预定数值不太好确定，因为如果预定数值设置太小，则会影响频率调节的精确度。如果预设定值设置太大，则增加了频率调节时间。
另外，每次调节待校准时钟的频率，控制字只能以加1或者减1的方式跳变，跳变方式不灵活，且频率调节效率较低。
发明内容
本申请的目的是提供一种频率校准方法及装置，以解决计数器的计数时间较长的问题。
本申请的目的是通过以下技术方案实现的：
一种频率校准方法，包括：
将待校准时钟计数器的计数值与参考时钟计数器的计数值进行实时比较；
当待校准时钟计数器与参考时钟计数器的计数值不同时，根据比较结果输出用于调整待校准时钟频率的控制字。
本申请实施例提供的方法，对两个计数值进行实时比较，只要两个计数器的计数值不同，即可输出控制字来调整待校准时钟的频率，在不影响频率调节精确度的前提下，提高了频率调节的效率。
较佳地，将上述待校准时钟计数器的计数值与上述参考时钟计数器的计数值在参考时钟域进行实时比较。
具体可以是：在待校准时钟域，将上述待校准时钟计数器的计数值的格式由二进制数转换为格雷码；在上述参考时钟域，将转换为格雷码的上述待校准时钟计数器的计数值进行用于消除亚稳态的延时后转换为二进制数；在该参考时钟域，将转换为二进制数的上述待校准时钟计数器的计数值进行用于控制时序的延时后，与进行了相同延时的参考时钟计数器的计数值进行比较。
其中，相同延时是指，参考时钟计数器的计数值进行的延时，与待校准时钟计数器的计数值进行用于消除亚稳态的延时和用于控制时序的延时相同。
基于上述任意方法实施例，较佳地，当待校准时钟计数器与参考时钟计数器的计数值不同时，根据比较结果输出用于调整待校准时钟频率的控制字的具体实现方式可以但不仅限于是：当上述参考时钟计数器的计数值大于上述待校准时钟计数器的计数值，但小于预设的计数阈值时，输出用于调高上述待校准时钟频率的控制字；当上述待校准时钟计数器的计数值大于上述参考时钟计数器的计数值，但小于该预设的计数阈值时，输出用于调低该述待校准时钟频率的控制字。
较佳地，输出用于调高上述待校准时钟频率的控制字的条件进一步包括：上述参考时钟计数器的计数值大于该待校准时钟计数器的计数值+1；输出用于调低该待校准时钟频率的控制字的条件进一步包括：该待校准时钟计数器的计数值大于该参考时钟计数器的计数值+1。
基于上述任意方法实施例，较佳地，根据比较结果输出用于调整待校准时钟频率的控制字时，具体可以是：根据比较结果采用二分法输出用于调整待校准时钟频率的控制字；或者，根据比较结果采用1/4跳变法输出用于调整待校准时钟频率的控制字；或者，根据比较结果采用加2减1跳变法输出用于调整待校准时钟频率的控制字。如果预先设置了多个控制字跳变方式，较佳地，根据比较结果输出用于调整待校准时钟频率的控制字之前，还可以包括如下操作：当控制字的累积跳变次数未达到最大可跳变次数时，根据待校准时钟频率与参考时钟频率的差值，从预设的N种控制字跳变方式中选择输出控制字所采用的控制字跳变方式，其中，该差值越大，选择的控制字跳变方式的跳变步长越长，N为不小 于2的整数；相应的，根据比较结果输出用于调整待校准时钟频率的控制字的具体实现方式可以是：根据比较结果采用选择的控制字跳变方式输出用于调整待校准时钟频率的控制字。
选择控制字跳变方式后，还可以根据预先设定的控制字跳变方式与待校准时钟稳定等待时间的对应关系，确定与选择的控制字跳变方式对应的待校准时钟稳定等待时间，作为本次输出控制字调整待校准时钟频率后等待待校准时钟稳定的时间。其中，选择的控制字跳变方式的跳变步长越长，对应的待校准时钟稳定等待时间越长，或者，选择的控制字跳变方式的跳变步长越长，对应的待校准时钟稳定等待时间越短。
基于与上述方法同样的发明构思，本申请实施例还提供一种频率校准装置，包括：
计数实时比较模块，将待校准时钟计数器的计数值与参考时钟计数器的计数值进行实时比较；
控制字输出模块，用于当待校准时钟计数器与参考时钟计数器的计数值不同时，根据比较结果输出用于调整待校准时钟频率的控制字。
本申请实施例提供的装置，只要两个计数器的计数值不同，即可输出控制字来调整待校准时钟的频率，在不影响频率调节精确度的前提下，提高了频率调节的效率。
较佳地，计数实时比较模块具体用于：将所述待校准时钟计数器的计数值与所述参考时钟计数器的计数值在参考时钟域进行实时比较。
在此基础上，较佳地，所述计数实时比较模块具体用于：
在待校准时钟域，将所述待校准时钟计数器的计数值的格式由二进制数转换为格雷码；
在所述参考时钟域，将转换为格雷码的所述待校准时钟计数器的计数值进行用于消除亚稳态的延时后转换为二进制数；
在所述参考时钟域，将转换为二进制数的所述待校准时钟计数器的计数值进行用于控制时序的延时后，与进行了相同延时的参考时钟计数器的计数值进行比较。
其中，相同延时是指，参考时钟计数器的计数值进行的延时，与待校准时钟计数器的计数值进行用于消除亚稳态的延时和用于控制时序的延时相同。
基于上述任意装置实施例，较佳地，控制字输出模块具体用于：
当所述参考时钟计数器的计数值大于所述待校准时钟计数器的计数值，但小于预设的计数阈值时，输出用于调高所述待校准时钟频率的控制字；
当所述待校准时钟计数器的计数值大于所述参考时钟计数器的计数值，但小于所述预设的计数阈值时，输出用于调低所述待校准时钟频率的控制字。
较佳地，输出用于调高所述待校准时钟频率的控制字的条件进一步包括：所述参考时钟计数器的计数值大于所述待校准时钟计数器的计数值+1；输出用于调低所述待校准时钟 频率的控制字的条件进一步包括：所述待校准时钟计数器的计数值大于所述参考时钟计数器的计数值+1。
基于上述任意装置实施例，较佳地，控制字输出模块具体可以用于：根据比较结果采用二分法输出用于调整待校准时钟频率的控制字；或者，根据比较结果采用1/4跳变法输出用于调整待校准时钟频率的控制字；或者，根据比较结果采用加2减1跳变法输出用于调整待校准时钟频率的控制字。如果预先设置了多个控制字跳变方式，较佳地，根据比较结果输出用于调整待校准时钟频率的控制字之前，控制字输出模块还可以用于：当控制字的累积跳变次数未达到最大可跳变次数时，根据待校准时钟频率与参考时钟频率的差值，从预设的N种控制字跳变方式中选择输出控制字所采用的控制字跳变方式，其中，所述差值越大，选择的控制字跳变方式的跳变步长越长，所述N为不小于2的整数；相应的，根据比较结果输出用于调整待校准时钟频率的控制字时，所述控制字输出模块用于：根据比较结果采用选择的控制字跳变方式输出用于调整待校准时钟频率的控制字。
在此基础上，还可以包括等待时间确定模块，用于在所述控制字输出模块选择控制字跳变方式后，根据预先设定的控制字跳变方式与待校准时钟稳定等待时间的对应关系，确定与选择的控制字跳变方式对应的待校准时钟稳定等待时间，作为本次输出控制字调整待校准时钟频率后等待待校准时钟稳定的时间；其中，选择的控制字跳变方式的跳变步长越长，对应的待校准时钟稳定等待时间越长，或者，选择的控制字跳变方式的跳变步长越长，对应的待校准时钟稳定等待时间越短。
本申请的另一个目的是提供一种频率校准方法及装置，以解决控制字跳变方式不灵活，且频率调节效率较低的问题。
本申请的目的是通过以下技术方案实现的：
一种频率校准方法，包括：
将待校准时钟计数器的计数值与参考时钟计数器的计数值进行比较；
当控制字的累积跳变次数未达到最大可跳变次数时，根据待校准时钟频率与参考时钟频率的差值，从预设的N种控制字跳变方式中选择一种控制字跳变方式，其中，该差值越大，选择的控制字跳变方式的跳变步长越长，N为不小于2的整数；
根据待校准时钟计数器的计数值与参考时钟计数器的计数值的比较结果，采用选择的控制字跳变方式输出用于调整待校准时钟频率的控制字。
本申请实施例提供的方法，根据待校准时钟频率与参考时钟频率的差值，灵活选择合适的控制字跳变方式。当差值越大，选择的控制字跳变方式的跳变步长越长，从而可以减少待校准时钟的调节次数，提高调节效率。
较佳地，选择控制字跳变方式后，还可以根据预先设定的控制字跳变方式与待校准时钟稳定等待时间的对应关系，确定与选择的控制字跳变方式对应的待校准时钟稳定等待时 间，作为本次输出控制字调整待校准时钟频率后等待待校准时钟稳定的时间；其中，选择的控制字跳变方式的跳变步长越长，对应的待校准时钟稳定等待时间越长，或者，选择的控制字跳变方式的跳变步长越长，对应的待校准时钟稳定等待时间越短。
基于与方法同样的发明构思，本申请实施例还提供一种频率校准装置，包括：
计数比较模块，用于将待校准时钟计数器的计数值与参考时钟计数器的计数值进行比较；
控制字跳变方式选择模块，用于当控制字的累积跳变次数未达到最大可跳变次数时，根据待校准时钟频率与参考时钟频率的差值，从预设的N种控制字跳变方式中选择一种控制字跳变方式，其中，所述差值越大，选择的控制字跳变方式的跳变步长越长，所述N为不小于2的整数；
控制字输出模块，用于根据待校准时钟计数器的计数值与参考时钟计数器的计数值的比较结果，采用选择的控制字跳变方式输出用于调整待校准时钟频率的控制字。
本申请实施例提供的装置，根据待校准时钟频率与参考时钟频率的差值，灵活选择合适的控制字跳变方式。当差值越大，选择的控制字跳变方式的跳变步长越长，从而可以减少待校准时钟的调节次数，提高调节效率。
较佳地，还包括等待时间确定模块，用于在所述控制字跳变方式选择模块选择控制字跳变方式后，根据预先设定的控制字跳变方式与待校准时钟稳定等待时间的对应关系，确定与选择的控制字跳变方式对应的待校准时钟稳定等待时间，作为本次输出控制字调整待校准时钟频率后等待待校准时钟稳定的时间；其中，选择的控制字跳变方式的跳变步长越长，对应的待校准时钟稳定等待时间越长，或者，选择的控制字跳变方式的跳变步长越长，对应的待校准时钟稳定等待时间越短。
附图说明
图1为本申请实施例提供的一种频率校准方法示意图；
图2为本申请实施例提供的实时比较处理过程示意图；
图3为本申请实施例提供的二分法跳变示意图；
图4为本申请实施例提供的第一种频率校准装置示意图；
图5为本申请实施例提供的频率校准电路结构示意图；
图6为本申请实施例提供的另一种频率校准方法示意图；
图7为本申请实施例提供的另一种频率校准装置示意图。
具体实施方式
下面将结合附图，对本申请实施例提供的技术方案进行详细说明。
本申请实施例提供的一种频率校准方法如图1所示，具体包括如下操作：
步骤100、将待校准时钟计数器的计数值与参考时钟计数器的计数值进行实时比较。
步骤110、当待校准时钟计数器与参考时钟计数器的计数值不同时，根据比较结果输出用于调整待校准时钟频率的控制字。
本申请实施例提供的方法，只要两个计数器的计数值不同，即可输出控制字来调整待校准时钟的频率，在不影响频率调节精确度的前提下，提高了频率调节的效率。
本申请实施例中，将待校准时钟计数器的计数值与参考时钟计数器的计数值的具体实现方式有多种。如果待校准时钟与参考时钟的相位不存在任何关系，则这两个时钟为异步时钟。对于异步时钟，需要将异步时钟在同一时钟域中进行实时比较。本申请实施例中，较佳地，在参考时钟域对这两个时钟进行实时比较。当然，也可以在待校准时钟域对这两个时钟进行实时比较。
其中，在同一时钟域中对这两个时钟进行实时比较的具体实现方式有多种。本申请仅以在参考时钟域实时比较为例进行说明：在待校准时钟域，将上述待校准时钟计数器的计数值的格式由二进制数转换为格雷码；在上述参考时钟域，将转换为格雷码的上述待校准时钟计数器的计数值进行用于消除亚稳态的延时后转换为二进制数；在该参考时钟域，将转换为二进制数的上述待校准时钟计数器的计数值进行用于控制时序的延时后，与进行了相同延时的参考时钟计数器的计数值进行比较。
其中，相同延时是指，参考时钟计数器的计数值进行的延时，与待校准时钟计数器的计数值进行用于消除亚稳态的延时和用于控制时序的延时相同。
较佳地，将转换为格雷码的上述待校准时钟计数器的计数值进行两拍延时，且将转换为二进制数的上述待校准时钟计数器的计数值进行一拍延时。那么，上述实时比较的处理过程如图2所示。其中，将二进制数转换成格雷码的目的是避免将待校准时钟的计数值转换到参考时钟域后发生状态错误。延时通过触发器实现，经过一级触发器和二级触发器，待校准时钟计数器的计数值实现两拍延时，其目的是为了消除亚稳态。经过二级触发器后，将待校准时钟计数器的计数值转换为二进制数，以便与参考时钟计数器的计数值进行比较。经三级触发器实现一拍延时的目的是出于时序考虑。为了让两个计数器送入实时比较器的延时基本一致，对参考时钟计数器的计数值也进行三拍延时处理。
基于上述任意方法实施例，较佳地，当两个计数器的计数值不同时，根据比较结果输出用于调整待校准时钟频率的控制字的具体实现方式可以但不仅限于是：当上述参考时钟计数器的计数值大于上述待校准时钟计数器的计数值，但小于预设的计数阈值时，输出用 于调高上述待校准时钟频率的控制字；当上述待校准时钟计数器的计数值大于上述参考时钟计数器的计数值，但小于该预设的计数阈值时，输出用于调低该述待校准时钟频率的控制字。
由于待校准时钟频率与参考时钟频率相等或非常接近时，在很长一段时间内都无法判断两个计数器的计数值差异。本申请实施例引入了计数阈值，当达到计数阈值还没有判断出两个计数器的计数值差异时，将终止实时比较(即停止频率校准)。
进一步的，当达到计数阈值还没有判断出两个计数器的计数值差异时，输出的控制字不变。
较佳地，为了避免慢时钟比快时钟提前一个时钟周期计数的极端情况影响实时比较结果的准确性，较佳地，在根据比较结果输出控制字时，对慢时钟计数器的计数值进行加1的处理。那么，输出用于调高上述待校准时钟频率的控制字的条件进一步包括：上述参考时钟计数器的计数值大于该待校准时钟计数器的计数值+1；输出用于调低该待校准时钟频率的控制字的条件进一步包括：该待校准时钟计数器的计数值大于该参考时钟计数器的计数值+1。
基于上述任意方法实施例，较佳地，根据比较结果输出用于调整待校准时钟频率的控制字时，具体可以是：根据比较结果采用二分法输出用于调整待校准时钟频率的控制字；或者，根据比较结果采用1/4跳变法输出用于调整待校准时钟频率的控制字；或者，根据比较结果采用加2减1跳变法输出用于调整待校准时钟频率的控制字。如果预先设置了多种控制字跳变方式，较佳地，根据比较结果输出用于调整待校准时钟频率的控制字之前，还可以包括如下操作：当控制字的累积跳变次数未达到最大可跳变次数时，根据待校准时钟频率与上述参考时钟频率的差值，从预设的N种控制字跳变方式中选择输出控制字所采用的控制字跳变方式，其中，该差值越大，选择的控制字跳变方式的跳变步长越长，N为不小于2的整数；相应的，根据比较结果输出用于调整待校准时钟频率的控制字的具体实现方式可以是：根据比较结果采用选择的控制字跳变方式输出用于调整待校准时钟频率的控制字。其中，控制字跳变方式可以是二分法跳变、1/4跳变法、加2减1跳变法、步长固定为1的跳变法等等。具体的，可以划分差值的取值范围，每个取值范围对应一种控制字跳变方式。按照差值由大到小的顺序，控制字跳变方式的选择顺序可以是：二分法跳变—>1/4跳变法—>加2减1跳变法—>步长固定为1的跳变法。
本申请实施例中，参考时钟频率是固定的，例如24兆赫兹(MHz)。由于实时比较的两个计数值的采样时间相同，那么，从初始采样时刻到本次采样时刻，两个时钟所经过的总时长相同。待校准时钟频率可以通过如下公式得到：
待校准时钟频率＝参考时钟频率×参考时钟计数器的计数值÷待校准时钟计数器的计数值
本申请实施例中，所谓二分法是指每次输出的控制字跳变步长都是前一次输出的控制字跳变步长的1/2。以图3所示为例，假设控制字的初始值为5’b10000，初始跳变步长为8。如果需要输出用于调高上述待校准时钟频率的控制字，则控制字向大跳变，如果需要输出用于调低上述待校准时钟频率的控制字，则控制字向小跳变。图3给出了两种经4次跳变完成频率校准的控制字跳变过程。所谓一次跳变，即输出一次控制字。
本申请实施例中，所谓1/4跳变法是指每次输出的控制字跳变步长都是前一次输出的控制字跳变步长的1/4。
本申请实施例中，所谓加2减1跳变法是指：每次输出的控制字跳变步长为2。例如，当前控制字为word，下一次控制字将为word+2或word-2，如果控制字经过一次或多次加2或减2后，待校准时钟计数器的计数值由大于(或小于)参考时钟计数器的计数值变为小于(或大于)参考时钟计数器的计数值，那么，控制字减1(或加1)。
本申请实施例中，所谓控制字的跳变步长，是指本次输出的控制字相对于前一次输出的控制字的差值。
现有技术中，没有考虑到PLL的稳定等待时间与输出时钟跨度的关系。以输出时钟跨度越大，稳定等待时间越长的PLL为例。对于输出时钟跨度变化的场景，现有的稳定等待时间的设置不够灵活。为解决这一问题，本申请实施例中，选择控制字跳变方式后，还可以根据预先设定的控制字跳变方式与待校准时钟稳定等待时间的对应关系，确定与选择的控制字跳变方式对应的待校准时钟稳定等待时间，作为本次输出控制字调整待校准时钟频率后等待待校准时钟稳定的时间。
其中，调节PLL时，如果PLL输出时钟跨度越大，稳定等待时间越长。那么，选择的控制字跳变方式的跳变步长越长，对应的待校准时钟稳定等待时间越长。由于常规的PLL在同一调节档位有跨度越大，稳定等待时间越长这样的特性，该实现方式除了能有效减少跳变次数，还能针对这类PLL的该特性调节稳定等待时间，进一步减少调节时钟所用的总时间，从而提高调节效率。
调节PLL时，如果PLL输出时钟跨度越大，稳定等待时间越短。那么，选择的控制字跳变方式的跳变步长越长，对应的待校准时钟稳定等待时间越短。
基于与上述方法同样的发明构思，本申请实施例还提供一种频率校准装置，如图4所示，具体包括：
计数实时比较模块401，将待校准时钟计数器的计数值与参考时钟计数器的计数值进行实时比较；
控制字输出模块402，用于当待校准时钟计数器与参考时钟计数器的计数值不同时，根据比较结果输出用于调整待校准时钟频率的控制字。
本申请实施例提供的装置，只要两个计数器的计数值不同，即可输出控制字来调整待 校准时钟的频率，在不影响频率调节精确度的前提下，提高了频率调节的效率。
较佳地，计数实时比较模块401具体用于：将所述待校准时钟计数器的计数值与所述参考时钟计数器的计数值在参考时钟域进行实时比较。
在此基础上，较佳地，所述计数实时比较模块401具体用于：
在待校准时钟域，将所述待校准时钟计数器的计数值的格式由二进制数转换为格雷码；在所述参考时钟域，将转换为格雷码的所述待校准时钟计数器的计数值进行用于消除亚稳态的延时后转换为二进制数；在所述参考时钟域，将转换为二进制数的所述待校准时钟计数器的计数值进行用于控制时序的延时后，与进行了相同延时的参考时钟计数器的计数值进行比较。
其中，相同延时是指，参考时钟计数器的计数值进行的延时，与待校准时钟计数器的计数值进行用于消除亚稳态的延时和用于控制时序的延时相同。
基于上述任意装置实施例，较佳地，控制字输出模块402具体用于：
当所述参考时钟计数器的计数值大于所述待校准时钟计数器的计数值，但小于预设的计数阈值时，输出用于调高所述待校准时钟频率的控制字；当所述待校准时钟计数器的计数值大于所述参考时钟计数器的计数值，但小于所述预设的计数阈值时，输出用于调低所述待校准时钟频率的控制字。
较佳地，输出用于调高所述待校准时钟频率的控制字的条件进一步包括：所述参考时钟计数器的计数值大于所述待校准时钟计数器的计数值+1；输出用于调低所述待校准时钟频率的控制字的条件进一步包括：所述待校准时钟计数器的计数值大于所述参考时钟计数器的计数值+1。
基于上述任意装置实施例，较佳地，控制字输出模块402具体可以用于：根据比较结果采用二分法输出用于调整待校准时钟频率的控制字；或者，根据比较结果采用1/4跳变法输出用于调整待校准时钟频率的控制字；或者，根据比较结果采用加2减1跳变法输出用于调整待校准时钟频率的控制字。如果预先设置了多个控制字跳变方式，较佳地，根据比较结果输出用于调整待校准时钟频率的控制字之前，控制字输出模块还可以用于：当控制字的累积跳变次数未达到最大可跳变次数时，根据待校准时钟频率与参考时钟频率的差值，从预设的N种控制字跳变方式中选择输出控制字所采用的控制字跳变方式，其中，所述差值越大，选择的控制字跳变方式的跳变步长越长，所述N为不小于2的整数；相应的，根据比较结果输出用于调整待校准时钟频率的控制字时，所述控制字输出模块用于：根据比较结果采用选择的控制字跳变方式输出用于调整待校准时钟频率的控制字。
在此基础上，还可以包括等待时间确定模块，用于在所述控制字输出模块选择控制字跳变方式后，根据预先设定的控制字跳变方式与待校准时钟稳定等待时间的对应关系，确定与选择的控制字跳变方式对应的待校准时钟稳定等待时间，作为本次输出控制字调整待 校准时钟频率后等待待校准时钟稳定的时间；其中，选择的控制字跳变方式的跳变步长越长，对应的待校准时钟稳定等待时间越长，或者，选择的控制字跳变方式的跳变步长越长，对应的待校准时钟稳定等待时间越短。
图5所示为本申请实施例提供的优选的频率校准电路结构示意图。
假设控制字跳变方式有三种，分别为二分法跳变、1/4跳变法、加2减1跳变法。相应的，有四个待校准时钟稳定等待时间(T1～T4)，其中，T1是进行频率校准之前的等待时间，用于确保待校准时钟稳定；T2是二分法跳变对应的等待时间，T3是1/4跳变法对应的等待时间，T4是加2减1跳变法对应的等待时间。如果PLL输出时钟跨度越大，需要的稳定时间越长，则T2>T3>T4；如果PLL输出时钟跨度越大，需要的稳定时间越短，则T2<T3<T4。
等待待校准时钟稳定电路控制待校准时钟稳定后，计数器控制电路触发参考时钟计数器和待校准时钟计数器开始计数。参考时钟计数器和待校准时钟计数器实时将计数值传送给计数值实时比较电路，由计数值实时比较电路对输入的两个计数值进行比较，其具体实现方式可以参照上述实施例的描述，这里不再赘述。当计数阈值>参考时钟计数器的计数值>待校准时钟计数器的计数值+1时，指示控制字输出电路增加控制字的值(即输出用于调高待校准时钟频率的控制字)，还将两个时钟的计数值发送给控制字跳变方式选择电路；当参考时钟计数器的计数值+1<待校准时钟计数器的计数值<计数阈值时，指示控制字输出电路减小控制字的值(即输出用于调低待校准时钟频率的控制字)，还将两个时钟的计数值发送给控制字跳变方式选择电路；当计数阈值＝参考时钟计数器的计数值(即到达计数阈值，仍然无法判断两个计数器的计数值差异)，指示控制字输出电路不改变控制字的值。控制字跳变方式选择电路根据接收到的两个计数值，确定两个时钟频率的差值，进而根据时钟频率的差值从上述三种控制字跳变方式中选择一种，将选择的控制字跳变方式通知给控制字输出电路，可选的，控制字跳变方式选择电路首先判断控制字累积跳变次数是否达到最大可跳变次数，只有未达到时，才进行控制字跳变方式的选择，否则通知计数器控制电路停止计数，结束频率校准流程。控制字输出电路中相应的状态机根据计数值实时比较电路的指示，输出相应的控制字以进行振荡器电容的调整，从而调节振荡器震荡频率(即待校准时钟频率)；如果输出的控制字发生跳变，则控制字累积跳变次数加1；如果控制字跳变方式选择电路不进行控制字累积跳变次数的判断，控制字输出电路实现该判断，且仅在控制字累积跳变次数未达到最大可跳变次数时，通知相应的状态机工作。
本申请实施例中，时钟频率的差值与控制字跳变方式的对应关系预先设定。例如，差值取值范围x1～x2对应二分法跳变，差值取值范围x2～x3对应1/4跳变法，差值取值范围x3～x4对应加2减1跳变法。其中，x1<x2<x3<x4。
本申请实施例中，如果控制字跳变方式选择电路选择二分法跳变方式，则控制字输出 电路通知二分法状态机工作，如果选择1/4跳变法，则控制字输出电路通知1/4状态机工作，如果选择加2减1跳变法，则控制字输出电路通知加2减1状态机工作。
进一步的，如果控制字跳变方式选择电路选择二分法跳变方式，则将选择的控制字跳变方式通知给等待时钟稳定电路，等待时钟稳定电路确定待校准时钟稳定等待时间为T2；如果控制字跳变方式选择电路选择1/4跳变法，则将选择的控制字跳变方式通知给等待时钟稳定电路，等待时钟稳定电路确定待校准时钟稳定等待时间为T3；如果控制字跳变方式选择电路选择加2减1跳变法，则将选择的控制字跳变方式通知给等待时钟稳定电路，等待时钟稳定电路确定待校准时钟稳定等待时间为T4。其中，调节PLL时，如果PLL输出时钟跨度越大，稳定等待时间越长，那么，T2>T3>T4；如果PLL输出时钟跨度越大，稳定等待时间越短，那么，T2<T3<T4。
以二分法跳变为例，二分法状态机具体工作原理如下：如果计数值实时比较电路指示控制字输出电路增加控制字的值或减少控制字的值，则二分法状态机相应的增加或减少控制字的值，且本次输出的控制字的跳变步长为上一次跳变的控制字的跳变步长的1/2，如果计数值实时比较电路指示控制字输出电路不改变控制字的值，二分法状态机既可以不输出控制字，也可以输出没有改变的控制字。其中，控制字的初始值预先设定。
应当指出的是，如果没有图5中所示的控制字跳变方式选择电路，本申请实施例仍然可以实现，即采用固定的控制字跳变方式。相应的，控制字输出电路可以通过固定的一个控制字状态机实现。
本申请实施例提供的另一种频率校准方法如图6所示，具体包括如下操作：
步骤600、将待校准时钟计数器的计数值与参考时钟计数器的计数值进行比较。
其中，既可以采用本申请上述实施例提供的实时比较方式，对这两个计数器的计数值进行比较。也可以采用现有的比较方式实现，例如，同时在一段时间内对待校准时钟与参考时钟进行计数，通过判断哪个时钟计数器的计数值先到达预定数值，来比较这两个计数器的计数值。
步骤610、当控制字的累积跳变次数未达到最大可跳变次数时，根据待校准时钟频率与参考时钟频率的差值，从预设的N种控制字跳变方式中选择一种控制字跳变方式，其中，该差值越大，选择的控制字跳变方式的跳变步长越长，N为不小于2的整数。
其中，待校准时钟频率与参考时钟频率既可以按照上述实施例提供的方法进行实时比较，也可以按照现有方式进行比较。如果按现有方式进行比较，在确定有计数器的计数值先达到预定数值时，进一步计算两个时钟频率的差值。
步骤620、根据待校准时钟计数器的计数值与参考时钟计数器的计数值的比较结果，采用选择的控制字跳变方式输出用于调整待校准时钟频率的控制字。
本申请实施例提供的方法，根据待校准时钟频率与参考时钟频率的差值，灵活选择合 适的控制字跳变方式。当差值越大，选择的控制字跳变方式的跳变步长越长，从而可以减少待校准时钟的调节次数，提高调节效率。
较佳地，选择控制字跳变方式后，还可以根据预先设定的控制字跳变方式与待校准时钟稳定等待时间的对应关系，确定与选择的控制字跳变方式对应的待校准时钟稳定等待时间，作为本次输出控制字调整待校准时钟频率后等待待校准时钟稳定的时间；其中，选择的控制字跳变方式的跳变步长越长，对应的待校准时钟稳定等待时间越长，或者，选择的控制字跳变方式的跳变步长越长，对应的待校准时钟稳定等待时间越短。
基于与方法同样的发明构思，本申请实施例还提供一种频率校准装置，如图7所示，具体包括：
计数比较模块701，用于将待校准时钟计数器的计数值与参考时钟计数器的计数值进行比较；
控制字跳变方式选择模块702，用于当控制字的累积跳变次数未达到最大可跳变次数时，根据待校准时钟频率与参考时钟频率的差值，从预设的N种控制字跳变方式中选择一种控制字跳变方式，其中，所述差值越大，选择的控制字跳变方式的跳变步长越长，所述N为不小于2的整数；
控制字输出模块703，用于根据待校准时钟计数器的计数值与参考时钟计数器的计数值的比较结果，采用选择的控制字跳变方式输出用于调整待校准时钟频率的控制字。
本申请实施例提供的装置，根据待校准时钟频率与参考时钟频率的差值，灵活选择合适的控制字跳变方式。当差值越大，选择的控制字跳变方式的跳变步长越长，从而可以减少待校准时钟的调节次数，提高调节效率。
较佳地，还包括等待时间确定模块，用于在所述控制字跳变方式选择模块选择控制字跳变方式后，根据预先设定的控制字跳变方式与待校准时钟稳定等待时间的对应关系，确定与选择的控制字跳变方式对应的待校准时钟稳定等待时间，作为本次输出控制字调整待校准时钟频率后等待待校准时钟稳定的时间；其中，选择的控制字跳变方式的跳变步长越长，对应的待校准时钟稳定等待时间越长，或者，选择的控制字跳变方式的跳变步长越长，对应的待校准时钟稳定等待时间越短。
本领域内的技术人员应明白，本申请的实施例可提供为方法、***、或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本申请是参照根据本申请实施例的方法、设备(***)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流 程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
尽管已描述了本申请的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本申请范围的所有变更和修改。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (16)

  1. 一种频率校准方法，其特征在于，包括：
    将待校准时钟计数器的计数值与参考时钟计数器的计数值进行实时比较；
    当所述待校准时钟计数器与所述参考时钟计数器的计数值不同时，根据比较结果输出用于调整待校准时钟频率的控制字。
  2. 根据权利要求1所述的方法，其特征在于，将待校准时钟计数器的计数值与参考时钟计数器的计数值进行实时比较，包括：
    在待校准时钟域，将所述待校准时钟计数器的计数值的格式由二进制数转换为格雷码；
    在所述参考时钟域，将转换为格雷码的所述待校准时钟计数器的计数值进行用于消除亚稳态的延时后转换为二进制数；
    在所述参考时钟域，将转换为二进制数的所述待校准时钟计数器的计数值进行用于控制时序的延时后，与进行了相同延时的参考时钟计数器的计数值进行比较。
  3. 根据权利要求1或2所述的方法，其特征在于，当所述待校准时钟计数器与所述参考时钟计数器的计数值不同时，根据比较结果输出用于调整待校准时钟频率的控制字，包括：
    当所述参考时钟计数器的计数值大于所述待校准时钟计数器的计数值+1，但小于预设的计数阈值时，输出用于调高所述待校准时钟频率的控制字；
    当所述待校准时钟计数器的计数值大于所述参考时钟计数器的计数值+1，但小于所述预设的计数阈值时，输出用于调低所述待校准时钟频率的控制字。
  4. 根据权利要求3所述的方法，其特征在于，根据比较结果输出用于调整待校准时钟频率的控制字，包括：
    根据比较结果采用二分法输出用于调整待校准时钟频率的控制字；或者，
    根据比较结果采用1/4跳变法输出用于调整待校准时钟频率的控制字；或者，
    根据比较结果采用加2减1跳变法输出用于调整待校准时钟频率的控制字。
  5. 根据权利要求3所述的方法，其特征在于，根据比较结果输出用于调整待校准时钟频率的控制字之前，该方法还包括：
    当控制字的累积跳变次数未达到最大可跳变次数时，根据待校准时钟频率与参考时钟频率的差值，从预设的N种控制字跳变方式中选择输出所述控制字所采用的控制字跳变方式，其中，所述差值越大，选择的跳变方式的跳变步长越长，所述N为不小于2的整数；
    根据比较结果输出用于调整待校准时钟频率的控制字，包括：
    根据比较结果采用选择的控制字跳变方式输出用于调整待校准时钟频率的控制字。
  6. 根据权利要求5所述的方法，其特征在于，选择控制字跳变方式后，该方法还包括：
    根据预先设定的控制字跳变方式与待校准时钟稳定等待时间的对应关系，确定与选择的控制字跳变方式对应的待校准时钟稳定等待时间，作为本次输出控制字调整待校准时钟频率后等待待校准时钟稳定的时间；其中，选择的控制字跳变方式的跳变步长越长，对应的待校准时钟稳定等待时间越长，或者，选择的控制字跳变方式的跳变步长越长，对应的待校准时钟稳定等待时间越短。
  7. 一种频率校准方法，其特征在于，包括：
    将待校准时钟计数器的计数值与参考时钟计数器的计数值进行比较；
    当控制字的累积跳变次数未达到最大可跳变次数时，根据待校准时钟频率与参考时钟频率的差值，从预设的N种控制字跳变方式中选择一种控制字跳变方式，其中，所述差值越长，选择的控制字跳变方式的跳变步长越长，所述N为不小于2的整数；
    根据所述待校准时钟计数器的计数值与参考时钟计数器的计数值的比较结果，采用选择的控制字跳变方式输出用于调整待校准时钟频率的控制字。
  8. 根据权利要求7所述的方法，其特征在于，选择控制字跳变方式后，该方法还包括：
    根据预先设定的控制字跳变方式与待校准时钟稳定等待时间的对应关系，确定与选择的控制字跳变方式对应的待校准时钟稳定等待时间，作为本次输出控制字调整待校准时钟频率后等待待校准时钟稳定的时间；其中，选择的控制字跳变方式的跳变步长越长，对应的待校准时钟稳定等待时间越长，或者，选择的控制字跳变方式的跳变步长越长，对应的待校准时钟稳定等待时间越短。
  9. 一种频率校准装置，其特征在于，包括：
    计数实时比较模块，将待校准时钟计数器的计数值与参考时钟计数器的计数值进行实时比较；
    控制字输出模块，用于当所述待校准时钟计数器与所述参考时钟计数器的计数值不同时，根据比较结果输出用于调整待校准时钟频率的控制字。
  10. 根据权利要求9所述的装置，其特征在于，所述计数实时比较模块具体用于：
    在待校准时钟域，将所述待校准时钟计数器的计数值的格式由二进制数转换为格雷码；
    在所述参考时钟域，将转换为格雷码的所述待校准时钟计数器的计数值进行用于消除亚稳态的延时后转换为二进制数；
    在所述参考时钟域，将转换为二进制数的所述待校准时钟计数器的计数值进行用于控 制时序的延时后，与进行了相同延时的参考时钟计数器的计数值进行比较。
  11. 根据权利要求9或10所述的装置，其特征在于，所述控制字输出模块具体用于：
    当所述参考时钟计数器的计数值大于所述待校准时钟计数器的计数值+1，但小于预设的计数阈值时，输出用于调高所述待校准时钟频率的控制字；
    当所述待校准时钟计数器的计数值大于所述参考时钟计数器的计数值+1，但小于所述预设的计数阈值时，输出用于调低所述待校准时钟频率的控制字。
  12. 根据权利要求11所述的装置，其特征在于，所述控制字输出模块具体用于：
    根据比较结果采用二分法输出用于调整待校准时钟频率的控制字；或者，
    根据比较结果采用1/4跳变法输出用于调整待校准时钟频率的控制字；或者，
    根据比较结果采用加2减1跳变法输出用于调整待校准时钟频率的控制字。
  13. 根据权利要求11所述的装置，其特征在于，根据比较结果输出用于调整待校准时钟频率的控制字之前，所述控制字输出模块还用于：
    当控制字的累积跳变次数未达到最大可跳变次数时，根据待校准时钟频率与参考时钟频率的差值，从预设的N种控制字跳变方式中选择输出所述控制字所采用的控制字跳变方式，其中，所述差值越大，选择的控制字跳变方式的跳变步长越长，所述N为不小于2的整数；
    根据比较结果输出用于调整待校准时钟频率的控制字时，所述控制字输出模块用于：根据比较结果采用选择的控制字跳变方式输出用于调整待校准时钟频率的控制字。
  14. 根据权利要求13所述的装置，其特征在于，还包括等待时间确定模块，用于在所述控制字输出模块选择控制字跳变方式后，根据预先设定的控制字跳变方式与待校准时钟稳定等待时间的对应关系，确定与选择的控制字跳变方式对应的待校准时钟稳定等待时间，作为本次输出控制字调整待校准时钟频率后等待待校准时钟稳定的时间；其中，选择的控制字跳变方式的跳变步长越长，对应的待校准时钟稳定等待时间越长，或者，选择的控制字跳变方式的跳变步长越长，对应的待校准时钟稳定等待时间越短。
  15. 一种频率校准装置，其特征在于，包括：
    计数比较模块，用于将待校准时钟计数器的计数值与参考时钟计数器的计数值进行比较；
    控制字跳变方式选择模块，用于当控制字的累积跳变次数未达到最大可跳变次数时，根据待校准时钟频率与参考时钟频率的差值，从预设的N种控制字跳变方式中选择一种控制字跳变方式，其中，所述差值越大，选择的控制字跳变方式的跳变步长越长，所述N为不小于2的整数；
    控制字输出模块，用于根据所述待校准时钟计数器的计数值与参考时钟计数器的计数值的比较结果，采用选择的控制字跳变方式输出用于调整待校准时钟频率的控制字。
  16. 根据权利要求15所述的装置，其特征在于，还包括等待时间确定模块，用于在所述控制字跳变方式选择模块选择控制字跳变方式后，根据预先设定的控制字跳变方式与待校准时钟稳定等待时间的对应关系，确定与选择的控制字跳变方式对应的待校准时钟稳定等待时间，作为本次输出控制字调整待校准时钟频率后等待待校准时钟稳定的时间；其中，选择的控制字跳变方式的跳变步长越长，对应的待校准时钟稳定等待时间越长，或者，选择的控制字跳变方式的跳变步长越长，对应的待校准时钟稳定等待时间越短。
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