WO2015043282A1 - 阵列基板及其制造方法和显示装置 - Google Patents

阵列基板及其制造方法和显示装置 Download PDF

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Publication number
WO2015043282A1
WO2015043282A1 PCT/CN2014/081898 CN2014081898W WO2015043282A1 WO 2015043282 A1 WO2015043282 A1 WO 2015043282A1 CN 2014081898 W CN2014081898 W CN 2014081898W WO 2015043282 A1 WO2015043282 A1 WO 2015043282A1
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Prior art keywords
photoresist
film
gate
transparent conductive
electrode
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PCT/CN2014/081898
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English (en)
French (fr)
Inventor
李田生
谢振宇
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京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/422,334 priority Critical patent/US9716110B2/en
Priority to EP14847683.1A priority patent/EP3054483B1/en
Publication of WO2015043282A1 publication Critical patent/WO2015043282A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Definitions

  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the existing array substrate includes: a gate line, a data line, a thin film transistor (TFT), and a pixel electrode.
  • the gate lines are laterally disposed on the base substrate, the data lines are vertically disposed on the base substrate, and the TFTs are disposed at intersections of the » lines and the data lines.
  • the TFT is an active switching element.
  • the conventional array substrate includes: a gate electrode 10, a gate insulating layer 20, an active layer 30, a source electrode 50, a drain electrode 60, and a passivation layer 70.
  • the above structures are all disposed on the base substrate 80.
  • the drain electrode 10 and the gate line are integrally formed, and the source electrode 50 and the drain electrode 60 are integrally formed with the data line, and the drain electrode 60 is electrically connected to the pixel electrode 90.
  • the active layer 30 conducts, and the data signal of the data line can pass from the source electrode 50 through the TFT channel 31 to the drain electrode 60, and finally to the pixel electrode 90.
  • the pixel electrode 90 obtains a signal and forms an electric field for driving the liquid crystal to rotate with the common electrode 91.
  • high PPI Pigels Per Inch
  • the requirements for preparing high PPI are higher, and it takes 7 times to form a structural pattern to complete the structure.
  • the gate driver circuit In order to integrate the GOA technology (Gate Driver on Array), the gate driver circuit (Gate driver ICs) is directly fabricated on the array substrate instead of the driver chip fabricated by the external germanium wafer. Technology. The application of this technology can be directly around the panel, reducing the production process, reducing the cost of the product, and improving
  • the high integration of the TF LCD panel allows the panel to be thinner and to produce sufficiently small vias.
  • Each The sub-patterning process includes mask exposure, development, etching, and stripping processes, respectively.
  • the etching process includes dry etching and wet etching, so the number of patterning processes can be used to measure the complexity of manufacturing the TF LCD array substrate. The degree to which the number of patterning processes is reduced means a reduction in manufacturing costs.
  • ADS Advanced Super-Dimensional Field Conversion Technology
  • ADS is the core technology collectively represented by BOE's independent innovation and represented by wide viewing angle technology. It is an advanced super-dimensional field conversion technology for the planar electric field wide viewing angle core technology. Its core technical characteristics are described as: a multi-dimensional electric field is formed by the electric field generated by the edge of the slit electrode in a plane and the electric field generated between the slit electrode layer and the plate electrode layer.
  • a germanium line is formed on a glass substrate by a first patterning process; then, the gate insulating layer 20 and the active layer 30 are deposited, and the active layer 30 pattern is formed by a second patterning process; then, the pixel electrode is deposited Forming a pixel electrode by a third patterning process; then, forming a via hole (GI via) on the gate insulating layer 20 by a fourth patterning process; then, depositing a metal layer, forming a signal line by a fifth patterning process and An active layer 30 pattern in which a signal line is turned on by a GI via and a gate line, and a pattern of a signal line and an active layer 30 is formed in the channel region; then, a passivation layer (PVX) is deposited, and The passivation layer via holes are formed by the sixth patterning process; finally, the conductive layer is deposited, and the common electrode is formed by the seventh patterning process, thereby completing the structure pattern of the array substrate by a total of seven mask processes.
  • An object of the embodiments of the present invention is to provide an array substrate, a preparation method thereof and a display device, which can reduce the process and improve the product quality.
  • the technical solutions provided by the embodiments of the present invention are as follows:
  • a method of fabricating an array substrate includes a gate electrode, an active layer, a source electrode, a drain electrode, and a pixel electrode, wherein the active layer includes a doped semiconductor layer and a semiconductor layer; and the manufacturing method includes:
  • Step 1 depositing a gate metal film on the base substrate, and forming a first pattern including the cabinet by a first patterning process;
  • Step 2 sequentially depositing a gate insulating film, a first transparent conductive film, a source and a drain metal film, and a doped a-Si film on the base substrate on which the first pattern is formed, and forming a pixel including the pixel by a second patterning process a second pattern of the electrode, the source electrode, the drain electrode, and the doped semiconductor layer;
  • Step 3 depositing an a-Si film on the base substrate on which the second pattern is formed, and forming a third pattern including a TFT channel, a semiconductor layer, and a gate insulating layer via by a third patterning process, wherein » a pole insulating layer via is disposed at a position corresponding to the gate;
  • Step 4 depositing a passivation layer film on the base substrate on which the third pattern is formed, and forming a fourth pattern including a passivation layer via hole by a fourth patterning process, wherein the passivation layer via hole and the Corresponding to the position of the via hole of the gate insulating layer;
  • Step 5 depositing a second transparent conductive film on the base substrate forming the fourth pattern, forming a fifth pattern including an electrical connection portion by a fifth patterning process, wherein at least a portion of the electrical connection portion is located
  • the passivation layer via and the gate insulating layer via are electrically connected to the gate and at least one of the source electrode and the drain electrode.
  • step 1 specifically includes:
  • the remaining photoresist is stripped.
  • step 2 specifically includes:
  • the complete retention area of the glue includes a position corresponding to the source electrode and the drain electrode, and the semi-reserved area of the photoresist corresponds to a position corresponding to the pixel electrode, and the complete removal area of the photoresist corresponds to the complete photoresist. a region other than the retention region and the photoresist semi-retention region, wherein the photoresist complete removal region includes a location corresponding to the TFT channel and the gate insulating layer via;
  • the doped a- S1 film and the source and drain metal films of the semi-reserved region of the photoresist are completely etched away by a third etching process;
  • the remaining photoresist is stripped.
  • step 3 specifically includes:
  • the remaining photoresist is stripped.
  • step 4 specifically includes:
  • the exposed passivation layer film is candled out by a fifth etching process;
  • the remaining photoresist is stripped.
  • step 5 specifically includes:
  • the remaining photoresist is stripped.
  • step 5 depositing a second transparent conductive film on the base substrate forming the fourth pattern, forming the electrical connection portion by the fifth patterning process, and passing the fifth time
  • the patterning process forms a common electrode
  • the step 5 specifically includes:
  • the remaining photoresist is stripped.
  • the gate insulating layer is provided with a gate insulating via, and the via is located at least a portion of the upper portion of the gate;
  • a second transparent conductive portion disposed in the same layer as the pixel electrode, wherein the second transparent conductive portion and the first transparent conductive portion are respectively located at two sides of the gate;
  • a source electrode disposed on the first transparent conductive portion; a drain electrode disposed on the second transparent conductive portion and disposed in the same layer as the source electrode, wherein the source electrode and the drain electrode are respectively located on two sides of the gate, wherein a part of the source electrode And forming a TFT channel region between the drain electrode and another portion of the gate insulating layer via hole between the source electrode and the drain electrode;
  • Doped semiconductor layers respectively formed on the source electrode and the drain electrode;
  • the semiconductor layer is disposed only at a position corresponding to the drain electrode and the source electrode constituting the TFT channel region to form a TFT channel;
  • a passivation layer formed over the semiconductor layer, wherein the passivation layer is provided with a passivation layer via at a position corresponding to the via of the gate insulating layer, and the passivation layer via Passing through the via hole of the cabinet insulating layer, and disposed in the passivation layer via hole and the gate insulating layer via hole for disposing the cabinet electrode and the source electrode and the drain electrode At least one electrical connection for electrical connection
  • the column substrate further includes: a common electrode formed on the passivation layer; the common electrode and the electrical connection portion are made of the same material - integrally formed by the same patterning process.
  • the array substrate includes a display area and a peripheral area disposed around the periphery of the display area;
  • a part of the gate is located in the display area, and another part is located in the peripheral area, and the gate insulating layer via is disposed on a c of the gate of the peripheral area. , including the array substrate as described above.
  • the array substrate provided by the embodiments of the present invention and the manufacturing method thereof have the following advantages;
  • the TFT channel is formed during the process of depositing the semiconductor layer. Compared with the conventional etching method to form the TFT channel, the TFT channel defect is fundamentally avoided, and the product quality is greatly improved.
  • 1 is a cross-sectional view of a conventional TFTNLCD array substrate;
  • FIG. 2 is a schematic diagram of a 7 mask process of a conventional TF LCD array substrate
  • FIG. 3 is a cross-sectional view showing a gate electrode formed on a substrate by a first patterning process according to an embodiment of the present invention
  • FIG. 4 is a cross-sectional view showing a gate insulating film, a first transparent conductive film, a source and a drain metal film, and an a-Si doped film sequentially deposited on a substrate on which a first pattern is formed, according to an embodiment of the present invention
  • FIG. 5 is a cross-sectional view showing the structure of FIG. 4 after the photoresist is coated, and the photoresist is exposed and developed;
  • Figure 6 is a cross-sectional view showing the structure of Figure 5 after a second etching process
  • Figure ⁇ shows a cross-sectional view of the photoresist in Figure 6 after the ashing process
  • Figure 8 is a cross-sectional view showing the structure of Figure 7 after a third etching process
  • Figure 9 is a cross-sectional view showing the structure of Figure 8 with the remaining photoresist removed;
  • Figure 10 is a cross- sectional view showing a sequentially deposited a S1 film on a substrate on which a second pattern is formed;
  • Figure 11 is a view showing the structure of Figure 10 coated with a photoresist, and the photoresist is applied. a cross-sectional view after exposure and development processing;
  • Figure 12 is a cross-sectional view showing the fourth etching process of the structure of the i i and stripping off the remaining photoresist;
  • Figure 13 is a cross-sectional view showing the fourth patterning process of the structure of Figure 12;
  • Figure 14 is a cross-sectional view showing the fifth patterning process of the structure of Figure 13;
  • FIG. 15 is a cross-sectional view showing the structure of an array substrate according to an embodiment of the present invention.
  • the "upper” in the "X is set on Y" in the embodiment of the present invention includes the contact of X and Y, and the meaning of "X" is above Y, as in the embodiment of the present invention.
  • the substrate substrate is defined as being disposed at the bottom; the patterning process referred to in the embodiments of the present invention includes photoresist coating, masking, exposure, development, etching, photoresist stripping, etc., light Glue with positive Photoresist is an example.
  • the TF1HLCD array substrate provided by the embodiment of the present invention will be described below.
  • the TTTH LCD array substrate mainly includes a gate line, a data line, a TFT and a pixel electrode, and the mutually perpendicular gate lines and data lines define a pixel unit, the TTT and the pixel electrode are formed in the pixel unit, and the cabinet line is used to provide opening to the TFT.
  • the signal, the data line ffi provides a data signal to the pixel electrode.
  • the TFT is an active switching element.
  • FIG. 15 is a cross-sectional view showing a TF LCD array substrate according to an embodiment of the present invention.
  • the TF LCD column substrate provided by the embodiment of the present invention is provided with a display area and a peripheral area disposed around the display area.
  • the array substrate includes:
  • a gate electrode 200 formed on the substrate substrate 100, wherein a portion of the »pole 200 is located in a display region of the array substrate, and another portion of the gate electrode 200 is located at a peripheral region of the array substrate; And covering the gate insulating layer 300 of the entire substrate 100, a gate insulating layer via 301 is disposed on the gate insulating layer 300, and the gate insulating via 301 is located at least in part Above the gate 200, for example, the gate insulating layer via 301 is disposed above the gate 200 of the peripheral region;
  • a second transparent conductive portion 402 disposed in the same layer as the pixel electrode 400, the second transparent conductive portion 402 and the first transparent conductive portion 401 are respectively located on two sides of the gate 200; a source electrode 501 on a transparent conductive portion 401; a drain electrode 502 disposed on the second transparent conductive portion 402 and disposed in the same layer as the source electrode 501, the source electrode 501 and the drain electrode 502 are respectively located at two sides of the gate 200, for example, a part of the source electrode 501 and the drain electrode 502 are located between the display region of the array substrate to form a TFT channel region, and another portion of the source electrode 501 and the
  • the drain electrode 502 is located at a peripheral region of the array substrate, and two sides of the gate insulating layer via 301 are disposed;
  • a doped semiconductor layer 600 formed on the source electrode 501 and the drain electrode 502, respectively; a semiconductor layer 700 formed over the doped semiconductor layer 600, wherein the semiconductor layer 700 is disposed in a display region
  • the drain electrode 502 and the source electrode constituting the TFT channel region a corresponding position of the pole 501, forming a TFT channel 220;
  • the gate 200 is electrically connected to at least one of the source electrode 501 and the drain electrode 502.
  • the second transparent conductive portion 402 is integrally connected to the pixel electrode 400.
  • the first transparent conductive portion 401, the second transparent conductive portion 402, and the pixel electrode 400 can be etched from the same transparent conductive layer by the same patterning process in the embodiment, as an example, as shown in FIG.
  • the array substrate further includes: a common electrode 902 formed over the passivation layer 800.
  • the common electrode 902 of the ADS panel is also disposed on the array substrate.
  • the common electrode may not be disposed on the array substrate.
  • the common electrode 902 and the electrical connecting portion 901 are made of the same material - integrally formed by the same patterning process. It can be understood that, in practical applications, the common electrode 902 and the electrical connection portion 901 ffi may be made of different materials and formed by different patterning processes.
  • the source electrode 501 is matched with the shape of the first transparent conductive portion 401; the shape of the drain electrode 502 and the second transparent conductive portion 402 is match.
  • the source electrode 501 may be integrally formed with the first transparent conductive portion 401 under the same through a same patterning process (gray mask process); the drain electrode 502 may be located below The second transparent conductive portion 402 is integrally formed by the same patterning process (gray mask process).
  • the array substrate further includes a gate line (not shown) and a data line (not shown), wherein the gate line is disposed in the same layer as the gate 200, and The pole line is the same as the material of the pole 200, and is integrally formed by the same patterning process; the data line is disposed in the same layer as the source electrode 501 and the drain electrode 502, and the data line is Source electrode 501 The material of the drain electrode 502 is the same and is integrally formed by the same patterning process.
  • a portion of the gate 200 is located in the display region, another portion of the gate 200 is located in the peripheral region, and the gate insulating layer via 301 is disposed at Located above the gate 200 of the peripheral region. It should be understood that, in actual practice, the gate insulating via 30] may also be disposed above the gate 200 of the display region.
  • the fabrication method of the TF'I ⁇ LCD provided by the embodiment of the present invention reduces the number of patterning processes compared with the conventional TF'H D array substrate manufacturing method.
  • the number of patterning processes in the embodiment of the present invention is 5 times, which is reduced by 2
  • the secondary process reduces manufacturing cost and increases productivity; and, in the embodiment of the present invention, the TFT channel is formed during the process of depositing the semiconductor layer 700, and is fundamentally compared with the conventional TFT channel formed by etching. Avoiding the occurrence of TFT channel defects, thus greatly improving production
  • the embodiment of the present invention further provides a display device including the TFTiCD array substrate according to the embodiment of the present invention.
  • the embodiment of the present invention further provides a method for fabricating the above TFT D array substrate, comprising: Step 1 : depositing a gate metal film on the substrate, and forming a first pattern including the gate 200 by a first patterning process;
  • Step 2 sequentially depositing a gate insulating film, a first transparent conductive film, a source and a drain metal film, and a doped a- ⁇ film on the base substrate on which the first pattern is formed, and forming a pixel including the second patterning process a second pattern of the electrode 400, the source electrode 501, the drain electrode 502, and the doped semiconductor layer 600;
  • Step 3 depositing an a-Si film on the substrate substrate on which the second pattern is formed, and forming by the third patterning process a third pattern of the TFT channel, the semiconductor layer 700, and the gate insulating layer via 301, wherein the gate insulating layer via 301 is disposed at a position corresponding to the gate 200;
  • Step 4 depositing a passivation layer film on the base substrate on which the third pattern is formed, and forming a fourth pattern including a passivation layer via 801 by a fourth patterning process, wherein the passivation layer via 801 and The position of the gate insulating layer via 301 corresponds to;
  • Step 5 depositing a second transparent conductive film on the base substrate on which the fourth pattern is formed, and forming a fifth pattern including the electrical connection portion 901 by a fifth patterning process, wherein at least the electrical connection portion 901 a portion is located in the passivation layer via 801 and the via insulating via 301, and electrically connect the gate 200 to at least one of the source electrode 501 and the drain electrode 502 Pick up.
  • FIG. 3 to FIG. 14 sequentially illustrate the manufacturing process of the TFT ⁇ LCD array substrate provided by the embodiment of the present invention.
  • a method of manufacturing the TF LCD array substrate provided by the embodiment of the present invention will be specifically described.
  • FIG. 3 is a cross-sectional view showing the gate electrode 200 formed on the base substrate by the first patterning process.
  • the process of forming the cabinet 200 by the first patterning process on the substrate substrate includes: providing a substrate substrate 00;
  • a gate metal film is deposited on the base substrate 100 by magnetron sputtering, thermal evaporation or other film forming methods, wherein the metal film of the cabinet may be molybdenum, aluminum, aluminum-bismuth alloy, tungsten, chromium, copper.
  • a single-layer film formed by a metal, ffi may be a multilayer film formed by depositing the above metal layers;
  • the photoresist is exposed and developed through a common mask such that the photoresist remains at least at a corresponding position of the gate 200;
  • the exposed gate metal film is etched away by a first etching process to form a first pattern including the gate electrode 200;
  • the first patterning process is completed, and the gate electrode 200 is formed on the base substrate 100.
  • the photoresist may be left at a position corresponding to the gate line during exposure and development processing, so that the exposed gate can be etched away by the first etching process. After the metal film, a gate line is formed.
  • FIG. 4 is a cross-sectional view showing the gate insulating film, the first transparent conductive film, the source and drain metal films, and the doped a- S1 film sequentially deposited on the base substrate 100 on which the first pattern is formed.
  • FIG. 5 is a cross-sectional view showing the photoresist after exposure and development processing after the photoresist is coated on the structure of FIG. 4.
  • FIG. 6 is a cross-sectional view showing the structure of FIG. 5 after the second etching process.
  • FIG. 7 is a cross-sectional view showing the photoresist in FIG. 6 after the ashing process.
  • Figure 8 is a cross-sectional view showing the structure of Figure 7 after a third etching process.
  • Figure 9 is a cross-sectional view of the structure of Figure 8 with the remaining photoresist removed.
  • the pixel electrode 400, the source electrode 501, the drain electrode 502, and the doped semiconductor layer 600 are formed on the substrate substrate 100 by a second patterning process, including: First, as shown in FIG. 4, using plasma enhanced chemical vapor deposition (PECVD), magnetron sputtering a gate insulating film 101, a first transparent conductive film, a source, a drain metal film 103, and a doping a are sequentially deposited on a base substrate 100 (such as a glass substrate or a quartz substrate) by a film, thermal evaporation, or other film forming method.
  • PECVD plasma enhanced chemical vapor deposition
  • the Si film 104 wherein the source and drain metal film 103 may be a single layer film formed of a metal such as molybdenum, aluminum, aluminum bismuth alloy, tungsten, chromium, copper or the like, or may be a multilayer film formed by depositing the above metal layers.
  • the first transparent conductive film 102 may be ⁇ , ⁇ , or the like;
  • a photoresist is applied on the doped a Si film 104, and the photolithography is performed through a double-tone mask (halftone mask or gray tone mask).
  • the adhesive 1000 is subjected to exposure and development processing, so that the photoresist 1000 forms a photoresist completely reserved region, a photoresist semi-reserved region, and a photoresist completely removed region, wherein the photoresist completely reserved region includes the source electrode 501.
  • the TFT channel may be disposed on a display area of the array substrate;
  • the first transparent conductive film 102, the source and drain metal films 103, and the doping a of the photoresist completely removed region are completely etched away by the second etching process.
  • a Si thin film 104 forming the first transparent conductive portion 401, the second transparent conductive portion 402, the source electrode 501, the drain electrode 502, and the doped semiconductor layer 600, and forming between the source electrode 501 and the drain electrode 502 a TFT channel region 220' and a first transparent conductive film 102 over the gate insulating layer 300, a source and a drain metal film i03, and a doped a- S1 film 104 at a position of the drain insulating layer via 301;
  • the dry etching and the wet etching are combined, and specifically, the doped a-Si film (for example, N+ a-Si) 104 may be etched by a gas such as SF 6 , HCL Cl 2 or He,
  • the photoresist 1000 of the photoresist semi-retained region is removed by an ashing process, and the doped a-Si film of the photoresist semi-reserved region is exposed.
  • 104 that is, the doped a-Si film 104 at a position corresponding to the pixel electrode 400 is exposed;
  • the catastrophic a-Si film and the source and drain metal films of the photoresist semi-reserved region are completely etched by the third etching process, that is, the pixels are etched away.
  • Electrode 400 a square source, a drain metal film, and an doped a-Si film, exposing the pixel electrode 400; finally, stripping the remaining photoresist] 000, thereby obtaining a junction formed with a second pattern as shown in FIG. Complete the second patterning process.
  • the photoresist 00 in the second patterning process, can be retained at the position corresponding to the data line during the exposure and development processing, so that the first etching can be performed by the second etching process.
  • the transparent conductive film 102, the source and drain metal films 103, and the doped a si film 104 form a pattern of data lines.
  • FIG. 10 is a cross-sectional view showing the a ⁇ film sequentially deposited on the base substrate 100 on which the second pattern is formed.
  • FIG. 11 is a cross-sectional view showing the photoresist 1000 after exposure and development processing after the photoresist 1000 is applied to the structure of FIG.
  • Figure 12 is a cross-sectional view showing the structure of Figure 1 after a fourth etching process and stripping away the remaining photoresist 1000.
  • a TFT channel 220, a semiconductor layer 700, and a gate insulating via 301 are formed on the base substrate 100 by a third patterning process, including:
  • a layer of a-Si film 201 can be deposited by PECVD or other film forming methods. After the deposition is completed, the data line, the source electrode 501 and the drain electrode 502 correspond to each other. Position, the a-Si film 201 is deposited on the doped semiconductor layer 600. At the position corresponding to the pixel electrode 400, the a-Si film 201 is deposited on the pixel electrode 400 in other regions (including the TFT channel 220 and the gate insulating layer). The layer corresponding to the layer via 301), the a-si film 201 is deposited on the gate insulating layer 300 ⁇ ;
  • the photoresist 1000 is first coated on the a-Si film 201, and then the photoresist 1000 is exposed and developed through a common mask to enable photolithography.
  • the glue 1000 covers the position corresponding to the semiconductor layer 700, and the remaining regions have no residual photoresist 1000.
  • the photoresist 1000 covers only the TFT channel 220 of the display region of the column substrate and the positions of the source electrode 501 and the drain electrode 502 on both sides thereof, and on the array substrate. a gate insulating layer via hole in the peripheral region and a position corresponding to the source electrode 501 and the drain electrode 502 on both sides thereof are not present in the photoresist 1000;
  • the etchant is used to engrave the candle by the fourth engraving process.
  • the gate insulating layer 300 can be etched by using the relationship of the engraving rate selection ratio (ie, the process condition that the etching rate of the f
  • Fig. 13 is a cross-sectional view showing the fourth patterning process of the structure of Fig. 12. Specifically, the process of forming the passivation layer 800 by the fourth patterning process includes:
  • a passivation layer film is deposited on the entire base substrate 100 by PECVD or other film formation method to form a passivation layer 800.
  • the passivation layer film may be a single layer film of SiNx, SiOx or SiOxNy, or a multilayer film formed by multilayer deposition of the above materials;
  • the photoresist is exposed and developed through the mask, and the photoresist is removed at least at a position corresponding to the via hole 801 of the passivation layer, wherein the passivation layer via 801 and the gate insulating layer pass through
  • the position of the hole 301 corresponds to;
  • the exposed passivation layer film is etched away by a fifth etching process to form a passivation layer via 801 communicating with the gate insulating layer via 301;
  • Fig. 14 is a cross-sectional view showing the fifth patterning process of the structure of Fig. 13. Specifically, the process of forming the electrical connection portion 901 by the fifth patterning process includes:
  • a second transparent conductive film is deposited on the base substrate 100 forming the fourth pattern, and the second transparent conductive film may be ⁇ , ⁇ , or the like;
  • the photoresist is exposed and developed through a common mask, and the photoresist is retained at least at a position corresponding to the passivation layer via 801;
  • the exposed second transparent conductive film is engraved by a sixth etching process, thereby forming an electrical connection portion 901 at the passivation layer via 801;
  • the photoresist may be retained at a position corresponding to the common electrode 902 during exposure and development processing, and then The common electrode 902 is simultaneously formed on the passivation layer 800 through the sixth etching process, that is, the structure as shown in FIG. 15 is obtained.
  • the TFTTLCD array substrate of the embodiment of the present invention is obtained by five patterning processes.

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Abstract

一种阵列基板及其制备方法和显示装置，所述方法包括：在衬底基板上沉积栅金属薄膜，通过第一次构图工艺形成包括栅极的第一图形；依次沉积栅极绝缘膜、第一透明导电薄膜、源、漏金属薄膜和掺杂a-si薄膜，通过第二次构图工艺形成包括像素电极、源电极、漏电极及掺杂半导体层的第二图形；沉积a-si薄膜，通过第三次构图工艺形成包括TFT沟道、半导体层及栅极绝缘层过孔的第三图形；沉积钝化层薄膜，通过第四次构图工艺形成包括钝化层过孔的第四图形，其中钝化层过孔与栅极绝缘层过孔的位置相对应；沉积第二透明导电薄膜，通过第五次构图工艺形成包括电性连接部的第五图形。所述制备方法能够减少制程，提高产品品质。

Description

阵列基板及其制造方法和显示装置
本申请主张在 2013 年 9 月 30 日在中国提交的中国专利申请号 No. 201310462378.9的优先权， 其全部内容通过引用包含于此。
Figure imgf000003_0001
薄膜晶体管液晶显示装置 (Thin Film Transistor Liquid Crystal Display, TFT-LCD) 是一种主要的平板显示装置。 现有的阵列基板 （Array Substrate) 包括： 栅线、 数据线、 薄膜晶体管 （Thin Film Transistor, TFT) 以及像素电 极。 栅线横向设置在衬底基板上， 数据线纵向设置在衬底基板之上， »线与 数据线的交叉处设置有 TFT。 TFT为有源开关元件。
如图 1所示， 现有的阵列基板包括： 栅极 10、栅绝缘层 20、 有源层 30、 源电极 50、 漏电极 60、 钝化层 70。 上述结构皆设置于衬底基板 80上。 其中 概极 10与栅线一体成型， 源电极 50、 漏电极 60与数据线一体成型， 漏电极 60与像素电极 90电连接。 当栅线中输入导通信号时， 有源层 30导电， 数据 线的数据信号可从源电极 50经 TFT沟道 31到达漏电极 60， 最终输入至像 素电极 90。 像素电极 90得到信号后与公共电极 91形成用于驱动液晶转动的 电场。 目前为了适应更高的集成度， 高 PPI (Pixels Per Inch) 产品已经成为 显示的主流， 但就此产品而言， 制备高 PPI的产品要求较高， 需要 7次构图 工艺形成结构图形来完成因为这样才能集成 GOA技术 （GOA技术即 Gate Driver on Array (阵列基板行驱动技术）， 是直接將栅极驱动电路（Gate driver ICs)制作在阵列基板上， 來代替由外接矽晶片制作的驱晶片一种技术。 该技 术的应用可直接做在面板周围， 減少制作程序， ϋ降低产品成本， 提高
TF LCD面板的高集成度， 使面板能更薄型化以及制备足够小的过孔。 每一 次构图工艺中又分别包括掩膜曝光、 显影、 刻蚀和剥离等工艺， 其中刻蚀工 艺包括干法刻蚀和湿法刻蚀， 所以构图工艺的次数可以衡量制造 TF LCD 阵列基板的繁筒程度， 减少构图工艺的次数就意味着制造成本的降低。
传统的 ADS模式的 TF iCD阵列基板的制程如图 3所示。 高级超维场 转换技术 ADSDS (ADvanced Super Dimension Switch)。 ADS是京东方自主 创新的以宽视角技术为代表的核心技术统称。 是平面电场宽视角核心技术高 级超维场转换技术， 其核心技术特性描述为： 通过 一平面内狭缝电极边缘 所产生的电场以及狹缝电极层与板状电极层间产生的电场形成多维电场， 使 液晶盒内狭缝电极间、 电极正上方所有取向液晶分子都能够产生旋转， 从而 提高了液晶工作效率并增大了透光效率。 高级超维场开关技术可以提高 T'F LCD产品的画面品质， 具有高分辨率、 高透过率、 低功耗、 宽视角、 高 开口率、 低色差、 无挤压水波纹 （push Mura) 等优点。 首先， 通过第一次构 图工艺在玻璃基板 （glass) 上形成欐线； 然后， 沉积栅绝缘层 20 和有源层 30, 通过第二次构图工艺形成有源层 30图形； 然后， 沉积像素电极， 通过第 三次构图工艺形成像素电极； 然后， 在栅绝缘层 20上通过第四次构图工艺形 成过孔 （GI 过孔）； 然后， 沉积金属层， 通过第五次构图工艺形成信号线和 有源层 30图形， 其中信号线通过 GI过孔与栅线实现导通， 并— 在沟道区域 形成信号线和有源层 30的图形； 然后， 沉积钝化层 （PVX)， 并通过第六次 构图工艺形成钝化层过孔； 最后， 沉积导电层， 并通过第七次构图工艺形成 公共电极， 由此， 共七次掩膜版工艺来完成阵列基板的结构图形。
由此可见， 目前对于 TFT^LCD阵列基板制程来说， 当制备高 PPI并—巨.包 含 GOA的产品时，为了布线密集等因素往往在制备过程中采用 7mask制备， 故常常由于 mask较多产量得不到提升； 并且， 现有 TFT^LCD阵列基板中沟 道的形成是利 刻蚀形成的， 往往由于刻蚀过程中工艺和设备等原因造成沟 道不良， 而且这种不良在生产线中经常高发， 影响产品品质。
本发明实施例的目的是提供一种阵列基板及其制备方法和显示装置， 能 够减少制程， 提高产品品质。 本发明实施例所提供的技术方案如下：
一种阵列基板的制作方法， 所述阵列基板包括栅极、 有源层、 源电极、 漏电极及像素电极， 所述有源层包括掺杂半导体层和半导体层； 所述制作方 法包括：
步骤 1， 在衬底基板上沉积栅金属薄膜， 通过第一次构图工艺形成包括 櫥极的第一图形；
步骤 2， 在形成所述第一图形的衬底基板上依次沉积栅极绝缘膜、 第一 透明导电薄膜、 源、 漏金属薄膜和掺杂 a- si薄膜， 通过第二次构图工艺形成 包括像素电极、 源电极、 漏电极及掺杂半导体层的第二图形；
步骤 3，在形成所述第二图形的衬底基板上沉积 a- si薄膜，通过第三次构 图工艺形成包括 TFT沟道、 半导体层以及栅极绝缘层过孔的第三图形， 其中 所述 »极绝缘层过孔设置于与所述栅极对应的位置；
步骤 4, 在形成所述第三图形的衬底基板上沉积钝化层薄膜， 通过第四 次构图工艺形成包括钝化层过孔的第四图形， 其中所述钝化层过孔与所述栅 极绝缘层过孔的位置相对应；
步骤 5， 在形成所述第四图形的衬底基板上沉积第二透明导电薄膜， 通 过第五次构图工艺形成包括电性连接部的第五图形， 其中所述电性连接部的 至少一部分位于所述钝化层过孔和所述栅极绝缘层过孔内， 并将所述栅极与 所述源电极、 所述漏电极中的至少一个电性连接。
进一步的， 所述步骤 1具体包括：
提供衬底基板；
在所述衬底基板上沉积栅金属薄膜；
在所述栅金属薄膜上涂覆光刻胶；
通过掩膜板对光刻胶进行曝光和显影处理， 至少在所述栅极对应的位置 保留光刻胶；
通过第一刻蚀工艺刻蚀掉暴露出的栅金属薄膜；
剥离剩余光刻胶。
进一步的， 所述歩骤 2具体包括：
在形成所述第一图形的衬底基板上依次沉积極极绝缘膜、 第一透明导电 薄膜、 源、 漏金属薄膜和掺杂 a si薄膜；
在掺杂 a-si薄膜上涂敷光刻胶；
通过双调掩模板对所述光刻胶进行曝光及显影处理， 使得所述光刻胶形 成光刻胶完全保留区、 光刻胶半保留区和光刻胶完全去除区， 其中所述光刻 胶完全保留区包括所述源电极、 所述漏电极对应的位置， 所述光刻胶半保留 区域对应包括像素电极对应的位置， 所述光刻胶完全去除区对应除所述光刻 胶完全保留区和所述光刻胶半保留区之外的位置， 其中所述光刻胶完全去除 区包括 TFT沟道及栅极绝缘层过孔对应的位置；
通过第二刻蚀工艺完全刻蚀掉所述光刻胶完全去除区的第一透明导电薄 膜、 源、 漏金属薄膜和掺杂 a-si薄膜；
通过灰化工艺去除所述光刻胶半保留区的光刻胶， 暴露出所述光刻胶半 保留区的掺杂 a—si薄膜；
通过第三刻蚀工艺完全刻蚀掉所述光刻胶半保留区的糁杂 a- S1薄膜和源、 漏金属薄膜；
剥离剩余光刻胶。
进一步的， 所述步骤 3具体包括：
在形成所述第二图形的衬底基板上沉积 a- 薄膜；
在所述 a- Si薄膜上涂覆光刻胶；
通过掩膜板对光刻胶进行曝光和显影处理， 仅在所述有源层对应的位置 保留光刻胶， 其中所述栅极绝缘层过孔所对应的位置去除光刻胶；
通过第四刻蚀工艺刻蚀掉暴露出的 a- S1薄膜， 并且在所述栅极绝缘层过 孔对应的位置通过所述第四刻蚀工艺刻蚀所述栅极绝缘层；
剥离剩余光刻胶。
进一步的， 所述步骤 4具体包括：
在形成所述第三图形的衬底基板上沉积钝化层薄膜；
在所述钝化层薄膜上涂覆光刻胶；
通过掩膜板对光刻胶进行曝光和显影处理， 至少在钝化层过孔对应的位 置去除光刻胶， 其中所述钝化层过孔与所述極极绝缘层过孔的位置对应； 通过第五刻蚀工艺刻烛掉暴露出的钝化层薄膜； 剥离剩余光刻胶。
进一步的， 所述步骤 5具体包括：
在形成所述第四图形的衬底基板上沉积第二透明导电薄膜；
在所述第二透明导电薄膜上涂覆光刻胶；
通过掩膜板对光刻胶进行曝光和显影处理， 至少在所述钝化层过孔对应 的位置保留光刻胶；
通过第六刻蚀工艺刻馊掉暴露出的第二透明导电薄膜；
剥离剩余光刻胶。
进一步的， 所述步骤 5中， 在形成所述第四图形的衬底基板上沉积第二 透明导电薄膜， 通过第五次构图工艺形成包括电性连接部的同时， 还通过所 述第五次构图工艺形成公共电极；
所述步骤 5具体包括：
在形成所述第四图形的衬底基板上沉积第二透明导电薄膜；
在所述第二透明导电薄膜上涂覆光刻胶；
通过掩膜板对光刻胶进行曝光和显影处理， 至少在公共电极及所述钝化 层过孔对应的位置保留光刻胶；
通过第六刻蚀工艺刻蚀掉暴露出的第二透明导电薄膜；
剥离剩余光刻胶。
一种阵列基板， 所述阵列基板包括：
衬底基板；
形成于所述衬底基板之上的 *极；
形成于所述栅极之上， 并覆盖整个所述衬底基板的栅极绝缘层， 所述栅 极绝缘层上设有栅极绝缘层过孔， 且所述 »极绝缘层过孔位于至少一部分所 述栅极的上方；
形成于所述 »极绝缘层之上的像素电极；
与所述像素电极同层设置的第一透明导电部；
与所述像素电极同层设置的第二透明导电部， 所述第二透明导电部与所 述第一透明导电部分别位于所述栅极的两侧；
设置于所述第一透明导电部之上的源电极； 设置于所述第二透明导电部之上， 并与所述源电极同层设置的漏电极， 所述源电极和所述漏电极分别位于所述栅极的两侧， 其中一部分所述源电极 和所述漏电极之间形成 TFT沟道区域， 另一部分所述源电极和所述漏电极之 间设置所述栅极绝缘层过孔；
分别形成于所述源电极和所述漏电极之上的揍杂半导体层；
形成于所述掺杂半导体层之上的半导体层， 其中所述半导体层仅设置在 构成所述 TFT沟道区域的所述漏电极和所述源电极相对应的位置，形成 TFT 沟道；
形成于所述半导体层之上的钝化层， 其中所述钝化层在与所述栅极绝缘 层过孔相对应的位置处设置有钝化层过孔， ϋ所述钝化层过孔与所述櫥极绝 缘层过孔相贯通， 且在所述钝化层过孔和所述栅极绝缘层过孔内设置有用于 将所述櫥极与所述源电极、 所述漏电极中的至少一个进行电性连接的电性连 接言 I
进一步的， 所述 列基板还包括： 形成于所述钝化层上的公共电极； 所述公共电极与所述电性连接部采用相同材质— 通过同一次构图工艺一 体成型。
进一步的， 所述阵列基板包括显示区域和设置于所述显示区域周边的周 边区域；
其中， 所述栅极中一部分位于所述显示区域， 另一部分位于所述周边区 进一歩的， 所述栅极绝缘层过孔设置在位于周边区域的所述栅极的 c上 一种显示装置， 包括如上所述的阵列基板。
本发明实施例所提供的阵列基板及其制作方法具有以下优点；
与传统的 TFT D阵列基板制造方法相比， 降低了构图工艺次数， 减少 了制程， 降低了制造成本， 提高了产能； 并且， 本发明实施例中， TFT沟道 是在沉积半导体层过程中形成， 与传统的采用刻蚀方式形成 TFT沟道相比， 从根本上避免了 TFT沟道不良的发生， 认而大大提升了产品品质。 图 1为传统的 TFTNLCD阵列基板的断面剖视图；
图 2为传统的 TF LCD阵列基板的 7mask制程示意图；
图 3所示为根据本发明实施例在衬底基板上通过第一次构图工艺形成栅 极后的剖面图；
图 4所示为根据本发明实施例在形成第一图形的衬底基板上依次沉积栅 极绝缘膜、第一透明导电薄膜、源、漏金属薄膜和掺杂 a- si薄膜后的剖面图； 图 5所示为图 4 的结构上涂覆了光刻胶后，并对光刻胶进行了曝光及显 影处理后的剖面图；
图 6所示为对图 5的结构进行了第二刻蚀工艺后的剖面图；
图 Ί所示为对图 6 中的光刻胶进行了灰化工艺之后的剖面图；
图 8为对图 7的结构进行了第三刻蚀工艺后的剖面图；
图 9为图 8的结构上剥离掉了剩余光刻胶后的剖面图；
图 10所示为在形成第二图形的衬底基板上依次沉积 a S1薄膜后的剖面图; 图 11所示为图 10的结构上涂覆了光刻胶后， 并对光刻胶进行了曝光及 显影处理后的剖面图；
图 12 为对图 i i的结构进行了第四刻蚀工艺，并剥离掉了剩余光刻胶后 的剖面图；
图 13所示为对图 12中的结构进行第四次构图工艺后的剖视图；
图 14所示为对图 13中的结构进行第五次构图工艺后的剖视图；
图 15所示为本发明实施例所提供的阵列基板的结构剖视图。
以下结合附图对本发明的原理和特征进行描述， 所举实例只用于解释本 发明， 并非用于限定本发明的范围。
需要说明的是：本发明实施例中所述的例如 "X 设置于 Y上"中的"上" 包含了 X与 Y接触， 并— § X位于 Y的上方的意思， 本发明实施例中如附图 所示， 将衬底基板定义为设置于最下方； 本发明实施例所称的构图工艺包括 光刻胶涂覆、 掩模、 曝光、 显影、 刻蚀、 光刻胶剥离等工艺， 光刻胶以正性 光刻胶为例。
以下说明本发明实施例所提供的 TF1HLCD阵列基板。
本实施例 TTTHLCD阵列基板主要包括栅线、 数据线、 TFT和像素电极， 相互垂直的栅线和数据线定义了像素单元， TTT和像素电极形成在像素单元 内， 櫥线用于向 TFT提供开启信号， 数据线 ffi于向像素电极提供数据信号。
TFT为有源开关元件。
如图 15所示为本发明实施例 TF LCD阵列基板的断面剖视图。 本发明 实施例所提供的 TF LCD 列基板设有显示区域和设置于所述显示区域周 边的周边区域； 如图 15所示， 所述阵列基板包括：
衬底基板 100;
形成于所述衬底基板 100之上的栅极 200, 其中， »极 200的一部分位 于阵列基板的显示区域， 栅极 200的另一部分位于阵列基板的周边区域； 形成于所述 »极 200之上， 并覆盖整个所述衬底基板 100的栅极绝缘层 300， 在所述栅极绝缘层 300上设有栅极绝缘层过孔 301， 且所述欐极绝缘层 过孔 301位于至少一部分所述栅极 200的上方， 例如， 所述栅极绝缘层过孔 301设置在位于所述周边区域的栅极 200的上方；
形成于所述 *极绝缘层 300之上的像素电极 400;
与所述像素电极 400同层设置的第一透明导电部 401 ;
与所述像素电极 400 同层设置的第二透明导电部 402, 所述第二透明导 电部 402与所述第一透明导电部 401分别位于所述栅极 200的两侧； 设置于 所述第一透明导电部 401之上的源电极 501 ;设置于所述第二透明导电部 402 之上， 并与所述源电极 501 同层设置的漏电极 502， 所述源电极 501和所述 漏电极 502分别位于所述栅极 200的两侧，例如，其中一部分所述源电极 501 和所述漏电极 502之间位于阵列基板的显示区域形成 TFT沟道区域， 另一部 分所述源电极 501和所述漏电极 502位于阵列基板的周边区域， 设置所述栅 极绝缘层过孔 301的两侧；
分别形成于所述源电极 501和所述漏电极 502之上的惨杂半导体层 600; 形成于所述掺杂半导体层 600之上的半导体层 700， 其中所述半导体层 700设置在显示区域的构成所述 TFT沟道区域的所述漏电极 502和所述源电 极 501相对应的位置， 丛而形成 TFT沟道 220;
形成于所述半导体层 700之上的钝化层 800， 其中， 所述钝化层 800在 周边区域内与所述栅极绝缘层过孔 301 相对应的位置处设置有钝化层过孔 801， 且所述钝化层过孔 801与所述栅极绝缘层过孔 301相贯通， 且在所述钝 化层过孔 80】和所述栅极绝缘层过孔 30〗 内设置有用于将所述栅极 200与所 述源电极 501、所述漏电极 502中的至少一个进行电性连接的电性连接部 901。
本实施例中， 作为示例， 如图 15所示， 所述第二透明导电部 402与所述 像素电极 400连为一体。 采用上述方案， 第一透明导电部 401、 第二透明导 电部 402和像素电极 400可以通过同一次构图工艺由同一透明导电层经刻蚀 本实施例中， 作为示例， 如图 15所示， 所述阵列基板还包括： 形成于所 述钝化层 800之上的公共电极 902。 ADS面板的公共电极 902也设置于阵列 基板上， 当然可以理解的是， 对于其他类型面板， 公共电极也可以不设置于 阵列基板上。
本实施例中， 作为示例， 如图 15所示， 所述公共电极 902与所述电性连 接部 901采用相同材质― 通过同一次构图工艺一体成型。当然可以理解的是， 实际应用中， 所述公共电极 902与所述电性连接部 901 ffi可以是采用不同材 质， 并通过不同构图工艺形成。
本实施例中， 作为示例， 如图 15所示， 所述源电极 501与所述第一透明 导电部 401的形状相匹配； 所述漏电极 502与所述第二透明导电部 402的形 状相匹配。
采用上述方案， 所述源电极 501可以是与位于其下方的所述第一透明导 电部 401通过同一次构图工艺 （灰阶掩膜工艺） 一体成型； 所述漏电极 502 可以是与位于其下方的所述第二透明导电部 402通过同一次构图工艺 （灰阶 掩膜工艺） 一体成型。
此外， 本实施例中， 作为示例， 所述阵列基板还包括栅线 （未示出） 和 数据线（未示出）， 其中， 所述栅线与所述栅极 200同层设置， 且所述極线与 所述極极 200的材质相同， 并通过同一次构图工艺一体成型； 所述数据线与 所述源电极 501和所述漏电极 502同层设置， ϋ所述数据线与所述源电极 501 和所述漏电极 502的材质相同， 并通过同一次构图工艺一体成型。 此外， 需要说明的是， 本实施例中， 所述栅极 200的一部分位于所述显 示区域， 所述栅极 200的另一部分位于所述周边区域， 所述栅极绝缘层过孔 301 设置在位于周边区域的所述栅极 200的上方。 应当理解的是， 在实际应 ^中， 所述栅极绝缘层过孔 30】也可以设置于显示区域的栅极 200的上方。
本发明实施例所提供的 TF'I^LCD, 其制作方法与传统的 TF'H D阵列 基板制造方法相比， 降低了构图工艺次数， 本发明实施例构图工艺次数是 5 次， 减少了 2次制程， 降低了制造成本， 提高了产能； 并且， 本发明实施例 中， TFT沟道是在沉积半导体层 700过程中形成， 与传统的采用刻蚀方式形 成 TFT沟道相比， 从根本上避免了 TFT沟道不良的发生， 从而大大提升了产
1：：) πζ· 此外， 本发明实施例还提供了一种显示装置， 其包括本发明实施例所述 的 TFTiCD阵列基板。
本发明实施例还提供一种上述 TFT D阵列基板的制造方法， 包括： 步骤 1 , 在衬底基板上沉积栅金属薄膜， 通过第一次构图工艺形成包括 栅极 200的第一图形；
步骤 2 , 在形成所述第一图形的衬底基板上依次沉积栅极绝缘膜、 第一 透明导电薄膜、 源、 漏金属薄膜和掺杂 a- ^薄膜， 通过第二次构图工艺形成 包括像素电极 400、源电极 501、漏电极 502及掺杂半导体层 600的第二图形； 步骤 3，在形成所述第二图形的衬底基板上沉积 a- si薄膜，通过第三次构 图工艺形成包括 TFT沟道、 半导体层 700以及栅极绝缘层过孔 301的第三图 形， 其中所述栅极绝缘层过孔 301设置于与所述栅极 200对应的位置；
步骤 4, 在形成所述第三图形的衬底基板上沉积钝化层薄膜， 通过第四 次构图工艺形成包括钝化层过孔 801 的第四图形， 其中所述钝化层过孔 801 与所述栅极绝缘层过孔 301的位置相对应；
步骤 5， 在形成所述第四图形的衬底基板上沉积第二透明导电薄膜， 通 过第五次构图工艺形成包括电性连接部 901 的第五图形， 其中所述电性连接 部 901的至少一部分位于所述钝化层过孔 801和所述櫥极绝缘层过孔 301内， 并将所述栅极 200与所述源电极 501、 所述漏电极 502中的至少一个电性连 接。
图 3至图 14依次说明了本发明实施例所提供的 TFT^LCD阵列基板的制 造流程。以下具体说明本发明实施例所提供的 TF LCD阵列基板的制造方法。
如图 3所示为在衬底基板上通过第一次构图工艺形成栅极 200后的剖面 图。 具体地， 在衬底基板上通过第一次构图工艺形成櫥极 200的过程包括： 提供衬底基板】00;
首先， 采用磁控溅射、 热蒸发或其它成膜方法， 在所述衬底基板 100上 沉积一层栅金属薄膜， 其中櫥金属薄膜可以是钼、 铝、 铝钹合金、 钨、 铬、 铜等金属形成的单层薄膜， ffi可以是以上金属多层沉积形成的多层薄膜；
其次， 在所述栅金属薄膜上涂覆光刻胶；
然后， 通过普通掩膜板对光刻胶进行曝光和显影处理， 使得至少在栅极 200对应的位置保留光刻胶；
然后， 通过第一刻蚀工艺刻蚀掉暴露出的栅金属薄膜， 以形成包括栅极 200的第一图形；
最后， 剥离剩余光刻胶， 得到如图 3所示的第一图形的结构。
至此， 完成第一次构图工艺， 在衬底基板 100上形成栅极 200。
需要说明的是， 在第一次构图工艺中， 也可以在曝光、 显影处理时， 在 与栅线对应的位置保留光刻胶， 从而可以在通过第一刻蚀工艺刻蚀掉暴露出 的栅金属薄膜后， 形成栅线。
如图 4所示为在形成第一图形的衬底基板 100上依次沉积栅极绝缘膜、 第一透明导电薄膜、 源、 漏金属薄膜和掺杂 a- S1薄膜后的剖面图。 如图 5所 示为图 4 的结构上涂覆了光刻胶后，对光刻胶进行了曝光及显影处理后的剖 面图。 如图 6所示为对图 5的结构进行了第二刻蚀工艺后的剖面图。 如图 7 所示为对图 6 中的光刻胶进行了灰化工艺之后的剖面图。 图 8 为对图 7 的 结构进行了第三刻蚀工艺后的剖面图。 图 9为图 8的结构上剥离掉了剩余光 刻胶后的剖面图。
请结合图 4至 9以及图 15， 具体地， 在衬底基板 100上通过第二次构图 工艺形成像素电极 400、源电极 501、漏电极 502及掺杂半导体层 600，包括： 首先， 如图 4所示， 采用等离子增强化学气相沉积 （PECVD)、 磁控溅 射、 热蒸发或其它成膜方法， 在衬底基板 100 (如玻璃基板或石英基板） 上 依次沉积栅极绝缘膜 101、 第一透明导电薄膜】 02、 源、 漏金属薄膜 103和掺 杂 a- si薄膜 104，其中源、漏金属薄膜 103可以是钼、铝、铝钕合金、钨、铬、 铜等金属形成的单层薄膜， 也可以是以上金属多层沉积形成的多层薄膜。 第 一透明导电薄膜 102可以为 ΙΤΌ、 ΪΖΟ等；
其次， 如图 5和图 15所示， 在揍杂 a si薄膜 104上涂敷光刻胶】000， 通 过双调掩模板（半调掩膜板或灰调掩膜板）对所述光刻胶 1000进行曝光及显 影处理， 使得所述光刻胶 1000形成光刻胶完全保留区、 光刻胶半保留区和光 刻胶完全去除区， 其中所述光刻胶完全保留区包括源电极 501、 漏电极 502 所对应的位置，所述光刻胶半保留区域对应包括像素电极 400所对应的位置， 所述光刻胶完全去除区对应除所述光刻胶完全保留区和所述光刻胶半保留区 之外的位置， 其中 TFT沟道 220及栅极绝缘层过孔 301所对应的位置不存在 光刻胶 1000， 位于所述光刻胶完全去除区， 其中栅极绝缘层过孔可以设置于 阵列基板的周边区域， TFT沟道可以设置于阵列基板的显示区域；
然后， 如图 6、 图 5和图 15所示， 通过第二刻蚀工艺完全刻蚀掉所述光 刻胶完全去除区的第一透明导电薄膜 102、 源、 漏金属薄膜 103 和糁杂 a- si 薄膜 104， 丛而形成所述第一透明导电部 401、 第二透明导电部 402、 源电极 501、 漏电极 502以及掺杂半导体层 600， 并在源电极 501和漏电极 502之间 形成 TFT沟道区域 220' 以及在欐极绝缘层过孔 301位置处去除栅极绝缘层 300上方的第一透明导电薄膜 102、源、漏金属薄膜 i03和掺杂 a- S1薄膜 104; 其中， 可以采用干刻和湿刻结合的刻蚀方式， 具体地， 可以通过 SF6、 HCL Cl2、 He等气体对掺杂 a- si薄膜（例如， N+ a- Si) 104进行刻蚀， 通过磷酸和 硝酸的混合物制得的刻蚀剂对源、 漏金属薄膜 103进行刻蚀， 通过硫酸或过 氧化物等刻蚀剂对第一透明导电薄膜 102 (ITO或 IZO) 进行刻蚀；
然后， 如图 7、 图 6和图 15所示， 通过灰化工艺去除所述光刻胶半保留 区的光刻胶 1000， 暴露出所述光刻胶半保留区的掺杂 a- si薄膜 104， 即暴露 出像素电极 400所对应的位置处的掺杂 a- si薄膜 104;
之后， 如图 8、 图 7和图 15所示， 通过第三刻蚀工艺完全刻蚀掉所述光 刻胶半保留区的惨杂 a- si薄膜和源、 漏金属薄膜， 即刻蚀掉像素电极 400上 方的源、 漏金属薄膜和掺杂 a- si薄膜， 暴露出所述像素电极 400; 最后， 剥离剩余光刻胶】 000， 得到如图 9所示的形成有第二图形后的结 至此， 完成第二次构图工艺。
需要说明的是， 在第二次构图工艺中， 也可以在曝光、 显影处理时， 在 与数据线对应的位置处保留光刻胶】000， 从而可以通过第二刻蚀工艺刻蚀掉 第一透明导电薄膜 102、 源、 漏金属薄膜 103和揍杂 a si薄膜 104， 形成数据 线的图形。
如图 10所示为在形成第二图形的衬底基板 100上依次沉积 a ^薄膜后的 剖面图。如图 11所示为图 10的结构上涂覆了光刻胶 1000后，对光刻胶 1000 进行了曝光及显影处理后的剖面图。 图 12为对图 1】的结构进行了第四刻蚀 工艺并剥离掉了剩余光刻胶 1000后的剖面图。
如图 10至 12所示， 并结合图 i5， 具体地， 在衬底基板 100上通过第三 次构图工艺形成 TFT沟道 220、 半导体层 700以及栅极绝缘层过孔 301， 包 括：
首先， 如图 10和图 15所示， 通常可以采用 PECVD或其它成膜方法， 沉积一层 a- si薄膜 201 ; 完成本次沉积后， 在数据线、 源电极 501和漏电极 502所对应的位置， a- si薄膜 201沉积在掺杂半导体层 600上，在像素电极 400 所对应的位置， a- si薄膜 201沉积在像素电极 400上， 在其它区域（包括 TFT 沟道 220和栅极绝缘层过孔 301所对应的位置）， a-si薄膜 201沉积在栅极绝 缘层 300 ±；
然后，如图 11、图 10和图 15所示，先在 a- si薄膜 201上涂覆光刻胶 1000， 然后通过普通掩膜板，对光刻胶 1000进行曝光及显影处理，使得光刻胶 1000 覆盖半导体层 700所对应的位置上， 其它区域无剩余光刻胶 1000。 例如， 如 图 11和图 15所示， 光刻胶 1000仅覆盖在 列基板的显示区域的 TFT沟道 220及其两侧的源电极 501和漏电极 502所对应的位置， 而在阵列基板的周 边区域的栅极绝缘层过孔及其两侧的源电极 501和漏电极 502所对应的位置 不存在光刻胶 1000;
然后， 如图 12、 图 11和图 15所示， 通过第四刻烛工艺利用刻蚀剂刻烛 掉没有光刻胶】000覆盖的 薄膜 201， 形成了半导体层 700的图形， 并且 在所述栅极绝缘层过孔 301对应的位置通过所述第四刻蚀工艺刻蚀所述栅极 绝缘层 300， 形成了 »极绝缘层过孔 301 ; 其中， 半导体层 700形成在显示区 域的 TTT沟道及其两侧的源电极 501和漏电极 502之上，位于 TFT沟道区域 上的半导体层 700即形成了 TTT沟道 220， 这样， 利用 a- si薄膜 20】沉积而 不需刻蚀直接形成 TFT沟道， 避免由于刻蚀形成 TFT沟道而产生的问题， 并 且， 在半导体层 700刻蚀完成后， 可以利用刻馊速率选择比的关系 （即： 利 ffi栅极 200保护层刻蚀速率远高于数据线金属刻蚀速率的工艺条件） 对栅极 绝缘层 300进行刻蚀， 而以不会或者较少的将数据线金属刻蚀的方式进行， 从而形成栅极绝缘层过孔 301 ;
最后， 剥离掉了剩余的光刻胶 1000， 得到如图 12所示的形成有第三图 形后的结构。
如图 13所示为对图 12中的结构进行第四次构图工艺后的剖视图。 具体 地， 通过第四次构图工艺形成钝化层 800的过程包括：
首先， 在整个衬底基板 100采用 PECVD或其它成膜方法沉积一层钝化 层薄膜， 形成钝化层 800。 钝化层薄膜可以采 SiNx、 SiOx 或 SiOxNy的单 层薄膜， 或上述材料多层沉积形成的多层薄膜；
其次， 在所述钝化层薄膜上涂覆光刻胶；
然后，通过掩膜板对光刻胶进行曝光和显影处理，至少在钝化层过孔 801 所对应的位置去除光刻胶， 其中所述钝化层过孔 801与所述栅极绝缘层过孔 301的位置对应；
然后， 通过第五刻蚀工艺刻蚀掉暴露出的钝化层薄膜， 形成与所述栅极 绝缘层过孔 301相通的钝化层过孔 801；
最后， 剥离剩余光刻胶， 得到如图 13所示的形成有包括钝化层 800的第 四图形的结构。
如图 14所示为对图 13中的结构进行第五次构图工艺后的剖视图。 具体 地， 通过第五次构图工艺形成电性连接部 901的过程包括：
首先， 在形成所述第四图形的衬底基板 100上沉积第二透明导电薄膜， 第二透明导电薄膜可以为 ΙΤΟ、 ΙΖΟ等； 其次， 在所述第二透明导电薄膜上涂覆光刻胶；
然后， 通过普通掩膜板对光刻胶进行曝光和显影处理， 至少在所述钝化 层过孔 801对应的位置保留光刻胶；
然后， 通过第六刻蚀工艺刻馊掉暴露出的第二透明导电薄膜， 从而在所 述钝化层过孔 801处形成电性连接部 901 ;
最后， 剥离剩余光刻胶， 即得到本发明实施例所提供的 TF LCD阵列基 板。
需要说明的是， 对于 ADS模式的阵列基板来说， 在形成所述电性连接部 901 的同时， 可以通过在曝光、 显影处理时， 在公共电极 902所对应的位置 处保留光刻胶，再经所述第六刻蚀工艺同时在钝化层 800上形成公共电极 902， 即得到如图 15所示的结构。
至此， 通过 5次构图制程得到本发明实施例的 TFTTLCD阵列基板。
以上所述是本发明的优选实施方式， 应当指出， 对于本技术领域的普通 技术人员来说， 在不脱离本发明所述原理的前提下， 还可以作出若干改进和 润饰， 这些改进和润饰也应视为本发明的保护范围。

Claims

1 . 一种阵列基板的制作方法，所述阵列基板包括栅极、有源层、源电极、 漏电极及像素电极； 所述制作方法包括：
步骤 1， 在衬底基板上沉积栅金属薄膜， 通过第一次构图工艺形成包括 櫥极的第一图形；
步骤 2， 在形成所述第一图形的衬底基板上依次沉积栅极绝缘膜、 第一 透明导电薄膜、 源、 漏金属薄膜和掺杂 a- si薄膜， 通过第二次构图工艺形成 包括像素电极、 源电极、 漏电极及掺杂半导体层的第二图形；
步骤 3，在形成所述第二图形的衬底基板上沉积 a- si薄膜，通过第三次构 图工艺形成包括薄膜晶体管 TFT沟道、 半导体层以及 »极绝缘层过孔的第三 图形， 其中所述櫥极绝缘层过孔设置于与所述栅极对应的位置；
步骤 4, 在形成所述第三图形的衬底基板上沉积钝化层薄膜， 通过第四 次构图工艺形成包括钝化层过孔的第四图形， 其中所述钝化层过孔与所述栅 极绝缘层过孔的位置相对应；
步骤 5， 在形成所述第四图形的衬底基板上沉积第二透明导电薄膜， 通 过第五次构图工艺形成包括电性连接部的第五图形， 其中所述电性连接部的 至少一部分位于所述钝化层过孔和所述栅极绝缘层过孔内， 并将所述栅极与 所述源电极、 所述漏电极中的至少一个电性连接。
2. 根据权利要求 1所述的制作方法， 其中， 所述步骤 1包括： 提供衬底基板；
在所述衬底基板上沉积栅金属薄膜；
在所述栅金属薄膜上涂覆光刻胶；
通过掩膜板对光刻胶进行曝光和显影处理， 至少在所述栅极对应的位置 保留光刻胶；
通过第一刻蚀工艺刻蚀掉暴露出的栅金属薄膜；
剥离剩余光刻胶。
3. 根据权利要求 1或 2所述的制作方法， 其中， 所述步骤 2包括： 在形成所述第一图形的衬底基板上依次沉积極极绝缘膜、 第一透明导电 薄膜、 源、 漏金属薄膜和掺杂 a si薄膜；
在掺杂 a-si薄膜上涂敷光刻胶；
通过双调掩模板对所述光刻胶进行曝光及显影处理， 使得所述光刻胶形 成光刻胶完全保留区、 光刻胶半保留区和光刻胶完全去除区， 其中所述光刻 胶完全保留区包括所述源电极、 所述漏电极对应的位置， 所述光刻胶半保留 区域对应包括像素电极对应的位置， 所述光刻胶完全去除区对应除所述光刻 胶完全保留区和所述光刻胶半保留区之外的位置， 其中所述光刻胶完全去除 区包括 TFT沟道及栅极绝缘层过孔对应的位置；
通过第二刻蚀工艺完全刻蚀掉所述光刻胶完全去除区的第一透明导电薄 膜、 源、 漏金属薄膜和掺杂 a-si薄膜；
通过灰化工艺去除所述光刻胶半保留区的光刻胶， 暴露出所述光刻胶半 保留区的掺杂 a—si薄膜；
通过第三刻蚀工艺完全刻蚀掉所述光刻胶半保留区的糁杂 a- S1薄膜和源、 漏金属薄膜；
剥离剩余光刻胶。
4. 根据权利要求 1至 3中任一项所述的制作方法， 其中，
所述歩骤 3包括：
在形成所述第二图形的衬底基板上沉积 a- S1薄膜；
在所述 a- si薄膜上涂覆光刻胶；
通过掩膜板对光刻胶进行曝光和显影处理， 在所述有源层对应的位置保 留光刻胶， 其中所述栅极绝缘层过孔所对应的位置去除光刻胶；
通过第四刻蚀工艺刻蚀掉暴露出的 a- ^薄膜， 并且在所述栅极绝缘层过 孔对应的位置通过所述第四刻蚀工艺刻蚀所述栅极绝缘层；
剥离剩余光刻胶。
5. 根据权利要求 1至 4中任一项所述的制作方法， 其中，
所述步骤 4包括：
在形成所述第三图形的衬底基板上沉积钝化层薄膜； 置去除光刻胶， 其中所述钝化层过孔与所述栅极绝缘层过孔的位置对应； 通过第五刻蚀工艺刻蚀掉暴露出的钝化层薄膜；
剥离剩余光刻胶。
6. 根据权利要求 1至 5中任一项所述的制作方法， 其中，
所述步骤 5包括：
在形成所述第四图形的衬底基板上沉积第二透明导电薄膜；
在所述第二透明导电薄膜上涂覆光刻胶；
通过掩膜板对光刻胶进行曝光和显影处理， 至少在所述钝化层过孔对应 的位置保留光刻胶；
通过第六刻蚀工艺刻蚀掉暴露出的第二透明导电薄膜；
剥离剩余光刻胶。
7. 根据权利要求 1至 6中任一项所述的制作方法， 其中，
所述歩骤 5中， 在形成所述第四图形的衬底基板上沉积第二透明导电薄 膜， 通过第五次构图工艺形成包括电性连接部的同时， 还通过所述第五次构 图工艺形成公共电极。
8. 根据权利要求 7所述的制作方法， 其中，
所述歩骤 5还包括：
在形成所述第四图形的衬底基板上沉积第二透明导电薄膜；
在所述第二透明导电薄膜上涂覆光刻胶；
通过掩膜板对光刻胶进行曝光和显影处理， 至少在公共电极及所述钝化 层过孔对应的位置保留光刻胶；
通过第六刻蚀工艺刻蚀掉暴露出的第二透明导电薄膜；
剥离剩余光刻胶。
9. 一种阵列基板， 包括：
衬底基板；
形成于所述衬底基板之上的栅极；
形成于所述栅极之上， 并覆盖整个所述衬底基板的極极绝缘层， 所述櫥 极绝缘层上设有栅极绝缘层过孔， 且所述栅极绝缘层过孔位于至少一部分所 述栅极的上方； 形成于所述 »极绝缘层之上的像素电极；
与所述像素电极同层设置的第一透明导电部；
与所述像素电极同层设置的第二透明导电部， 所述第二透明导电部与所 述第一透明导电部分别位于所述栅极的两侧；
设置于所述第一透明导电部之上的源电极；
设置于所述第二透明导电部之上， 并与所述源电极同层设置的漏电极， 所述源电极和所述漏电极分别位于所述栅极的两侧， 其中一部分所述源电极 和所述漏电极之间形成 TFT沟道区域， 另一部分所述源电极和所述漏电极之 间设置所述栅极绝缘层过孔；
分别形成于所述源电极和所述漏电极之上的掺杂半导体层；
形成于所述掺杂半导体层之上的半导体层， 其中所述半导体层仅设置在 构成所述 T'FT沟道区域的所述漏电极和所述源电极相对应的位置，形成 TFT 沟道；
形成于所述半导体层之上的钝化层， 其中所述钝化层在与所述栅极绝缘 层过孔相对应的位置处设置有钝化层过孔， ― §所述钝化层过孔与所述 »极绝 缘层过孔相贯通， 且在所述钝化层过孔和所述栅极绝缘层过孔内设置有用于 将所述欐极与所述源电极、 所述漏电极中的至少一个进行电性连接的电性连 接部。
10.根据权利要求 9所述的阵列基板， 其中，
所述阵列基板还包括： 形成于所述钝化层上的公共电极；
所述公共电极与所述电性连接部采用相同材质— 通过同一次构图工艺一 体成型。
11. 根据权利要求 9或 10所述的阵列基板， 其中，
所述阵列基板包括显示区域和设置于所述显示区域周边的周边区域； 其中， 所述栅极的一部分位于所述显示区域， 所述 »极的另一部分位于 所述周边区域。
12. 根据权利要求 11所述的阵列基板， 其中，
所述栅极绝缘层过孔设置在位于周边区域的所述栅极的上方或者位于显 示区域的所述櫥极的上方。
3. 一种显示装置， 包 I要求 9至】 2中任一项所述的阵列基板,
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