WO2014015453A1 - 薄膜晶体管、阵列基板及其制作方法、显示装置 - Google Patents

薄膜晶体管、阵列基板及其制作方法、显示装置 Download PDF

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Publication number
WO2014015453A1
WO2014015453A1 PCT/CN2012/001510 CN2012001510W WO2014015453A1 WO 2014015453 A1 WO2014015453 A1 WO 2014015453A1 CN 2012001510 W CN2012001510 W CN 2012001510W WO 2014015453 A1 WO2014015453 A1 WO 2014015453A1
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Prior art keywords
layer
electrode
gate
pattern
transparent conductive
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PCT/CN2012/001510
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English (en)
French (fr)
Inventor
张学辉
刘翔
薛建设
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京东方科技集团股份有限公司
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Priority to EP12867720.0A priority Critical patent/EP2879187B1/en
Priority to KR1020137018073A priority patent/KR20140024267A/ko
Priority to JP2015523358A priority patent/JP2015525000A/ja
Priority to US13/985,196 priority patent/US9209308B2/en
Publication of WO2014015453A1 publication Critical patent/WO2014015453A1/zh

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    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
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    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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    • H01L27/1259—Multistep manufacturing methods
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H—ELECTRICITY
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO

Definitions

  • Embodiments of the present invention relate to a thin film transistor, an array substrate, a method of fabricating the same, and a display device. Background technique
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • IPS In-Plane Switching
  • VA Very Alignment
  • AD-SDS Advanced-Super Dimensional Switching, also known as ADS
  • a multi-dimensional electric field is formed by the electric field generated by the edge of the slit electrode in the same plane and the electric field generated between the slit electrode layer and the plate electrode layer, so that all the liquid crystals are directly above the slit electrode in the liquid crystal cell and above the electrode.
  • the molecules are capable of rotating, thereby improving the efficiency of the liquid crystal and increasing the light transmission efficiency.
  • a low-resistance material such as copper has a resistance of only 2 ⁇ , which has low adhesion to the substrate and the semiconductor, and is liable to cause poor contact of the electrode material, and reacts with Si at a lower temperature to diffuse to the active layer, thereby affecting Device performance.
  • Embodiments of the present invention provide a solution for diffusing a low-resistance material to an active layer and A thin film transistor, an array substrate, a method for fabricating the same, and a display device, which have technical problems such as poor adhesion of a board and a semiconductor material.
  • a first aspect of the present invention provides a thin film transistor including a gate electrode, a gate insulating layer, an active layer, an electrode metal layer, and a passivation layer formed on a substrate;
  • the electrode metal layer includes a source electrode and a drain electrode, and a source electrode and The drain electrodes are isolated from each other to define a channel region between each other; a second transparent conductive layer is formed between the active layer and the electrode metal layer.
  • a first transparent conductive layer is formed between the gate and the substrate.
  • the material of the gate and the electrode metal layer is copper; and between the first transparent conductive layer and the gate and/or between the second transparent conductive layer and the electrode metal layer, respectively Layer metal layer.
  • the material of the metal layer is one of molybdenum, aluminum, tantalum, titanium or an alloy thereof.
  • the active layer is an amorphous silicon or an oxide semiconductor material.
  • the first transparent conductive layer and/or the second transparent conductive layer are an oxide, an indium tin oxide, an indium oxide, a polyethylene dioxythiophene or a graphene material.
  • a second aspect of the present invention provides a method of fabricating a thin film transistor, comprising the steps of: forming a gate on a substrate; forming a gate insulating layer and an active layer on the gate; A second transparent conductive layer is formed on the source layer, and source and drain electrodes are spaced apart from each other on the second transparent conductive layer; a passivation layer is formed on the source and drain electrodes, and the second transparent conductive layer.
  • forming the gate on the substrate includes: forming a first transparent conductive layer on the substrate as a reinforcing adsorption layer between the gate and the substrate.
  • an array substrate comprising the thin film transistor according to any one of the above, or a thin film transistor produced by the method of any one of the above.
  • the array substrate is provided with a pixel electrode and a common electrode, the pixel electrode and the common electrode are disposed on different layers of the array substrate, and the pixel electrode and the common electrode An insulating layer is provided therebetween, and the shape of the pixel electrode is a slit shape.
  • the common electrode and the first transparent conductive layer are made of the same material, and both are formed in the same photolithography process; the pixel electrode and the second transparent conductive layer are the same Materials, and both are formed in the same lithography process.
  • a fourth aspect of the present invention further provides a method for fabricating an array substrate, comprising the steps of: forming a gate pattern, a gate line pattern, and a gate line PAD area pattern on a substrate; sequentially forming a gate An insulating layer and an active layer; a second transparent conductive layer, source and drain electrodes spaced apart from each other, a data line and a data line PAD region are sequentially formed; a passivation layer is formed to expose the gate line PAD region and the data line PAD region.
  • the array substrate is in an ADS mode, and forming a gate pattern, a gate line pattern, and a gate line PAD area pattern on the substrate includes:
  • the photoresist pattern is subjected to multi-step exposure development, and the gate metal layer is separately etched after each exposure and development to form a gate pattern, a gate line pattern, a gate line PAD area pattern, and a common electrode pattern.
  • the array substrate is in a TN mode, and forming a gate pattern, a gate line pattern, and a gate line PAD area pattern on the substrate includes:
  • the photoresist is spin-coated on the gate metal layer, and the mask is used for exposure and development to retain the photoresist corresponding to the gate pattern, the gate line pattern, and the gate line PAD area pattern;
  • the gate pattern, the gate line pattern, and the gate line PAD area pattern are formed by etching.
  • sequentially forming the gate insulating layer and the active layer further includes patterning the protective layer, including: continuously depositing a gate insulating layer , an oxide semiconductor layer and a protective layer;
  • Exposure development is performed using a halftone or gray tone mask, so that the photoresist of the protective layer pattern region is completely retained, and the portions of the photoresist for the contact regions coupled to the source and drain electrodes are retained; Etching forms an oxide semiconductor layer pattern and a protective layer pattern.
  • sequentially forming the gate insulating layer and the active layer includes:
  • a gate insulating layer, an active layer, and the active layer includes an intrinsic layer and an N-type layer;
  • the intrinsic layer and the N-type layer of the unretained photoresist region are etched away.
  • the open source and drain electrodes, data lines, and data line PAD areas include:
  • the patterning of the second transparent conductive layer and the electrode metal layer is included:
  • Exposure development is performed using a halftone or gray tone mask to completely retain the source electrode, the drain electrode and the data line, and the photoresist of the data line PAD region, so that the photoresist portion of the pixel electrode region remains;
  • the source electrode, the drain electrode and the data line, and the data line PAD area pattern are formed by multi-step etching.
  • the method further includes: etching the N-type layer of the channel region.
  • a fifth aspect of the invention provides a display device comprising the array substrate according to any one of the above, or the array substrate produced by the above-described manufacturing method.
  • the thin film transistor in the embodiment of the invention adds a transparent conductive layer between the substrate and the gate metal layer, between the active layer and the electrode metal layer, enhances the adhesion between the gate metal layer and the substrate, and blocks the electrode.
  • the diffusion of the metal layer to the active layer improves the performance of the product.
  • the method for fabricating the array substrate in the embodiment of the invention is simple, so that the array substrate and the display device based on the array substrate are low in cost and high in cost performance.
  • FIG. 1 to FIG. 1 are respectively schematic diagrams showing processes of forming a transparent conductive layer, a gate pattern, a gate line pattern, and a gate line PAD area pattern on a substrate in the first embodiment of the present invention
  • FIGS. 2a to 2e are schematic views showing a process of forming a gate insulating layer, an active layer and a protective layer on a substrate after FIG If in the first embodiment of the present invention
  • 3a to 3e are schematic diagrams showing processes of forming a second transparent conductive layer, an electrode metal layer, a passivation layer, and a data PAD region pattern on the substrate subsequent to FIG. 2e in the first embodiment of the present invention
  • FIG. 4 is a cross-sectional view of an array substrate in the first embodiment of the present invention.
  • Figure 5 is a cross-sectional view of the array substrate in the second embodiment of the present invention
  • 6 is a cross-sectional view of an array substrate in Embodiment 3 of the present invention
  • FIG. 7a to 7d are schematic views showing a process of fabricating an array substrate according to a third embodiment of the present invention.
  • FIG. 8 is a schematic diagram of a liquid crystal display device according to a fifth embodiment of the present invention.
  • 1 substrate; 2: first transparent conductive layer; 2a: enhanced adsorption layer; 2b: common electrode; 3: gate/gate film; 4: gate insulating layer; 5: active layer; 6: protective layer; : second transparent conductive layer; 7a: blocking diffusion layer; 7b: pixel electrode; 8: electrode metal layer; 8a: source electrode; 8b: drain electrode; 9: passivation layer; 10: intrinsic layer; Layer; 15: photoresist; 110: gate line PAD; 120: data line PAD. detailed description
  • the array substrate of the embodiment of the present invention may include a plurality of gate lines and a plurality of data lines, the gate lines and the data lines crossing each other thereby defining a plurality of pixel units arranged in a matrix.
  • Each of the pixel units includes, for example, a thin film transistor as a switching element and a pixel electrode for controlling alignment of the liquid crystal.
  • the gate of the thin film transistor of each pixel is electrically connected or integrally formed with the corresponding gate line
  • the source is electrically connected or integrally formed with the corresponding data line
  • the drain is electrically connected or integrally formed with the corresponding pixel electrode.
  • This embodiment is an application in an ADS mode LCD, and the active layer used is an oxide semiconductor material.
  • the ADS mode is an example of a horizontal electric field type.
  • the gate electrode 3, the source electrode 8a, and the drain electrode 8b of the thin film transistor of the present embodiment are all made of copper; of course, these electrodes Materials such as molybdenum, aluminum, tantalum, copper, titanium, or the like, or alloys of each metal element may be used as needed.
  • the second transparent conductive layer 7 is between the metal copper electrodes 8a, 8b and the active layer 5, which prevents the diffusion of the electrode metal toward the active layer 5 caused by the reaction of the metal copper electrode with the active layer 5.
  • the gate line PAD 110 and the data line PAD 120 exemplarily show peripheral circuit portions of the array substrate for connection with external circuits such as input gate driving signals and data signals.
  • a first transparent conductive layer 2 may be disposed between the gate 3 and the substrate 1; the first transparent conductive layer 2 may increase the adhesion between the substrate 1 and the metal copper of the gate 3 to improve product stability. .
  • the first transparent conductive layer 2 shown in FIG. 4 can be further divided into two parts from its function, which are respectively the enhanced adsorption layer 2a between the gate 3 and the substrate 1 in the figure, and the gate insulating layer 4 and the substrate 1 Between the common electrode 2b.
  • the first transparent conductive layer 2 can simultaneously form the enhanced adsorption layer 2a and the common electrode 2b during the formation process.
  • the reinforced adsorption layer 2a increases the adhesion between the substrate 1 and the gate 3 metal copper to improve the stability of the product.
  • the formation of the reinforcing electrode layer 2a also forms the common electrode 2b, which simplifies the fabrication steps of separately forming the common electrode. It not only improves the quality of the thin film transistor, but also simplifies its fabrication process.
  • the second transparent conductive layer 7 shown in FIG. 4 is further divided into two parts from its function, which are respectively between the source electrode 8a and the active layer 5 in the illustration, and between the drain electrode 8b and the active layer 5.
  • the barrier diffusion layer 7a and the pixel electrode 7b can be simultaneously formed, which can improve the quality of the thin film transistor and simplify the fabrication process thereof.
  • the first transparent conductive layer 2 and the second transparent conductive layer 7 may be transparently used respectively or simultaneously, such as indium tin oxide, indium oxide, indium tin oxide, polyethylene dioxythiophene or graphene.
  • a preferred example of the conductive material is ITO or the like.
  • An embodiment of fabricating an array substrate including the above thin film transistor includes the following steps.
  • a first transparent conductive layer 2 is formed on the substrate 1, and then a metallic copper gate film 3 is formed on the first transparent conductive layer 2.
  • the substrate 1 may be selected from substrates of different materials such as a glass substrate or a quartz substrate.
  • the method of the gate film 3 may be, for example, plasma enhanced chemical vapor deposition (PECVD), magnetron sputtering, thermal evaporation, or other film forming methods.
  • the first transparent conductive layer 2 may be formed by a deposition method, a spin coating method or a roll coating method.
  • a layer of photoresist 15 is spin-coated on the gate film 3.
  • the formation of the photoresist 15 can also be carried out by means of a spin: residual mode or a roll: residual mode.
  • a photoresist pattern having a height difference is formed on the gate layer.
  • exposure can be performed with different exposure amounts according to different positions of the photoresist layer, followed by development, so that different amounts of photoresist can be emitted at different positions of the photoresist layer, for example, two-tone mask can be used.
  • the template (for example, a halftone or gray tone mask) is subjected to exposure development.
  • the photoresist 15 after exposure and development is divided into a completely removed region I, a completely reserved region II, and a partially reserved region III.
  • the photoresist completely reserved region II corresponds to the gate pattern, the gate line and the gate line PAD 110 region pattern, the photoresist portion reserved region III corresponds to the common electrode pattern region, and the photoresist completely removed region I corresponds to the photoresist.
  • the region outside the region II and the photoresist portion retention region III is completely reserved.
  • Gate Line PAD Area and Data Line The PAD area refers to the peripheral circuit portion of the array substrate. It is used to connect to an external circuit board and input gate drive signals and data signals.
  • the multi-step etching includes, for example, a first etching ⁇ ashing ⁇ second etching.
  • the first transparent conductive layer 2 and the copper gate film 3 of the region I are completely removed by the first etching; and then, as shown in FIG. 1D, on the array substrate shown in FIG.
  • the photoresist 15 is ashed, the photoresist 15 of the partial retention region III is removed, and the photoresist completely preserved region is also partially thinned; then the array substrate shown in FIG.
  • the copper gate film 3 in the resist portion III of the photoresist is etched away to obtain a common electrode pattern.
  • the cross-sectional view of the array substrate is shown in FIG. As shown in Fig. If the etching is completed, the photoresist 15 is peeled off. go with
  • the ionic liquid stripping can be carried out by using direct peeling, or using PGMEA or EGMEA as a solvent.
  • the first transparent conductive layer 2 can increase the adhesion between the substrate 1 and the metal copper of the gate 3, and the stability of the product can be improved. Further, in the formation process of the first transparent conductive layer 2, if the enhanced adsorption layer 2a and the common electrode 2b are simultaneously formed, the quality of the thin film transistor can be improved, and the manufacturing process thereof can be simplified.
  • the gate insulating layer 4, the active layer 5, and the protective layer 6 are successively deposited;
  • a layer of photoresist 15 is spin-coated on the protective layer 6;
  • exposure development is performed using a two-tone mask such as a halftone or gray tone mask.
  • the photoresist 15 after exposure and development is divided into a completely removed region I, a partially reserved region II, and a completely reserved region III.
  • the photoresist completely reserved region III correspondingly forms a protective layer region for protecting the oxide semiconductor to prevent damage to the oxide semiconductor during the etching process
  • the photoresist partially reserved region II is used for forming the source electrode and the leakage current. Extreme contact area.
  • the protective layer 6 is not required, it can be removed by the exposure and development process of the photoresist.
  • the multi-step etching includes: first etching ⁇ ashing ⁇ second etching.
  • the first etching is performed using the above photoresist layer, and the photoresist is completely etched away to completely remove the active layer 5 and the protective layer 6 of the region I.
  • the photoresist 15 on the array substrate shown in FIG. 2b is ashed, and the photoresist 15 of the partial retention region II is removed, and the photoresist in the photoresist completely remains in the region.
  • a second etching is performed on the array substrate shown in FIG. 2c, and the protective layer 6 of the photoresist portion remaining region II is etched away to expose the oxide semiconductor, and the array substrate is completed.
  • the cross section is shown in Figure 2d.
  • the photoresist 15 is peeled off, and the removal method can be the same as the first step described above.
  • a second transparent conductive layer 7 and an electrode metal layer 8 are continuously formed on the substrate 1;
  • a layer of photoresist 15 is spin-coated on the electrode metal layer 8;
  • exposure development is performed using a two-tone mask such as a halftone or gray tone mask.
  • the photoresist 15 after exposure and development is divided into a completely removed region I, a completely reserved region II, and a partially reserved region III.
  • the photoresist completely reserved region II corresponds to the patterned source region 8a, the drain electrode 8b, the data line and the data line PAD120
  • the photoresist portion reserved region III corresponds to the pixel electrode region pattern
  • the photoresist completely removed region I corresponds to a region other than the photoresist completely remaining region II and the partially reserved region III.
  • the multi-step etching process includes: first etching ⁇ ashing ⁇ second etching.
  • the first etching is performed using the above photoresist layer, and the photoresist is completely etched away to completely remove the second transparent conductive layer 7 and the electrode metal layer 8 of the region I.
  • the photoresist 15 on the array substrate shown in FIG. 3b is ashed, and the photoresist 15 of the partial retention region III is removed, and the photolithography is completely lithographically preserved in the region.
  • the adhesive portion is thinned; then the second etching is performed on the array substrate shown in FIG. 3c, and the electrode metal layer 8 of the photoresist portion remaining region III is etched away to expose the second transparent conductive layer 7, and the array is completed.
  • a cross-sectional view of the substrate is shown in Figure 3d.
  • the photoresist 15 is peeled off, for example, in the same manner as in the first step.
  • a passivation layer 9 is deposited on the array substrate on which the third step described above is completed. As shown in Fig. 4, the gate line PAD region and the data line PAD region are exposed by exposure etching.
  • the fabrication of the thin film transistor array substrate of the embodiment of the present invention is completed.
  • the pixel electrode and the common pixel electrode are electrically connected to a source or a drain of the thin film transistor, and the electrodes are disposed on different layers of the array substrate.
  • An insulating layer is disposed between the pixel electrode and the common electrode, the common electrode covers substantially the entire pixel region, and the pixel electrode has a slit shape.
  • the fabrication process of the thin film transistor array substrate of the embodiment can be realized by using four patterning processes, that is, based on the fact that the number of patterning processes is not increased compared with the prior art, The fabrication of the thin film transistor array substrate is completed.
  • the TN mode is an example of a vertical electric field type.
  • Fig. 5 is a cross-sectional view showing a pixel unit including a thin film transistor in the array substrate of the present embodiment, which is different from the ADS mode LCD in the first embodiment.
  • the pixel electrode formed by the second transparent conductive layer 7 in the ADS mode LCD has a slit shape, and in the TN mode LCD, the pixel electrode formed by the second transparent conductive layer 7 has a plate shape or a sheet shape. Then, the first patterning process in the manufacturing process does not require a multi-step etching process using a halftone or gray tone mask for exposure development.
  • the difference between the array substrate of the present embodiment and the method for fabricating the array substrate of the first embodiment will be described below.
  • the method for fabricating the array substrate of this embodiment includes the following steps.
  • first transparent conductive layer 2 and the gate metal layer are formed, exposure and development are performed using a mask of the gate pattern, and the photoresist 15 of the gate, gate line, and gate line PAD110 region pattern is retained;
  • the above-mentioned laminate on the substrate 1 is etched to completely etch away the first transparent conductive layer and the gate metal layer in the regions other than the gate, gate, and gate line PAD110 regions.
  • the same steps as in the embodiment are performed to form the gate insulating layer 4, the active layer 6, the protective layer 6, the second transparent conductive layer 7, the source electrode 8a, the drain electrode 8b, and the passivation layer 9;
  • the second transparent conductive layer 7 forms a pixel electrode, the block structure of the pixel electrode may be ensured.
  • a transparent conductive layer is added between the active layer and the electrode metal layer in the thin film transistor, which can prevent the electrode metal from diffusing toward the active layer, thereby improving product performance.
  • the copper material is more diffusive to the active layer; in one example, to further prevent copper from diffusing toward the active layer and increasing the adsorption force of the copper, it is also possible at the gate and the first A metal layer is added between the transparent conductive layers and/or between the electrode metal layer and the second transparent conductive layer.
  • the material of the metal layer may be selected from a simple substance such as molybdenum, aluminum, tantalum or titanium or an alloy corresponding to each elemental substance.
  • the active layer in another embodiment of the present invention is an amorphous silicon material, and this embodiment is applicable to an ADS mode LCD, a TN mode LCD, or the like.
  • Figure 6 is a cross-sectional view showing a thin film transistor of this embodiment.
  • Active layer package The lower intrinsic layer 10 and the upper N-type layer 11 are used.
  • the intrinsic layer 10 is a-Si
  • the N-type layer 11 is N+ a- doped with an N-type dopant atom in a-Si. Si.
  • the structure of the thin film transistor of this embodiment is similar to that of the thin film transistor of the first embodiment, except that the active layer has a two-layer structure in this embodiment, and there is no protective layer structure of the thin film transistor of the first embodiment.
  • the steps of forming the gate pattern, the gate line pattern, the gate line PAD pattern, and the first transparent conductive layer pattern on the substrate 1 are the same as in the first embodiment. After the gate metal layer and the first transparent conductive layer structure are formed on the substrate, the following steps are performed.
  • a gate insulating layer 4 an a-Si material intrinsic layer 10, an N+ a-Si material N-type layer 11 are sequentially deposited on the substrate 1;
  • the photoresist 15 is exposed and developed to retain the photoresist of the active layer pattern region.
  • the cross-sectional view of the array substrate is as shown in Fig. 7a.
  • the intrinsic layer 10 and the N-type layer 11 of the unretained photoresist region are etched away.
  • the cross-sectional view of the array substrate is as shown in Fig. 7b.
  • the steps in the first embodiment are performed on the array substrate obtained through the above steps, and the source electrode, the drain electrode, the data line, and the data line PAD region pattern are formed on the array substrate, and the cross-sectional view of the array substrate is as shown in FIG. 7c.
  • the fabrication process of the array substrate of the embodiment further includes the following steps: etching the N-type layer of the channel region .
  • a cross-sectional view of the array substrate after etching the N-type layer of the channel region is shown in Fig. 7d.
  • a passivation layer 9 is deposited on the array substrate, and the gate line PAD region and the data line PAD region are exposed by exposure etching, thereby completing the fabrication of the thin film transistor array substrate of the present embodiment.
  • a transparent conductive layer is added between the active layer and the electrode metal layer in the thin film transistor of the present embodiment, thereby preventing diffusion of the electrode metal to the active layer, thereby improving product performance.
  • the metal electrode uses a copper material
  • the copper material is more diffusive to the active layer; in one example, in order to further prevent copper from diffusing into the active layer and increasing the adsorption force of copper, it is also possible to be transparent at the gate and the first Adding a metal layer between the conductive layers and/or between the electrode metal layer and the second transparent conductive layer, the material of the metal layer may be Select materials such as molybdenum, aluminum, tantalum, titanium, or the like, or alloys corresponding to each element.
  • the pattern of the metal layer in the array substrate of the above structure is the same as the pattern of the gate layer and the electrode metal layer, and the manufacturing method thereof is basically the same as that of the above embodiment, and the patterning of the metal layer is completed simultaneously when the gate layer and the electrode metal layer are patterned. .
  • the thin film transistor array substrate of this embodiment can also be completed by other fabrication methods.
  • this embodiment structurally adds a first transparent conductive layer 2 and a second transparent conductive layer 7, which can be formed by a separate patterning process. Although this increases the number of patterning processes and increases the manufacturing cost, the fabrication of the thin film transistor array substrate of this embodiment can still be completed.
  • This embodiment provides a method for fabricating a thin film transistor, including:
  • a passivation layer is formed on the electrode metal layer and the second transparent conductive layer.
  • the step of forming a gate on the substrate may include: first forming a first transparent conductive layer on the substrate as an enhanced adsorption layer between the gate and the substrate.
  • the gate electrode and the enhanced adsorption layer can be formed in the same step.
  • a common electrode for enhancing the adsorption layer and the array substrate can be simultaneously formed, which can improve the quality of the thin film transistor and simplify the fabrication process of the array substrate.
  • a first transparent conductive layer and a gate metal layer are continuously formed on the substrate; a photoresist pattern is formed on the gate metal layer; and the photoresist pattern is exposed and developed, and each exposure and development is respectively performed
  • the gate metal layer is etched to form a corresponding pattern. It should be noted that when the first transparent conductive layer simultaneously forms the common electrode of the array substrate, it is required to form a photoresist pattern having a height difference on the gate metal layer, and perform corresponding photoresist multi-step exposure development. .
  • the step of forming the gate insulating layer and the active layer on the gate includes: forming a gate insulating layer, an active layer continuously on the gate electrode, and forming a photoresist on the active layer a pattern; exposure and development of the photoresist pattern, etching after each exposure and development to form a corresponding pattern.
  • the active layer is an oxide semiconductor
  • a gate is formed on the gate continuously a rim layer, an active layer, a protective layer, and a photoresist is formed on the protective layer.
  • a gate insulating layer, an oxide semiconductor layer, and a protective layer are continuously deposited on the gate; a photoresist is spin-coated on the protective layer; and exposure and development are performed using, for example, a halftone or gray tone mask to make a protective layer pattern region
  • the photoresist is completely retained, leaving two portions of the photoresist for the contact regions coupled to the source and drain electrodes to remain; the oxide semiconductor layer pattern and the protective layer pattern are formed by multi-step etching.
  • the active layer when the active layer is an amorphous silicon material, the active layer includes an intrinsic layer and an N-type layer.
  • a gate insulating layer, an intrinsic layer, and an N-type layer For example, continuously depositing a gate insulating layer, an intrinsic layer, and an N-type layer; spin-coating a photoresist on the N-type layer; performing exposure development to leave a photoresist in an active layer pattern region; etching away unreserved lithography The intrinsic layer and the N-type layer of the glue region.
  • the step includes: continuously forming a second transparent conductive layer and an electrode metal layer on the gate insulating layer and the active layer; forming a photoresist pattern on the electrode metal layer; exposing and developing the photoresist pattern, each exposure Etching is performed after development to form a corresponding pattern.
  • the second transparent conductor layer may further form a pixel electrode required for the array substrate in the process step, and the pixel electrode may be formed into a slit shape or a plate shape or the like as needed.
  • etching is performed to form a source electrode and a drain electrode.
  • the active layer when the active layer is an amorphous silicon material, it further includes an N-type layer in which the channel region is etched away.
  • the photoresist completely retained region does not mean that the photoresist in the region does not change after development, but is substantially retained, and the thickness is greater than the thickness in the remaining portion of the photoresist portion.
  • An embodiment of the present invention also provides a display device comprising the array substrate of any of the above embodiments.
  • the liquid crystal display device includes a liquid crystal panel 100.
  • the array substrate 200 and the opposite substrate 300 are opposed to each other to form a liquid crystal cell, and are sealed by a sealant 350; the liquid crystal cell is filled with a liquid crystal material 400.
  • the counter substrate 300 is, for example, a color filter substrate.
  • a common electrode is formed on the opposite substrate 300 for forming a liquid crystal capacitance with each pixel electrode on the array substrate; for the ADS type, a common electrode may not be formed on the opposite substrate 300.
  • the pixel electrode of each pixel unit of the array substrate is used to apply an electric field to control the degree of rotation of the liquid crystal material to perform a display operation.
  • the liquid crystal display device further includes a backlight that provides backlighting for the array substrate.

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Abstract

提供了一种薄膜晶体管，其包括基板（1），以及在基板（1）上依次形成的栅极层（3）、栅绝缘层（4）、有源层（5）、电极金属层（8）和钝化层（9）；电极金属层（8）包括源电极（8a）和漏电极（8b），源电极（8a）和漏电极（8b）互相隔离，之间界定了沟道区域；栅极层（3）和基板（1）之间有第一透明导电层（2）；有源层（5）和电极金属层（8）之间有第二透明导电层（7）。由于增加了透明导电层（2，7），增强了栅极层（3）与基板（1）之间的附着力，阻止了电极金属向有源层（5）的扩散。

Description

薄膜晶体管、 阵列基板及其制作方法、 显示装置 技术领域
本发明的实施例涉及一种薄膜晶体管、 阵列基板及其制作方法、 显示装 置。 背景技术
薄膜晶体管液晶显示器 (Thin Film Transistor Liquid Crystal Display , TFT-LCD)具有体积小、 功耗低、无辐射等特点， 在当前的平板显示器市场占 据了主导地位。 对于 TFT-LCD来说， 薄膜晶体管阵列基板以及制造工艺决 定了其产品性能、 成品率和价格。 普通的 TN ( Twisted Nematic , 扭曲向列） 型液晶显示器的显示效果已经不能满足市场的需求。 目前， 各大厂商正逐渐 将显示效果更好的各种广视角显示技术应用于移动产品中， 这些技术比如包 括 IPS ( In-Plane Switching, 共面转换） 、 VA ( Vertical Alignment, 垂直配 向） 、 AD-SDS ( Advanced-Super Dimensional Switching, 高级超维场开关， 又简称 ADS )等。
在 ADS模式下， 通过同一平面内狭缝电极边缘所产生的电场以及狭缝 电极层与板状电极层间产生的电场形成多维电场， 使液晶盒内狭缝电极间、 电极正上方所有取向液晶分子都能够产生旋转， 从而提高了液晶工作效率并 增大了透光效率。
通过减小电极材料的电阻， 可降低电阻 /电容时间延迟（RC延迟） ， 由 此有助于提高开口率； 将驱动方式由两侧驱动变为单侧驱动， 可使驱动 IC 的数量可减半。 因此， 业界需要开发低电阻的电极材料。 目前， 当使用低电 阻材料作为电极材料时， 存在以下问题。 低电阻材料例如铜， 电阻仅为 2μΩ·οπι, 其与基板及半导体附着力小， 容易造成电极材料的接触不良， 而且 在较低温度下会与 Si发生反应， 扩散至有源层， 从而影响器件性能。 发明内容
本发明的实施例提供了一种可解决低电阻材料向有源层层扩散以及与基 板和半导体材料附着力差等技术问题的薄膜晶体管、阵列基板及其制作方法、 显示装置。
本发明的第一方面提供一种薄膜晶体管， 包括形成在基板上的栅极、 栅 绝缘层、 有源层、 电极金属层和钝化层； 电极金属层包括源电极和漏电极， 源电极和漏电极互相隔离， 在彼此之间界定了沟道区域； 所述有源层和电极 金属层之间形成有第二透明导电层。
在该薄膜晶体管中，例如，所述栅极和基板之间形成有第一透明导电层。 在该薄膜晶体管中， 例如， 所述栅极与电极金属层的材料为铜； 所述第 一透明导电层与栅极之间和 /或第二透明导电层与电极金属层之间分别形成 有一层金属层。 例如， 所述金属层的材料为钼、 铝、 钕、 钛或者其合金中的 一种。
在该薄膜晶体管中， 例如， 所述有源层为非晶硅或氧化物半导体材料。 在该薄膜晶体管中， 例如， 所述第一透明导电层和 /或第二透明导电层为 辞氧化物， 铟锡氧化物、 铟辞氧化物、 聚乙撑二氧噻吩或石墨烯材料。
本发明的第二方面还提供了一种薄膜晶体管的制作方法， 包括步骤： 在 基板上形成栅极； 在所述栅极上形成栅绝缘层和有源层； 在所述栅绝缘层和 有源层上形成第二透明导电层， 以及位于第二透明导电层上彼此隔开的源电 极和漏电极； 在所述源电极和漏电极、 以及第二透明导电层上形成钝化层。
该制作方法中， 例如， 在基板上形成栅极包括： 在基板上先形成第一透 明导电层， 作为栅极和基板之间的增强吸附层。
本发明的第三方面提供了一种阵列基板， 其包括上述任一项所述的薄膜 晶体管或上述任一项制作方法所制作的薄膜晶体管。
在该阵列基板中， 例如， 所述阵列基板上设置有像素电极和公共电极， 所述像素电极和所述公共电极设置在所述阵列基板的不同层， 所述像素电极 和所述公共电极之间设置有绝缘层， 所述像素电极的形状为狭缝状。
在该阵列基板中， 例如， 所述公共电极和第一透明导电层釆用相同的材 料， 且两者在同一次光刻工艺中形成； 所述像素电极和第二透明导电层釆用 相同的材料， 且两者在同一次光刻工艺中形成。
本发明的第四方面进一步提供了一种阵列基板的制作方法， 包括如下步 骤： 在基板上形成栅极图形、 栅线图形、 栅线 PAD 区域图形； 顺序形成栅 绝缘层和有源层； 顺序形成第二透明导电层、 彼此隔开的源电极和漏电极、 数据线以及数据线 PAD区域； 形成钝化层， 暴露出栅线 PAD区域以及数据 线 PAD区域。
在该阵列基板制作方法之中， 例如， 所述阵列基板为 ADS模式， 在基 板上形成栅极图形、 栅线图形、 栅线 PAD区域图形包括：
在基板上连续形成第一透明导电层和栅极金属层；
在所述栅极金属层上形成具有高度差的光刻胶图案；
对所述光刻胶图案进行多步曝光显影， 每次曝光显影之后分别对所述栅 极金属层进行刻蚀， 以形成栅极图形、 栅线图形、 栅线 PAD 区域图形和公 共电极图形。
在该阵列基板制作方法之中， 例如， 所述阵列基板为 TN模式， 在基板 上形成栅极图形、 栅线图形、 栅线 PAD区域图形的包括：
在基板上连续形成第一透明导电层和栅极金属层；
在栅极金属层上旋涂光刻胶， 使用掩膜版进行曝光显影， 使栅极图形、 栅线图形、 栅线 PAD区域图形所对应的光刻胶保留；
经过刻蚀形成栅极图形、 栅线图形、 栅线 PAD区域图形。
在该阵列基板制作方法之中， 例如， 当所述有源层为氧化物半导体材料 时， 顺序形成栅绝缘层和有源层还包括对保护层进行图形化， 其包括： 连续沉积栅绝缘层、 氧化物半导体层和保护层；
在保护层上旋涂光刻胶；
使用半色调或灰色调掩膜版进行曝光显影， 使保护层图形区域的光刻胶 完全保留， 使两个用于与源电极和漏电极联接的接触区的光刻胶部分保留； 经过多步刻蚀形成氧化物半导体层图形和保护层图形。
在该阵列基板制作方法之中， 例如， 当所述有源层为非晶硅材料时， 顺 序形成栅绝缘层和有源层包括：
连续沉积栅绝缘层、 有源层， 有源层包括本征层和 N型层；
在 N型层上旋涂光刻胶；
进行曝光显影， 使有源层图形区域的光刻胶保留；
刻蚀掉未保留光刻胶区域的本征层和 N型层。
在该阵列基板制作方法之中， 例如， 顺序形成第二透明导电层、 彼此隔 开的源电极和漏电极、 数据线以及数据线 PAD区域包括：
包括对第二透明导电层和电极金属层进行图形化：
连续沉积第二透明导电层和电极金属层；
在电极金属层上旋涂光刻胶；
使用半色调或灰色调掩膜版进行曝光显影， 使源电极、 漏电极和数据线 以及数据线 PAD 区域的光刻胶完全保留， 使像素电极区域的光刻胶部分保 留；
经过多步刻蚀形成源电极、 漏电极和数据线以及数据线 PAD区域图形。 在该阵列基板制作方法之中， 例如， 当所述有源层为非晶硅材料时， 还 包括： 刻蚀掉沟道区域的 N型层。
本发明的第五方面提供了一种显示装置， 其包括上述任一项所述的阵列 基板或者上述任一项制作方法所制作的阵列基板。
本发明实施例中的薄膜晶体管在基板和栅极金属层之间、 有源层和电极 金属层之间增加了透明导电层， 增强了栅极金属层与基板之间的附着力， 阻 止了电极金属层向有源层的扩散， 提高了产品性能； 本发明实施例的阵列基 板的制作方法简单， 使得阵列基板及基于该阵列基板的显示装置成本低， 性 价比高。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 la至图 If分别是本发明实施例一中在基板上形成透明导电层、 栅极 图形、 栅线图形、 栅线 PAD区域图形的过程示意图；
图 2a至图 2e分别是本发明实施例一中在图 If之后的基板上形成栅绝缘 层、 有源层和保护层的过程示意图；
图 3a至图 3e分别是本发明实施例一中在图 2e之后的基板上形成第二透 明导电层、 电极金属层、 钝化层和数据 PAD区域图形的过程示意图；
图 4是本发明实施例一中阵列基板截面图；
图 5是本发明实施例二中阵列基板截面图； 图 6是本发明实施例三中阵列基板截面图；
图 7a至图 7d分别是本发明实施例三中阵列基板的制作过程示意图； 图 8为本发明实施例五中的液晶显示装置的示意图。
附图标记
1 : 基板； 2: 第一透明导电层； 2a: 增强吸附层； 2b: 公共电极； 3: 栅 极 /栅极薄膜； 4: 栅绝缘层； 5: 有源层； 6: 保护层； 7: 第二透明导电层； 7a: 阻挡扩散层； 7b: 像素电极； 8: 电极金属层； 8a: 源电极； 8b: 漏电极； 9: 钝化层； 10: 本征层； 11 : N型层； 15: 光刻胶； 110: 栅线 PAD; 120: 数据线 PAD。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
除非另作定义， 此处使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。 本发明专利申请说明书以及权 利要求书中使用的 "第一" 、 "第二" 以及类似的词语并不表示任何顺序、 数量或者重要性，而只是用来区分不同的组成部分。同样， "一个 "或者 "一" 等类似词语也不表示数量限制， 而是表示存在至少一个。 "包括" 或者 "包 含" 等类似的词语意指出现在 "包括" 或者 "包含" 前面的元件或者物件涵 盖出现在 "包括" 或者 "包含" 后面列举的元件或者物件及其等同， 并不排 除其他元件或者物件。 "连接" 或者 "相连" 等类似的词语并非限定于物理 的或者机械的连接， 而是可以包括电性的连接， 不管是直接的还是间接的。 "上" 、 "下" 、 "左" 、 "右" 等仅用于表示相对位置关系， 当被描述对 象的绝对位置改变后， 则该相对位置关系也可能相应地改变。
本发明实施例的阵列基板可以包括多条栅线和多条数据线， 这些栅线和 数据线彼此交叉由此限定了排列为矩阵的多个像素单元。 每个像素单元例如 包括作为开关元件的薄膜晶体管和用于控制液晶的排列的像素电极。 例如， 每个像素的薄膜晶体管的栅极与相应的栅线电连接或一体形成， 源极与相应 的数据线电连接或一体形成， 漏极与相应的像素电极电连接或一体形成。 下 面的描述和附图主要针对单个或多个像素单元进行， 但是其他像素单元可以 相同地形成。
实施例一
本实施例是在 ADS模式 LCD中的应用， 所釆用的有源层为氧化物半导 体材料。 ADS模式为水平电场型的一个示例。
图 4是本实施例的阵列基板中的一个像素单元的包括薄膜晶体管的截面 图， 本实施例的薄膜晶体管中的栅极 3、 源电极 8a和漏电极 8b均为铜材质； 当然， 这些电极根据需要还可选用钼、 铝、 钕、 铜、 钛等金属单质， 或者每 种金属单质的合金等材料。 在源电极 8a和有源层 5之间、 漏电极 8b和有源 层 5之间有第二透明导电层 7。 第二透明导电层 7处于金属铜电极 8a、 8b和 有源层 5之间， 这可以阻止金属铜电极与有源层 5发生反应引起的电极金属 朝有源层 5的扩散。 栅线 PAD110和数据线 PAD120示范性示出了阵列基板 的***电路部分，用于与外部电路连接，例如输入栅极驱动信号和数据信号。
优选的， 在栅极 3和基板 1之间还可以设置有第一透明导电层 2; 第一 透明导电层 2可以增加基板 1和栅极 3金属铜之间的附着力， 提高产品的稳 定性。
图 4中所示的第一透明导电层 2从其功能又可以分为两部分， 分别为图 示中的栅极 3和基板 1之间的增强吸附层 2a, 以及栅绝缘层 4和基板 1之间 的公共电极 2b。第一透明导电层 2在形成过程中，可同时形成增强吸附层 2a 和公共电极 2b。 增强吸附层 2a增加基板 1和栅极 3金属铜之间的附着力， 提高产品的稳定性。 在形成增强吸附层 2a的同时还形成公共电极 2b, 简化 了单独形成公共电极的制作步骤。 既能够提高薄膜晶体管的质量， 又简化了 其制作工艺。
图 4中所示的第二透明导电层 7从其功能又分为两部分， 分别为图示中 的源电极 8a和有源层 5之间、 漏电极 8b与有源层 5之间的阻挡扩散层 7a, 以及像素区位于栅极绝缘层上的像素电极 7b。第二透明导电层 7在形成过程 中， 可同时形成阻挡扩散层 7a和像素电极 7b, 这既能够提高薄膜晶体管的 质量， 又简化了其制作工艺。 第一透明导电层 2和第二透明导电层 7可以分别或同时釆用辞氧化物， 铟锡氧化物、 铟辞氧化物、 铟辞锡氧化物、 聚乙撑二氧噻吩或石墨烯等透明 导电材料， 一个优选的示例为 ITO等。
制作包含上述薄膜晶体管的阵列基板的实施例， 包括以下步骤。
第一步骤
首先， 如图 la所示， 在基板 1上形成一层第一透明导电层 2, 然后在第 一透明导电层 2上形成金属铜栅极薄膜 3。 基板 1根据需要可选用不同材质 的基板， 如玻璃基板或石英基板。 栅极薄膜 3的方法例如可以为等离子增强 化学气相沉积（PECVD ) 、 磁控溅射、 热蒸发或其它成膜方法。 另外， 第一 透明导电层 2的形成可以釆用沉积方式、 旋涂方式或滚涂方式。
其次， 在栅极薄膜 3上旋涂一层光刻胶 15。 光刻胶 15的形成还可以釆 用旋：余方式或滚：余方式。
接下来， 在所述栅极层上形成具有高度差的光刻胶图案。 这例如可根据 光刻胶层的不同位置釆用不同的曝光量进行曝光， 随后进行显影， 从而在光 刻胶层的不同位置出去不同量的光刻胶,对此例如可以釆用双色调掩模板（例 如半色调或灰色调掩膜版）进行曝光显影。如图 lb所示， 曝光显影后光刻胶 15分为完全去除区域 I、 完全保留区域 II和部分保留区域 III。 光刻胶完全保 留区域 II对应于形成栅极、 栅线以及栅线 PAD 110区域图形， 光刻胶部分保 留区域 III对应于形成公共电极图形区域， 光刻胶完全去除区域 I对应于光刻 胶完全保留区域 II与光刻胶部分保留区域 III之外的区域。 栅线 PAD 区域和 数据线 PAD 区域是指阵列基板***电路部分， 用于与外部电路板连接， 输 入栅极驱动信号和数据信号。
然后， 进行多步刻蚀以得到需要的图形。 该多步刻蚀例如包括： 第一次 刻蚀→灰化→第二次刻蚀。
如图 lc所示， 第一次刻蚀掉光刻胶完全去除区域 I的第一透明导电层 2 与铜栅极薄膜 3; 接着如图 Id所示， 对图 lc所示的阵列基板上的光刻胶 15 进行灰化，部分保留区域 III的光刻胶 15被去除掉，而光刻胶完全保留区域也 被部分减薄； 然后对图 Id所示的阵列基板进行第二次刻蚀，刻蚀掉光刻胶部 分保留区域 III中的铜栅极薄膜 3 , 得到公共电极图形， 完成后阵列基板的截 面图如图 le所示。 如图 If所示， 在刻蚀完成后， 将光刻胶 15剥离去除。 去 除光刻胶 15可以釆用直接剥离， 或釆用 PGMEA或 EGMEA作为溶剂进行 离子液剥离。
由上可以理解的是， 如果在本步骤中不增加在栅极 3和基板 1的第一透 明导电层 2时，那么可以在图 lb中部分保留区域 III改为完全保留区域 II ,与 栅极同层制作公共电极。
如果在栅极 3和基板 1之间还形成有第一透明导电层 2, 则第一透明导 电层 2可以增加基板 1和栅极 3金属铜之间的附着力， 可以提高产品的稳定 性。 并且， 在第一透明导电层 2在形成过程中， 如果还同时形成增强吸附层 2a和公共电极 2b, 则既能够提高薄膜晶体管的质量， 又简化了其制作工艺。
第二步骤
在完成上述第一步骤的基板上依次进行下述工艺。
首先， 连续沉积栅绝缘层 4, 有源层 5 , 保护层 6;
其次， 在保护层 6上旋涂一层光刻胶 15;
接下来， 使用双色调掩模板（例如半色调或灰色调掩膜版）进行曝光显 影。
如图 2a所示， 类似地， 曝光显影后光刻胶 15分为完全去除区域 I、 部 分保留区域 II和完全保留区域 III。 这里， 光刻胶完全保留区域 III对应形成保 护层区域， 用于保护氧化物半导体， 以免在刻蚀过程中对氧化物半导体造成 破坏， 光刻胶部分保留区域 II用于形成与源电极和漏电极的接触区。 当然， 在不需要保护层 6时， 可以通过光刻胶的曝光显影工序后去掉。
然后， 进行多步刻蚀以得到需要的图形。 该多步刻蚀包括： 第一次刻蚀 →灰化→第二次刻蚀。
如图 2b所示，使用上述光刻胶层进行第一次刻蚀，刻蚀掉光刻胶完全去 除区域 I的有源层 5与保护层 6。 接着如图 2c所示， 对图 2b所示的阵列基 板上的光刻胶 15进行灰化， 部分保留区域 II的光刻胶 15被去除掉， 同时光 刻胶完全保留区域中的光刻胶也被部分减薄； 然后，对图 2c所示的阵列基板 进行第二次刻蚀， 刻蚀掉光刻胶部分保留区域 II的保护层 6, 以暴露出氧化 物半导体， 完成后阵列基板的截面图如图 2d所示。 如图 2e所示， 在刻蚀完 成后， 将光刻胶 15剥离去除， 去除方法可与上述第一步骤相同。
第三步骤 在完成上述第二步骤的基板上依次进行下述工艺。
首先， 在基板 1上连续形成第二透明导电层 7和电极金属层 8;
其次， 在电极金属层 8上旋涂一层光刻胶 15;
接下来， 使用双色调掩模板（例如半色调或灰色调掩膜版）进行曝光显 影。
如图 3a所示， 类似地， 曝光显影后光刻胶 15分为完全去除区域 I、 完 全保留区域 II和部分保留区域 III。 这里， 光刻胶完全保留区域 II对应形成保 护源电极 8a、 漏电极 8b、数据线以及数据线 PAD120图形区域， 光刻胶部分 保留区域 III对应于形成像素电极区域图形， 光刻胶完全去除区域 I对应于光 刻胶完全保留区域 II与部分保留区域 III以外的区域。
然后， 进行多步刻蚀以得到需要的图形。 该多步刻蚀的过程包括： 第一 次刻蚀→灰化→第二次刻蚀。
如图 3b所示，使用上述光刻胶层进行第一次刻蚀，刻蚀掉光刻胶完全去 除区域 I的第二透明导电层 7与电极金属层 8。 接着如图 3c所示， 对图 3b 所示的阵列基板上的光刻胶 15进行灰化， 部分保留区域 III的光刻胶 15被去 除掉， 同时将光刻胶完全保留区域中的光刻胶部分减薄； 然后对图 3c所示的 阵列基板进行第二次刻蚀， 刻蚀掉光刻胶部分保留区域 III的电极金属层 8, 以暴露出第二透明导电层 7,完成后阵列基板的截面图如图 3d所示。如图 3e 所示，在刻蚀完成后，将光刻胶 15剥离去除， 其方法例如与第一步骤中的相 同。
第四步骤
最后， 在完成上述第三步骤的阵列基板上沉积一层钝化层 9。 如图 4所 示， 通过曝光刻蚀暴露出栅线 PAD区域以及数据线 PAD区域。
剥离光刻胶 15后即完成本发明实施例的薄膜晶体管阵列基板的制作。 在本实施例的 ADS模式的阵列基板上， 所述像素电极和所述公共所述 像素电极与所述薄膜晶体管的源极或漏极电连接， 电极设置在所述阵列基板 的不同层， 所述像素电极和所述公共电极之间设置有绝缘层， 所述公共电极 大致覆盖整个像素区， 所述像素电极的形状为狭缝状。
由以上可以看出， 本实施例的薄膜晶体管阵列基板的制作过程可以釆用 四次构图工艺实现， 即相对于现有技术不增加构图工艺次数的基础上， 可以 完成薄膜晶体管阵列基板的制作。
实施例二
本发明另一实施例用于 TN模式 LCD中。 TN模式是垂直电场型的一个 示例。
图 5 是本实施例的阵列基板中一个像素单元的包括薄膜晶体管的截面 图， 其与实施例一中 ADS模式 LCD不同之处说明如下。 在 ADS模式 LCD 中由第二透明导电层 7形成的像素电极为狭缝状， 而在 TN模式 LCD中， 第 二透明导电层 7形成的像素电极为板状或片状。 那么， 在制作过程中第一次 构图工艺时不需要釆用半色调或灰色调掩膜版进行曝光显影的多步刻蚀工 艺。
本实施例的阵列基板与实施例一的阵列基板制作方法的区别说明如下。 该实施例的阵列基板的制作方法包括如下步骤。
首先， 在形成第一透明导电层 2和栅极金属层之后， 使用栅极图案的掩 膜版进行曝光显影，保留栅极、栅线以及栅线 PAD110区域图形的光刻胶 15; 其次，对基板 1上的上述叠层进行刻蚀，将栅极、栅线以及栅线 PAD110 区域图形以外区域的第一透明导电层和栅极金属层完全刻蚀掉。
接下来进行与实施例一种相同的步骤来形成栅绝缘层 4、有源层 6、保护 层 6、 第二透明导电层 7、 源电极 8a、 漏电极 8b和钝化层 9即可； 由第二透 明导电层 7形成像素电极时， 保证像素电极的块状结构即可。
可以看出， 上述两个实施例中， 薄膜晶体管中的有源层和电极金属层之 间增加了透明导电层， 其可以阻止了电极金属向有源层扩散， 由此提高了产 品性能。
当金属电极使用铜材料形成时， 铜材料对有源层的扩散性更强； 在一个 示例中， 为进一步阻止铜向有源层扩散以及增加铜的吸附力， 还可以在栅极 和第一透明导电层之间和 /或电极金属层和第二透明导电层之间增加一金属 层， 金属层的材料可以选择钼、 铝、 钕、 钛等单质或者每种单质所对应的合 金等材料。
实施例三
本发明的另一实施例中的有源层为非晶硅材料， 该实施例适用于 ADS 模式 LCD、 TN模式 LCD等。 图 6是本实施例薄膜晶体管截面图。 有源层包 括下部的本征层 10和上部的 N型层 11 , 本实施例中本征层 10为 a-Si, N型 层 11是在 a-Si中掺有 N型掺杂剂原子的 N+ a-Si。
本实施例薄膜晶体管的结构与实施例一中薄膜晶体管的结构类似， 其区 别在于本实施例中有源层具有双层结构， 并且没有实施例一中薄膜晶体管的 保护层结构。
在制作包含本实施例薄膜晶体管的阵列基板时， 在基板 1上形成栅极图 形、 栅线图形、 栅线 PAD 区域图形和第一透明导电层图案的步骤与实施例 一相同。在基板上形成栅极金属层和第一透明导电层结构后，执行以下步骤。
首先， 在基板 1上依次沉积栅绝缘层 4, a-Si材料本征层 10, N+ a-Si材 料 N型层 11;
其次， 在 N型层上旋涂光刻胶 15;
接下来， 对光刻胶 15进行曝光显影， 保留有源层图形区域的光刻胶 15, 完成后阵列基板截面图如图 7a所示。
然后， 刻蚀掉未保留光刻胶区域的本征层 10和 N型层 11。
完成上述步骤并去除光刻胶 15后阵列基板截面图如图 7b所示。
然后在经过上述步骤得到的阵列基板上进行实施例一中的步骤， 在阵列 基板上形成源电极、 漏电极、 数据线以及数据线 PAD 区域图形， 此时阵列 基板截面图如图 7c所示。
与实施例一不同之处在于， 本实施例薄膜晶体管有源层是双层结构， 并 且没有保护层， 所以本实施例阵列基板制作过程还包括以下步骤： 刻蚀掉沟 道区域的 N型层。 刻蚀掉沟道区域的 N型层后阵列基板的截面图如图 7d所 示。
完成以上步骤并去除光刻胶 15后， 在阵列基板上沉积一层钝化层 9, 通 过曝光刻蚀暴露出栅线 PAD区域以及数据线 PAD区域， 从而完成本实施例 薄膜晶体管阵列基板的制作。
本实施例的薄膜晶体管中的有源层和电极金属层之间增加了透明导电 层， 由此可以阻止了电极金属向有源层扩散， 提高了产品性能。 当金属电极 使用铜材料时， 铜材料对有源层的扩散性更强； 在一个示例中， 为进一步阻 止铜向有源层扩散以及增加铜的吸附力， 还可以在栅极和第一透明导电层之 间和 /或电极金属层和第二透明导电层之间增加一金属层，该金属层的材料可 以选择钼、 铝、 钕、 钛等单质或者每种单质所对应的合金等材料。 上述结构 的阵列基板中金属层图案与栅极层、 电极金属层图案相同， 其制作方法与以 上实施例基本相同， 在对栅极层、 电极金属层图形化时， 同时完成金属层的 图形化。
当然， 本实施例的薄膜晶体管阵列基板还可以由其他制作方法完成。 相 比现有技术， 本实施例在结构上增加了第一透明导电层 2和第二透明导电层 7 ,二者可以通过单独的构图工艺形成。虽然，这样做增加了构图工艺的次数， 而增加了制造成本,但依然可以完成本实施例的薄膜晶体管阵列基板的制作。
实施例四
本实施例提供一种薄膜晶体管的制作方法， 包括：
在基板上形成栅极；
在所述栅极上形成栅绝缘层和有源层；
在所述栅绝缘层和有源层上形成第二透明导电层， 以及位于第二透明导 电层上电极金属层；
在所述电极金属层以及第二透明导电层上形成钝化层。
例如， 在基板上形成栅极的步骤可以包括： 在基板上先形成一层第一透 明导电层， 作为栅极和基板之间的增强吸附层。 栅极和增强吸附层可以在同 一步骤中形成。 与此同时， 第一透明导电层在形成过程中， 还可同时形成增 强吸附层和阵列基板的公共电极， 这既能够提高薄膜晶体管的质量， 又简化 了制作阵列基板的制作工艺。
例如， 在基板上连续形成第一透明导电层和栅极金属层； 在所述栅极金 属层上形成光刻胶图案； 对所述光刻胶图案进行曝光显影， 每次曝光显影之 后分别对所述栅极金属层进行刻蚀， 以形成相应的图形。 需要说明的， 在第 一透明导电层在同时形成阵列基板的公共电极时， 需要在所述栅极金属层上 形成具有高度差的光刻胶图案， 并进行相应的光刻胶多步曝光显影。
例如， 在形成所述栅极上的栅绝缘层和有源层的步骤包括： 在形成在所 述栅极上连续形成栅绝缘层、 有源层， 在所述有源层上形成光刻胶图案； 对 所述光刻胶图案进行曝光显影， 每次曝光显影之后进行刻蚀， 以形成相应的 图形。
例如， 在有源层为氧化物半导体时， 在形成在所述栅极上连续沉积栅绝 缘层、 有源层、 保护层， 并在保护层上形成光刻胶。
例如， 所述栅极上连续沉积栅绝缘层、 氧化物半导体层和保护层； 在保 护层上旋涂光刻胶； 使用例如半色调或灰色调掩膜版进行曝光显影， 使保护 层图形区域的光刻胶完全保留， 使两个用于与源电极和漏电极联接的接触区 的光刻胶部分保留； 经过多步刻蚀形成氧化物半导体层图形和保护层图形。
例如， 有源层为非晶硅材料时， 该有源层包括本征层和 N型层。
例如， 连续沉积栅绝缘层、 本征层和 N型层； 在 N型层上旋涂光刻胶； 进行曝光显影， 使有源层图形区域的光刻胶保留； 刻蚀掉未保留光刻胶区域 的本征层和 N型层。
在所述栅绝缘层和有源层上形成第二透明导电层， 以及位于第二透明导 电层上的金属层的步骤中， 所述金属层包括彼此隔开的源电极和漏电极， 两 者之间为沟道区域。 该步骤包括： 在所述栅绝缘层和有源层上连续形成第二 透明导电层和电极金属层； 在电极金属层上形成光刻胶图案； 对光刻胶图案 进行曝光显影， 每次曝光显影之后进行刻蚀， 以形成相应的图形。
例如， 第二透明导体层还可以在该工艺步骤中形成阵列基板所需的像素 电极， 该像素电极可以根据需要制作成狭缝状或板状等。
例如， 在所述栅绝缘层和有源层上， 连续沉积第二透明导电层和电极金 属层； 在电极金属层上旋涂光刻胶； 使用半色调或灰色调掩膜版进行曝光显 影， 曝光显影之后进行刻蚀形成源电极、 漏电极。
例如，当所述有源层为非晶硅材料时，还包括刻蚀掉沟道区域的 N型层。 在上述实施例中， 光刻胶完全保留区域并非表示该区域中的光刻胶在显 影之后没有任何改变， 而是基本上得到保留， 厚度大于光刻胶部分保留区域 中的厚度。
实施例五
本发明的实施例还提供了一种显示装置， 其包括上述任一实施例的阵列 基板。
该显示装置的一个示例为例如 ADS模式或例如 TN模式的液晶显示装 置； 如图 8所示， 该液晶显示显示装置包括液晶面板 100。 在液晶面板 100 中，阵列基板 200与对置基板 300彼此对置以形成液晶盒，并通过封框胶 350 密封； 在液晶盒中填充有液晶材料 400。 该对置基板 300例如为彩膜基板。 例如， 对于 TN型， 在对置基板 300上形成公共电极， 用于与阵列基板上的 各个像素电极形成液晶电容； 对于 ADS型， 对置基板 300上则可以没有形 成公共电极。
阵列基板的每个像素单元的像素电极用于施加电场对液晶材料的旋转的 程度进行控制从而进行显示操作。
在一些示例中， 该液晶显示装置还包括为阵列基板提供背光的背光源。 以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、 一种薄膜晶体管， 包括形成在基板上的栅极、 栅绝缘层、 有源层、 电 极金属层和钝化层； 其中， 电极金属层包括源电极和漏电极， 源电极和漏电 极互相隔离， 在彼此之间界定了沟道区域； 其中， 所述有源层和电极金属层 之间形成有第二透明导电层。
2、如权利要求 1中所述的薄膜晶体管， 其中， 所述栅极和基板之间形成 有第一透明导电层。
3、如权利要求 2中所述的薄膜晶体管， 其中， 所述栅极与电极金属层的 材料为铜；所述第一透明导电层与栅极之间和 /或第二透明导电层与电极金属 层之间分别形成有一层金属层。
4、如权利要求 1中所述的薄膜晶体管， 其中， 所述有源层为非晶硅或氧 化物半导体材料。
5、 如权利要求 2中所述的薄膜晶体管， 其中， 所述第一透明导电层和 / 或第二透明导电层为辞氧化物， 铟锡氧化物、 铟辞氧化物、 聚乙撑二氧噻吩 或石墨烯材料。
6、 一种薄膜晶体管的制作方法， 如下步骤：
在基板上形成栅极；
在所述栅极上形成栅绝缘层和有源层；
在所述栅绝缘层和有源层上形成第二透明导电层， 以及位于第二透明导 电层上彼此隔开的源电极和漏电极；
在所述源电极和漏电极、 以及第二透明导电层上形成钝化层。
7、如权利要求 6中所述的薄膜晶体管的制作方法， 其中，在基板上形成 栅极包括： 在基板上先形成第一透明导电层， 作为栅极和基板之间的增强吸 附层。
8、 一种阵列基板， 包括如权利要求 1-5中任一项所述的薄膜晶体管。
9、如权利要求 8所述的阵列基板， 其中， 所述阵列基板上设置有像素电 极和公共电极， 所述像素电极与所述薄膜晶体管的源极或漏极电连接， 所述 像素电极和所述公共电极设置在所述阵列基板的不同层， 所述像素电极和所 述公共电极之间设置有绝缘层， 所述像素电极的形状为狭缝状。
10、 一种阵列基板的制作方法， 包括如下步骤：
在基板上形成栅极图形、 栅线图形、 栅线 PAD区域图形；
顺序形成栅绝缘层和有源层；
顺序形成第二透明导电层、 彼此隔开的源电极和漏电极、 数据线以及数 据线 PAD区域；
形成钝化层， 暴露出栅线 PAD区域以及数据线 PAD区域。
11、如权利要求 10所述的阵列基板的制作方法， 其中， 所述阵列基板为 ADS模式， 在基板上形成栅极图形、 栅线图形、 栅线 PAD区域图形包括： 在基板上连续形成第一透明导电层和栅极金属层；
在所述栅极金属层上形成具有高度差的光刻胶图案；
对所述光刻胶图案进行多步曝光显影， 每次曝光显影之后分别对所述栅 极金属层进行刻蚀， 以形成栅极图形、 栅线图形、 栅线 PAD 区域图形和公 共电极图形。
12、如权利要求 10所述的阵列基板的制作方法， 其中， 当所述有源层为 氧化物半导体材料时， 顺序形成栅绝缘层和有源层还包括对保护层进行图形 化， 包括：
连续沉积栅绝缘层、 氧化物半导体层和保护层；
在保护层上旋涂光刻胶；
使用半色调或灰色调掩膜版进行曝光显影， 使保护层图形区域的光刻胶 完全保留， 使两个用于与源电极和漏电极联接的接触区的光刻胶部分保留； 经过多步刻蚀形成氧化物半导体层图形和保护层图形。
13、如权利要求 10所述的阵列基板的制作方法， 其中， 当所述有源层为 非晶硅材料时， 顺序形成栅绝缘层和有源层包括：
连续沉积栅绝缘层、 有源层， 有源层包括本征层和 N型层；
在 N型层上旋涂光刻胶；
进行曝光显影， 使有源层图形区域的光刻胶保留；
刻蚀掉未保留光刻胶区域的本征层和 N型层。
14、如权利要求 10所述的阵列基板的制作方法， 其中， 顺序形成第二透 明导电层、 彼此隔开的源电极和漏电极、 数据线以及数据线 PAD区域包括： 包括对第二透明导电层和电极金属层进行图形化： 连续沉积第二透明导电层和电极金属层；
在电极金属层上旋涂光刻胶；
使用半色调或灰色调掩膜版进行曝光显影， 使源电极、 漏电极和数据线 以及数据线 PAD 区域的光刻胶完全保留， 使像素电极区域的光刻胶部分保 留；
经过多步刻蚀形成源电极、 漏电极和数据线以及数据线 PAD区域图形。
15、如权利要求 14所述的阵列基板的制作方法， 其中， 当所述有源层为 非晶硅材料时， 还包括： 刻蚀掉沟道区域的 N型层。
16、 一种显示装置， 包括上述权利要求 8-9中任一项所述的阵列基板。
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CN102769040A (zh) 2012-11-07
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