WO2015096312A1 - 阵列基板及其制作方法和显示装置 - Google Patents

阵列基板及其制作方法和显示装置 Download PDF

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Publication number
WO2015096312A1
WO2015096312A1 PCT/CN2014/075809 CN2014075809W WO2015096312A1 WO 2015096312 A1 WO2015096312 A1 WO 2015096312A1 CN 2014075809 W CN2014075809 W CN 2014075809W WO 2015096312 A1 WO2015096312 A1 WO 2015096312A1
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Prior art keywords
array substrate
gate
electrode
photoresist
line
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PCT/CN2014/075809
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English (en)
French (fr)
Inventor
刘圣烈
崔承镇
金熙哲
宋泳锡
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京东方科技集团股份有限公司
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Priority to US14/421,947 priority Critical patent/US10134786B2/en
Publication of WO2015096312A1 publication Critical patent/WO2015096312A1/zh
Priority to US16/160,223 priority patent/US10998353B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]

Definitions

  • the present invention relates to the field of display, and in particular, to an array substrate, a manufacturing method thereof, and a display device. Background technique
  • the existing method for fabricating an array substrate for a multi-dimensional electric field display panel can be completed by 6-7 patterning processes.
  • Each patterning process includes the formation of an etched material, photoresist coating, exposure and development, etching, and photoresist removal.
  • a common method of fabricating an array substrate includes:
  • a pattern including a pixel electrode is formed by a sixth patterning process.
  • An object of the present invention is to provide a method for fabricating an array substrate having a simple fabrication process, high production efficiency, low cost, and economical efficiency, an array substrate produced by the method, and a display device including the array substrate.
  • a method for fabricating an array substrate comprising: forming a pattern including an active layer, a source, a drain, a data line, and a pixel electrode on a substrate by a patterning process;
  • a pattern including a gate and a gate line is formed by one patterning process.
  • the step of forming a pattern of an active layer, a source, a drain, a data line, and a pixel electrode on a base substrate by one patterning process includes:
  • Coating a photoresist on the semiconductor film exposing and developing the photoresist through a two-tone mask, completely retaining the photoresist corresponding to the active layer region, partially retaining the source, the drain, and the data a photoresist corresponding to the line and the pixel electrode region, completely removing the photoresist in the remaining region to expose the semiconductor film;
  • the photoresist is subjected to ashing treatment to thin the photoresist corresponding to the active layer region and expose the semiconductor film in a region other than the active layer region;
  • the remaining photoresist is removed.
  • the step of forming the pattern of the gate and the gate lines by one patterning process further includes forming a pattern of the common electrode lines and the comb-shaped common electrodes.
  • the steps of forming the pattern of the gate and the gate lines by one patterning process, and the pattern of the common electrode lines and the comb-shaped common electrodes include:
  • Coating a photoresist on the metal film exposing and developing the photoresist through a two-tone mask, completely retaining the photoresist corresponding to the gate, the gate line and the common electrode line region, and partially retaining the comb a photoresist corresponding to the common electrode region, removing the photoresist in the remaining region to expose the metal film;
  • the photoresist is ashed to thin the photoresist corresponding to the gate, the gate line and the common electrode line region, and expose a metal film in a region other than the gate, the gate line and the common electrode line region; An exposed metal film;
  • the remaining photoresist is removed to form a pattern of gate, gate lines, common electrode lines, and comb common electrodes.
  • the pixel electrode is comb-shaped.
  • the material of the semiconductor film is selected from the group consisting of indium gallium oxide and indium gallium tin oxide. At least one of an indium tin oxide.
  • an array substrate including a plurality of gate lines formed on a base substrate, a plurality of data lines, and a plurality of pixel units defined by a plurality of gate lines and a plurality of data lines
  • Each of the pixel units includes a thin film transistor and a pixel electrode connected to the thin film transistor, and the pixel electrode, the data line, the active layer, the source and the drain of the thin film transistor are disposed in the same layer.
  • the array substrate further includes an insulating layer disposed on the pixel electrode, the data line, the active layer, the source, and the drain; and a gate disposed above the insulating layer.
  • the array substrate further includes a common electrode line disposed over the insulating layer and a comb-shaped common electrode connected to the common electrode line.
  • the gate, the gate line, and the common electrode line are disposed above the common electrode.
  • the pixel electrode is comb-shaped.
  • the material of the active layer, the source, and the drain of the pixel electrode, the data line, and the thin film transistor is at least one selected from the group consisting of indium gallium oxide, indium gallium tin oxide, and indium tin oxide. .
  • a display device comprising the above array substrate.
  • FIG. 1 is a flow chart of a method of fabricating an array substrate according to an embodiment of the invention
  • FIG. 2 is a flow chart of forming a pattern including an active layer, a source, a drain, a data line, and a pixel electrode, in accordance with an embodiment of the present invention
  • FIG. 3 is a flow chart of forming a pattern including a gate, a gate line, a common electrode, and a common electrode line, in accordance with an embodiment of the present invention
  • 4a to 16a are schematic cross-sectional views showing an array substrate of a method for fabricating an array substrate according to an embodiment of the invention
  • FIGS. 4a to 16a are schematic plan views of an array substrate according to an embodiment of the present invention, wherein FIGS. 4a to 16a are cross-sectional views taken along line A-A of FIG. 4b to FIG. 16b;
  • FIG. 17 is a schematic cross-sectional structural view of an array substrate according to an embodiment of the present invention. detailed description
  • An embodiment of the present invention provides a method for fabricating an array substrate, as shown in FIG. 1, which may include:
  • Step S1 forming a pattern of an active layer, a source, a drain, a data line, and a pixel electrode on the base substrate by one patterning process;
  • Step S2 forming a pattern of the insulating layer
  • Step S3 forming a pattern of the gate and the gate line by one patterning process.
  • step S2 on the pattern formed in step S1, a pattern of an insulating layer is formed by depositing the insulating layer, wherein the deposition may be performed by any of the existing deposition methods, and in this embodiment, a vapor deposition method is preferred.
  • the array substrate may be a top gate thin film transistor, so that a pattern of gate lines and gate lines is formed in the last step S3.
  • Step S3 may include, for example, forming a gate and a gate line using a mask by one patterning process.
  • the patterning process includes depositing an etched material, coating, exposing, developing, etching, and stripping of the photoresist.
  • the step S1 may include:
  • a semiconductor thin film 2 is formed on the base substrate 1.
  • the semiconductor thin film 2 may be formed by various methods such as deposition by chemical vapor deposition (CVD), sputtering, or the like, which is not limited herein.
  • S102 as shown in FIG. 5a and FIG. 5b, coating a photoresist on the semiconductor film 2, exposing and developing the photoresist through a two-tone mask, so as to correspond to an active layer region after development.
  • the photoresist 31 is completely retained, corresponding to the source, drain, data lines, and photoresist regions of the pixel electrode regions.
  • the portions 33, 32, 35, and 34 are retained and have a thickness smaller than the thickness of the photoresist 31, and the photoresist corresponding to the remaining region is completely removed to expose the semiconductor thin film 2.
  • the two-tone mask can be a halftone mask or a gray mask.
  • S103 The exposed semiconductor film 2 is etched as shown in Figs. 6a and 6b.
  • the exposed semiconductor film 2 is changed into a conductor by plasma treatment, thereby forming patterns of the source electrode 42, the drain electrode 43, the data line 46, and the pixel electrode 45.
  • the plasma treatment the material of the exposed semiconductor thin film 2 is changed, and the semiconductor becomes a conductor. Due to the protection of the photoresist, the material of the semiconductor film corresponding to the active layer region does not change during the plasma treatment, and the semiconductor layer can still be used as the active layer of the thin film transistor.
  • the source electrode 42, the drain electrode 43, the data line 46, and the pixel electrode 45 are formed, thereby forming the active layer 41, the source electrode 42, the drain electrode 43,
  • the data line 46 and the pixel electrode 45 require only one patterning process.
  • These components need to be completed by 3-5 patterning processes in the existing fabrication process, and each patterning process includes at least the formation of the etched material, the coating of the photoresist, the exposure and development, the etching, and the etching. Photoresist removal. Therefore, in contrast, the method for fabricating the array substrate of the present embodiment greatly reduces the complexity and cost of the manufacturing process and improves the production efficiency.
  • the pixel electrode 45 may be a comb-shaped pixel electrode (or a strip-shaped, slit-like pixel electrode) as described in Figs. 8a and 8b, or may be a flat-shaped pixel electrode.
  • the step S2 may include: a base substrate on which the active layer 41, the source electrode 42, the drain electrode 43, the data line 46, and the pixel electrode 45 are formed
  • the insulating layer 5 is formed (by deposition, spin coating or printing, etc.).
  • the insulating layer 5 may be composed of, for example, at least one of silicon nitride, silicon oxide, or silicon oxynitride.
  • the pixel electrode 45 is preferably formed as a flat pixel electrode. Since the common electrode is located on the opposite substrate (for example, the color filter substrate) disposed opposite to the array substrate, it is not necessary to form the common electrode and the common electrode line in step S3, and only the gate electrode and the gate line are formed.
  • step S3 may include: depositing a gate metal film on the base substrate 1 on which the insulating layer 5 is formed, and then forming a pattern of the gate and the gate lines by a patterning process, the gate and the gate lines are integrally formed, and the gate It is formed above the corresponding active layer 41.
  • the step S3 may include: forming a pattern of the gate and the gate line by one patterning process, and a pattern of the comb-shaped common electrode and the common electrode line. As shown in FIG. 3, the step S3 may include, for example:
  • a transparent conductive film 6 is formed (by deposition, spin coating, printing, etc.) on the insulating layer 5, and is shown on the transparent conductive film 6 as shown in FIGS. 11a to 11B. Forming (by deposition, spin coating or printing, etc.) a metal film 7;
  • a photoresist is coated on the metal thin film 7, and the photoresist is exposed and developed through a two-tone mask to make a gate, a gate line and a common electrode line.
  • the photoresists 81 and 82 corresponding to the regions are completely retained, so that the photoresist 83 corresponding to the comb-shaped common electrode region is partially retained, and the thickness of the photoresist 83 is smaller than the thickness of the photoresists 81 and 82, and the light in the remaining region is removed.
  • the glue is peeled to expose the metal film 7.
  • the gate electrode 101 is composed of a gate metal portion in which the gate line 104 overlaps the active layer 41 and a transparent conductive film 6 therebelow.
  • the metal thin film 7 a single-layer film formed of a metal such as Cr, W, Ti, Ta, Mo, Al, Cu or the like and an alloy thereof, or a composite film composed of a plurality of metal thin films can be used.
  • Transparent conductive film 6 ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide) can be used.
  • the gate electrode 101, the gate line 104, and the common electrode line 103 can be considered to be only composed of a metal thin film, and the gate electrode 101, the gate line 104, and the common electrode line 103 are located at the comb-shaped common electrode 102.
  • the gate electrode 101, the gate line 104, and the common electrode line 103 are each composed of two parts, and a metal thin film and a transparent conductive film are sequentially arranged from top to bottom. In this case, since both the metal thin film and the transparent conductive film are conductors, not only the conductivity of the gate electrode 101, the gate line 104, and the common electrode line 103 is maintained, but also the light-shielding property of the metal film is maintained.
  • the gate electrode 101, the gate line 104, the common electrode 102, and the common electrode line 103 are formed by one patterning process, which greatly reduces the complexity and cost of the fabrication process, and improves the production efficiency.
  • the material of the semiconductor thin film 2 may be at least one of indium gallium oxide, indium gallium tin oxide, and indium tin oxide.
  • Indium gallium oxide (IGZO) is preferred because of its high carrier mobility, so that the thin film transistor formed using the material has a fast reaction rate, thereby increasing the reaction rate of the array substrate.
  • the fabrication of the array substrate is completed by only two patterning processes, which is simple and quick to manufacture, high in production efficiency, reduces the number of masks, and reduces light. Loss of consumables such as glue and developer, which reduces manufacturing costs and improves production efficiency and economic efficiency.
  • the array substrate may include: a plurality of gate lines formed on the base substrate 1, a plurality of data lines (not shown), and a plurality of gate lines and a plurality of data lines intersecting each other.
  • a pixel unit (not shown); wherein each pixel unit includes a thin film transistor (not shown) and a pixel electrode 25 connected to the thin film transistor, the pixel electrode 25, the data line, and the thin film transistor are active Layer 21, source 22 and drain 23 are on the same layer.
  • the active layer is usually located above the source 22 and the drain 23.
  • the pixel electrode 25 is on the surface of the base substrate 1. Since the array substrate described in this embodiment has the active layer 21, the source 22, the drain 23, the data line, and the pixel electrode 25 disposed on the same layer, the fabrication process can be completed only by one patterning process, so the fabrication process is simple and fast. And reduce the number of masks, reduce the loss of photoresist, developer and other consumables, thereby reducing manufacturing costs and improving Production efficiency and economic benefits.
  • the array substrate may further include an insulating layer 29 on the pixel electrode 25, the active layer 21, the source 22, the drain 23, and the data line; and a gate above the insulating layer 29. Extreme 27.
  • the gate 27 and the gate line are integrally formed, and the gate line transmits a signal for turning on or off the thin film transistor.
  • the thin film transistor is of a top gate type. If the array substrate of the present embodiment is used to fabricate a TN-type liquid crystal display panel, the common electrode disposed opposite to the pixel electrode 25 is disposed on a counter substrate (such as a color filter substrate) disposed opposite to the array substrate, so that the array is It is not necessary to make a common electrode and a common electrode line in the substrate, but only a gate electrode and a gate line need to be formed, and can be fabricated by a common patterning process.
  • a counter substrate such as a color filter substrate
  • the array substrate described in this embodiment is used to fabricate a multi-dimensional electric field type (for example, ADS type or IPS type) liquid crystal display panel
  • a common electrode and a common electrode line for supplying a voltage to the common electrode are also required to be formed on the array substrate.
  • the common electrode is a comb-shaped common electrode.
  • the array substrate of the embodiment may further include a common electrode line 28 disposed above the insulating layer 29 and a comb-shaped common electrode 26 connected to the common electrode line 28. Further, the gate 27, the gate line and the common electrode line 28 are located above the common electrode 26.
  • the formation of the common electrode 26, the common electrode line 28, the gate 27 and the gate line is completed by only one patterning process, which is easy to manufacture, low in cost of consumables and equipment, and economical. Good benefits and other advantages.
  • the pixel electrode 25 in the present embodiment is a comb-shaped pixel electrode 25.
  • the pixel electrode 25 may also be a plate electrode located within the pixel area.
  • the material of the pixel electrode 25, the data line, and the active layer 21, the source 22, and the drain 23 of the thin film transistor may be selected from at least one of indium gallium oxide, indium gallium tin oxide, and indium tin oxide. . Preferably, they are all made of IGZO.
  • the active layer 21 is a semiconductor layer, and the IGZO itself is a semiconductor, and the source 21, the drain 22, the data line, and the pixel electrode 25 are all conductors. Therefore, in the manufacturing process, the IGZO is converted into a conductor by using a laser process. Ensure the quality of the array substrate.
  • the array substrate described in this embodiment has the advantages of simple structure, low manufacturing cost, and good economic efficiency.
  • the top gate thin film transistor is taken as an example. Ming, but not limited to this.
  • the array substrate of the bottom gate thin film transistor it is only necessary to exchange the active layer 21, the source 22, the drain 23, the pixel electrode 25 and the data line in the same layer in FIG. 17 with the layer above the insulating layer 29, That is, the active layer 21, the source 22, the drain 23, the pixel electrode 25, and the data line are located above the insulating layer 29, and the gate 27, the gate line, the common electrode 26, and the common electrode line 28 are located under the insulating layer 29.
  • the manufacturing method it is only necessary to adjust the order of the above steps S1 and S3, and the steps S3-S2-S1 can be made, and the manufacturing process of each step is unchanged.
  • Another embodiment of the present invention further provides a display device comprising the array substrate fabricated by the method for fabricating the array substrate of the embodiment of the invention, or the array substrate according to the embodiment of the invention.
  • the display device may be any product or component having a display function such as an electronic paper, a liquid crystal display panel, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the fabrication of the array substrate is completed only by two patterning processes with respect to the conventional fabrication process, so that the fabrication steps are few and simple, and the fabrication is greatly reduced.
  • the complexity and cost which greatly improve production efficiency and economic efficiency.

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Abstract

提供一种阵列基板及其制作方法和显示装置。阵列基板的制作方法包括：通过一次构图工艺在衬底基板（1）上形成有源层（21）、源极（22）、漏极（23）、数据线以及像素电极（25）的图形；形成绝缘层（29）的图形；通过一次构图工艺形成栅极（27）及栅线的图形。在本发明阵列基板制作方法、阵列基板及显示装置中，仅需两次构图工艺即完成阵列基板的制作，因此制作步骤少且简便，大大的降低了制作的复杂度和成本，从而极大的提升了生产效率和经济效益。

Description

阵列基板及其制作方法和显示装置 技术领域
本发明涉及显示领域，尤其涉及一种阵列基板及其制作方法和显示装置。 背景技术
现有的用于多维电场显示面板的阵列基板的制作方法经过 6-7次构图工 艺才能完成。 而每一次构图工艺均包括被刻蚀材料的形成， 光刻胶的涂布、 曝光以及显影， 刻蚀， 光刻胶的去除。 例如， 常见的阵列基板的制作方法包 括：
通过第一次构图工艺形成包括公共电极、 公共电极线、 栅极以及栅线的 图形；
通过第二次构图工艺形成有源层；
通过第三次构图工艺形成过孔；
通过第四次构图工艺形成包括源极和漏极的图形；
通过第五次构图工艺形成绝缘层；
通过第六次构图工艺形成包括像素电极的图形。
由此可见， 阵列基板的现有制作方法具有制作工艺复杂、 生产效率低、 成本高且经济效益低的缺点。 发明内容
本发明目的在于提供一种制作工艺简单、 生产效率高、 成本低且经济效 益好的阵列基板制作方法、 由该方法制作的阵列基板及包括该阵列基板的显 示装置。
根据本发明的第一方面， 提供了一种阵列基板制作方法， 包括： 通过一次构图工艺在衬底基板上形成包括有源层、 源极、 漏极、 数据线 以及像素电极的图形；
形成包括绝缘层的图形； 以及
通过一次构图工艺形成包括栅极及栅线的图形。 在一个示例中，所述通过一次构图工艺在衬底基板上形成有源层、源极、 漏极、 数据线以及像素电极的图形的步骤包括：
在衬底基板上形成半导体薄膜；
在所述半导体薄膜上涂布光刻胶， 通过双色调掩膜板对所述光刻胶进行 曝光、 显影， 完全保留有源层区域对应的光刻胶， 部分保留源极、 漏极、 数 据线以及像素电极区域对应的光刻胶， 完全去除剩余区域中的光刻胶以暴露 出半导体薄膜；
刻蚀暴露出的半导体薄膜；
对光刻胶进行灰化处理， 以减薄有源层区域对应的光刻胶并且暴露出除 有源层区域之外的区域的半导体薄膜；
通过等离子处理使暴露出的半导体薄膜变成导体， 以形成源极、 漏极、 数据线以及像素电极的图形； 以及
去除剩余的光刻胶。
在一个示例中， 所述通过一次构图工艺形成栅极及栅线的图形的步骤还 包括形成公共电极线及梳状公共电极的图形。
在一个示例中， 所述通过一次构图工艺形成栅极及栅线的图形， 以及公 共电极线及梳状公共电极的图形的步骤， 包括：
在绝缘层之上依次形成透明导电薄膜和金属薄膜；
在所述金属薄膜上涂布光刻胶， 通过双色调掩膜板对所述光刻胶进行曝 光、 显影， 完全保留栅极、 栅线以及公共电极线区域对应的光刻胶， 部分保 留梳状公共电极区域对应的光刻胶， 去除剩余区域中的光刻胶以暴露出金属 薄膜；
刻蚀暴露的金属薄膜及下方的透明导电薄膜；
对光刻胶进行灰化处理， 以减薄栅极、 栅线以及公共电极线区域对应的 光刻胶， 暴露出除栅极、 栅线及公共电极线区域之外的区域的金属薄膜； 刻蚀暴露的金属薄膜；
去除剩余的光刻胶， 形成栅极、 栅线、 公共电极线以及梳状公共电极的 图形。
在一个示例中， 所述像素电极为梳状。
在一个示例中， 所述半导体薄膜的材质选自铟镓辞氧化物、 铟镓锡氧化 物、 铟锡氧化物中的至少一种。
根据本发明的第二方面， 提供了一种阵列基板， 包括形成在衬底基板上 的多条栅线、 多条数据线及由多条栅线和多条数据线交叉限定的多个像素单 元;其中每个像素单元包括薄膜晶体管及与所述薄膜晶体管连接的像素电极， 所述像素电极、数据线、 薄膜晶体管的有源层、 源极以及漏极设置在同一层。
在一个示例中， 所述阵列基板还包括设置在所述像素电极、 数据线、 有 源层、 源极以及漏极上的绝缘层； 以及设置在所述绝缘层上方的栅极。
在一个示例中， 所述阵列基板还包括设置在所述绝缘层上方的公共电极 线以及与所述公共电极线连接的梳状公共电极。
在一个示例中， 所述栅极、 栅线及公共电极线设置在公共电极上方。 在一个示例中， 所述像素电极为梳状。
在一个示例中， 所述像素电极、 数据线和薄膜晶体管的有源层、 源极以 及漏极的材质选自铟镓辞氧化物、铟镓锡氧化物、铟锡氧化物中的至少一种。
根据本发明的第三方面， 提供了一种显示装置， 包括上述的阵列基板。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为根据本发明实施例的阵列基板制作方法的流程图；
图 2为根据本发明实施例的形成包括有源层、 源极、 漏极、 数据线以及 像素电极的图形的流程图；
图 3为根据本发明实施例的形成包括有栅极、 栅线、 公共电极以及公共 电极线的图形的流程图；
图 4a〜图 16a为根据本发明实施例的阵列基板制作方法的阵列基板剖面 示意图；
图 4b〜图 16b为根据本发明实施例的阵列基板制作方法的阵列基板平面 示意图， 其中图 4a〜图 16a为对应的图 4b〜图 16b沿 A-A剖面图；
图 17为本发明实施例的阵列基板的剖面结构示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图， 对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
本发明的一个实施例提供了一种阵列基板的制作方法， 如图 1所示， 可 包括：
步骤 S1 : 通过一次构图工艺在衬底基板上形成有源层、 源极、 漏极、 数 据线以及像素电极的图形；
步骤 S2: 形成绝缘层的图形；
步骤 S3： 通过一次构图工艺形成栅极及栅线的图形。
步骤 S2中， 在步骤 S1所形成的图形上， 通过沉积所述绝缘层形成绝缘 层的图形， 其中所述沉积可以选用现有的任意一种沉积法， 在本实施例中优 选气相沉积法。
在本实施例中， 所述的阵列基板可以是顶栅薄膜晶体管， 故在最后的步 骤 S3中形成栅极以及栅线的图形。 步骤 S3例如可包括： 通过一次构图工艺 使用掩模板形成栅极以及栅线。 所述构图工艺包括沉积被刻蚀材料， 光刻胶 的涂布、 曝光、 显影， 刻蚀， 光刻胶的剥离。
在本实施例所述的阵列基板制作方法中， 仅在步骤 S1以及步骤 S3中各 釆用了一次构图工艺， 相对于现有技术中用到的 6-7次次构图工艺， 步骤少 且简单快捷， 从而大大的提升了生产效率， 降低了生产成本， 提高了经济效 益。
在一个示例中， 如图 2所示， 所述步骤 S1可包括：
S101 : 如图 4a、 图 4b所示， 在衬底基板 1上形成半导体薄膜 2。 例如， 半导体薄膜 2可以釆用诸如化学气相沉积（CVD )的沉积、 溅射等多种方式 形成， 在此不做限定。
S102: 如图 5a、 图 5b所示， 在所述半导体薄膜 2上涂布光刻胶， 通过 双色调掩膜板对所述光刻胶进行曝光、 显影， 使得显影后对应有源层区域的 光刻胶 31 完全保留， 对应源极、 漏极、 数据线以及像素电极区域的光刻胶 33、 32、 35、 34部分保留并且厚度小于光刻胶 31的厚度， 完全去除剩余区 域对应的光刻胶以暴露出半导体薄膜 2。双色调掩膜板可以是半色调掩膜板， 也可是灰色调掩膜板。
S103: 如图 6a、 图 6b所示， 刻蚀暴露出的半导体薄膜 2。
S104: 如图 7a、 图 7b所示， 对光刻胶进行灰化处理以去掉部分保留的 光刻胶 32、 33、 34、 35， 并且减薄有源层区域对应的光刻胶 31， 从而暴露出 除有源层区域之外的区域的半导体薄膜 2。
S105: 如图 8a和图 8b所示， 通过等离子（Plasma )处理使暴露出的半 导体薄膜 2变成导体， 从而形成源极 42、 漏极 43、 数据线 46以及像素电极 45的图形。通过等离子处理，使得暴露出的半导体薄膜 2的材质发生了改变， 由半导体变成导体。 而由于有光刻胶的防护， 在进行 Plasma处理时， 有源层 区域对应的半导体薄膜的材质不发生改变， 依旧为半导体故可用作薄膜晶体 管的有源层。
S106: 去除剩余的光刻胶 31， 从而暴露出有源层 41， 在此情况下， 在 衬底基板 1上形成了薄膜晶体管的有源层 41、 源极 42、 漏极 43、 数据线 46 以及像素电极 45， 且它们均位于同一层中。
在本实施例中， 由于通过等离子处理使半导体薄膜 2变成导体， 形成源 极 42、 漏极 43、 数据线 46以及像素电极 45， 因此形成有源层 41、 源极 42、 漏极 43、数据线 46以及像素电极 45只需要一次构图工艺。 而这些部件在现 有的制作工艺中需要釆用 3-5次构图工艺才能完成， 并且每一次构图工艺至 少包括被刻蚀材料的形成、 光刻胶的涂布、 曝光以及显影， 刻蚀以及光刻胶 的去除。 因此， 相比之下， 本实施例的阵列基板的制作方法， 大大减少了制 作工艺的复杂性及成本， 提高了生产效率。
像素电极 45可以是如图 8a和 8b中所述的梳状像素电极（或称条状、狭 缝状像素电极）， 或者还可以是平板状像素电极。
在一个示例中， 如图 9a以及图 9b所示， 所述步骤 S2可包括： 在形成有 所述有源层 41、 源极 42、 漏极 43、数据线 46以及像素电极 45的衬底基板 1 上形成（通过沉积、 旋涂或印刷等）绝缘层 5。 所述绝缘层 5例如可由氮化 硅、 氧化硅或氮氧化硅中的至少一种构成。
若本发明所有实施例中的阵列基板用于制作 TN ( Twisted Nematic, 扭 曲向列）型液晶显示面板， 则像素电极 45优选形成为平板状像素电极。 由于 公共电极位于与阵列基板相对设置的对置基板（如彩膜基板）上， 因此在步 骤 S3 中无需制作公共电极以及公共电极线， 而仅形成栅极以及栅线即可。 在一个示例中， 步骤 S3可包括： 在形成有绝缘层 5的衬底基板 1上沉积栅 金属薄膜，然后通过构图工艺形成栅极和栅线的图形，栅极和栅线一体形成， 栅极形成在对应有源层 41的上方。
当本实施例所述制作方法用于制作多维电场型 （例如 ADS 型或者 IPS 型等） 阵列基板时， 则还需在基板上形成梳状公共电极以及连接梳状公共电 极的公共电极线。 在一个示例中， 步骤 S3 可包括： 通过一次构图工艺形成 栅极及栅线的图形， 以及梳状公共电极及公共电极线的图形。 如图 3所示， 该步骤 S3例如可包括：
S301: 如图 10a〜图 10b所示， 在绝缘层 5上形成（通过沉积、 旋涂或印 刷等）透明导电薄膜 6， 并且如图 11a〜图 lib所示， 在所述透明导电薄膜 6 上形成（通过沉积、 旋涂或印刷等）金属薄膜 7;
S302: 如图 12a〜图 12b所示， 在所述金属薄膜 7上涂覆光刻胶， 通过双 色调掩膜板对所述光刻胶曝光、 显影， 使栅极、 栅线及公共电极线区域对应 的光刻胶 81、 82完全保留，使梳状公共电极区域对应的光刻胶 83部分保留， 并且光刻胶 83的厚度小于光刻胶 81和 82的厚度，去除剩余区域内的光刻胶， 以暴露出金属薄膜 7。
S303:如图 13a〜图 13b所示，刻蚀暴露的金属薄膜 7及透明导电薄膜 6。
S304: 如图 14a〜图 14b所示， 釆用灰化工艺去除梳状公共电极区域对应 的光刻胶 83并且减薄栅极、栅线以及公共电极线区域对应的光刻胶 81和 82， 从而暴露出除栅极、 栅线及公共电极线区域之外的区域的金属薄膜 7;
S305: 如图 15a〜图 15b所示， 刻蚀暴露的金属薄膜 7;
S306: 如图 16a〜图 16b所示， 去除剩余的光刻胶 81和 82， 以形成栅极
101、栅线 104、梳状公共电极 102以及公共电极线 103的图形。本实施例中， 栅极 101由栅线 104与有源层 41相重叠的栅金属部分和其下方的透明导电薄 膜 6组成。
所述金属薄膜 7可以使用由 Cr、 W、 Ti、 Ta、 Mo、 Al、 Cu等金属及其 合金形成的单层薄膜， 或由多层金属薄膜组成的复合薄膜。 透明导电薄膜 6 可以使用 ITO ( Indium Tin Oxide, 铟锡氧化物）或 IZO ( Indium Zinc Oxide, 铟辞氧化物 )等。
在本实施例中， 所述栅极 101、栅线 104、公共电极线 103可认为仅由金 属薄膜， 则所述栅极 101、栅线 104、公共电极线 103位于所述梳状公共电极 102上方。还可认为所述栅极 101、栅线 104以及公共电极线 103均由两部分 组成， 从上至下依次是金属薄膜和透明导电薄膜。 在此情况下， 由于金属薄 膜以及透明导电薄膜都是导体， 故不仅保持了栅极 101、 栅线 104以及公共 电极线 103的导电性， 还利用金属薄膜的不透光性保持了遮光性。
在本实施例中， 栅极 101、 栅线 104、 公共电极 102以及公共电极线 103 通过一次构图工艺形成， 大大减少了制作工艺的复杂性及成本， 提高了生产 效率。
所述半导体薄膜 2的材质可为铟镓辞氧化物、 铟镓锡氧化物、 铟锡氧化 物中的至少一种。 优选为铟镓辞氧化物（IGZO )， 因为其载流子迁移速率高， 所以利用该材质形成的薄膜晶体管反应速率快， 从而提高了阵列基板的反应 速率。
综合上述， 在本实施例所述的阵列基板制作方法中， 仅用两次构图工艺 就完成了阵列基板的制作， 制作简便、 快捷， 生产效率高， 减少了掩膜板的 数量， 降低了光刻胶、 显影液等耗材的损耗， 从而降低了制造成本， 提高了 生产效率和经济效益。
本发明的另一实施例还提供了一种阵列基板， 其中该阵列基板为釆用上 述的阵列基板制作方法制作而成。如图 17所示， 所述阵列基板可包括： 形成 在衬底基板 1上的多条栅线、 多条数据线（未示出）及由多条栅线和多条数 据线交叉限定的多个像素单元（未示出）；其中每个像素单元包括薄膜晶体管 (未示出）及与所述薄膜晶体管连接的像素电极 25， 所述像素电极 25、数据 线和所述薄膜晶体管的有源层 21、 源极 22以及漏极 23位于同一层。 然而现 有技术当中， 有源层通常位于所述源极 22、 漏极 23之上。 如图 17所示， 所 述像素电极 25在所述衬底基板 1的表面上。本实施例所述的阵列基板由于将 有源层 21、 源极 22、 漏极 23、 数据线以及像素电极 25设置在同一层， 仅需 一次构图工艺即可完成制作， 因此制作工艺简单， 快捷， 且减少了掩膜板的 数量， 降低了光刻胶、 显影液等耗材的损耗， 从而降低了制造成本， 提高了 生产效率和经济效益。
在一个示例中，所述阵列基板还可包括位于所述像素电极 25、有源层 21、 源极 22、漏极 23以及数据线上的绝缘层 29; 以及位于所述绝缘层 29上方的 栅极 27。 栅极 27与栅线可一体形成， 栅线传输用于开启或关闭薄膜晶体管 的信号。
在本实施例所述的阵列基板中薄膜晶体管为顶栅型的。 若本实施例所述 的阵列基板用于制作 TN型的液晶显示面板，与像素电极 25相对设置的公共 电极设置在与阵列基板相对设置的对置基板（如彩膜基板）上， 故在阵列基 板中无需制作公共电极以及公共电极线， 而仅需制作栅极以及栅线即可， 且 可以釆用普通的构图工艺制作。
当本实施例所述的阵列基板用于制作多维电场型（例如 ADS型或者 IPS 型等） 的液晶显示面板时， 则阵列基板上还需制作公共电极以及为公共电极 提供电压的公共电极线， 且所述公共电极为梳状公共电极。 在此情况下， 本 实施例所述阵列基板还可包括设置在所述绝缘层 29上方的公共电极线 28以 及与所述公共电极线 28连接的梳状公共电极 26。 进一步地， 所述栅极 27、 栅线及公共电极线 28位于公共电极 26上方。
釆用本实施例所述的阵列基板， 仅需釆用一次构图工艺就完成了公共电 极 26、 公共电极线 28、 栅极 27以及栅线的形成， 具有制作简便， 耗材和设 备成本低， 经济效益好等优点。
在一个示例中， 如图 17所示， 本实施例中所述像素电极 25为梳状像素 电极 25。 在其他示例中， 像素电极 25还可以是位于像素区域内的平板电极。
所述像素电极 25、 数据线和薄膜晶体管的有源层 21、 源极 22以及漏极 23的材质可选自铟镓辞氧化物、 铟镓锡氧化物、 铟锡氧化物中的至少一种。 优选地， 它们的材质均为 IGZO。
有源层 21为半导体层， 而 IGZO本身就是半导体， 而源极 21、 漏极 22、 数据线、像素电极 25均为导体，故在制作过程中需釆用 Plasma处理将 IGZO 转换成导体， 从而保证阵列基板的品质。
综合上述， 本实施例所述的阵列基板， 具有结构简单， 制作成本低， 经 济效益好等优点。
上述阵列基板及其制作方法的实施例中均以顶栅薄膜晶体管为例进行说 明，但不限于此。对于底栅薄膜晶体管的阵列基板只需将图 17中位于同一层 的有源层 21、 源极 22、 漏极 23、 像素电极 25及数据线与绝缘层 29上方的 层交换层级位置即可， 即有源层 21、 源极 22、 漏极 23、 像素电极 25及数据 线位于绝缘层 29上方， 栅极 27、 栅线、 公共电极 26和公共电极线 28位于 绝缘层 29下方。 在制作方法上只需调整上述步骤 S1和 S3的顺序， 按照步 骤 S3-S2-S1制作即可， 每一步的制作工艺不变。
本发明的另一实施例还提供了一种显示装置， 包括由本发明实施例所述 阵列基板制作方法所制作的阵列基板，或包括本发明实施例所述的阵列基板。 所述显示装置可以是电子纸、 液晶显示面板、 OLED面板、 手机、 平板电脑、 电视机、 显示器、 笔记本电脑、 数码相框、 导航仪等任何具有显示功能的产 品或部件。
在本发明上述实施例的阵列基板及其制作方法和显示装置中， 相对于传 统的制作工艺， 仅需两次构图工艺即完成阵列基板的制作， 因此制作步骤少 且简便， 大大的降低了制作的复杂度和成本， 从而极大的提升了生产效率和 经济效益。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、 一种阵列基板的制作方法， 包括：
通过一次构图工艺在衬底基板上形成有源层、 源极、 漏极、 数据线以及 像素电极的图形；
形成绝缘层的图形； 以及
通过一次构图工艺形成栅极及栅线的图形。
2、根据权利要求 1所述的阵列基板制作方法，其中所述通过一次构图工 艺在衬底基板上形成有源层、 源极、 漏极、 数据线以及像素电极的图形的步 骤包括：
在衬底基板上形成半导体薄膜；
在所述半导体薄膜上涂布光刻胶， 通过双色调掩膜板对所述光刻胶进行 曝光、 显影， 完全保留有源层区域对应的光刻胶， 部分保留源极、 漏极、 数 据线以及像素电极区域对应的光刻胶， 完全去除剩余区域中的光刻胶以暴露 出半导体薄膜；
刻蚀暴露出的半导体薄膜；
对光刻胶进行灰化处理， 以减薄有源层区域对应的光刻胶并且暴露出除 有源层区域之外的区域的半导体薄膜；
通过等离子处理使暴露出的半导体薄膜变成导体， 以形成源极、 漏极、 数据线以及像素电极的图形； 以及
去除剩余的光刻胶。
3、根据权利要求 1或 2所述的阵列基板制作方法，其中所述通过一次构 图工艺形成栅极及栅线的图形的步骤还包括形成公共电极线及梳状公共电极 的图形。
4、根据权利要求 3所述的阵列基板制作方法，其中所述通过一次构图工 艺形成栅极及栅线的图形， 以及公共电极线及梳状公共电极的图形的步骤， 包括：
在绝缘层之上依次形成透明导电薄膜和金属薄膜；
在所述金属薄膜上涂布光刻胶， 通过双色调掩膜板对所述光刻胶进行曝 光、 显影， 完全保留栅极、 栅线以及公共电极线区域对应的光刻胶， 部分保 留梳状公共电极区域对应的光刻胶， 去除剩余区域中的光刻胶以暴露出金属 薄膜；
刻蚀暴露的金属薄膜及下方的透明导电薄膜；
对光刻胶进行灰化处理， 以减薄栅极、 栅线以及公共电极线区域对应的 光刻胶， 暴露出除栅极、 栅线及公共电极线区域之外的区域的金属薄膜； 刻蚀暴露的金属薄膜；
去除剩余的光刻胶， 形成栅极、 栅线、 公共电极线以及梳状公共电极的 图形。
5、根据权利要求 1-4任一项所述的阵列基板制作方法， 其中所述像素电 极为桥夫。
6、根据权利要求 2-5任一项所述的阵列基板制作方法， 其中所述半导体 薄膜的材质选自铟镓辞氧化物、 铟镓锡氧化物、 铟锡氧化物中的至少一种。
7、 一种阵列基板， 包括形成在衬底基板上的多条栅线、 多条数据线及由 多条栅线和多条数据线交叉限定的多个像素单元； 其中每个像素单元包括薄 膜晶体管及与所述薄膜晶体管连接的像素电极， 所述像素电极、 数据线、 薄 膜晶体管的有源层、 源极以及漏极设置在同一层。
8、根据权利要求 7所述的阵列基板，其中所述阵列基板还包括设置在所 述像素电极、 数据线、 有源层、 源极以及漏极上的绝缘层； 以及设置在所述 绝缘层上方的栅极。
9、根据权利要求 8所述的阵列基板，其中所述阵列基板还包括设置在所
10、 根据权利要求 9所述的阵列基板， 其中所述栅极、 栅线及公共电极 线设置在公共电极上方。
11、根据权利要求 7-10任一项所述的阵列基板， 其中所述像素电极为梳 状。
12、 根据权利要求 7-10任一项所述的阵列基板， 其中所述像素电极、 数 据线和薄膜晶体管的有源层、 源极以及漏极的材质选自铟镓辞氧化物、 铟镓 锡氧化物、 铟锡氧化物中的至少一种。
13、 一种显示装置， 包括权利要求 7-12任一项所述的阵列基板。
PCT/CN2014/075809 2013-12-26 2014-04-21 阵列基板及其制作方法和显示装置 WO2015096312A1 (zh)

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