WO2014141958A1 - 表示装置およびその駆動方法 - Google Patents
表示装置およびその駆動方法 Download PDFInfo
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- WO2014141958A1 WO2014141958A1 PCT/JP2014/055550 JP2014055550W WO2014141958A1 WO 2014141958 A1 WO2014141958 A1 WO 2014141958A1 JP 2014055550 W JP2014055550 W JP 2014055550W WO 2014141958 A1 WO2014141958 A1 WO 2014141958A1
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Definitions
- the present invention relates to a display device and a driving method thereof, and more particularly to a display device including a pixel circuit including an electro-optical element such as an organic EL (Electro-Luminescence) element and a driving method thereof.
- a display device including a pixel circuit including an electro-optical element such as an organic EL (Electro-Luminescence) element and a driving method thereof.
- an electro-optical element such as an organic EL (Electro-Luminescence) element
- organic EL display devices that use organic EL elements, which are self-luminous electro-optic elements, can be easily reduced in thickness, power consumption, brightness, etc., compared to liquid crystal display devices that require backlights and color filters. Can be achieved. Accordingly, in recent years, organic EL display devices have been actively developed.
- an organic EL display device As a driving method of an organic EL display device, a passive matrix method (also called a simple matrix method) and an active matrix method are known.
- An organic EL display device adopting a passive matrix system has a simple structure but is difficult to increase in size and definition.
- an organic EL display device adopting an active matrix method hereinafter referred to as an “active matrix type organic EL display device” is larger and has higher definition than an organic EL display device employing a passive matrix method. Can be easily realized.
- a pixel circuit of an active matrix organic EL display device typically includes an input transistor that selects a pixel and a drive transistor that controls the supply of current to the organic EL element.
- the current flowing from the drive transistor to the organic EL element may be referred to as “drive current”.
- FIG. 44 is a circuit diagram showing a configuration of a conventional general pixel circuit 91.
- the pixel circuit 91 is provided corresponding to each intersection of the plurality of data lines S and the plurality of scanning lines G arranged in the display unit.
- the pixel circuit 91 includes two transistors T1 and T2, one capacitor Cst, and one organic EL element OLED.
- the transistor T1 is an input transistor
- the transistor T2 is a drive transistor.
- the transistor T1 is provided between the data line S and the gate terminal of the transistor T2.
- a gate terminal is connected to the scanning line G, and a source terminal is connected to the data line S.
- the transistor T2 is provided in series with the organic EL element OLED.
- a drain terminal is connected to a power supply line that supplies a high-level power supply voltage ELVDD, and a source terminal is connected to an anode terminal of the organic EL element OLED.
- a power supply line that supplies the high-level power supply voltage ELVDD is hereinafter referred to as a “high-level power supply line”, and the high-level power supply line is given the same sign ELVDD as the high-level power supply voltage.
- the capacitor Cst one end is connected to the gate terminal of the transistor T2, and the other end is connected to the source terminal of the transistor T2.
- the cathode terminal of the organic EL element OLED is connected to a power supply line that supplies a low level power supply voltage ELVSS.
- the power supply line that supplies the low-level power supply voltage ELVSS is hereinafter referred to as “low-level power supply line”, and the same sign ELVSS as the low-level power supply voltage is attached to the low-level power supply line.
- a connection point between the gate terminal of the transistor T2, one end of the capacitor Cst, and the drain terminal of the transistor T1 is referred to as a “gate node VG” for convenience.
- the higher of the drain and the source is called the drain, but in the description of this specification, one is defined as the drain and the other is defined as the source. Therefore, the source potential is higher than the drain potential. May be higher.
- FIG. 45 is a timing chart for explaining the operation of the pixel circuit 91 shown in FIG.
- the scanning line G Prior to time t1, the scanning line G is in a non-selected state. Therefore, before the time t1, the transistor T1 is in an off state, and the potential of the gate node VG maintains an initial level (for example, a level corresponding to writing in the previous frame).
- the scanning line G is selected and the transistor T1 is turned on.
- the data voltage Vdata corresponding to the luminance of the pixel (subpixel) formed by the pixel circuit 91 is supplied to the gate node VG via the data line S and the transistor T1.
- the potential of the gate node VG changes according to the data voltage Vdata.
- the capacitor Cst is charged to the gate-source voltage Vgs which is the difference between the potential of the gate node VG and the source potential of the transistor T2.
- the scanning line G is in a non-selected state.
- the transistor T1 is turned off, and the gate-source voltage Vgs held by the capacitor Cst is determined.
- the transistor T2 supplies a drive current to the organic EL element OLED according to the gate-source voltage Vgs held by the capacitor Cst. As a result, the organic EL element OLED emits light with a luminance corresponding to the drive current.
- a thin film transistor (TFT) is typically employed as a drive transistor.
- the threshold voltage tends to vary for the thin film transistor.
- a technique for suppressing deterioration in display quality in an organic EL display device has been conventionally proposed.
- Japanese Unexamined Patent Application Publication No. 2005-31630 discloses a technique for compensating for variations in threshold voltage of drive transistors.
- 2007-128103 disclose a technique for making the current flowing from the pixel circuit to the organic EL element OLED constant. Furthermore, Japanese Unexamined Patent Application Publication No. 2007-233326 discloses a technique for displaying an image with uniform brightness regardless of the threshold voltage and electron mobility of a driving transistor.
- Japanese Patent Publication No. 2008-523448 discloses a technique for correcting data based on the characteristics of the organic EL element OLED in addition to the technique for correcting data based on the characteristics of the driving transistor.
- Japanese Unexamined Patent Publication No. 2005-31630 Japanese Unexamined Patent Publication No. 2003-195810 Japanese Unexamined Patent Publication No. 2007-128103 Japanese Unexamined Patent Publication No. 2007-233326 Japanese Special Table 2008-523448
- An object of the present invention is to provide a driving method capable of simultaneously compensating for both deterioration of a driving transistor and deterioration of a light emitting element in a display device without causing special light emission when detecting characteristics. To do.
- n ⁇ m electro-optical elements whose luminance is controlled by current and driving transistors for controlling the current to be supplied to the electro-optical elements (n and m are 2).
- One frame period includes a selection period in which preparation for causing the electro-optical element to emit light and a light-emitting
- the processing of both the first characteristic detection step and the second characteristic detection step is performed in only one row of the pixel matrix per frame period,
- a line in which both the first characteristic detection step and the second characteristic detection step are performed in each frame is defined as a monitor line, and a line other than the monitor line is defined as a non-monitor line, the monitor
- the length of the selection period for a row is longer than the length of the selection period for the non-monitoring row
- the processing of the first characteristic detection step is performed during the selection period.
- One process of the first characteristic detection step and the second characteristic detection step is performed in only one row of the pixel matrix per frame period, When attention is paid to one row of the pixel matrix, the process of the first characteristic detection step and the process of the second characteristic detection step are alternately performed, The processing of the first characteristic detection step is performed during the light emission period.
- the characteristic of the electro-optical element is detected by measuring the voltage of the anode of the electro-optical element in a state where a constant current is applied to the electro-optical element.
- the length of time during which the constant current is applied to the electro-optical element is adjusted according to target luminance.
- a sixth aspect of the present invention is the fourth aspect of the present invention,
- a plurality of levels of the constant current are applied to the electro-optical element within a range in which the integrated value of the light emission current in one frame period becomes a value corresponding to the target gradation.
- a plurality of characteristics are detected as the characteristics of the electro-optical element.
- the characteristic of the electro-optical element is detected by measuring a current flowing through the electro-optical element in a state where a constant voltage is applied to the electro-optical element. To do.
- the length of time during which the constant voltage is applied to the electro-optical element is adjusted according to target luminance.
- a plurality of levels of the constant voltage are applied to the electro-optic element within a range in which the integrated value of the light emission current in one frame period becomes a value corresponding to the target gradation.
- a plurality of characteristics are detected as the characteristics of the electro-optical element.
- the current flowing between the drain and the source of the driving transistor is measured in a state in which the voltage between the gate and the source of the driving transistor is set to a predetermined magnitude, so that the characteristic of the driving transistor is measured. Is detected.
- the correction data storage unit includes an offset value storage unit that stores an offset value as the correction data and a gain value storage unit that stores a gain value as the correction data.
- the correction data storing step The sum of the offset value obtained based on the detection result in the first characteristic detection step and the offset value obtained based on the detection result in the second characteristic detection step is used as the new offset value.
- the product of the gain value obtained based on the detection result in the first characteristic detection step and the correction coefficient obtained based on the detection result in the second characteristic detection step is the gain value as a new gain value. It is stored in the storage unit.
- a twelfth aspect of the present invention is the eleventh aspect of the present invention,
- the display device A characteristic detector for detecting characteristics of the driving transistor and characteristics of the electro-optic element; M monitor lines provided so as to correspond to the respective columns of the pixel matrix and configured to be electrically connected to the characteristic detection units and the pixel circuits of the corresponding columns;
- the selection period includes a first period in which processing of the first characteristic detection step is performed and a second period following the first period,
- the gain value storage unit defines a difference value between the offset value stored in the offset value storage unit and the offset value obtained based on the detection result in the first characteristic detection step as a first value.
- a voltage corresponding to the sum of the first value and the second value is applied to each monitor line.
- the correction data storage unit stores an offset value corresponding to the drive transistor as the correction data, and stores an offset value corresponding to the electro-optical element as the correction data.
- An offset value storage unit, a drive transistor gain value storage unit that stores a gain value corresponding to the drive transistor as the correction data, and an electro-optical element gain that stores a gain value corresponding to the electro-optical element as the correction data It consists of a value storage unit,
- An offset value obtained based on the detection result in the first characteristic detection step is stored in the drive transistor offset value storage unit as a new offset value
- a gain value obtained based on the detection result in the first characteristic detection step is stored in the drive transistor gain value storage unit as a new gain value.
- the offset value obtained based on the detection result in the second characteristic detection step is stored in the electro-optic element offset value storage unit as a new offset value
- the correction coefficient obtained based on the detection result in the second characteristic detection step is stored in the electro-optic element gain value storage unit as a new gain value.
- a fourteenth aspect of the present invention is the thirteenth aspect of the present invention.
- the characteristic of the electro-optical element is detected by measuring the voltage of the anode of the electro-optical element in a state where a constant current is applied to the electro-optical element.
- the magnitude of the constant current is adjusted according to a gain value stored in the electro-optic element gain value storage unit.
- the characteristic of the electro-optical element is detected by measuring a current flowing through the electro-optical element in a state where a constant voltage is applied to the electro-optical element.
- the constant voltage is adjusted in accordance with a gain value stored in the electro-optic element gain value storage unit.
- the display device A characteristic detector for detecting characteristics of the driving transistor and characteristics of the electro-optic element; M monitor lines provided so as to correspond to the respective columns of the pixel matrix and configured to be electrically connected to the characteristic detection units and the pixel circuits of the corresponding columns;
- the selection period includes a first period in which processing of the first characteristic detection step is performed and a second period following the first period, In the second period, each monitor line is obtained based on the offset value stored in the electro-optical element offset value storage unit and the gain value stored in the electro-optical element gain value storage unit. A voltage corresponding to the sum of the values is applied.
- the display device A current detection unit for measuring current, and a characteristic detection unit for detecting the characteristics of the drive transistor and the electro-optical element; M monitor lines provided so as to correspond to the respective columns of the pixel matrix and configured to be electrically connected to the characteristic detection units and the pixel circuits of the corresponding columns;
- the voltage between the gate and the source of the driving transistor is set to a predetermined level in a state where the m monitor lines are electrically connected to the corresponding pixel circuit and the current measuring unit. In this state, the current flowing between the drain and source of the driving transistor is measured by the current measuring unit.
- the characteristic detection unit further includes a voltage measurement unit for measuring a voltage
- a voltage of the anode of the electro-optical element is measured by the voltage measuring unit in a state where a constant current is applied to the electro-optical element.
- a current flowing through the electro-optical element in a state where a constant voltage is applied to the electro-optical element is measured by the current measuring unit.
- K is an integer of 2 to m
- One of the K monitor lines is electrically connected to the characteristic detector, The monitor line that is not electrically connected to the characteristic detection unit is in a high impedance state.
- the second characteristic detection step is not performed on pixels that are displayed in black or almost black.
- a monitor area storage prepared in advance with information specifying the area where one or both of the first characteristic detection step and the second characteristic detection step has been performed last.
- a monitor area storing step of storing in the unit After the display device is turned on, one or both of the first characteristic detection step and the second characteristic detection step are performed from an area near the area obtained based on information stored in the monitor area storage unit. The following process is performed.
- the driving transistor is a thin film transistor in which a channel layer is formed of an oxide semiconductor.
- the oxide semiconductor is indium gallium zinc oxide containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O) as main components.
- n ⁇ m electro-optical elements whose luminance is controlled by a current and driving transistors for controlling a current to be supplied to the electro-optical elements (n and m are 2).
- a display device having a pixel matrix of n rows ⁇ m columns composed of pixel circuits of the above integer), A pixel circuit driving unit that drives the n ⁇ m pixel circuits while performing a first characteristic detection process for detecting the characteristic of the driving transistor and a second characteristic detection process for detecting the characteristic of the electro-optic element; A correction data storage unit for storing characteristic data obtained based on the detection result in the first characteristic detection process and the detection result in the second characteristic detection process as correction data for correcting the video signal; A video signal correction unit that corrects the video signal based on correction data stored in the correction data storage unit and generates a data signal to be supplied to the n ⁇ m pixel circuits; One frame period includes a selection period in which preparation for causing the electro-optical element to emit light and a light-emitting period in which light emission of the electro-optical element is performed, The pixel circuit driving unit includes: Performing one or both of the first characteristic detection process and the second characteristic detection process for only one row of the pixel matrix
- a pixel circuit including an electro-optical element (for example, an organic EL element) whose luminance is controlled by a current and a driving transistor for controlling a current to be supplied to the electro-optical element.
- an electro-optical element for example, an organic EL element
- a driving transistor for controlling a current to be supplied to the electro-optical element.
- the characteristics of the driving transistor and the characteristics of the electro-optical element are detected.
- the video signal is corrected using correction data obtained in consideration of both detection results. Since the data signal based on the video signal corrected in this way is supplied to the pixel circuit, a driving current having such a magnitude as to compensate for the deterioration of the driving transistor and the deterioration of the electro-optical element is supplied to the electro-optical element.
- the characteristics of the electro-optical element are detected during the light emission period of the electro-optical element. Therefore, the length of the light emission period is not shorter than that in the past in order to detect the characteristics of the drive transistor and the electro-optical element. As described above, in the display device, both the deterioration of the driving transistor and the deterioration of the electro-optic element can be compensated at the same time without causing special light emission when detecting characteristics.
- the length of the selection period for the monitor row (the row where the characteristic is detected in each frame) is longer than the length of the selection period for the non-monitor row. Yes. Then, the characteristics of the driving transistor are detected during the selection period. Therefore, a sufficient period for detecting the characteristics of the drive transistor is ensured.
- both the detection of the characteristics of the drive transistor and the detection of the characteristics of the electro-optical element are performed during the light emission period of the electro-optical element. For this reason, unlike the configuration in which the characteristics are detected even during the selection period, it is not necessary to lengthen the selection period of the monitor row. Therefore, a sufficiently long light emission period is ensured. Further, variation in the length of the selection period depending on the row is prevented. As described above, the display device emits special light when detecting characteristics of both the deterioration of the drive transistor and the deterioration of the electro-optic element while ensuring a sufficient light emission period without causing variations in the length of the selection period. It is possible to compensate at the same time.
- a constant current is supplied to the electro-optical element that detects the characteristic. Therefore, by adjusting the time for supplying a constant current to the electro-optical element, it becomes possible to cause the electro-optical element to emit light with a desired luminance.
- the electro-optical element it is possible to cause the electro-optical element to emit light with a desired luminance while detecting the characteristics of the electro-optical element.
- the sixth aspect of the present invention since a plurality of characteristics are detected as the characteristics of the electro-optic element, it is possible to more effectively compensate for the deterioration of the drive transistor.
- the measurement time for detecting the characteristics of the electro-optic element can be shortened.
- the electro-optical element it is possible to cause the electro-optical element to emit light with a desired luminance while detecting the characteristics of the electro-optical element.
- the ninth aspect of the present invention since a plurality of characteristics are detected as the characteristics of the electro-optic element, it is possible to more effectively compensate for the deterioration of the drive transistor.
- the display device includes a component for measuring current
- the same effect as that of the first aspect of the present invention can be achieved.
- the offset value storage unit stores correction data considering both the characteristics of the drive transistor and the electro-optical element
- the gain value storage unit also stores the characteristics and electrical characteristics of the drive transistor. Correction data considering both characteristics of the optical element is stored. Therefore, it is possible to easily correct the video signal in consideration of both the characteristics of the driving transistor and the characteristics of the electro-optical element.
- a voltage corresponding to the degree of deterioration of the electro-optic element is applied to the monitor line before the light emission period, and the length of the charging time in the light emission period is shortened.
- the storage unit that stores the offset value and the storage unit that stores the gain value each cause deterioration of the storage unit and the electro-optic element used to compensate for the deterioration of the drive transistor. It is divided into a storage unit used for compensation. For this reason, it is possible to adjust the current supplied to the electro-optical element in consideration of only the deterioration of the electro-optical element. At this time, it is possible to compensate for burn-in by increasing the current in accordance with the deterioration level of the pixel with the least deterioration.
- the magnitude of the current supplied to the electro-optical element during the light emission period is the gain stored in the gain value storage unit for the electro-optical element. It is adjusted according to the value (correction coefficient). That is, the current magnitude is adjusted according to the degree of deterioration of the electro-optic element. This compensates for a decrease in current efficiency.
- the magnitude of the voltage applied to the electro-optic element during the light emission period is the gain value stored in the gain value storage unit for the electro-optic element. It is adjusted according to (correction coefficient). As a result, a voltage having a magnitude corresponding to the degree of deterioration of the electro-optical element is applied to the electro-optical element during the light emission period.
- a voltage corresponding to the degree of deterioration of the electro-optic element is applied to the monitor line before the light emission period, and the length of the charging time in the light emission period is shortened.
- the seventeenth aspect of the present invention it is possible to detect the characteristics of both the drive transistor and the electro-optic element included in each column with a single monitor line.
- the electro-optic element emits light so that display closer to the desired gradation is performed.
- the measurement time for detecting the characteristics of the electro-optic element can be shortened.
- one characteristic detection unit is shared by a plurality of monitor lines. For this reason, it is possible to simultaneously compensate for both the deterioration of the drive transistor and the deterioration of the electro-optical element without causing special light emission during characteristic detection while suppressing an increase in circuit area.
- the twenty-second aspect of the present invention for example, a difference in the number of detections of the characteristics of the driving transistor and the characteristics of the electro-optic element between the upper row and the lower row is prevented. For this reason, it is possible to uniformly compensate for the deterioration of the driving transistor and the deterioration of the electro-optic element over the entire screen, and the occurrence of variations in luminance is effectively prevented.
- the video signal is corrected using the correction data considering the temperature change. Therefore, in the display device, it is possible to simultaneously compensate for both the deterioration of the driving transistor and the deterioration of the electro-optical element regardless of the temperature without causing special light emission when detecting the characteristics.
- a thin film transistor in which a channel layer is formed of an oxide semiconductor is used as a drive transistor provided in a pixel circuit. For this reason, the effect of high definition and low power consumption can be obtained. Further, since the off-state current is extremely small, an effect that a sufficient S / N ratio can be ensured when the current is detected can be obtained.
- the same effect as in the twenty-fourth aspect of the present invention can be reliably achieved.
- the same effect as in the first aspect of the present invention can be achieved in the invention of the display device.
- FIG. 5 is a flowchart for explaining an outline of operations related to detection of TFT characteristics and OLED characteristics in the first embodiment of the present invention.
- the said 1st Embodiment it is a block diagram which shows the whole structure of an organic electroluminescent display apparatus.
- 5 is a timing chart for explaining an operation of a gate driver in the first embodiment.
- 5 is a timing chart for explaining an operation of a gate driver in the first embodiment.
- 5 is a timing chart for explaining an operation of a gate driver in the first embodiment.
- FIG. 3 is a block diagram illustrating a schematic configuration of a signal conversion circuit in the first embodiment. It is a figure which shows the structure of the pixel circuit and monitor circuit in the said 1st Embodiment.
- the said 1st Embodiment it is a figure for demonstrating the application to the data line of the reference voltage in a TFT characteristic detection period. In the said 1st Embodiment, it is a figure for demonstrating the flow of the electric current in the light emission period. In the said 1st Embodiment, it is a figure for demonstrating adjustment of the light emission time of an organic EL element. In the said 1st Embodiment, it is a figure for demonstrating the difference in the length of the light emission period in a monitoring line and a non-monitoring line. 6 is a flowchart for explaining a procedure for updating an offset memory and a gain memory in the first embodiment.
- FIG 4 is a diagram illustrating a configuration of a video signal correction unit in the first embodiment. It is a figure for demonstrating the effect in the said 1st Embodiment. It is a block diagram which shows the whole structure of the organic electroluminescence display in the 1st modification of the said 1st Embodiment. 12 is a flowchart for explaining a procedure for updating a TFT offset memory, an OLED offset memory, a TFT gain memory, and an OLED gain memory in the first modification of the first embodiment. It is a figure for demonstrating the effect in the 1st modification of the said 1st Embodiment. It is a figure which shows the structure of the one end part vicinity of the monitor line in the 2nd modification of the said 1st Embodiment.
- FIG. 10 is a timing chart for explaining an OLED characteristic detection operation in a pixel circuit (a pixel circuit of i rows and j columns) included in a monitor row in the second embodiment.
- FIG. 10 is a timing chart for explaining a TFT characteristic detection operation in a pixel circuit (pixel circuit of i rows and j columns) included in a monitor row in the second embodiment.
- TFT characteristic the characteristic of the driving transistor provided in the pixel circuit
- OLED characteristic the characteristic of the organic EL element provided in the pixel circuit
- FIG. 2 is a block diagram showing the overall configuration of the active matrix organic EL display device 1 according to the first embodiment of the present invention.
- the organic EL display device 1 includes a display unit 10, a control circuit 20, a source driver (data line driving circuit) 30, a gate driver (scanning line driving circuit) 40, an offset memory 51, and a gain memory 52.
- the source driver 30 and the gate driver 40 may be formed integrally with the display unit 10.
- the offset memory 51 and the gain memory 52 may be physically constituted by one memory.
- a pixel circuit driving unit is realized by the source driver 30 and the gate driver 40, and a correction data storage unit is realized by the offset memory 51 and the gain memory 52.
- the display unit 10 is provided with m data lines S (1) to S (m) and n scanning lines G1 (1) to G1 (n) orthogonal thereto.
- the extending direction of the data lines is defined as the Y direction
- the extending direction of the scanning lines is defined as the X direction.
- Components along the Y direction may be referred to as “columns”
- components along the X direction may be referred to as “rows”.
- the display unit 10 is provided with m monitor lines M (1) to M (m) so as to correspond to the m data lines S (1) to S (m) on a one-to-one basis. ing.
- the data lines S (1) to S (m) and the monitor lines M (1) to M (m) are parallel to each other.
- the display unit 10 is provided with n monitor control lines G2 (1) to G2 (n) so as to correspond to the n scanning lines G1 (1) to G1 (n) on a one-to-one basis.
- the scanning lines G1 (1) to G1 (n) and the monitor control lines G2 (1) to G2 (n) are parallel to each other.
- the display unit 10 has n ⁇ m so as to correspond to the intersections of the n scanning lines G1 (1) to G1 (n) and the m data lines S (1) to S (m).
- Pixel circuits 11 are provided. By providing n ⁇ m pixel circuits 11 in this manner, a pixel matrix of n rows ⁇ m columns is formed in the display unit 10.
- the display unit 10 is provided with a high level power supply line for supplying a high level power supply voltage and a low level power supply line for supplying a low level power supply voltage.
- the data lines are simply represented by a symbol S.
- the monitor lines are simply represented by the symbol M, and the n scan lines G1 (1) to G1 (n) If it is not necessary to distinguish the monitor lines from each other, the scanning line is simply indicated by G1, and if it is not necessary to distinguish the n monitor control lines G2 (1) to G2 (n) from each other, the monitor control lines are simply denoted by reference numerals. Represented by G2.
- the control circuit 20 controls the operation of the source driver 30 by supplying the data signal DA, the source control signal SCTL, and the switching control signal SW to the source driver 30, and transmits the gate control signal GCTL to the gate driver 40.
- the operation of the driver 40 is controlled.
- the source control signal SCTL includes, for example, a source start pulse, a source clock, and a latch strobe signal.
- the gate control signal GCTL includes, for example, a gate start pulse and a gate clock.
- the control circuit 20 receives the monitor data MO given from the source driver 30 and updates the offset memory 51 and the gain memory 52. Note that the monitor data MO is data measured for obtaining TFT characteristics and OLED characteristics.
- the gate driver 40 is connected to n scanning lines G1 (1) to G1 (n) and n monitor control lines G2 (1) to G2 (n).
- the gate driver 40 includes a shift register and a logic circuit.
- Detection of TFT characteristics and OLED characteristics for the third row is performed.
- detection of TFT characteristics and OLED characteristics for n rows is performed over an n frame period.
- the frame in which the TFT characteristic and the OLED characteristic for the first row are detected is defined as the (k + 1) th frame
- n scanning lines G1 (1) to G1 (n) and n monitor control lines G2 (1) to G2 (n) are driven as shown in FIG. 3 at the (k + 1) th frame, driven at the (k + 2) th frame as shown in FIG. 4, and at the (k + n) th frame.
- the high level state is an active state.
- a period in which the scanning line G1 is in an active state is referred to as a “selection period”.
- This selection period is a period for preparing to emit light from the organic EL element provided in the pixel circuit 11.
- a selection period is a period for preparing to emit light from the organic EL element provided in the pixel circuit 11.
- the monitor control line G2 corresponding to the non-monitor row is maintained in an inactive state.
- the monitor control line G2 corresponding to the monitor row is activated from the beginning of the selection period for a predetermined period and inactive for the remaining period of the selection period. In the period up to about one frame period, it becomes active again.
- the gate driver 40 is driven so that the n scanning lines G1 (1) to G1 (n) and the n monitor control lines G2 (1) to G2 (n) are driven as described above. It is configured.
- the source driver 30 is connected to m data lines S (1) to S (m) and m monitor lines M (1) to M (m).
- the source driver 30 includes a drive signal generation circuit 31, a signal conversion circuit 32, and an output unit 33 including m output circuits 330.
- the m output circuits 330 in the output unit 33 respectively correspond to the corresponding data line S and m monitor lines M (1) to M (m) among the m data lines S (1) to S (m). Are connected to the corresponding monitor line M.
- the drive signal generation circuit 31 includes a shift register, a sampling circuit, and a latch circuit.
- the shift register sequentially transfers the source start pulse from the input end to the output end in synchronization with the source clock.
- a sampling pulse corresponding to each data line S is output from the shift register.
- the sampling circuit sequentially stores the data signals DA for one row according to the timing of the sampling pulse.
- the latch circuit fetches and holds the data signal DA for one row stored in the sampling circuit according to the latch strobe signal.
- FIG. 6 is a block diagram showing a schematic configuration of the signal conversion circuit 32.
- the signal conversion circuit 32 includes a gradation signal generation circuit 321 and a monitor circuit 322.
- the gradation signal generation circuit 321 includes a D / A converter.
- the data signal DA for one row held in the latch circuit in the drive signal generation circuit 31 as described above is converted into an analog voltage by the D / A converter in the gradation signal generation circuit 321.
- the converted analog voltage is applied to the output circuit 330 in the output unit 33.
- the monitor circuit 322 includes an A / D converter. In the A / D converter in the monitor circuit 322, an analog voltage that appears on the monitor line M and represents the TFT characteristics and the OLED characteristics is converted into monitor data MO that is a digital signal.
- the monitor data MO is given to the control circuit 20 via the drive signal generation circuit 31. A detailed description of the monitor circuit 322 will be given later.
- the output circuit 330 in the output unit 33 applies the analog voltage supplied from the gradation signal generation circuit 321 in the signal conversion circuit 32 to the data line S as a data voltage through the buffer.
- the output circuit 330 in the output unit 33 switches the connection destination of the monitor line M based on the switching control signal SW. A detailed description thereof will be described later.
- the offset memory 51 and the gain memory 52 store correction data used for correcting a video signal sent from the outside.
- the offset memory 51 stores an offset value as correction data
- the gain memory 52 stores a gain value as correction data.
- the number of offset values and gain values equal to the number of pixels in the display unit 10 are stored in the offset memory 51 and the gain memory 52, respectively.
- a buffer memory for temporarily holding an offset value hereinafter referred to as “offset value buffer”
- gain value buffer a buffer memory for temporarily holding a gain value
- the control circuit 20 updates the offset value in the offset memory 51 and the gain value in the gain memory 52 based on the monitor data MO given from the source driver 30.
- the control circuit 20 reads the offset value stored in the offset memory 51 and the gain value stored in the gain memory 52 and corrects the video signal. Data obtained by the correction is sent to the source driver 30 as a data signal DA.
- FIG. 7 is a diagram illustrating the configuration of the pixel circuit 11 and the monitor circuit 322.
- the pixel circuit 11 illustrated in FIG. 7 is the pixel circuit 11 of i rows and j columns.
- the pixel circuit 11 includes one organic EL element OLED, three transistors T1 to T3, and one capacitor Cst.
- the transistor T1 functions as an input transistor for selecting a pixel
- the transistor T2 functions as a drive transistor for controlling supply of current to the organic EL element OLED
- the transistor T3 controls whether to detect TFT characteristics or OLED characteristics. Functions as a monitor control transistor.
- the transistor T1 is provided between the data line S (j) and the gate terminal of the transistor T2.
- a gate terminal is connected to the scanning line G1 (i), and a source terminal is connected to the data line S (j).
- the transistor T2 is provided in series with the organic EL element OLED.
- the gate terminal is connected to the drain terminal of the transistor T1, the drain terminal is connected to the high-level power supply line ELVDD, and the source terminal is connected to the anode terminal of the organic EL element OLED.
- the gate terminal is connected to the monitor control line G2 (i)
- the drain terminal is connected to the anode terminal of the organic EL element OLED
- the source terminal is connected to the monitor line M (j).
- the capacitor Cst one end is connected to the gate terminal of the transistor T2, and the other end is connected to the source terminal of the transistor T2.
- the cathode terminal of the organic EL element OLED is connected to the low level power line ELVSS.
- the transistors T1 to T3 in the pixel circuit 11 are all n-channel type.
- oxide TFTs thin film transistors using an oxide semiconductor as a channel layer
- oxide TFTs are employed for the transistors T1 to T3.
- InGaZnOx indium gallium zinc oxide
- IGZO indium gallium zinc oxide
- an oxide TFT such as an IGZO-TFT is particularly effective when employed as an n-channel transistor included in the pixel circuit 11.
- the present invention does not exclude the use of a p-channel oxide TFT.
- a transistor using an oxide semiconductor other than IGZO for the channel layer can also be employed.
- at least one of indium, gallium, zinc, copper (Cu), silicon (Si), tin (Sn), aluminum (Al), calcium (Ca), germanium (Ge), and lead (Pb) is included.
- the same effect can be obtained when a transistor using an oxide semiconductor for a channel layer is employed.
- the present invention does not exclude the use of a transistor other than a transistor using an oxide semiconductor for a channel layer.
- the monitor circuit 322 includes a current measurement unit 38 and a voltage measurement unit 39.
- the monitor circuit 322 implements a characteristic detection unit.
- either the current measuring unit 38 or the voltage measuring unit 39 is selected based on the switching control signal SW given from the control circuit 20 to the output circuit 330. Is connected to the monitor line M (j). In FIG. 7, only a part of the configuration of the output circuit 330 is shown.
- FIG. 8 is a diagram illustrating a configuration example of the current measuring unit 38.
- the current measuring unit 38 includes an operational amplifier 381, a capacitor 382, a switch 383, and an A / D converter 384.
- the operational amplifier 381 the non-inverting input terminal is connected to the low-level power supply line ELVSS, and the inverting input terminal is connected to the monitor line M.
- the capacitor 382 and the switch 383 are provided between the output terminal of the operational amplifier 381 and the monitor line M.
- the current measuring unit 38 is configured by an integrating circuit. In such a configuration, first, the switch 383 is turned on by the control clock signal Sclk.
- the output terminal and the inverting input terminal of the operational amplifier 381 are short-circuited, and the potential of the output terminal of the operational amplifier 381 and the monitor line M becomes equal to the potential of the low-level power supply line ELVSS.
- the switch 383 is turned off by the control clock signal Sclk.
- the potential of the output terminal of the operational amplifier 381 changes according to the magnitude of the current flowing through the monitor line M.
- the change in potential is reflected in the digital signal output from the A / D converter 384.
- the digital signal is output from the current measuring unit 38 as monitor data MO.
- FIG. 9 is a diagram illustrating a configuration example of the voltage measurement unit 39.
- the voltage measuring unit 39 includes an amplifier 391 and an A / D converter 392.
- the voltage between the node 393 and the low-level power supply line ELVSS is amplified by the amplifier 391 in a state where a constant current is passed through the monitor line M by the constant current source 37.
- the amplified voltage is converted into a digital signal by the A / D converter 392.
- the digital signal is output from the voltage measurement unit 39 as monitor data MO.
- a driving method in the present embodiment will be described.
- detection of TFT characteristics and OLED characteristics in one row is performed for each frame.
- an operation for detecting the TFT characteristic and the OLED characteristic (hereinafter referred to as “characteristic detection operation”) is performed for the monitor row, and a normal operation is performed for the non-monitor row. That is, if the frame in which the TFT characteristic and the OLED characteristic for the first row are detected is defined as the (k + 1) th frame, the operation of each row changes as shown in FIG.
- the offset memory 51 and the gain memory 52 are updated using the detection result. Then, the video signal is corrected using the correction data stored in the offset memory 51 and the gain memory 52.
- FIG. 12 is a timing chart for explaining the operation of the pixel circuit 11 (referred to as the pixel circuit 11 of i rows and j columns) included in the monitor row.
- “one frame period” is represented on the basis of the selection period start point of the i-th row in a frame in which the i-th row is a monitor row.
- TFT characteristics detection period a period for detecting TFT characteristics (hereinafter referred to as “TFT characteristics detection period”) Ta and data corresponding to black display are written in one frame period.
- a period (hereinafter referred to as “black writing period”) Tb for a period of time and a period (hereinafter referred to as “light emission period”) Tc for causing the organic EL element OLED to emit light are included.
- the first predetermined period in the selection period is the TFT characteristic detection period Ta
- the period other than the TFT characteristic detection period Ta in the selection period is the black writing period Tb.
- the first period is realized by the TFT characteristic detection period Ta
- the second period is realized by the black writing period Tb.
- the scanning line G1 (i) and the monitor control line G2 (i) are activated. Accordingly, the transistor T1 and the transistor T3 are turned on.
- a reference voltage Vref for detecting the TFT characteristics is applied to the data line S (j). As a result, the reference voltage Vref is written, and the transistor T2 is also turned on.
- the current flowing through the transistor T2 is output to the monitor line M (j) via the transistor T3. Further, the monitor line M (j) is connected to the current measuring unit 38 by the switching control signal SW during the TFT characteristic detection period Ta.
- the current (sink current) output to the monitor line M (j) is measured by the current measuring unit 38.
- the magnitude of the current flowing between the drain and source of the transistor T2 is measured in a state where the voltage between the gate and source of the transistor T2 is set to a predetermined level (the magnitude of the reference voltage Vref). TFT characteristics are detected.
- first reference voltage Vref1 and second reference voltage Vref2 are used as the reference voltage Vref on the data line S (j ).
- the scanning line G1 (i) is maintained in an active state, and the monitor control line G2 (i) is in an inactive state. Accordingly, the transistor T1 is maintained in the on state, and the transistor T3 is in the off state.
- the voltage Vblack corresponding to black display is applied to the data line S (j), so that the transistor T2 is turned off. Thus, no current flows through the transistor T2.
- Applied to the monitor line M (j) is a sum of the light emission voltage equivalent voltage (second value) calculated from the gain value obtained and the gain value obtained in the TFT characteristic detection period Ta. Is done. Thereby, a voltage corresponding to the degree of deterioration of the organic EL element OLED is applied to the monitor line M (j) before the light emission period Tc, and the length of the charging time in the light emission period Tc is shortened.
- the scanning line G1 (i) is in an inactive state
- the monitor control line G2 (i) is in an active state.
- the transistor T2 since writing based on the voltage Vblack corresponding to black display is performed in the black writing period Tb before the light emission period Tc, the transistor T2 is in an off state.
- the monitor line M (j) is connected to the voltage measuring unit 39, and a constant current is supplied to the monitor line M (j).
- a data current that is a constant current is supplied from the monitor line M (j) to the organic EL element OLED as indicated by an arrow 73 in FIG.
- the voltage measuring unit 39 measures the light emission voltage of the organic EL element OLED.
- the OLED characteristic is detected by measuring the voltage of the anode of the organic EL element OLED in a state where a constant current is applied to the organic EL element OLED.
- the data current supplied to the organic EL element OLED in the light emission period Tc is a constant current.
- the length of time during which the organic EL element OLED emits light is adjusted.
- the constant current is set to a current corresponding to white display, the light emission time is lengthened as the gradation is higher, and the light emission time is shortened as the gradation is lower.
- the period Tc1 in which the monitor line M is connected to the voltage measuring unit 39 is lengthened as the gray level is higher, and the monitor line M is more current as the gray level is lower.
- the period Tc2 connected to the measurement unit 38 is lengthened.
- the lengths of the periods Tc1 and Tc2 are adjusted based on the deterioration correction coefficient obtained from the difference between the gain value stored in the gain memory 52 and the gain value obtained in the TFT characteristic detection period Ta. .
- the length of time that the organic EL element OLED emits light is adjusted so that the integrated value of the light emission current in one frame period becomes a value corresponding to a desired gradation. In other words, the length of time for applying a constant current to the organic EL element OLED is adjusted according to the target luminance.
- the current value is changed during the light emission period Tc, and characteristics (current-voltage) at a plurality of operating points are changed. (Characteristic) may be measured.
- the current value may be changed according to the gradation while the length of time during which the organic EL element OLED emits light is constant.
- the magnitude of the current supplied to the monitor line M is obtained based on the deterioration correction coefficient obtained from the difference between the gain value stored in the gain memory 52 and the gain value obtained in the TFT characteristic detection period Ta. And good. Since the gain memory 52 stores gain values considering both TFT characteristics and OLED characteristics, the gain value stored in the gain memory 52 and the gain value obtained in the TFT characteristic detection period Ta are The difference is a value representing the OLED characteristic.
- the length of the selection period is longer in the monitor row than in the non-monitor row. Therefore, the length of the light emission period is different between the monitor row and the non-monitor row. Therefore, the data current is adjusted so that the integrated value of the light emission current in one frame period becomes a value corresponding to a desired gradation.
- the OLED characteristic is not detected for pixels that display black or substantially black in a pixel matrix of n rows ⁇ m columns. Thereby, unnecessary light emission can be prevented. Since the organic EL element OLED does not deteriorate if it does not emit light, it is not necessary to detect the characteristics.
- FIG. 18 is a flowchart for explaining a procedure for updating the offset memory 51 and the gain memory 52. Here, attention is paid to an offset value and a gain value corresponding to one pixel.
- step S110 detection of TFT characteristics based on the first reference voltage Vref1 is performed (step S110).
- step S110 an offset value for correcting the video signal is obtained.
- the offset value obtained in step S110 is stored in the offset value buffer (step S120).
- step S130 the TFT characteristic is detected based on the second reference voltage Vref2 (step S130).
- step S130 a gain value for correcting the video signal is obtained.
- the gain value obtained in step S130 is stored in the gain value buffer (step S140).
- step S150 OLED characteristics are detected during the light emission period Tc (step S150).
- step S150 an offset value and a deterioration correction coefficient for correcting the video signal are obtained.
- step S160 the sum of the offset value stored in the offset value buffer and the offset value obtained in step S150 is stored in the offset memory 51 as a new offset value (step S160).
- step S170 the product of the gain value stored in the gain value buffer and the deterioration correction coefficient obtained in step S150 is stored in the gain memory 52 as a new gain value (step S170).
- the offset value and gain value corresponding to one pixel are updated.
- m offset values in the offset memory 51 and m gain values in the gain memory 52 per frame Is updated.
- the characteristic data is realized by data (offset value, gain value, deterioration correction coefficient) obtained based on the detection results in step S110, step S130, and step S150.
- the light emission voltage of the organic EL element OLED is measured during the light emission period Tc.
- the greater the detected voltage as the measurement result the greater the degree of deterioration of the organic EL element OLED. Therefore, the offset memory 51 and the gain memory 52 are updated so that the offset value increases and the gain value increases as the detection voltage increases.
- FIG. 19 is a diagram illustrating a configuration of the video signal correction unit.
- the video signal correction unit includes an LUT 211, a multiplication unit 212, and an addition unit 213. In such a configuration, the value of the video signal corresponding to each pixel is corrected as follows.
- gamma correction is performed on the video signal sent from the outside using the LUT 211. That is, the gradation P indicated by the video signal is converted to the control voltage Vc by gamma correction.
- the multiplier 212 receives the control voltage Vc and the gain value B read from the gain memory 52, and outputs a value “Vc ⁇ B” obtained by multiplying them.
- the adder 213 receives the value “Vc ⁇ B” output from the multiplier 212 and the offset value Vt read from the offset memory 51, and outputs the value “Vc ⁇ B + Vt” obtained by adding them. To do.
- the value “Vc ⁇ B + Vt” obtained as described above is sent from the control circuit 20 to the source driver 30 as the data signal DA.
- FIG. 1 is a flowchart for explaining an outline of operations related to detection of TFT characteristics and OLED characteristics.
- the TFT characteristic is detected during the TFT characteristic detection period Ta (step S10).
- the OLED characteristic is detected during the light emission period Tc (step S20).
- the offset memory 51 and the gain memory 52 are updated using the detection results in step S10 and step S20.
- the correction of the video signal sent from the outside is performed using the correction data stored in the offset memory 51 and the gain memory 52 (step S40).
- the first characteristic detection step is realized by step S10
- the second characteristic detection step is realized by step S20
- the correction data storage step is realized by step S30
- the video signal is obtained by step S40.
- a correction step is realized.
- the first characteristic detection process is realized by the process of step S10
- the second characteristic detection process is realized by the process of step S20.
- TFT characteristic detection period Ta the TFT characteristic detection period
- OLED characteristic detection period the OLED characteristic is detected during the light emission period.
- the video signal sent from the outside is corrected using correction data (offset value and gain value) obtained in consideration of both the detection result of the TFT characteristic and the detection result of the OLED characteristic.
- the organic EL element OLED in each pixel circuit 11 Since the data voltage based on the video signal (the data signal DA) corrected in this manner is applied to the data line S, when the organic EL element OLED in each pixel circuit 11 is caused to emit light, A drive current having such a magnitude as to compensate for the deterioration of the organic EL element OLED is supplied to the organic EL element OLED (see FIG. 20).
- the detection of the OLED characteristic is performed during the light emission period as described above. Therefore, in order to detect TFT characteristics and OLED characteristics, the length of the light emission period does not become shorter than the conventional one.
- the organic EL display device it is possible to simultaneously compensate for both the deterioration of the driving transistor and the deterioration of the organic EL element OLED without causing special light emission when detecting characteristics. Become.
- an oxide TFT (specifically, IGZO-TFT) is employed for the transistors T1 to T3 in the pixel circuit 11, an effect of ensuring a sufficient S / N ratio is obtained. It is done. This will be described below.
- IGZO-TFT and LTPS (Low Temperature Polysilicon) -TFT are compared, IGZO-TFT has much smaller off current than LTPS-TFT.
- LTPS-TFT is adopted for the transistor T3 in the pixel circuit 11
- the off-current is about 1 pA at maximum.
- an IGZO-TFT is employed for the transistor T3 in the pixel circuit 11, the off-current is about 10 fA at maximum.
- the off current for 1000 rows is about 1 nA at the maximum when LTPS-TFT is adopted, and is about 10 pA at the maximum when IGZO-TFT is adopted.
- the detected current is about 10 to 100 nA in any case.
- the monitor line M is connected not only to the pixel circuit 11 in the monitor row but also to the pixel circuit 11 in the non-monitor row. Therefore, the S / N ratio of the monitor line M depends on the total leakage current of the transistors T3 in the non-monitor row. Specifically, the S / N ratio of the monitor line M is represented by “detection current / (leakage current ⁇ number of non-monitor rows)”.
- the S / N ratio is about 10 when the LTPS-TFT is employed, whereas the IGZO- When TFT is employed, the S / N ratio is about 1000.
- a sufficient S / N ratio can be ensured when performing current detection.
- FIG. 21 is a block diagram showing an overall configuration of an active matrix organic EL display device 2 according to a first modification of the first embodiment.
- a TFT offset memory 51a instead of the offset memory 51 and the gain memory 52 in the first embodiment, a TFT offset memory 51a, an OLED offset memory 51b, a TFT gain memory 52a, and an OLED gain memory 52b are provided. ing. That is, in this modification, each of the offset memory and the gain memory is divided into a memory used for compensating for the deterioration of the driving transistor and a memory used for compensating for the deterioration of the organic EL element OLED. .
- the TFT offset memory 51a stores an offset value based on the detection result of the TFT characteristics.
- the OLED offset memory 51b stores an offset value based on the detection result of the OLED characteristic.
- the TFT gain memory 52a stores a gain value based on the detection result of the TFT characteristics.
- the OLED gain memory 52b stores a deterioration correction coefficient based on the detection result of the OLED characteristic.
- FIG. 22 is a flowchart for explaining a procedure for updating the TFT offset memory 51a, the OLED offset memory 51b, the TFT gain memory 52a, and the OLED gain memory 52b.
- attention is paid to an offset value and a gain value corresponding to one pixel.
- step S210 detection of TFT characteristics based on the first reference voltage Vref1 is performed (step S210).
- step S210 an offset value for correcting the video signal is obtained.
- step S220 the offset value obtained in step S210 is stored in the TFT offset memory 51a as a new offset value (step S220).
- step S230 the TFT characteristic is detected based on the second reference voltage Vref2 (step S230).
- step S230 a gain value for correcting the video signal is obtained.
- the gain value obtained in step S230 is stored in the TFT gain memory 52a as a new gain value (step S240).
- step S250 an offset value and a deterioration correction coefficient for correcting the video signal are obtained.
- the offset value obtained in step S250 is stored in the OLED offset memory 51b as a new offset value (step S260).
- the deterioration correction coefficient obtained in step S250 is stored in the OLED gain memory 52b as a new deterioration correction coefficient (step S270).
- the offset memory and the gain memory are updated as described above.
- t_charge Cmp ⁇ Vd / i_L (1)
- Vd 3 V
- i_L 10 nA
- Cmp 30 pF
- the time t_charge required for charging is 9 milliseconds.
- the driving frequency is 60 Hz
- the “offset value stored in the OLED offset memory 51b” and the “deterioration correction coefficient stored in the OLED gain memory 52b” are calculated during the black writing period Tb. A sum of the voltage corresponding to the light emission voltage is applied to the monitor line M.
- the monitor line M is charged in advance so that the potential of the monitor line M becomes a potential close to the light emission threshold value of the organic EL element OLED.
- Vd of the above formula (1) becomes small and the time required for charging is shortened.
- the current supplied from the monitor line M to the organic EL element OLED in the light emission period Tc is stored in the OLED gain memory 52b. It is adjusted based on the coefficient. That is, since the current is adjusted according to the degree of deterioration of the organic EL element OLED, a decrease in current efficiency is compensated. In the normal operation in the non-monitoring row, compensation is performed in consideration of both the deterioration of the driving transistor and the deterioration of the organic EL element OLED.
- each of the offset memory and the gain memory is divided into a memory used for compensating for the deterioration of the driving transistor and a memory used for compensating for the deterioration of the organic EL element OLED. .
- the monitor line M is connected to either the current measuring unit 38 or the voltage measuring unit 39 as shown in FIG.
- the present invention is not limited to this, and a configuration (configuration of the present modification) that can put the monitor line M in a high impedance state can also be adopted.
- FIG. 24 is a diagram showing a configuration in the vicinity of one end of the monitor line M in the present modification.
- the monitor line M is connected to the current measuring unit 38, connected to the voltage measuring unit 39, or is in a high impedance state by the switching control signal SW.
- the switching control signal SW is one of them.
- the monitor line M can be brought into a high impedance state.
- the first embodiment has been described on the assumption that one monitor circuit 322 including the current measurement unit 38 and the voltage measurement unit 39 is provided for each column.
- the present invention is not limited to this, and a configuration in which one monitor circuit 322 is shared by a plurality of columns (configuration of this modification) can also be adopted.
- the monitor line M is connected to the current measurement unit 38, connected to the voltage measurement unit 39, or in a high impedance state. It will be either.
- the vicinity of one end of the monitor line M has the configuration shown in FIG. That is, one monitor circuit 322 is provided for every K monitor lines M.
- the monitor lines M in the columns other than the characteristic detection target column are maintained in a high impedance state.
- the reference voltage Vref not the reference voltage
- a normal data voltage voltage corresponding to the target luminance
- the monitor line M is in a high impedance state, so that in the columns other than the characteristic detection target column, current flows through the monitor line M. No current flows to the organic EL element OLED, in normal operation as well as the organic EL element OLED emits light. Monitored characteristic detection target string of the rows, the above-described characteristic detection operation is performed.
- one monitor circuit 322 is provided for every 100 monitor lines M. It ’s fine.
- both the deterioration of the drive transistor and the deterioration of the organic EL element OLED are not caused to emit special light during characteristic detection. It is possible to compensate at the same time.
- a monitor row storage unit 201 for storing a monitor row is provided in the control circuit 20, as shown in FIG.
- the monitor row storage unit 201 when the power is turned off, information for specifying the row in which the TFT characteristic and the OLED characteristic are finally detected is stored in the monitor row storage unit 201.
- a monitor area storing step is realized by this processing. After the power is turned on, the TFT characteristic and the OLED characteristic are detected from the line next to the line specified based on the information stored in the monitor line storage unit 201.
- a monitor area storage unit is realized by the monitor row storage unit 201.
- the row where the TFT characteristic and the OLED characteristic are first detected after the power is turned on is not limited to the row next to the row specified based on the information stored in the monitor row storage unit 201.
- a row in the vicinity of a row specified based on information stored in the storage unit 201 may be used.
- information for specifying the column in which the TFT characteristic and the OLED characteristic are finally detected may be stored, and both the row and the column in which the TFT characteristic and the OLED characteristic are finally detected are specified.
- Information to be stored may be stored.
- FIG. 27 is a diagram for explaining the temperature dependence of the current-voltage characteristics of the organic EL element.
- FIG. 27 shows the current-voltage characteristics of the organic EL element at the temperature TE1, the current-voltage characteristics of the organic EL element at the temperature TE2, and the current-voltage characteristics of the organic EL element at the temperature TE3.
- TE1>TE2> TE3 As can be understood from FIG. 27, in order to supply a predetermined current to the organic EL element, it is necessary to increase the voltage as the temperature decreases. As described above, the current-voltage characteristic of the organic EL element greatly depends on the temperature. Therefore, it is preferable to employ a configuration that can compensate for temperature changes (the configuration of this modification).
- FIG. 28 is a block diagram showing the overall configuration of the organic EL display device 4 in the present modification.
- a temperature sensor 60 is provided in addition to the components in the first embodiment.
- the control circuit 20 is provided with a temperature change compensation unit 202.
- the temperature sensor 60 gives temperature information TE, which is a result of measuring the temperature, to the control circuit 20 as needed.
- the temperature change compensation unit 202 corrects the monitor data MO given from the source driver 30 based on the temperature information TE.
- the temperature change compensator 202 converts the value of the monitor data MO corresponding to the temperature at the time of detection into a value corresponding to a certain standard temperature, and stores the value in the offset memory 51 based on the value obtained by the conversion.
- the offset value and the gain value in the gain memory 52 are updated.
- the temperature detection step is realized by the process of the temperature sensor 60
- the temperature change compensation step is realized by the process of the temperature change compensation unit 202.
- FIG. 29 is a flowchart for explaining a procedure for updating the offset memory 51 and the gain memory 52 in the present modification.
- the processing in steps S310 to S350 in the present modification (FIG. 29) is the same as the processing in steps S110 to S150 in the first embodiment (FIG. 18), and the steps in this modification (FIG. 29).
- the processing from S360 to S370 is the same as the processing from S160 to S170 in the first embodiment (FIG. 18).
- the offset value and the gain value are corrected based on the temperature information TE given by the temperature sensor 60. Is applied (step S355).
- the video signal sent from the outside is corrected by the correction data (offset value and gain value) considering the temperature change. Therefore, in the organic EL display device, it is possible to simultaneously compensate for both the deterioration of the drive transistor and the deterioration of the organic EL element OLED regardless of the temperature change.
- the OLED characteristic is detected by measuring the voltage of the anode of the organic EL element OLED in a state where a constant current is applied to the organic EL element OLED.
- the present invention is not limited to this, and the configuration in which the OLED characteristic is detected by measuring the current flowing through the organic EL element OLED in a state where a constant voltage is applied to the organic EL element OLED (in this modification example). Configuration).
- FIG. 30 is a diagram showing a detailed configuration of the monitor circuit 323 in the present modification.
- the monitor circuit 323 includes an operational amplifier 3231, a capacitor 3232, a first switch 3233, a second switch 3234, an offset / amplification rate adjustment unit 3235, and an A / D converter 3236.
- the operational amplifier 3231 the non-inverting input terminal is connected to the second switch 3234 and the inverting input terminal is connected to the monitor line M.
- the capacitor 3232 and the first switch 3233 are provided between the output terminal of the operational amplifier 3231 and the monitor line M.
- the offset / amplification factor adjustment unit 3235 is provided between the output terminal of the operational amplifier 3231 and the A / D converter 3236.
- the second switch 3234 functions as a switch for switching the potential of the non-inverting input terminal of the operational amplifier 3231 between the potential of the low-level power supply line ELVSS and the potential Vel for detecting OLED characteristics.
- the monitor circuit 323 is composed of an integration circuit.
- the potential Vel for detecting the OLED characteristics is “the difference between the offset value stored in the offset memory 51 and the offset value obtained in the TFT characteristic detection period Ta” (first value) and “in the gain memory 52. This is a potential corresponding to the sum of the voltage corresponding to the light emission voltage (second value) calculated from the stored gain value and the gain value obtained in the TFT characteristic detection period Ta.
- the potential of the non-inverting input terminal of the operational amplifier 3231 is set to the potential of the low-level power supply line ELVSS by the second control clock signal Sclk2. In this state, the same operation as in the first embodiment is performed.
- the potential of the non-inverting input terminal of the operational amplifier 3231 is set to the potential Vel for detecting the OLED characteristic by the second control clock signal Sclk2.
- the first switch 3233 is turned on by the control clock signal Sclk1.
- the output terminal and the inverting input terminal of the operational amplifier 3231 are short-circuited, and the potential of the monitor line M becomes equal to the potential Vel for detecting OLED characteristics.
- the first switch 3233 is turned off by the first control clock signal Sclk1.
- the potential of the output terminal of the operational amplifier 3231 changes according to the magnitude of the current flowing through the monitor line M (source current supplied to the organic EL element OLED).
- the change in potential is reflected in the digital signal output from the A / D converter 3236.
- the digital signal is output from the monitor circuit 323 as monitor data MO.
- the offset / amplification factor adjustment unit 3235 has a function of making the input level to the A / D converter 3236 the same when detecting TFT characteristics and when detecting OLED characteristics.
- the OLED characteristic is detected by measuring the current flowing through the organic EL element OLED in a state where a constant voltage is applied to the organic EL element OLED as described above. Thereby, the measurement time can be shortened.
- the magnitude of the constant voltage applied to the organic EL element OLED is based on a deterioration correction coefficient obtained from the difference between the gain value stored in the gain memory 52 and the gain value obtained in the TFT characteristic detection period Ta. It is good to ask.
- a TFT offset memory 51a, an OLED offset memory 51b, a TFT gain memory 52a, and an OLED gain memory 52b are provided (first modified example)
- the OLED characteristics when detecting the OLED characteristics, it is preferable to adjust the length of time for which a constant voltage is applied to the organic EL element OLED according to the target luminance. Further, if the integrated value of the light emission current in one frame period becomes a value corresponding to a desired gradation, the voltage value is changed during the light emission period Tc, and the characteristics (current-voltage) at a plurality of operating points are changed. (Characteristic) may be measured.
- FIG. 31 is a block diagram showing the overall configuration of an active matrix organic EL display device 5 according to the second embodiment of the present invention.
- the display unit 10a includes m data lines S (1) to S (m) and m monitor lines M (1) to M (m), n.
- n scanning lines G1 (1) to G1 (n) and n monitor control lines G2 (1) to G2 (n) n high level power supply control lines G3 (1) to G3 (n) Is provided.
- the scanning lines G1 (1) to G1 (n), the monitor control lines G2 (1) to G2 (n), and the high level power supply control lines G3 (1) to G3 (n) are parallel to each other.
- the high-level power supply control line is simply denoted by reference numeral G3. Since the control circuit 20 and the source driver 30 are the same as those in the first embodiment, description thereof will be omitted.
- the gate driver 40a includes n scanning lines G1 (1) to G1 (n), n monitor control lines G2 (1) to G2 (n), and n high-level power supply control lines G3. (1) to G3 (n) are connected.
- the gate driver 40a is configured by a shift register, a logic circuit, and the like.
- a row in which TFT characteristic detection or OLED characteristic detection is performed is referred to as a “monitor row”.
- a frame in which the TFT characteristic is detected is referred to as a “TFT characteristic detection frame”
- a frame in which the OLED characteristic is detected is referred to as an “OLED characteristic detection frame”.
- the OLED characteristic when the OLED characteristic is detected for the first line in a certain frame, the OLED characteristic is detected for the second line in the next frame, and further, three lines are detected in the next frame. Detection of OLED characteristics for the eyes is performed. Thereafter, detection of OLED characteristics for the fourth to nth rows is sequentially performed. After the OLED characteristic is detected for the nth row, the TFT characteristic is detected for the first row. Then, detection of TFT characteristics for the second to nth rows is sequentially performed. As described above, the detection of TFT characteristics and the detection of OLED characteristics are performed in different frames. However, the gate driver 40a similarly drives the scanning line G1, the monitor control line G2, and the high level power supply control line G3 in the TFT characteristic detection frame and the OLED characteristic detection frame.
- n scanning lines G1 (1) to G1 (n), n monitoring control lines G2 (1 ) To G2 (n) and n high-level power supply control lines G3 (1) to G3 (n) are driven as shown in FIG. 32 in the (k + 1) th frame, and in the (k + 2) th frame. It is driven as shown in FIG. 33, and it is driven as shown in FIG. 34 at the (k + n) th frame.
- the length of the selection period (period in which the scanning line G1 is in an active state) is the same in all the rows. That is, in the present embodiment, the length of the selection period is constant regardless of whether or not it is a monitor row.
- the monitor control line G2 corresponding to the non-monitor row is maintained in an inactive state.
- the monitor control line G2 corresponding to the monitor row is in an active state from the start of the selection period until the lapse of one frame period.
- the high-level power supply control line G3 corresponding to the non-monitor row is maintained in an active state.
- the high-level power supply control line G3 corresponding to the monitor row is in an inactive state from the start of the selection period until the lapse of one frame period.
- n scanning lines G1 (1) to G1 (n) n monitor control lines G2 (1) to G2 (n), and n high level power supply control lines.
- the gate driver 40a is configured so that G3 (1) to G3 (n) are driven.
- each of the offset memory and the gain memory includes a memory used for compensating for the deterioration of the drive transistor and the organic EL element OLED. It is divided into memory used to compensate for deterioration. That is, the organic EL display device 5 includes TFT offset memory 51a, OLED offset memory 51b, and TFT gain memory as components for storing correction data used for correcting an externally transmitted video signal. 52a and an OLED gain memory 52b are provided.
- FIG. 35 is a diagram showing the configuration of the pixel circuit 11a and the monitor circuit 322 in the present embodiment. Note that the pixel circuit 11a illustrated in FIG. 35 is the pixel circuit 11 of i rows and j columns. Since the configuration of the monitor circuit 322 is the same as that of the first embodiment, description thereof is omitted. However, in the present embodiment, when the monitor line M is connected to the current measuring unit 38, the high-level power supply voltage ELVDD is supplied to the monitor line M.
- the pixel circuit 11a includes one organic EL element OLED, four transistors T1 to T4, and one capacitor Cst.
- the transistor T1 functions as an input transistor for selecting a pixel
- the transistor T2 functions as a drive transistor for controlling supply of current to the organic EL element OLED
- the transistor T3 controls whether to detect TFT characteristics or OLED characteristics.
- the transistor T4 functions as a high-level power supply control transistor that controls the supply of drive current from the high-level power supply line ELVDD.
- the transistor T1 is provided between the data line S (j) and the gate terminal of the transistor T2.
- a gate terminal is connected to the scanning line G1 (i), and a source terminal is connected to the data line S (j).
- the transistor T2 is provided in series with the organic EL element OLED.
- the gate terminal is connected to the drain terminal of the transistor T1
- the drain terminal is connected to the source terminal of the transistor T4, and the source terminal is connected to the anode terminal of the organic EL element OLED.
- the gate terminal is connected to the monitor control line G2 (i)
- the drain terminal is connected to the drain terminal of the transistor T2
- the source terminal is connected to the monitor line M (j).
- the transistor T4 is provided in series with the organic EL element OLED.
- the gate terminal is connected to the high-level power supply control line G3 (i)
- the drain terminal is connected to the high-level power supply line ELVDD
- the source terminal is connected to the drain terminal of the transistor T2.
- the capacitor Cst one end is connected to the gate terminal of the transistor T2, and the other end is connected to the source terminal of the transistor T2.
- the cathode terminal of the organic EL element OLED is connected to the low level power line ELVSS.
- oxide TFTs thin film transistors using an oxide semiconductor as a channel layer
- the present invention does not exclude the use of transistors other than oxide TFTs.
- TFT characteristic detection operation an operation for detecting TFT characteristics
- OLED characteristic detection operation an operation for detecting OLED characteristics
- the TFT characteristic detection operation is not performed in any row from the (k + 1) th frame to the (k + n) th frame. Also, the OLED characteristic detection operation is not performed in any row from the (k + n + 1) th frame to the (k + 2n) th frame.
- FIG. 38 is a timing chart for explaining an OLED characteristic detection operation in a pixel circuit 11a (referred to as a pixel circuit 11a of i rows and j columns) included in a monitor row.
- “one frame period” is expressed with reference to the selection period start point of the i-th row in a frame in which the i-th row is a monitor row.
- one frame period includes a selection period Tp and a light emission period Tq.
- the scanning line G1 (i) and the monitor control line G2 (i) are activated. Accordingly, the transistor T1 and the transistor T3 are turned on.
- the high-level power supply control line G3 (i) is inactive. As a result, the transistor T4 is turned off.
- the high voltage Vlen for causing the transistor T2 to operate linearly is applied to the data line S (j) in the selection period Tp. Thereby, writing based on the high voltage Vlen is performed, and the transistor T2 is turned on.
- the scanning line G1 (i) is inactive. As a result, the transistor T1 is turned off.
- the monitor control line G2 (i) is maintained in an active state, and the high level power supply control line G3 (i) is maintained in an inactive state. Thereby, the transistor T3 is maintained in the on state, and the transistor T4 is maintained in the off state.
- the transistor T2 since writing based on the high voltage Vlen is performed in the selection period Tp before the light emission period Tq, the transistor T2 is in an on state.
- the monitor line M (j) is connected to the voltage measuring unit 39, and a constant current is supplied to the monitor line M (j).
- a data current which is a constant current, is supplied from the monitor line M (j) to the organic EL element OLED as indicated by an arrow indicated by reference numeral 75 in FIG.
- the voltage measuring unit 39 measures the light emission voltage of the organic EL element OLED.
- the process of adjusting the length of the light emission time of the organic EL element OLED and the process of changing the current value according to the gradation are performed in the same manner as in the first embodiment so that a desired gradation display is performed. Done.
- FIG. 40 is a timing chart for explaining a TFT characteristic detection operation in a pixel circuit 11a (referred to as a pixel circuit 11a of i rows and j columns) included in a monitor row.
- the scanning line G1 (i) and the monitor control line G2 (i) are activated. Accordingly, the transistor T1 and the transistor T3 are turned on.
- the high-level power supply control line G3 (i) is inactive. As a result, the transistor T4 is turned off.
- the same data voltage as that in the normal operation is applied to the data line S (j).
- the transistor T2 is turned on by writing based on the data voltage.
- the scanning line G1 (i) is inactive. As a result, the transistor T1 is turned off.
- the monitor control line G2 (i) is maintained in an active state, and the high level power supply control line G3 (i) is maintained in an inactive state. Thereby, the transistor T3 is maintained in the on state, and the transistor T4 is maintained in the off state.
- the transistor T2 since writing based on the data voltage is performed in the selection period Tp before the light emission period Tq, the transistor T2 is in the on state.
- the monitor line M (j) is connected to the current measuring unit 38 by the switching control signal SW.
- the potential of the monitor line M (j) is the potential of the high-level power supply line ELVDD
- a drive current corresponding to the data voltage is applied to the monitor line M (j) as indicated by an arrow 76 in FIG.
- the current measuring unit 38 measures the current supplied from the monitor line M (j) to the organic EL element OLED. As described above, the TFT characteristics are detected.
- FIG. 42 is a flowchart for explaining a procedure for updating the TFT offset memory 51a, the OLED offset memory 51b, the TFT gain memory 52a, and the OLED gain memory 52b.
- attention is paid to an offset value and a gain value corresponding to one pixel.
- the detection of the TFT characteristics is performed after n frames of the frame in which the detection of the OLED characteristics is performed. Therefore, here, it is assumed that the OLED characteristic is detected in the K frame and the TFT characteristic is detected in the (K + n) frame.
- step S410 the OLED characteristic is detected during the light emission period Tq (step S410).
- step S410 an offset value and a deterioration correction coefficient for correcting the video signal are obtained.
- step S420 the offset value obtained in step S410 is stored in the OLED offset memory 51b as a new offset value (step S420).
- step S420 the deterioration correction coefficient obtained in step S410 is stored in the OLED gain memory 52b as a new deterioration correction coefficient (step S430).
- step S440 the TFT characteristic is detected during the light emission period Tq (step S440).
- step S440 an offset value and a gain value for correcting the video signal are obtained.
- step S440 is stored as a new offset value in the TFT offset memory 51a (step S450).
- step S460 the gain value obtained in step S440 is stored in the TFT gain memory 52a as a new gain value (step S460).
- the offset value and gain value corresponding to one pixel are updated.
- each frame is subjected to either OLED characteristic detection for one row or TFT characteristic detection for one row. Therefore, in the frame where the OLED characteristic is detected, m offset values in the OLED offset memory 51b and m deterioration correction coefficients in the OLED gain memory 52b are updated per frame, and the TFT characteristics are updated. In a frame in which detection is performed, m offset values in the TFT offset memory 51a and m gain values in the TFT gain memory 52a are updated per frame.
- the gain value B given to the multiplier 212 shown in FIG. 19 and the offset value Vt given to the adder 213 shown in FIG. 19 are different from those of the first embodiment.
- the product of the value read from the TFT gain memory 52a and the value read from the OLED gain memory 52b is given to the multiplier 212 as a gain value B, and the value read from the TFT offset memory 51a The sum with the value read from the OLED offset memory 51b is given to the adder 213 as the offset value Vt.
- the gradation P indicated by the video signal is corrected to “Vc ⁇ B + Vt”.
- Vc is the value of the control voltage after the gamma correction of the gradation P.
- both the detection of the OLED characteristic and the detection of the TFT characteristic are performed during the light emission period. For this reason, unlike the configuration in which the detection of these characteristics is performed during the selection period, it is not necessary to lengthen the monitoring row selection period. Therefore, a sufficiently long light emission period is ensured. Further, variation in the length of the selection period depending on the row is prevented.
- both the deterioration of the drive transistor and the deterioration of the organic EL element OLED are ensured while sufficiently securing the light emission period without causing variations in the length of the selection period. Can be compensated at the same time without causing special light emission during characteristic detection.
- the buffer (offset value buffer and gain value) is used as in the first embodiment.
- the offset memory and the gain memory are updated using the buffer. That is, in the second embodiment, the TFT offset memory 51a, the OLED offset memory 51b, the TFT gain memory 52a, and the OLED gain memory 52b are used to store correction data used for correcting the video signal.
- the organic EL display device to which the present invention is applicable is not limited to the one provided with the pixel circuits 11 and 11a exemplified in each embodiment and each modification.
- the pixel circuit includes at least an electro-optical element (organic EL element OLED) controlled by current, transistors T1 to T3, and a capacitor Cst, the pixel circuit has a configuration other than the configuration exemplified in each embodiment and each modification. There may be.
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Abstract
Description
前記駆動トランジスタの特性を検出する第1の特性検出ステップと、
前記電気光学素子の特性を検出する第2の特性検出ステップと、
前記第1の特性検出ステップでの検出結果および前記第2の特性検出ステップでの検出結果に基づいて得られる特性データを、映像信号を補正するための補正データとして、予め用意された補正データ記憶部に記憶させる補正データ記憶ステップと、
前記補正データ記憶部に記憶されている補正データに基づいて前記映像信号を補正して、前記n×m個の画素回路に供給すべきデータ信号を生成する映像信号補正ステップと
を含み、
1フレーム期間は、前記電気光学素子を発光させる準備が行われる選択期間と前記電気光学素子の発光が行われる発光期間とからなり、
前記第1の特性検出ステップおよび前記第2の特性検出ステップの一方または双方の処理が、1フレーム期間につき前記画素マトリクスの1つの行のみで行われ、
前記第2の特性検出ステップの処理は、前記発光期間に行われることを特徴とする。
前記第1の特性検出ステップおよび前記第2の特性検出ステップの双方の処理が、1フレーム期間につき前記画素マトリクスの1つの行のみで行われ、
各フレームにおいて前記第1の特性検出ステップおよび前記第2の特性検出ステップの双方の処理が行われる行をモニタ行と定義し、前記モニタ行以外の行を非モニタ行と定義したとき、前記モニタ行についての前記選択期間の長さは、前記非モニタ行についての前記選択期間の長さよりも長くなっていて、
前記第1の特性検出ステップの処理は、前記選択期間に行われることを特徴とする。
前記第1の特性検出ステップおよび前記第2の特性検出ステップの一方の処理が、1フレーム期間につき前記画素マトリクスの1つの行のみで行われ、
前記画素マトリクスの1つの行に着目したとき、前記第1の特性検出ステップの処理と前記第2の特性検出ステップの処理とは交互に行われ、
前記第1の特性検出ステップの処理は、前記発光期間に行われることを特徴とする。
前記第2の特性検出ステップでは、前記電気光学素子に一定の電流が与えられた状態で前記電気光学素子の陽極の電圧を測定することによって、前記電気光学素子の特性が検出されることを特徴とする。
前記第2の特性検出ステップでは、目標輝度に応じて、前記一定の電流を前記電気光学素子に与える時間の長さが調整されることを特徴とする。
前記第2の特性検出ステップでは、1フレーム期間での発光電流の積分値が目標階調に相当する値となる範囲内で複数レベルの前記一定の電流が前記電気光学素子に与えられることによって、前記電気光学素子の特性として複数の特性が検出されることを特徴とする。
前記第2の特性検出ステップでは、前記電気光学素子に一定の電圧が与えられた状態で前記電気光学素子に流れる電流を測定することによって、前記電気光学素子の特性が検出されることを特徴とする。
前記第2の特性検出ステップでは、目標輝度に応じて、前記一定の電圧を前記電気光学素子に与える時間の長さが調整されることを特徴とする。
前記第2の特性検出ステップでは、1フレーム期間での発光電流の積分値が目標階調に相当する値となる範囲内で複数レベルの前記一定の電圧が前記電気光学素子に与えられることによって、前記電気光学素子の特性として複数の特性が検出されることを特徴とする。
前記第1の特性検出ステップでは、前記駆動トランジスタのゲート-ソース間の電圧を所定の大きさにした状態で前記駆動トランジスタのドレイン-ソース間を流れる電流を測定することによって、前記駆動トランジスタの特性が検出されることを特徴とする。
前記補正データ記憶部は、前記補正データとしてオフセット値を記憶するオフセット値記憶部と前記補正データとしてゲイン値を記憶するゲイン値記憶部とからなり、
前記補正データ記憶ステップでは、
前記第1の特性検出ステップでの検出結果に基づいて得られるオフセット値と前記第2の特性検出ステップでの検出結果に基づいて得られるオフセット値との和が、新たなオフセット値として前記オフセット値記憶部に記憶され、
前記第1の特性検出ステップでの検出結果に基づいて得られるゲイン値と前記第2の特性検出ステップでの検出結果に基づいて得られる補正係数との積が、新たなゲイン値として前記ゲイン値記憶部に記憶されることを特徴とする。
前記表示装置は、
前記駆動トランジスタの特性および前記電気光学素子の特性を検出するための特性検出部と、
前記画素マトリクスの各列に対応するように設けられ、前記特性検出部および対応する列の画素回路と電気的に接続され得るように構成されたm本のモニタ線と
を更に有し、
前記選択期間は、前記第1の特性検出ステップの処理が行われる第1期間と前記第1期間に続く第2期間とからなり、
前記オフセット値記憶部に記憶されているオフセット値と前記第1の特性検出ステップでの検出結果に基づいて得られるオフセット値との差分の値を第1の値と定義し、前記ゲイン値記憶部に記憶されているゲイン値と前記第1の特性検出ステップでの検出結果に基づいて得られるゲイン値とに基づいて得られる値を第2の値と定義したとき、前記第2期間には、各モニタ線に、前記第1の値と前記第2の値との和に相当する電圧が印加されることを特徴とする。
前記補正データ記憶部は、前記補正データとして前記駆動トランジスタに対応するオフセット値を記憶する駆動トランジスタ用オフセット値記憶部,前記補正データとして前記電気光学素子に対応するオフセット値を記憶する電気光学素子用オフセット値記憶部,前記補正データとして前記駆動トランジスタに対応するゲイン値を記憶する駆動トランジスタ用ゲイン値記憶部,および前記補正データとして前記電気光学素子に対応するゲイン値を記憶する電気光学素子用ゲイン値記憶部からなり、
前記補正データ記憶ステップでは、
前記第1の特性検出ステップでの検出結果に基づいて得られるオフセット値が、新たなオフセット値として前記駆動トランジスタ用オフセット値記憶部に記憶され、
前記第1の特性検出ステップでの検出結果に基づいて得られるゲイン値が、新たなゲイン値として前記駆動トランジスタ用ゲイン値記憶部に記憶され、
前記第2の特性検出ステップでの検出結果に基づいて得られるオフセット値が、新たなオフセット値として前記電気光学素子用オフセット値記憶部に記憶され、
前記第2の特性検出ステップでの検出結果に基づいて得られる補正係数が、新たなゲイン値として前記電気光学素子用ゲイン値記憶部に記憶されることを特徴とする。
前記第2の特性検出ステップでは、前記電気光学素子に一定の電流が与えられた状態で前記電気光学素子の陽極の電圧を測定することによって、前記電気光学素子の特性が検出され、
前記一定の電流の大きさは、前記電気光学素子用ゲイン値記憶部に記憶されているゲイン値に応じて調整されることを特徴とする。
前記第2の特性検出ステップでは、前記電気光学素子に一定の電圧が与えられた状態で前記電気光学素子に流れる電流を測定することによって、前記電気光学素子の特性が検出され、
前記一定の電圧の大きさは、前記電気光学素子用ゲイン値記憶部に記憶されているゲイン値に応じて調整されることを特徴とする。
前記表示装置は、
前記駆動トランジスタの特性および前記電気光学素子の特性を検出するための特性検出部と、
前記画素マトリクスの各列に対応するように設けられ、前記特性検出部および対応する列の画素回路と電気的に接続され得るように構成されたm本のモニタ線と
を更に有し、
前記選択期間は、前記第1の特性検出ステップの処理が行われる第1期間と前記第1期間に続く第2期間とからなり、
前記第2期間には、各モニタ線に、前記電気光学素子用オフセット値記憶部に記憶されているオフセット値と前記電気光学素子用ゲイン値記憶部に記憶されているゲイン値に基づいて得られる値との和に相当する電圧が印加されることを特徴とする。
前記表示装置は、
電流を測定する電流測定部を少なくとも含み、前記駆動トランジスタの特性および前記電気光学素子の特性を検出するための特性検出部と、
前記画素マトリクスの各列に対応するように設けられ、前記特性検出部および対応する列の画素回路と電気的に接続され得るように構成されたm本のモニタ線と
を更に有し、
前記第1の特性検出ステップでは、前記m本のモニタ線が対応する画素回路および前記電流測定部と電気的に接続された状態で、前記駆動トランジスタのゲート-ソース間の電圧を所定の大きさにした状態で前記駆動トランジスタのドレイン-ソース間を流れる電流が前記電流測定部によって測定されることを特徴とする。
前記特性検出部は、電圧を測定する電圧測定部を更に含み、
前記第2の特性検出ステップでは、前記電気光学素子に一定の電流が与えられた状態で前記電気光学素子の陽極の電圧が前記電圧測定部によって測定されることを特徴とする。
前記第2の特性検出ステップでは、前記電気光学素子に一定の電圧が与えられた状態で前記電気光学素子に流れる電流が前記電流測定部によって測定されることを特徴とする。
前記特性検出部は、K本のモニタ線(Kは2以上m以下の整数)につき1つだけ設けられ、
各フレームにおいて、
前記K本のモニタ線のうちの1つが前記特性検出部と電気的に接続され、
前記特性検出部と電気的に接続されていないモニタ線は、ハイインピーダンスの状態にされていることを特徴とする。
前記n行×m列の画素マトリクスのうち黒色またはほぼ黒色の表示が行われる画素については、前記第2の特性検出ステップの処理が行われないことを特徴とする。
前記表示装置の電源オフの際に、最後に前記第1の特性検出ステップおよび前記第2の特性検出ステップの一方または双方の処理が行われた領域を特定する情報を予め用意されたモニタ領域記憶部に記憶するモニタ領域記憶ステップを更に含み、
前記表示装置の電源オン後には、前記モニタ領域記憶部に記憶されている情報に基づいて得られる領域近傍の領域から、前記第1の特性検出ステップおよび前記第2の特性検出ステップの一方または双方の処理が行われることを特徴とする。
温度を検出する温度検出ステップと、
前記特性データに対して前記温度検出ステップで検出された温度に基づく補正を施す温度変化補償ステップと
を更に含み、
前記補正データ記憶ステップでは、前記温度変化補償ステップの処理で得られたデータが前記補正データとして前記補正データ記憶部に記憶されることを特徴とする。
前記駆動トランジスタは、酸化物半導体によりチャネル層が形成された薄膜トランジスタであることを特徴とする。
前記酸化物半導体は、インジウム(In),ガリウム(Ga),亜鉛(Zn),および酸素(О)を主成分とする酸化インジウムガリウム亜鉛であることを特徴とする。
前記駆動トランジスタの特性を検出する第1の特性検出処理および前記電気光学素子の特性を検出する第2の特性検出処理を行いつつ前記n×m個の画素回路を駆動する画素回路駆動部と、
前記第1の特性検出処理での検出結果および前記第2の特性検出処理での検出結果に基づいて得られる特性データを、映像信号を補正するための補正データとして記憶する補正データ記憶部と、
前記補正データ記憶部に記憶されている補正データに基づいて前記映像信号を補正して、前記n×m個の画素回路に供給すべきデータ信号を生成する映像信号補正部と
を備え、
1フレーム期間は、前記電気光学素子を発光させる準備が行われる選択期間と前記電気光学素子の発光が行われる発光期間とからなり、
前記画素回路駆動部は、
前記第1の特性検出処理および前記第2の特性検出処理の一方または双方の処理を、1フレーム期間につき前記画素マトリクスの1つの行についてのみ行い、
前記第2の特性検出処理を前記発光期間に行うことを特徴とする。
<1.1 全体構成>
図2は、本発明の第1の実施形態に係るアクティブマトリクス型の有機EL表示装置1の全体構成を示すブロック図である。この有機EL表示装置1は、表示部10,コントロール回路20,ソースドライバ(データ線駆動回路)30,ゲートドライバ(走査線駆動回路)40,オフセットメモリ51,およびゲインメモリ52を備えている。なお、ソースドライバ30およびゲートドライバ40の一方または双方が表示部10と一体的に形成された構成であっても良い。また、オフセットメモリ51とゲインメモリ52とは物理的には1つのメモリで構成されていても良い。
図7は、画素回路11およびモニタ回路322の構成を示す図である。なお、図7に示す画素回路11は、i行j列の画素回路11である。この画素回路11は、1個の有機EL素子OLED,3個のトランジスタT1~T3,および1個のコンデンサCstを備えている。トランジスタT1は画素を選択する入力トランジスタとして機能し、トランジスタT2は有機EL素子OLEDへの電流の供給を制御する駆動トランジスタとして機能し、トランジスタT3はTFT特性やOLED特性を検出するか否かを制御するモニタ制御トランジスタとして機能する。
次に、本実施形態における駆動方法について説明する。上述したように、本実施形態においては、各フレームに1つの行のTFT特性およびOLED特性の検出が行われる。各フレームにおいて、モニタ行についてはTFT特性およびOLED特性の検出を行うための動作(以下、「特性検出動作」という。)が行われ、非モニタ行については通常動作が行われる。すなわち、1行目についてのTFT特性およびOLED特性の検出が行われるフレームを(k+1)フレーム目と定義すると、図10に示すように、各行の動作は推移する。また、TFT特性およびOLED特性の検出が行われると、その検出結果を用いて、オフセットメモリ51およびゲインメモリ52の更新が行われる。そして、オフセットメモリ51およびゲインメモリ52に記憶されている補正データを用いて映像信号の補正が行われる。
<1.3.1.1 通常動作>
各フレームにおいて、非モニタ行では、通常動作が行われる。非モニタ行に含まれる画素回路11では、目標輝度に対応するデータ電圧に基づく書き込みが選択期間に行われた後、トランジスタT1はオフ状態で維持される。データ電圧に基づく書き込みによってトランジスタT2はオン状態となる。トランジスタT3についてはオフ状態で維持される。以上より、図11で符号71で示す矢印のように、トランジスタT2を介して有機EL素子OLEDに駆動電流が供給される。これにより、駆動電流に応じた輝度で有機EL素子OLEDが発光する。
各フレームにおいて、モニタ行では、特性検出動作が行われる。図12は、モニタ行に含まれる画素回路11(i行j列の画素回路11とする)の動作を説明するためのタイミングチャートである。なお、図12では、i行目がモニタ行とされるフレームにおけるi行目の選択期間開始時点を基準にして「1フレーム期間」を表している。モニタ行については、図12に示すように、1フレーム期間には、TFT特性の検出を行うための期間(以下、「TFT特性検出期間」という。)Taと、黒色表示に相当するデータを書き込むための期間(以下、「黒書込期間」という。)Tbと、有機EL素子OLEDを発光させるための期間(以下、「発光期間」という。)Tcとが含まれている。選択期間のうちの最初の所定期間がTFT特性検出期間Taとなっていて、選択期間のうちのTFT特性検出期間Ta以外の期間が黒書込期間Tbとなっている。なお、本実施形態においては、TFT特性検出期間Taによって第1期間が実現され、黒書込期間Tbによって第2期間が実現されている。
次に、オフセットメモリ51に格納されているオフセット値およびゲインメモリ52に格納されているゲイン値がどのように更新されるかについて説明する。図18は、オフセットメモリ51およびゲインメモリ52の更新の手順を説明するためのフローチャートである。なお、ここでは1つの画素に対応するオフセット値およびゲイン値に着目する。
本実施形態においては、駆動トランジスタの劣化および有機EL素子OLEDの劣化を補償するために、オフセットメモリ51およびゲインメモリ52に格納されている補正データを用いて、外部から送られる映像信号の補正が行われる。以下、映像信号のこの補正について説明する。
図1は、TFT特性およびOLED特性の検出に関連する動作の概略を説明するためのフローチャートである。まず、モニタ行において、TFT特性検出期間TaにTFT特性の検出が行われる(ステップS10)。次に、モニタ行において、発光期間TcにOLED特性の検出が行われる(ステップS20)。その後、ステップS10およびステップS20での検出結果を用いて、オフセットメモリ51およびゲインメモリ52の更新が行われる。そして、オフセットメモリ51およびゲインメモリ52に格納されている補正データを用いて、外部から送られる映像信号の補正が行われる(ステップS40)。
本実施形態によれば、各フレームにおいて1つの行についてのTFT特性およびOLED特性の検出が行われる。モニタ行に着目すると、1フレーム期間において、選択期間中の一部の期間(TFT特性検出期間Ta)にTFT特性の検出が行われ、発光期間中にOLED特性の検出が行われる。そして、TFT特性の検出結果およびOLED特性の検出結果の双方を考慮して求められた補正データ(オフセット値およびゲイン値)を用いて、外部から送られる映像信号が補正される。このようにして補正された映像信号(上記データ信号DA)に基づくデータ電圧がデータ線Sに印加されるので、各画素回路11内の有機EL素子OLEDを発光させる際に、駆動トランジスタの劣化および有機EL素子OLEDの劣化が補償されるような大きさの駆動電流が有機EL素子OLEDに供給される(図20参照)。ここで、OLED特性の検出については、上述のように発光期間中に行われる。従って、TFT特性やOLED特性を検出するために発光期間の長さが従来よりも短くなることはない。以上のように、本実施形態によれば、有機EL表示装置において駆動トランジスタの劣化および有機EL素子OLEDの劣化の双方を特性検出の際に特別な発光をさせることなく同時に補償することが可能となる。
以下、上記第1の実施形態の変形例について説明する。なお、以下においては、第1の実施形態と異なる点についてのみ詳しく説明し、第1の実施形態と同様の点については説明を省略する。
図21は、第1の実施形態の第1の変形例に係るアクティブマトリクス型の有機EL表示装置2の全体構成を示すブロック図である。本変形例においては、第1の実施形態におけるオフセットメモリ51およびゲインメモリ52に代えて、TFT用オフセットメモリ51a,OLED用オフセットメモリ51b,TFT用ゲインメモリ52a,およびOLED用ゲインメモリ52bが設けられている。すなわち、本変形例においては、オフセットメモリおよびゲインメモリのそれぞれが、駆動トランジスタの劣化を補償するために用いられるメモリと有機EL素子OLEDの劣化を補償するために用いられるメモリとに分けられている。
t_charge=Cmp・Vd/i_L ・・・(1)
ここで、Vdが3Vであって、i_Lが10nAであって、Cmpが30pFであれば、充電に要する時間t_chargeは9ミリ秒となる。駆動周波数が60Hzのとき、1フレーム期間の長さは約16ミリ秒であるので、充電のために1フレーム期間の半分以上の期間が費やされる。この点、本変形例においては、黒書込期間Tbに、“OLED用オフセットメモリ51bに格納されているオフセット値”と“OLED用ゲインメモリ52bに格納されている劣化補正係数から計算される、発光電圧相当分の電圧”との和の電圧がモニタ線Mに印加される。すなわち、発光期間Tcの前に、モニタ線Mの電位が有機EL素子OLEDの発光閾値に近い電位になるよう予めモニタ線Mが充電される。これにより、上式(1)のVdが小さくなり、充電に要する時間が短縮される。
上記第1の実施形態においては、図7に示すように、モニタ線Mは電流測定部38または電圧測定部39のいずれかに接続される構成となっていた。しかしながら、本発明はこれに限定されず、モニタ線Mをハイインピーダンスの状態にすることが可能な構成(本変形例の構成)を採用することもできる。
上記第1の実施形態においては、1つの列につき電流測定部38と電圧測定部39とからなる1つのモニタ回路322が設けられていることを前提に説明していた。しかしながら、本発明はこれに限定されず、1つのモニタ回路322を複数の列で共有化する構成(本変形例の構成)を採用することもできる。
上記第1の実施形態によれば、有機EL表示装置1の短時間運転が繰り返されると、表示部10の上方の行と表示部10の下方の行との間で、TFT特性およびOLED特性の検出の回数に大きな差が生じる。そこで、本変形例に係る有機EL表示装置3においては、図26に示すように、コントロール回路20内にモニタ行を記憶するためのモニタ行記憶部201が設けられている。このような構成において、電源オフの際に、最後にTFT特性およびOLED特性の検出が行われた行を特定する情報がモニタ行記憶部201に格納される。この処理によってモニタ領域記憶ステップが実現されている。電源オン後には、モニタ行記憶部201に格納されている情報に基づいて特定される行の次の行から、TFT特性およびOLED特性の検出が行われる。なお、本実施形態においては、モニタ行記憶部201によってモニタ領域記憶部が実現されている。
図27は、有機EL素子の電流-電圧特性の温度依存性について説明するための図である。図27には、温度TE1における有機EL素子の電流-電圧特性,温度TE2における有機EL素子の電流-電圧特性,および温度TE3における有機EL素子の電流-電圧特性を示している。なお、“TE1>TE2>TE3”である。図27から把握されるように、有機EL素子に所定の電流を供給するためには、温度が低くなるほど電圧を高くする必要がある。このように、有機EL素子の電流-電圧特性は、温度に大きく依存している。そこで、温度変化を補償することのできる構成(本変形例の構成)を採用することが好ましい。
上記第1の実施形態においては、有機EL素子OLEDに一定の電流が与えられた状態で有機EL素子OLEDの陽極の電圧を測定することによってOLED特性の検出が行われていた。しかしながら、本発明はこれに限定されず、有機EL素子OLEDに一定の電圧が与えられた状態で有機EL素子OLEDに流れる電流を測定することによってOLED特性の検出が行われる構成(本変形例の構成)であっても良い。
<2.1 全体構成>
図31は、本発明の第2の実施形態に係るアクティブマトリクス型の有機EL表示装置5の全体構成を示すブロック図である。図31に示すように、本実施形態においては、表示部10aには、m本のデータ線S(1)~S(m),m本のモニタ線M(1)~M(m),n本の走査線G1(1)~G1(n),n本のモニタ制御線G2(1)~G2(n)に加えて、n本のハイレベル電源制御線G3(1)~G3(n)が設けられている。走査線G1(1)~G1(n)とモニタ制御線G2(1)~G2(n)とハイレベル電源制御線G3(1)~G3(n)とは互いに平行になっている。なお、以下においては、n本のハイレベル電源制御線G3(1)~G3(n)を互いに区別する必要がない場合にはハイレベル電源制御線を単に符号G3で表す。コントロール回路20およびソースドライバ30については、上記第1の実施形態と同様であるので説明を省略する。
図35は、本実施形態における画素回路11aおよびモニタ回路322の構成を示す図である。なお、図35に示す画素回路11aは、i行j列の画素回路11である。モニタ回路322の構成については、上記第1の実施形態と同様であるので説明を省略する。但し、本実施形態においては、モニタ線Mが電流測定部38に接続されているときにはモニタ線Mにハイレベル電源電圧ELVDDが供給される構成となっている。
次に、本実施形態における駆動方法について説明する。上述したように、本実施形態においては、各フレームに、1つの行についてのTFT特性の検出または1つの行についてのOLED特性の検出のいずれかが行われる。各フレームにおいて、モニタ行についてはTFT特性の検出を行うための動作(以下、「TFT特性検出動作」という。)またはOLED特性の検出を行うための動作(以下、「OLED特性検出動作」という。)のいずれかが行われ、非モニタ行については通常動作が行われる。すなわち、1行目についてのOLED特性の検出が行われるフレームを(k+1)フレーム目と定義すると、図36に示すように、各行の動作は推移する。なお、(k+1)フレーム目から(k+n)フレーム目までは、いずれの行においてもTFT特性検出動作は行われない。また、(k+n+1)フレーム目から(k+2n)フレーム目までは、いずれの行においてもOLED特性検出動作は行われない。
<2.3.1.1 通常動作>
各フレームにおいて、非モニタ行では、通常動作が行われる。非モニタ行に含まれる画素回路11aでは、目標輝度に対応するデータ電圧に基づく書き込みが選択期間に行われた後、トランジスタT1はオフ状態で維持される。データ電圧に基づく書き込みによってトランジスタT2はオン状態となる。トランジスタT3についてはオフ状態で維持され、トランジスタT4についてはオン状態で維持される。以上より、図37で符号74で示す矢印のように、トランジスタT4およびトランジスタT2を介して有機EL素子OLEDに駆動電流が供給される。これにより、駆動電流に応じた輝度で有機EL素子OLEDが発光する。
次に、OLED特性検出動作について説明する。図38は、モニタ行に含まれる画素回路11a(i行j列の画素回路11aとする)におけるOLED特性検出動作について説明するためのタイミングチャートである。なお、図38では、i行目がモニタ行とされるフレームにおけるi行目の選択期間開始時点を基準にして「1フレーム期間」を表している。図38に示すように、1フレーム期間には、選択期間Tpと発光期間Tqとが含まれている。
次に、TFT特性検出動作について説明する。図40は、モニタ行に含まれる画素回路11a(i行j列の画素回路11aとする)におけるTFT特性検出動作について説明するためのタイミングチャートである。
次に、本実施形態におけるオフセットメモリおよびゲインメモリの更新について説明する。図42は、TFT用オフセットメモリ51a,OLED用オフセットメモリ51b,TFT用ゲインメモリ52a,およびOLED用ゲインメモリ52bの更新の手順を説明するためのフローチャートである。なお、ここでは1つの画素に対応するオフセット値およびゲイン値に着目する。ところで、図36から把握されるように、本実施形態においては、任意の1つの画素に着目したとき、TFT特性の検出はOLED特性の検出が行われたフレームのnフレーム後に行われる。そこで、ここでは、Kフレーム目にOLED特性の検出が行われ、(K+n)フレーム目にTFT特性の検出が行われるものとする。
外部から送られる映像信号の補正については、図19に示す乗算部212に与えられるゲイン値Bおよび図19に示す加算部213に与えられるオフセット値Vtが上記第1の実施形態とは異なる。本実施形態においては、TFT用ゲインメモリ52aから読み出される値とOLED用ゲインメモリ52bから読み出される値との積がゲイン値Bとして乗算部212に与えられ、TFT用オフセットメモリ51aから読み出される値とOLED用オフセットメモリ51bから読み出される値との和がオフセット値Vtとして加算部213に与えられる。このような前提の下、映像信号が示す階調Pが“Vc・B+Vt”に補正される。なお、Vcは階調Pのガンマ補正後の制御電圧の値である。
本実施形態によれば、各画素について、nフレーム毎(nは画素マトリクスを構成する行の数)にOLED特性の検出とTFT特性の検出とが交互に行われる。そして、上記第1の実施形態と同様に、OLED特性の検出結果およびTFT特性の検出結果の双方を考慮して求められた補正データ(オフセット値およびゲイン値)を用いて、外部から送られる映像信号が補正される。このため、各画素回路11a内の有機EL素子OLEDを発光させる際に、駆動トランジスタの劣化および有機EL素子OLEDの劣化が補償されるような大きさの駆動電流が有機EL素子OLEDに供給される。ここで、本実施形態においては、OLED特性の検出についてもTFT特性の検出についても発光期間中に行われる。このため、それら特性の検出が選択期間中に行われる構成とは異なり、モニタ行の選択期間を長くする必要がない。従って、充分な長さの発光期間が確保される。また、行によって選択期間の長さにばらつきが生じることが防止される。以上のように、本実施形態によれば、有機EL表示装置において、選択期間の長さのばらつきを生ずることなく発光期間を充分に確保しつつ駆動トランジスタの劣化および有機EL素子OLEDの劣化の双方を特性検出の際に特別な発光をさせることなく同時に補償することが可能となる。
上記第2の実施形態においては、図36に示したように、まず1~n行目についてのOLED特性の検出が1フレームずつ順次に行われ、その後、1~n行目についてのTFT特性の検出が1フレームずつ順次に行われていた。しかしながら、本発明はこれに限定されない。図43に示すように、連続する2フレームにおいて1行目についてのOLED特性の検出と1行目についてのTFT特性の検出とを1フレームずつ行い、2~n行目について同様の動作を繰り返すようにしても良い。
本発明を適用可能な有機EL表示装置は、各実施形態および各変形例で例示した画素回路11,11aを備えるものに限定されるものではない。画素回路は、少なくとも、電流によって制御される電気光学素子(有機EL素子OLED),トランジスタT1~T3,およびコンデンサCstを備えていれば、各実施形態および各変形例で例示した構成以外の構成であっても良い。
10,10a…表示部
11,11a…画素回路
20…コントロール回路
30…ソースドライバ
31…駆動信号発生回路
32…信号変換回路
33…出力部
38…電流測定部
39…電圧測定部
40,40a…ゲートドライバ
51…オフセットメモリ
51a…TFT用オフセットメモリ
51b…OLED用オフセットメモリ
52…ゲインメモリ
52a…TFT用ゲインメモリ
52b…OLED用ゲインメモリ
60…温度センサ
201…モニタ行記憶部
202…温度変化補償部
321…階調信号発生回路
322,323…モニタ回路
330…出力回路
T1~T4…トランジスタ
Cst…コンデンサ
G1(1)~G1(n)…走査線
G2(1)~G2(n)…モニタ制御線
G3(1)~G3(n)…ハイレベル電源制御線
S(1)~S(m)…データ線
M(1)~M(m)…モニタ線
Claims (26)
- 電流によって輝度が制御される電気光学素子および前記電気光学素子に供給すべき電流を制御するための駆動トランジスタをそれぞれが含むn×m個(nおよびmは2以上の整数)の画素回路からなるn行×m列の画素マトリクスを有する表示装置の駆動方法であって、
前記駆動トランジスタの特性を検出する第1の特性検出ステップと、
前記電気光学素子の特性を検出する第2の特性検出ステップと、
前記第1の特性検出ステップでの検出結果および前記第2の特性検出ステップでの検出結果に基づいて得られる特性データを、映像信号を補正するための補正データとして、予め用意された補正データ記憶部に記憶させる補正データ記憶ステップと、
前記補正データ記憶部に記憶されている補正データに基づいて前記映像信号を補正して、前記n×m個の画素回路に供給すべきデータ信号を生成する映像信号補正ステップと
を含み、
1フレーム期間は、前記電気光学素子を発光させる準備が行われる選択期間と前記電気光学素子の発光が行われる発光期間とからなり、
前記第1の特性検出ステップおよび前記第2の特性検出ステップの一方または双方の処理が、1フレーム期間につき前記画素マトリクスの1つの行のみで行われ、
前記第2の特性検出ステップの処理は、前記発光期間に行われることを特徴とする、駆動方法。 - 前記第1の特性検出ステップおよび前記第2の特性検出ステップの双方の処理が、1フレーム期間につき前記画素マトリクスの1つの行のみで行われ、
各フレームにおいて前記第1の特性検出ステップおよび前記第2の特性検出ステップの双方の処理が行われる行をモニタ行と定義し、前記モニタ行以外の行を非モニタ行と定義したとき、前記モニタ行についての前記選択期間の長さは、前記非モニタ行についての前記選択期間の長さよりも長くなっていて、
前記第1の特性検出ステップの処理は、前記選択期間に行われることを特徴とする、請求項1に記載の駆動方法。 - 前記第1の特性検出ステップおよび前記第2の特性検出ステップの一方の処理が、1フレーム期間につき前記画素マトリクスの1つの行のみで行われ、
前記画素マトリクスの1つの行に着目したとき、前記第1の特性検出ステップの処理と前記第2の特性検出ステップの処理とは交互に行われ、
前記第1の特性検出ステップの処理は、前記発光期間に行われることを特徴とする、請求項1に記載の駆動方法。 - 前記第2の特性検出ステップでは、前記電気光学素子に一定の電流が与えられた状態で前記電気光学素子の陽極の電圧を測定することによって、前記電気光学素子の特性が検出されることを特徴とする、請求項1に記載の駆動方法。
- 前記第2の特性検出ステップでは、目標輝度に応じて、前記一定の電流を前記電気光学素子に与える時間の長さが調整されることを特徴とする、請求項4に記載の駆動方法。
- 前記第2の特性検出ステップでは、1フレーム期間での発光電流の積分値が目標階調に相当する値となる範囲内で複数レベルの前記一定の電流が前記電気光学素子に与えられることによって、前記電気光学素子の特性として複数の特性が検出されることを特徴とする、請求項4に記載の駆動方法。
- 前記第2の特性検出ステップでは、前記電気光学素子に一定の電圧が与えられた状態で前記電気光学素子に流れる電流を測定することによって、前記電気光学素子の特性が検出されることを特徴とする、請求項1に記載の駆動方法。
- 前記第2の特性検出ステップでは、目標輝度に応じて、前記一定の電圧を前記電気光学素子に与える時間の長さが調整されることを特徴とする、請求項7に記載の駆動方法。
- 前記第2の特性検出ステップでは、1フレーム期間での発光電流の積分値が目標階調に相当する値となる範囲内で複数レベルの前記一定の電圧が前記電気光学素子に与えられることによって、前記電気光学素子の特性として複数の特性が検出されることを特徴とする、請求項7に記載の駆動方法。
- 前記第1の特性検出ステップでは、前記駆動トランジスタのゲート-ソース間の電圧を所定の大きさにした状態で前記駆動トランジスタのドレイン-ソース間を流れる電流を測定することによって、前記駆動トランジスタの特性が検出されることを特徴とする、請求項1に記載の駆動方法。
- 前記補正データ記憶部は、前記補正データとしてオフセット値を記憶するオフセット値記憶部と前記補正データとしてゲイン値を記憶するゲイン値記憶部とからなり、
前記補正データ記憶ステップでは、
前記第1の特性検出ステップでの検出結果に基づいて得られるオフセット値と前記第2の特性検出ステップでの検出結果に基づいて得られるオフセット値との和が、新たなオフセット値として前記オフセット値記憶部に記憶され、
前記第1の特性検出ステップでの検出結果に基づいて得られるゲイン値と前記第2の特性検出ステップでの検出結果に基づいて得られる補正係数との積が、新たなゲイン値として前記ゲイン値記憶部に記憶されることを特徴とする、請求項1に記載の駆動方法。 - 前記表示装置は、
前記駆動トランジスタの特性および前記電気光学素子の特性を検出するための特性検出部と、
前記画素マトリクスの各列に対応するように設けられ、前記特性検出部および対応する列の画素回路と電気的に接続され得るように構成されたm本のモニタ線と
を更に有し、
前記選択期間は、前記第1の特性検出ステップの処理が行われる第1期間と前記第1期間に続く第2期間とからなり、
前記オフセット値記憶部に記憶されているオフセット値と前記第1の特性検出ステップでの検出結果に基づいて得られるオフセット値との差分の値を第1の値と定義し、前記ゲイン値記憶部に記憶されているゲイン値と前記第1の特性検出ステップでの検出結果に基づいて得られるゲイン値とに基づいて得られる値を第2の値と定義したとき、前記第2期間には、各モニタ線に、前記第1の値と前記第2の値との和に相当する電圧が印加されることを特徴とする、請求項11に記載の駆動方法。 - 前記補正データ記憶部は、前記補正データとして前記駆動トランジスタに対応するオフセット値を記憶する駆動トランジスタ用オフセット値記憶部,前記補正データとして前記電気光学素子に対応するオフセット値を記憶する電気光学素子用オフセット値記憶部,前記補正データとして前記駆動トランジスタに対応するゲイン値を記憶する駆動トランジスタ用ゲイン値記憶部,および前記補正データとして前記電気光学素子に対応するゲイン値を記憶する電気光学素子用ゲイン値記憶部からなり、
前記補正データ記憶ステップでは、
前記第1の特性検出ステップでの検出結果に基づいて得られるオフセット値が、新たなオフセット値として前記駆動トランジスタ用オフセット値記憶部に記憶され、
前記第1の特性検出ステップでの検出結果に基づいて得られるゲイン値が、新たなゲイン値として前記駆動トランジスタ用ゲイン値記憶部に記憶され、
前記第2の特性検出ステップでの検出結果に基づいて得られるオフセット値が、新たなオフセット値として前記電気光学素子用オフセット値記憶部に記憶され、
前記第2の特性検出ステップでの検出結果に基づいて得られる補正係数が、新たなゲイン値として前記電気光学素子用ゲイン値記憶部に記憶されることを特徴とする、請求項1に記載の駆動方法。 - 前記第2の特性検出ステップでは、前記電気光学素子に一定の電流が与えられた状態で前記電気光学素子の陽極の電圧を測定することによって、前記電気光学素子の特性が検出され、
前記一定の電流の大きさは、前記電気光学素子用ゲイン値記憶部に記憶されているゲイン値に応じて調整されることを特徴とする、請求項13に記載の駆動方法。 - 前記第2の特性検出ステップでは、前記電気光学素子に一定の電圧が与えられた状態で前記電気光学素子に流れる電流を測定することによって、前記電気光学素子の特性が検出され、
前記一定の電圧の大きさは、前記電気光学素子用ゲイン値記憶部に記憶されているゲイン値に応じて調整されることを特徴とする、請求項13に記載の駆動方法。 - 前記表示装置は、
前記駆動トランジスタの特性および前記電気光学素子の特性を検出するための特性検出部と、
前記画素マトリクスの各列に対応するように設けられ、前記特性検出部および対応する列の画素回路と電気的に接続され得るように構成されたm本のモニタ線と
を更に有し、
前記選択期間は、前記第1の特性検出ステップの処理が行われる第1期間と前記第1期間に続く第2期間とからなり、
前記第2期間には、各モニタ線に、前記電気光学素子用オフセット値記憶部に記憶されているオフセット値と前記電気光学素子用ゲイン値記憶部に記憶されているゲイン値に基づいて得られる値との和に相当する電圧が印加されることを特徴とする、請求項13に記載の駆動方法。 - 前記表示装置は、
電流を測定する電流測定部を少なくとも含み、前記駆動トランジスタの特性および前記電気光学素子の特性を検出するための特性検出部と、
前記画素マトリクスの各列に対応するように設けられ、前記特性検出部および対応する列の画素回路と電気的に接続され得るように構成されたm本のモニタ線と
を更に有し、
前記第1の特性検出ステップでは、前記m本のモニタ線が対応する画素回路および前記電流測定部と電気的に接続された状態で、前記駆動トランジスタのゲート-ソース間の電圧を所定の大きさにした状態で前記駆動トランジスタのドレイン-ソース間を流れる電流が前記電流測定部によって測定されることを特徴とする、請求項1に記載の駆動方法。 - 前記特性検出部は、電圧を測定する電圧測定部を更に含み、
前記第2の特性検出ステップでは、前記電気光学素子に一定の電流が与えられた状態で前記電気光学素子の陽極の電圧が前記電圧測定部によって測定されることを特徴とする、請求項17に記載の駆動方法。 - 前記第2の特性検出ステップでは、前記電気光学素子に一定の電圧が与えられた状態で前記電気光学素子に流れる電流が前記電流測定部によって測定されることを特徴とする、請求項17に記載の駆動方法。
- 前記特性検出部は、K本のモニタ線(Kは2以上m以下の整数)につき1つだけ設けられ、
各フレームにおいて、
前記K本のモニタ線のうちの1つが前記特性検出部と電気的に接続され、
前記特性検出部と電気的に接続されていないモニタ線は、ハイインピーダンスの状態にされていることを特徴とする、請求項17に記載の駆動方法。 - 前記n行×m列の画素マトリクスのうち黒色またはほぼ黒色の表示が行われる画素については、前記第2の特性検出ステップの処理が行われないことを特徴とする、請求項1に記載の駆動方法。
- 前記表示装置の電源オフの際に、最後に前記第1の特性検出ステップおよび前記第2の特性検出ステップの一方または双方の処理が行われた領域を特定する情報を予め用意されたモニタ領域記憶部に記憶するモニタ領域記憶ステップを更に含み、
前記表示装置の電源オン後には、前記モニタ領域記憶部に記憶されている情報に基づいて得られる領域近傍の領域から、前記第1の特性検出ステップおよび前記第2の特性検出ステップの一方または双方の処理が行われることを特徴とする、請求項1に記載の駆動方法。 - 温度を検出する温度検出ステップと、
前記特性データに対して前記温度検出ステップで検出された温度に基づく補正を施す温度変化補償ステップと
を更に含み、
前記補正データ記憶ステップでは、前記温度変化補償ステップの処理で得られたデータが前記補正データとして前記補正データ記憶部に記憶されることを特徴とする、請求項1に記載の駆動方法。 - 前記駆動トランジスタは、酸化物半導体によりチャネル層が形成された薄膜トランジスタであることを特徴とする、請求項1に記載の駆動方法。
- 前記酸化物半導体は、インジウム(In),ガリウム(Ga),亜鉛(Zn),および酸素(О)を主成分とする酸化インジウムガリウム亜鉛であることを特徴とする、請求項24に記載の駆動方法。
- 電流によって輝度が制御される電気光学素子および前記電気光学素子に供給すべき電流を制御するための駆動トランジスタをそれぞれが含むn×m個(nおよびmは2以上の整数)の画素回路からなるn行×m列の画素マトリクスを有する表示装置であって、
前記駆動トランジスタの特性を検出する第1の特性検出処理および前記電気光学素子の特性を検出する第2の特性検出処理を行いつつ前記n×m個の画素回路を駆動する画素回路駆動部と、
前記第1の特性検出処理での検出結果および前記第2の特性検出処理での検出結果に基づいて得られる特性データを、映像信号を補正するための補正データとして記憶する補正データ記憶部と、
前記補正データ記憶部に記憶されている補正データに基づいて前記映像信号を補正して、前記n×m個の画素回路に供給すべきデータ信号を生成する映像信号補正部と
を備え、
1フレーム期間は、前記電気光学素子を発光させる準備が行われる選択期間と前記電気光学素子の発光が行われる発光期間とからなり、
前記画素回路駆動部は、
前記第1の特性検出処理および前記第2の特性検出処理の一方または双方の処理を、1フレーム期間につき前記画素マトリクスの1つの行についてのみ行い、
前記第2の特性検出処理を前記発光期間に行うことを特徴とする、表示装置。
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Also Published As
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US9881552B2 (en) | 2018-01-30 |
US20170148385A1 (en) | 2017-05-25 |
US9711092B2 (en) | 2017-07-18 |
JPWO2014141958A1 (ja) | 2017-02-16 |
JP6138236B2 (ja) | 2017-05-31 |
US20150379940A1 (en) | 2015-12-31 |
CN105190739B (zh) | 2017-08-08 |
CN105190739A (zh) | 2015-12-23 |
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