WO2014012334A1 - 阵列基板的制造方法及阵列基板、显示装置 - Google Patents
阵列基板的制造方法及阵列基板、显示装置 Download PDFInfo
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- WO2014012334A1 WO2014012334A1 PCT/CN2012/086597 CN2012086597W WO2014012334A1 WO 2014012334 A1 WO2014012334 A1 WO 2014012334A1 CN 2012086597 W CN2012086597 W CN 2012086597W WO 2014012334 A1 WO2014012334 A1 WO 2014012334A1
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- electrode
- transparent electrode
- metal oxide
- forming
- oxide film
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Classifications
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- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
Definitions
- Embodiments of the present invention relate to a method of fabricating an array substrate, an array substrate, and a display device. Background technique
- a liquid crystal display is a commonly used flat panel display, and a Thin Film Transistor Liquid Crystal Display (TFT-LCD) is a main production port in a liquid crystal display.
- TFT-LCD Thin Film Transistor Liquid Crystal Display
- TFT-LCD based on ADvanced Super Dimension Switch is widely used due to its low power consumption and wide viewing angle.
- the ADS technology mainly forms a multi-dimensional electric field by the electric field generated by the edge of the slit electrode in the same plane and the electric field generated between the slit electrode layer and the plate electrode layer, so that all the aligned liquid crystal molecules are directly between the slit electrodes in the liquid crystal cell and above the electrode. Both can produce rotation, thereby improving the liquid crystal working efficiency and increasing the light transmission efficiency.
- Advanced super-dimensional field conversion technology can improve the picture quality of TFT-LCD products, with high resolution, high transmittance, wide viewing angle, high aperture ratio, low chromatic aberration, and push mura.
- the common electrode is also formed on the array substrate in the ADS type TFT-LCD, an additional patterning process for forming the common electrode is required in the fabrication process of the array substrate of the ADS type TFT-LCD.
- a multi-patterning process is usually required in the manufacturing process of an ADS type TFT-LCD array substrate, and each of the patterning processes includes a process of film formation, exposure, development, etching, and stripping, respectively. Therefore, reducing the number of patterning processes means reducing manufacturing costs.
- the prior art discloses that an ADS type TFT-LCD array substrate is manufactured by six patterning processes.
- the method includes:
- Step 1 depositing a first metal thin film, and forming a gate line, a gate electrode 11 and a common electrode line 12 by a first patterning process.
- Step 2 depositing a first insulating film, a semiconductor film, and a doped semiconductor film, and forming a gate insulating layer 13 and a semiconductor active layer 14 by a second patterning process (by the semiconductor layer and the doped semiconductor layer Composition).
- Step 3 depositing a first transparent conductive film, and forming a plate-shaped pixel electrode 14' by a third patterning process.
- step 4 a second metal thin film is deposited, and the source electrode 16, the drain electrode 17, and the data line are formed by a fourth patterning process.
- Step 5 depositing a second insulating film to form a passivation layer 18, and forming a via hole penetrating the passivation layer 18 and the gate insulating layer 13 by a fifth patterning process to expose the common electrode line 12.
- Step 6 depositing a second transparent conductive film, forming a common electrode 19 having slits through a sixth patterning process, and the common electrode 19 is electrically connected to the common electrode line 12 through the via holes formed in the step 5.
- Embodiments of the present invention provide a method for fabricating an array substrate, an array substrate, and a display device for reducing the number of patterning processes in the manufacturing process of the array substrate and reducing the production cost.
- a method of fabricating an array substrate forms a thin film transistor, a first transparent electrode, and a second transparent electrode, wherein the first transparent electrode and the second transparent electrode generate a multi-dimensional electric field, wherein Forming the first transparent electrode includes:
- a portion of the metal oxide film is metallized to form a first transparent electrode, and a portion not subjected to the metallization process forms a semiconductor active layer.
- the forming the thin film transistor, the first transparent electrode, and the second transparent electrode comprises: sequentially forming a metal oxide film and an etch barrier film on the substrate on which the gate line, the gate electrode, and the gate insulating layer are formed Processing the etch barrier film by a patterning process to form an etch barrier covering the channel region of the TFT; metallizing the metal oxide film not covered by the etch barrier to form a metal having conductor characteristics An oxide thin film; a portion of the metal oxide film covered by the etch barrier layer that is not subjected to the metallization treatment forms a semiconductor active layer; and the metal oxide film having the conductor property is processed by a patterning process to Forming a first transparent electrode and a source connection electrode and a drain connection electrode connected to the semiconductor active layer; Forming a source electrode, a drain electrode, a data line, a passivation layer and a second transparent electrode on the substrate of the semiconductor active layer, the etch barrier layer and the first transparent electrode, wherein the source electrode is electrically connected to the
- the gate line, the gate electrode, and the common electrode line may be further formed on the substrate. And forming a gate insulating layer on the substrate, the gate line, the gate electrode, and the common electrode line.
- Forming the source electrode, the drain electrode, the data line, the passivation layer, and the second transparent electrode on the substrate on which the semiconductor active layer, the etch barrier layer, and the first transparent electrode are formed may include: forming a semiconductor active layer, engraved Forming a data line, a source electrode, and a drain electrode electrically connected to the first transparent electrode on the substrate of the etch barrier layer and the first transparent electrode; forming a passivation layer including the first via hole, the first via hole penetrating The passivation layer and the gate insulating layer expose the common electrode line; and forming a second transparent electrode on the passivation layer, the second transparent electrode passing through the first via and the common The electrode wires are electrically connected.
- the method further includes: forming a gate line, a gate electrode, and a common electrode on the substrate. And a gate insulating layer; a second via hole formed in the gate insulating layer, wherein the second via hole is used to connect the first transparent electrode and the common electrode line.
- Forming the source electrode, the drain electrode, the data line, the passivation layer, and the second transparent electrode on the substrate on which the semiconductor active layer, the etch barrier layer, and the first transparent electrode are formed may include: forming the semiconductor active layer Forming a source electrode, a drain electrode, and a data line on the substrate of the etch barrier layer and the first transparent electrode; forming a passivation layer including a third via hole, the third via hole penetrating the passivation layer Exposing the drain electrode; and forming a second transparent electrode on the passivation layer, the second transparent electrode being electrically connected through the third via and the drain electrode.
- the forming the first transparent electrode by metallizing a portion of the metal oxide film may include: forming a metallization process on a portion of the metal oxide film by a plasma process or an annealing process.
- the first transparent electrode may include: forming a metallization process on a portion of the metal oxide film by a plasma process or an annealing process.
- the first transparent electrode may be a pixel electrode or a common electrode.
- the metal oxide film may be a transparent metal oxide material having semiconductor characteristics.
- the metal oxide material may be InGaZnO, InGaO, ITZO, ⁇
- an array substrate produced by the above method is provided.
- a display device including the above array substrate is provided.
- FIG. 1 is a schematic structural view of an array substrate in the prior art
- FIG. 2 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present invention
- FIG. 3 is a first schematic diagram of an array substrate according to Embodiment 2 of the present invention.
- FIG. 4 is a second schematic diagram of an array substrate according to Embodiment 2 of the present invention.
- FIG. 5 is a third schematic diagram of an array substrate according to Embodiment 2 of the present invention.
- FIG. 6 is a fourth schematic diagram of an array substrate according to Embodiment 2 of the present invention.
- FIG. 7 is a fifth schematic diagram of an array substrate according to Embodiment 2 of the present invention.
- FIG. 8 is a sixth schematic diagram of an array substrate according to Embodiment 2 of the present invention.
- FIG. 9 is a seventh schematic diagram of an array substrate according to Embodiment 2 of the present invention.
- FIG. 10 is an eighth schematic diagram of an array substrate according to Embodiment 2 of the present invention.
- FIG. 11 is a ninth schematic view of an array substrate according to Embodiment 2 of the present invention.
- FIG. 12 is a schematic cross-sectional structural view of an array substrate according to Embodiment 2 of the present invention.
- FIG. 13 is a first schematic diagram of an array substrate according to Embodiment 3 of the present invention.
- FIG. 14 is a schematic cross-sectional structural view of an array substrate according to Embodiment 3 of the present invention.
- FIG. 15 is a first schematic diagram of an array substrate according to Embodiment 4 of the present invention.
- FIG. 16 is a cross-sectional structural diagram of an array substrate according to Embodiment 4 of the present invention.
- a method for fabricating an array substrate according to an embodiment of the invention includes a process for fabricating a thin film transistor, a first transparent electrode, and a second transparent electrode.
- the first transparent electrode and the second transparent electrode generate a multi-dimensional electric field.
- the manufacturing process of the first transparent electrode includes:
- a metal oxide film is formed, and the metal oxide film has semiconductor characteristics.
- a portion of the metal oxide film is metallized to form a first transparent electrode, and a portion not subjected to the metallization treatment forms a semiconductor active layer.
- forming the first transparent electrode by metallizing a portion of the metal oxide film may include: forming a metallization treatment on a part of the metal oxide film by a plasma process or an annealing process or the like A transparent electrode.
- the first transparent electrode is a pixel electrode; or the first transparent electrode is a common electrode.
- the thin metal oxide is thin
- the film is metallized to exhibit a conductor characteristic to form a first transparent electrode, and a portion not subjected to metallization exhibits characteristics of a semiconductor to form a semiconductor active layer.
- the semiconductor active layer and the first transparent electrode are formed by one patterning process in the same metal oxide film having the conductor characteristics and the semiconductor characteristics, and the step of separately preparing the first transparent electrode is omitted, which reduces the manufacturing cost.
- a method for manufacturing an array substrate according to an embodiment of the present invention includes:
- a first metal thin film is formed on a substrate 10 (such as a glass substrate or a quartz substrate) by plasma enhanced chemical vapor deposition (PECVD), magnetron sputtering, thermal evaporation or other film forming methods.
- the first metal film may be a single layer film formed of a metal such as molybdenum, aluminum, aluminum bismuth alloy, tungsten, chromium, copper, or the like, or may be a multilayer film formed by depositing the above metal layers.
- a patterning process such as exposure, development, etching, and lift-off is performed through the mask to form the gate electrode 11 as shown in FIG. 3 and the gate line not shown in FIG. pattern.
- a gate insulating layer 13 is formed on the substrate 10, the gate line, and the gate electrode 11 by a method such as chemical vapor deposition or evaporation.
- a metal oxide film and an etch barrier film are sequentially formed on the substrate on which the gate line, the gate electrode, and the gate insulating layer are formed.
- a metal oxide film 140 and an etch barrier film 150 are sequentially formed on a substrate 10 on which a gate line, a gate electrode 11 and a gate insulating layer 13 are formed.
- the metal oxide film 140 and the etch barrier film 150 may be formed by magnetron sputtering, thermal evaporation, or chemical vapor deposition.
- the metal oxide film 140 may be a transparent metal oxide material having a semiconductor property, for example, a transparent metal oxide material such as InGaZnO, InGaO, ITZO, ⁇ ; the etch barrier film 150 may be a dense silicon nitride. , silicon oxide, silicon oxynitride and other materials.
- the etch stop film is processed by a patterning process to form a pattern of an etch stop layer covering the TFT channel region.
- the film is retained on the TFT channel region as shown in FIG. 5.
- the first photoresist 20, other regions are no photoresist.
- the etch barrier film 150 not covered by the first photoresist 20 is etched, and only the etch barrier film of the first photoresist 20 covering region (ie, the TFT channel region) is left after the process to form a capping TFT.
- the etch stop layer 15 of the channel region exposes the metal oxide film 140 not covered by the etch barrier layer 15.
- the exposed metal oxide film 140 may be metallized by a plasma process or an annealing process. This step can be implemented in the following three ways.
- Method 1 The substrate having the structure shown in Fig. 6 is placed in a vacuum chamber and heated to a certain temperature, and is kept in the air for a while and then cooled.
- the certain temperature value can be 200 ⁇ 300 °C
- the holding time can be 20 ⁇ 40 minutes.
- Method 2 The substrate having the structure shown in Fig. 6 is subjected to heat treatment at 200 to 400 ° C in a reducing atmosphere.
- Method 3 The substrate having the structure shown in FIG. 6 is placed in a vacuum chamber, and the plasma treatment method is generally performed at a power of 1500 2500 W, a pressure of 1000 to 2000 mtorr, and a hydrogen (H 2 ) plasma and oxygen ( 0 2 ) Plasma treatment Two methods, when using hydrogen plasma or oxygen plasma treatment, the gas flow rate of hydrogen or oxygen is generally 5000 15000 sccm.
- the carrier concentration of the metallized metal oxide film 140 can be improved to exhibit conductor characteristics, and it can replace the conventional pixel electrode material.
- the metal oxide film which is not subjected to metallization under the etching stopper layer 15 has a low carrier concentration and exhibits a semiconductor characteristic, that is, the semiconductor active layer 141.
- a second photoresist layer is coated on the substrate 10, and after exposure and development processing through the mask.
- the second photoresist 21 remaining on the etch stop layer 15 and on both sides thereof, and the corresponding first transparent electrode region remaining on the metal oxide film 140 having the conductor characteristics are obtained.
- Three photoresists 22, other areas are no photoresist.
- the exposed process is exposed by an etching process.
- a metal oxide film having a conductor property is etched to form a first transparent electrode 14, a source electrode 142 and a drain electrode 143 connected to the semiconductor active layer 141, and finally the second light shown in FIG. 9 is peeled off.
- the glue 21 and the third photoresist 22 are engraved.
- the first transparent electrode 14 is used as the pixel electrode (that is, it is electrically connected to the drain electrode), but the embodiment is not limited to the first transparent electrode 14 As a pixel electrode, the first transparent electrode 14 may also be a common electrode.
- the source and drain electrodes, the data line, the passivation layer, and the second transparent electrode may be formed by a three-time patterning process, respectively.
- a metal thin film is formed on the substrate 10 by a conventional film forming method such as magnetron sputtering or thermal evaporation, and a source electrode 16 electrically connected to the source connection electrode 142 is formed by a patterning process, and a drain electrode is formed.
- the drain electrode 17 electrically connected to the electrode 143 and the pattern of the data line (not shown in FIG. 10) are connected.
- the metal thin film forming the source and drain electrodes and the data line may be a single-layer film formed of a metal such as molybdenum, aluminum, aluminum-bismuth alloy, tungsten, chromium, copper, or the like, or may be a multilayer film formed by depositing the above metal layers. .
- an insulating film is formed on the substrate 10 by chemical vapor deposition or thermal evaporation to form a passivation layer 18.
- the insulating film may be a single layer film of silicon nitride, silicon oxide or silicon oxynitride, or a multilayer film formed by multilayer deposition of the above materials.
- a transparent conductive film is formed by magnetron sputtering or thermal evaporation, and a second transparent electrode 19 having slits is formed by a patterning process.
- a multi-dimensional electric field can be formed between the first transparent electrode 14 and the second transparent electrode 19.
- the material of the second transparent electrode 19 may be: a transparent conductive material such as ITO, ZnO, InGaZnO, InZnO or InGaO.
- the method for fabricating an array substrate according to an embodiment of the present invention forms a first transparent electrode by metallizing a part of the metal oxide film to exhibit a conductor characteristic, and forming a semiconductor by a portion of the metallization process that exhibits semiconductor characteristics.
- Active layer The semiconductor active layer and the first transparent electrode are formed by one patterning process in the same metal oxide film having the conductor characteristics and the semiconductor characteristics, and the step of separately preparing the first transparent electrode is omitted, which reduces the manufacturing cost.
- the metal oxide semiconductor material in the TFT channel region is easily oxidized in water or air, the metal oxide semiconductor material in the TFT channel region is easily subjected to wet etching in a subsequent process. To the destruction, the TFT characteristics are low.
- the corresponding TFT channel region is covered with an etch barrier layer, and the metal oxide semiconductor material of the TFT channel region can avoid the damage during etching under the protection of the etch barrier layer, thereby ensuring TFT characteristics, and further Ensure the display quality of the product.
- the basic process of the method for manufacturing the array substrate provided by the embodiment of the present invention is similar to that of the second embodiment, and reference may be made to the second embodiment.
- S201 of the second embodiment S201' of the embodiment includes: as shown in FIG. 13, a gate line (not shown in FIG. 13) is formed on the substrate 10, and the gate electrode 11 is formed. At the same time, the common electrode line 12 is also formed, and then the gate insulating layer 13 is formed on the substrate 10.
- the common electrode line 12 and the gate electrode 11 and the gate line can be formed by one patterning process.
- the example S206' includes: Referring to FIG. 14, a source electrode 16 and a drain electrode electrically connected to the first transparent electrode 14 are sequentially formed on the substrate on which the semiconductor active layer 141, the etch barrier layer 15 and the first transparent electrode 14 are formed. 17 and data lines.
- a passivation layer 18 including a first via hole 181 is formed on the substrate on which the data line, the source electrode 16 and the drain electrode 17 are formed, and the first via hole 181 penetrates the passivation layer 18 and the gate insulating layer 13 to expose the common Electrode line 12.
- a second transparent electrode 19 is formed on the passivation layer 18, and the second transparent electrode 19 is electrically connected to the common electrode line 12 through the first via 181, and the second transparent electrode 19 is a transparent electrode having a slit.
- the first transparent electrode 14 and the second transparent electrode 19 having a slit form a multi-dimensional electric field.
- the first transparent electrode 14 is a pixel electrode, which is in direct contact with the drain electrode 17 for electrical connection; the second transparent electrode 19 is a common electrode, and is electrically connected to the common electrode line 12 through the first via 181.
- the method for manufacturing an array substrate provided by the embodiment of the present invention forms a first transparent electrode by metallizing a part of the metal oxide film to exhibit a conductor characteristic, and the portion not subjected to metallization exhibits characteristics of a semiconductor to form a semiconductor. Active layer. Forming a semiconductor active layer by one patterning process in the same metal oxide film having conductor characteristics and semiconductor characteristics
- the first transparent electrode omits the step of separately preparing the first transparent electrode, which reduces the manufacturing cost.
- the common electrode is electrically connected to the common electrode line, which can greatly reduce the resistance of the common electrode. As the size of the panel increases, the resistance of the common electrode can cause problems such as picture delay or display abnormality, and the first via common electrode The above problems can be completely solved by directly making electrical connection with the common electrode line.
- the metal oxide semiconductor material of the TFT channel region is easily damaged in the wet etching in the subsequent process, resulting in poor TFT characteristics.
- the corresponding TFT channel region is covered with an etch barrier layer, and the metal oxide semiconductor material of the TFT channel region can avoid the damage during etching under the protection of the etch barrier layer, thereby ensuring TFT characteristics, and further Ensure the display quality of the product.
- the basic process of the method for manufacturing the array substrate provided by the embodiment of the present invention is similar to that of the second embodiment, and reference may be made to the second embodiment.
- the S201 of the embodiment includes: as shown in FIG. 15, a gate line (not shown in FIG. 15) and a gate electrode are formed on the substrate 10. 11 and the common electrode line 12, and the gate insulating layer 13. Thereafter, a second via hole 131 is formed on the gate insulating layer 13, and the second via hole 131 exposes the common electrode line 12 for connecting the first process formed by the subsequent process.
- the subsequent steps are similar to the steps S202-S204 of the second embodiment.
- the first transparent electrode 14 in this embodiment is connected to the common electrode line 12 through the second via 131.
- step S205 of the present embodiment includes: referring to FIG. 16, the formed metal oxide film having the conductor characteristics formed by the patterning process to form the first transparent electrode 14, and The source connection electrode 142 and the drain connection electrode 143 are connected to the semiconductor active layer 141.
- the first transparent electrode 14 is electrically connected to the common electrode line 12 through the second via hole 131.
- the step S206 of the present embodiment includes: referring to 16, the source electrode 16 is sequentially formed on the substrate 10 on which the semiconductor active layer 141, the etch barrier layer 15 and the first transparent electrode 14 are formed. After the drain electrode 17 and the data line (not shown in FIG. 16), a passivation layer 18 including a third via hole 182 is formed thereon, and the third via hole 182 penetrates the passivation layer 18 to expose leakage. The pole 17. Next, a second transparent electrode is formed on the passivation layer 18 on which the third via 182 is formed. 19. The second transparent electrode 19 is electrically connected to the drain electrode 17 through the third via 182.
- the first transparent electrode 14 is a common electrode, and is electrically connected to the common electrode line 12 through the second via 131 on the gate insulating layer 13.
- the second transparent electrode 19 is a pixel electrode and is electrically connected to the drain electrode 17 through a third via 182 on the passivation layer 18.
- a portion of the metal oxide film is metallized to exhibit a conductor characteristic to form a first transparent electrode, and a portion not subjected to metallization is characterized by a semiconductor to form a semiconductor.
- Active layer The semiconductor active layer and the first transparent electrode are formed by one patterning process in the same metal oxide film having the conductor characteristics and the semiconductor characteristics, and the step of separately preparing the first transparent electrode is omitted, which reduces the manufacturing cost.
- the common electrode is electrically connected to the common electrode line, which can greatly reduce the resistance of the common electrode. As the size of the panel increases, the resistance of the common electrode can cause problems such as picture delay or display abnormality, and the first via common electrode The above problems can be completely solved by directly making electrical connection with the common electrode line.
- the metal oxide semiconductor material of the TFT channel region is easily damaged in the wet etching in the subsequent process, resulting in poor TFT characteristics.
- the corresponding TFT channel region is covered with an etch barrier layer, and the metal oxide semiconductor material of the TFT channel region can avoid the damage during etching under the protection of the etch barrier layer, thereby ensuring TFT characteristics, and further Ensure the display quality of the product.
- the array substrate of the fifth embodiment includes a thin film transistor, a first transparent electrode and a second transparent electrode, the first transparent electrode and the second transparent electrode generate a multi-dimensional electric field, the semiconductor active layer of the thin film transistor and the first
- the transparent electrode is formed by the same metal oxide film by one patterning process, wherein the first transparent electrode is obtained by metallizing the metal oxide film, and the semiconductor active layer is not metallized.
- the metal oxide film is formed.
- the array substrate provided with the pixel electrode and the common electrode in different layers is taken as an example for description. It can be understood that, when the pixel electrode and the common electrode are disposed on the array substrate in the above embodiment, the active layer, the pixel electrode, and the common layer may be formed on a metal oxide film by a patterning process, a metallization process, or the like. The pattern of the electrodes. Therefore, the array substrate provided by the embodiment of the present invention can also be applied to an IPS (in-plane switching) type and an AD-SDS type TFT array substrate by appropriate modification.
- IPS in-plane switching
- the array substrate provided by the embodiment of the present invention forms a first transparent electrode by metallizing a part of the metal oxide film to exhibit conductor characteristics, and the portion not subjected to metallization exhibits characteristics of a semiconductor to form a semiconductor active layer.
- the semiconductor active layer and the first transparent electrode are formed by one patterning process in the same metal oxide film having the conductor characteristics and the semiconductor characteristics, and the step of separately preparing the first transparent electrode is omitted, which reduces the manufacturing cost.
- the display device provided by the embodiment of the present invention includes the array substrate according to the fifth embodiment, and the array substrate is obtained by the method for fabricating any one of the array substrates of the above-mentioned first to fourth embodiments.
- the array substrate includes a thin film transistor, a first transparent electrode and a second transparent electrode, the first transparent electrode and the second transparent electrode generate a multi-dimensional electric field, and the semiconductor active layer and the first transparent electrode of the thin film transistor are The same metal oxide film is formed by one patterning process, wherein the first transparent electrode is obtained by metallizing the metal oxide film, and the semiconductor active layer is formed of a metal oxide film which is not metallized.
- a portion of the metal oxide film is metallized on the array substrate to exhibit a conductor characteristic to form a first transparent electrode, and a portion not subjected to metallization exhibits a semiconductor characteristic.
- a semiconductor active layer is formed.
- the semiconductor active layer and the first transparent electrode are formed by one patterning process in the same metal oxide film having the conductor characteristics and the semiconductor characteristics, and the step of separately preparing the first transparent electrode is omitted, which reduces the manufacturing cost.
- the display device may be: a product or a component having any display function, such as a liquid crystal panel, an electronic paper, an OLED panel, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, or the like.
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Abstract
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JP2015521941A JP6129312B2 (ja) | 2012-07-20 | 2012-12-13 | アレイ基板の製造方法、アレイ基板及び表示装置 |
US13/984,090 US9040344B2 (en) | 2012-07-20 | 2012-12-13 | Method for fabricating array substrate, array substrate and display device |
EP12861051.6A EP2876676B1 (en) | 2012-07-20 | 2012-12-13 | Manufacturing method of array substrate and array substrate and display device |
KR1020137019943A KR101522481B1 (ko) | 2012-07-20 | 2012-12-13 | 어레이 기판을 제조하는 방법, 어레이 기판 및 표시 장치 |
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US20140167031A1 (en) | 2014-06-19 |
US9040344B2 (en) | 2015-05-26 |
EP2876676A4 (en) | 2016-11-30 |
KR20140037808A (ko) | 2014-03-27 |
JP6129312B2 (ja) | 2017-05-17 |
KR101522481B1 (ko) | 2015-05-21 |
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