WO2013077081A1 - 半導体装置および電子機器 - Google Patents
半導体装置および電子機器 Download PDFInfo
- Publication number
- WO2013077081A1 WO2013077081A1 PCT/JP2012/074973 JP2012074973W WO2013077081A1 WO 2013077081 A1 WO2013077081 A1 WO 2013077081A1 JP 2012074973 W JP2012074973 W JP 2012074973W WO 2013077081 A1 WO2013077081 A1 WO 2013077081A1
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- WIPO (PCT)
- Prior art keywords
- active element
- semiconductor device
- electrode pad
- switching active
- source electrode
- Prior art date
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Definitions
- the present invention relates to a semiconductor device including a normally-on type switching active element and an electronic apparatus including the semiconductor device.
- field effect transistors made of GaN (gallium nitride) -based group III nitride semiconductors have been developed for various semiconductor devices because of the advantage of low on-resistance.
- GaN gallium nitride field effect transistor
- AlGaN / GaN HFET Heterojunction FET
- AlGaN / GaN HFET has attracted attention because of its features such as low on-resistance, high-speed operation, high breakdown voltage, and high heat resistance.
- AlGaN / GaN HFET is normally a normally-on field effect transistor, it is turned on when the gate voltage is 0 V, and a negative voltage must be applied to the gate to turn it off. .
- a power device is required to be a normally-off type that cuts off a current at zero bias. Therefore, there is a problem that normally-on field effect transistors such as AlGaN / GaN HFETs cannot be used as power devices as they are.
- Patent Document 1 discloses a semiconductor device for realizing a normally-off operation using a normally-on type active element.
- a normally-on field effect transistor and a normally-off field effect transistor are cascode-connected.
- the drain of the normally-on type first field effect transistor is connected to the first node, and the source of the normally-off type second field effect transistor is connected to the second node.
- a switch element is connected between the control electrode of the first field effect transistor and the second node. The switch element operates so as not to exceed the breakdown voltage of the second field effect transistor when the first field effect transistor is on while the semiconductor device is off, and the voltage of the second control electrode is predetermined. When the value is greater than or equal to the value, conduction from the first node toward the second node occurs.
- the semiconductor device configured as described above operates as a normally-off transistor that is turned on by setting the voltage of the control electrode of the second field effect transistor to a positive voltage. Then, by sealing such a semiconductor device in a package such as TO220, it is possible to provide a normally-off type field effect transistor that can operate at high voltage and high speed.
- Japanese Patent Publication Japanese Patent Laid-Open No. 2011-29386 (published on February 10, 2011)”
- the limitation of the specifications of the semiconductor device means that, for example, when switching the switching of the semiconductor device from the on state to the off state, a switching speed delay due to ringing caused by the influence of the parasitic parameter of the package, power loss in the parasitic parameter, etc. Is included.
- the package parasitic parameters are not included in the design of the semiconductor device and are determined by the package material, structure, and layout (element arrangement, wiring position, etc.), the capacitance C, the resistance R, and the inductance of the current path including the transistor. It is L.
- the rectangular wave (pulse) of the drive voltage includes harmonics. Particularly during high-speed switching, the pulse has a steep rise, and thus includes high-frequency harmonics. Then, at the portion where the impedance changes due to the parasitic parameter, the above harmonics are reflected, and all the reflected waves (having various frequencies) are stacked to cause ringing or the like. While ringing persists (while decaying), current continues to leak from the current path, which causes power loss.
- the magnitude of the influence of the parasitic parameters on the electrical characteristics of the semiconductor device depends on the planar area (projection) of the package or the semiconductor device in plan view or side view in the region inside the loop formed by the current path of the semiconductor device. Area). In other words, the magnitude of the influence of the parasitic parameter is determined by the shape and length of the current path in the three-dimensional space. The smaller the area, the smaller the influence of parasitic parameters on the semiconductor device. The most important area (loop area) of the area inside the loop is the planar area in the plan view, but the planar area in the side view cannot be ignored.
- the planar area in the side view is determined by the length in which the conductive wire forming a part of the loop is drawn in the height direction with respect to the substrate of the semiconductor device.
- the length is determined by the thickness of the mold resin (sealing resin) laminated on the semiconductor device (height according to the package standard), the performance of the conductive wire, the mounting conditions of the semiconductor device, and the like.
- the loop area of the current path varies depending on the chip size (gate length, gate width, etc.) of the switching active element (transistor). This is because changing the chip size means changing the positions of the pads such as the source and drain, so that the bonding position of the conductive wire also changes, and as a result, the loop area also changes.
- the present invention has been made in view of the above problems, and an object of the present invention is to reduce the influence of the parasitic parameters of the package on the electrical characteristics of the semiconductor device by reducing the loop area. It is an object of the present invention to provide a semiconductor device and an electronic device that make it possible.
- the semiconductor device of the present invention is mounted and sealed on a conductive substrate so that a normally-on type first switching active element and a normally-off type second switching active element are cascode-connected.
- the first switching active element has a first source electrode pad, a first drain electrode pad and a first control electrode formed on a surface thereof, and the second switching active element is formed on a surface thereof.
- a second drain electrode pad and a second control electrode, and a second source electrode pad formed on the back surface of the second switching active element which is a contact surface with the conductive substrate.
- the first control electrode is connected to the conductive substrate by a first conductive wire, and the first source electrode pad and the second drain electrode pad are connected.
- the current path passing through the conductive wire and the first control electrode is formed in a loop shape.
- the second switching active element functions as a resistor, but also the above-mentioned parasitic parameters (capacitance, resistance, inductance) exist due to the pads and wires. For this reason, ringing occurs during switching because the current path functions as a resonance circuit.
- the attenuation coefficient ⁇ of the resonance circuit expressed by the following formula is 1 or more.
- the inductance of the current path should be small. In order to realize this, the length loop of the current path only needs to be shortened, in other words, the loop area described above only needs to be reduced.
- the semiconductor device since the first source electrode pad and the second drain electrode pad are arranged in close proximity, the second conductive wire connecting them can be shortened. Thereby, since the loop area of the current path is reduced, the inductance of the current path is also reduced. Therefore, the time until the ringing converges can be shortened.
- the resistance value of the wire can be adjusted to control ringing oscillation.
- the first source electrode pad and the second drain electrode pad are arranged so as to have a line-symmetric configuration with the first conductive wire as an axis of symmetry, and the first conductive wire is symmetrical. They are connected by a second conductive wire so as to have a line-symmetric configuration as an axis.
- the plurality of current paths formed so as to pass through the first source electrode pad and the second drain electrode pad are formed in line symmetry with the first conductive wire as the axis of symmetry. Therefore, the influence of the parasitic parameters of the package on the electrical characteristics of the semiconductor device can be suppressed.
- the first switching active element includes a plurality of first source electrode pads, the same number of first drain electrode pads as the first source electrode pads, and a first control.
- the second switching active element has the same number of second drain electrode pads, second control electrodes, and surface source electrode pads as the first source electrode pads formed on the surface thereof;
- One source electrode pad and the second drain electrode pad include at least the first switching active element and the second switching element on the conductive substrate.
- the first control electrode and the surface source electrode pad are connected to each other by a first conductive wire, and the surface source electrode pad is connected to the surface source electrode pad by a first conductive wire.
- the second switching active element is electrically connected to a second source electrode pad formed on a back surface which is a contact surface with the conductive substrate, and further, the first source electrode pad and the second drain electrode pad Are arranged so as to have a line-symmetric configuration with the first conductive wire as the axis of symmetry, and are connected by a second conductive wire so as to have a line-symmetric configuration with the first conductive wire as the axis of symmetry. Has been.
- the first source electrode pad and the second drain electrode pad are arranged to have a line-symmetric configuration with the first conductive wire as the symmetry axis, and the first conductive wire as the symmetry axis. They are connected by a second conductive wire so as to have a line-symmetric configuration.
- the plurality of current paths formed so as to pass through the first source electrode pad and the second drain electrode pad are formed in line symmetry with the first conductive wire as the axis of symmetry. Therefore, the influence of the parasitic parameters of the package on the electrical characteristics of the semiconductor device can be suppressed.
- the first switching active element has the same number of first drain electrode pads and first control electrodes as the first source electrode pads formed on the surface thereof, and the second switching active element. Has a surface source electrode pad formed on the surface thereof. In the above configuration, the first control electrode and the surface source electrode pad are connected by the first conductive wire.
- the semiconductor device according to the present invention has a configuration that is easy to mount. Therefore, the manufacturing process can be made easy and simple.
- the electronic apparatus includes any one of the semiconductor devices described above as a switching element.
- the semiconductor device described above in which the influence of parasitic parameters of the package on the electrical characteristics of the semiconductor device is suppressed as the switching element of the electronic device.
- the time required to converge the voltage fluctuation at the time of switching is shortened, so that the electronic apparatus can be operated stably while suppressing power consumption.
- the semiconductor device according to the present invention is configured as described above, so that the loop area of the current path formed in the semiconductor device can be reduced. Therefore, it is possible to suppress the influence of the parasitic parameters of the package on the electrical characteristics of the semiconductor device.
- (A) is a top view which shows the structure of the semiconductor device which concerns on the 1st Embodiment of this invention
- (b) is a side view of the said semiconductor device.
- It is a circuit diagram which shows the circuit structure of the said semiconductor device.
- It is a top view which shows the structure of the semiconductor device which concerns on the modification of 1st Embodiment.
- FIG. 4 is an enlarged plan view showing a main part of the semiconductor device of FIG. 3.
- (A) is a circuit diagram showing an equivalent circuit schematically showing a current path when the semiconductor device of FIG.
- FIG. 2 is switched on
- (b) is a schematic diagram of a current path when the semiconductor device of FIG. 2 is switched off.
- It is a circuit diagram which shows the equivalent circuit represented to. 6 is a graph showing a time change in voltage at the first control electrode of the first switching active element when the semiconductor device of FIG. 1 and the semiconductor device of FIG. 5 are switched off.
- (A) is a top view which shows the structure of the semiconductor device which concerns on the 2nd Embodiment of this invention
- (b) is a side view of the said semiconductor device.
- It is a circuit diagram which shows schematic structure of the motor drive system which concerns on the 4th Embodiment of this invention.
- FIG. 9 is a circuit diagram schematically showing a current path when the semiconductor device of FIG. 8A is switched on.
- FIG. 12 is a circuit diagram schematically showing a current path when the semiconductor device of FIG. 11A is switched on.
- Embodiment 1 A semiconductor device according to Embodiment 1 of the present invention will be described with reference to FIGS.
- FIG. 1A is a plan view showing the configuration of the semiconductor device 101 according to the first embodiment of the present invention.
- FIG. 1B is a side view showing the configuration of the semiconductor device 101.
- FIG. 2 is a circuit diagram showing a circuit configuration of the semiconductor device 101.
- the semiconductor device 101 is formed of a TO220 package having three external terminals.
- the semiconductor device 101 includes a conductive substrate 102, a first switching active element 103, a second switching active element 104, first to third external terminals 121 to 123, first and second conductive wires 131 and 132, a bonding wire. 133, 134, a resin mold 141, and a heat sink 142 are provided.
- the semiconductor device 101 includes first to third external terminals 121 to 123 as three external terminals.
- the drain electrode (first drain electrode pad 124) of the first switching active element 103 is connected to the first external terminal 121.
- the source electrode (first source electrode pad 125) of the first switching active element 103 is connected to the drain electrode (second drain electrode pad 126) of the second switching active element 104.
- the gate electrode (first control electrode 129) of the first switching active element 103 is connected to the second external terminal 122 through the conductive substrate 102.
- the source electrode (second source electrode pad 127) of the second switching active element 104 is also connected to the second external terminal 122.
- the gate electrode (second control electrode 130) of the second switching active element 104 is connected to the third external terminal 123.
- the first control electrode 129 and the second external terminal 122 are connected via the first conductive wire 131 and the conductive substrate 102. Further, the first source electrode pad 125 and the second drain electrode pad 126 are connected via the second conductive wire 132. These connection structures will be described in detail later.
- the first switching active element 103 is, for example, a field effect transistor (GaN field effect transistor) having a GaN layer, and is a normally-on type.
- the second switching active element 104 is, for example, a MOS field effect transistor (MOSFET) and is a normally-off type.
- the first switching active element 103 and the second switching active element 104 are cascode-connected.
- the second switching active element 104 drives the first switching active element 103, so that the semiconductor device 101 operates as a normally-off type switching active element.
- the normally-off type second switching active element 104 When the positive control voltage is not applied to the third external terminal 123, the normally-off type second switching active element 104 is off, and the normally-on type first switching active element 103 is the second switching active element. It is in a steady state at a voltage at a drain cutoff current value of 104. This state is referred to as an off state of the semiconductor device 101.
- the potential of the first source electrode pad 125 decreases when the second switching active element 104 is turned on.
- the first switching active element 103 is turned on.
- the first external terminal 121 and the second external terminal 122 are electrically connected.
- a loop-shaped current path 140 is formed.
- a current flows in the direction 129 (indicated by an arrow).
- the entire conductive substrate 102 and one end side of the first to third external terminals 121 to 123 are covered with a resin mold 141.
- the first external terminal 121 and the third external terminal 123 are arranged so that one ends thereof are close to the conductive substrate 102 at a predetermined interval.
- the second external terminal 122 is connected to the conductive substrate 102.
- the heat sink 142 is formed integrally with the conductive substrate 102 and is provided so as to be exposed to the outside of the resin mold 141.
- the heat radiating plate 142 is provided to release the heat generated by the first switching active element 103 and the second switching active element 104 disposed on the conductive substrate 102 to the outside.
- a first switching active element 103 and a second switching active element 104 are arranged on the conductive substrate 102.
- a first drain electrode pad 124, a first source electrode pad 125, and a first control electrode 129 are formed on the surface opposite to the contact surface with the conductive substrate 102 (hereinafter referred to as a surface).
- a second drain electrode pad 126 and a second control electrode 130 are formed on the surface opposite to the contact surface with the conductive substrate 102 (hereinafter referred to as the front surface), and the contact surface (hereinafter referred to as the back surface). ), A second source electrode pad 127 is formed.
- the first source electrode pad 125 and the second drain electrode pad 126 are disposed on the conductive substrate 102 with their nearest sides facing each other.
- the first drain electrode pad 124 and the first external terminal 121 are connected by a bonding wire 133.
- the second control electrode 130 and the third external terminal 123 are connected by a bonding wire 134.
- the first source electrode pad 125 and the second drain electrode pad 126 are connected via a second conductive wire 132.
- the first control electrode 129 and the conductive substrate 102 are connected via the first conductive wire 131.
- the first source electrode pad 125 and the second drain electrode pad 126 are arranged as close as possible. Thereby, the 2nd conductive wire 132 which connects them can be shortened.
- the height of the wiring in the semiconductor device 101 is determined by the thickness of the resin mold 141, the performance of the wire, the mounting conditions, and the like. Therefore, the loop area of the current path 140 can be further reduced by arranging the second conductive wire 132 so as to fall within such a range. Therefore, in the semiconductor device 101, the influence of the parasitic parameters on the electrical characteristics can be suppressed.
- the first switching active element 103 and the second switching active element 104 satisfy the constraint condition.
- the constraint conditions include bonding accuracy of a device (die bonder) for die-bonding the first and second switching active elements 103 and 104 to the conductive substrate 102, a die-bonding material (solder, silver paste, epoxy, etc.) after die-bonding. ) And the bonding accuracy (connection accuracy) of a device (wire bonder) for bonding the first conductive wire 131 to the conductive substrate 102.
- the minimum distance is a distance that can allow such a constraint, and is a minimum distance that should be satisfied as a distance (interval) between the first and second switching active elements 103 and 104.
- first conductive wire 131 is arranged so as to be hidden directly under the second conductive wire 132 in the plan view of the semiconductor device 101 shown in FIG. 1A, and the second conductive wire 132. It is arranged to overlap. For this reason, the first control electrode 129 is disposed closer to the second switching active element 104 than the first source electrode pad 125.
- the loop area of the current path 140 in the plan view is almost zero. Therefore, in the semiconductor device 101, the influence of the parasitic parameters on the electrical characteristics can be minimized.
- FIG. 3 is a plan view showing a configuration of a semiconductor device 901 according to the modification.
- FIG. 4 is an enlarged plan view showing a main part of the semiconductor device 901.
- the semiconductor device 901 is formed of a TO220 package, similar to the semiconductor device 101.
- the semiconductor device 901 includes a conductive substrate 902, a first switching active element 903, a second switching active element 904, first to third external terminals 921 to 923, first and second conductive wires 931 and 932, bonding wires. 933, 934, a resin mold 941, and a heat sink 942.
- the second switching active element 904, the first to third external terminals 921 to 923, the bonding wires 933 and 934, the resin mold 941 and the heat sink 942 are the second switching active element 104 and the first to third switching elements 104 in the semiconductor device 101.
- the third external terminals 121 to 123, the bonding wires 133 and 134, the resin mold 141, and the heat sink 142 have the same functions. Further, the first drain electrode pad 924 and the second control electrode 930 also have the same functions as the first drain electrode pad 124 and the second control electrode 130, respectively.
- the first conductive wire 931 connects the first control electrode 929 and the conductive substrate 902, and the second conductive wire 932 includes the first source electrode pad 925 and the second drain electrode pad 926. Is connected.
- the first source electrode pad 925, the second conductive wire 932, the second drain electrode pad 926, the second source electrode pad 927, the conductive substrate 902, the first A current path 960 is formed by the one conductive wire 931 and the first control electrode 929.
- the first control electrode 929 is disposed at a position away from the first source electrode pad 925 to the second external terminal 922 side in FIG.
- the first conductive wire 931 is also disposed at a position away from the second conductive wire 932 in the above direction. Therefore, unlike the first conductive wire 131 and the second conductive wire 132, the first conductive wire 931 and the second conductive wire 932 do not overlap in a plan view of the semiconductor device 901.
- the semiconductor device 901 is more greatly affected by the parasitic characteristics than the semiconductor device 101.
- the first source electrode pad 925 can be disposed closer to the second switching active element 904 than the above-described first source electrode pad 125, the second conductive wire 932 is more than the second conductive wire 132. Can also be shortened. Therefore, with respect to the second conductive wire 932, the influence of the parasitic parameters on the electrical characteristics can be made smaller than that of the semiconductor device 101.
- FIG. 5 is a plan view showing a configuration of a semiconductor device 801 according to the modification.
- the semiconductor device 801 is formed of a TO220 package, similar to the semiconductor device 101.
- the semiconductor device 801 includes conductive substrates 802 and 802a, a first switching active element 803, a second switching active element 804, first to second external terminals 821 to 823, first and second conductive wires 831 and 832, Bonding wires 833 and 834, a resin mold 841, and a heat sink 842 are provided.
- the first to second external terminals 821 to 823, the bonding wires 833 and 834, the resin mold 841 and the heat sink 842 are the first to third external terminals 121 to 123 in the semiconductor device 101, the bonding wires 133 and 134, Each of the resin mold 141 and the heat sink 142 has the same function.
- the first switching active element 803 has the same structure as the first switching active element 903 in the semiconductor device 901. However, the arrangement position of the first switching active element 803 is different from that of the first switching active element 903.
- the second switching active element 804 is mounted on a conductive substrate 802a formed on the conductive substrate 802, and the conductive substrate 802a is mounted such that a bonding surface with the conductive substrate 802 is in an insulating state. Yes.
- the second switching active element 804 has a second source electrode pad 827 and a second control electrode 830 formed on the surface.
- the second drain electrode pad 826 is formed on the back surface of the second switching active element 804 so as to be bonded to the conductive layer on the surface of the conductive substrate 802a. Implemented. As a result, the drain potential of the second switching active element 804 is taken out by the electrode pad 826a that is in conduction with the conductive layer on the mounting surface of the conductive substrate 802a.
- the first conductive wire 831 connects the first control electrode 829 and the conductive substrate 802 and the second conductive wire 832 connects the first source electrode pad 825 and the electrode pad 826a. ing. Accordingly, in the semiconductor device 801, the first source electrode pad 825, the second conductive wire 832, the electrode pad 826a, the second drain electrode pad 826, the second source electrode pad 827, the bonding wire 835, the conductive substrate 802, A current path is formed by the first conductive wire 831 and the first control electrode 829.
- the first switching active element 803 is different from the first switching active element 103, for example, and the distance between the second conductive wire 832 and the bonding wire 835 is large. For this reason, the current path has a larger loop area than the current path 140.
- FIG. 6A is a circuit diagram illustrating an equivalent circuit of the current path 140 when the semiconductor device 101 is switched on.
- FIG. 6B is a circuit diagram illustrating an equivalent circuit of the current path 140 when the semiconductor device 101 is switched off.
- the current path 140 in FIG. 3 includes the capacitance C and the inductance L of the current path 140 itself. Further, in the current path 140, the second switching active element 104 functions in the same way as the resistor R1 when switching is on. As a result, as shown in FIG. 6A, the current path 140 forms an RLC resonance circuit when switching off. On the other hand, the current path 140 functions in the same manner as the capacitor C1 when switching off. Furthermore, in the semiconductor device 101, the above-described parasitic parameters (capacitance, resistance, inductance) exist due to pads and wires.
- the current path 140 can be regarded as forming an RLC resonance circuit (series resonance circuit).
- the attenuation coefficient ⁇ of the RLC resonant circuit is expressed by the following equation.
- R, L, and C represent the resistance, inductance, and capacitance in the current path 140, respectively.
- the inductance L of the RLC resonant circuit should be as small as possible.
- the inductance L is reduced by reducing the loop length (loop area) of the current path 140.
- the loop area of the current path should be made as small as possible in order to attenuate ringing as quickly as possible.
- FIG. 7 is a graph showing a result of simulating the time change of the voltage of the first control electrode 129 when the semiconductor device 101 is switched off.
- the delay time from the switching-off to the stabilization of the off voltage is about half, and ringing is suppressed.
- the semiconductor device 101 can suppress the influence of the parasitic parameters on the electrical characteristics depending on the configuration.
- the semiconductor device 101 is manufactured by mounting the first switching active element 103 and the second switching active element 104 on the conductive substrate 102 of the package (TO220 package) and performing wiring processing.
- the first switching active element 103 and the second switching active element 104 are arranged on the conductive substrate 102 as shown in FIG. At this time, the first source electrode pad 125 of the first switching active element 103 and the second drain electrode pad 126 of the second switching active element 104 are close to each other, and as close as possible within a range in which a problem such as a short circuit does not occur. Arranged.
- the first control electrode 129 and the first external terminal 121 are connected by the bonding wire 133. Further, the second control electrode 130 and the third external terminal 123 are connected by a bonding wire 134.
- the bonding wires 133 and 134 are, for example, conductive wires made of aluminum.
- the first control electrode 129 and the conductive substrate 102 are connected by the first conductive wire 131.
- a line for connecting the second conductive wire 132 is determined in advance, and the first conductive wire 131 is connected to a position that is assumed to be parallel to the above line.
- the first source electrode pad 125 and the second drain electrode pad 126 are connected by the second conductive wire 132.
- the second conductive wire 132 is connected to be perpendicular to the opposing direction of the first source electrode pad 125 and the second drain electrode pad 126 in the plan view of the semiconductor device 101. At this time, it is desirable to connect the second conductive wire 132 so that the length when viewed from above the package is as short as possible.
- the 2nd conductive wire 132 is connected through the upper direction of the 1st conductive wire 131 arrange
- the second control electrode 130 and the third external terminal 123 are connected by the bonding wire 134. Further, the first drain electrode pad 124 and the first external terminal 121 are connected by a bonding wire 133. Finally, the sealing region including the conductive substrate 102 is sealed with the resin mold 141.
- the semiconductor device 101 is completed through the above steps.
- FIG. 8A is a plan view showing a configuration of a semiconductor device 201 according to the second embodiment of the present invention.
- FIG. 8B is a side view of the semiconductor device 201.
- the semiconductor device 201 is formed of a TO220 package, like the semiconductor device 101.
- the semiconductor device 201 includes a conductive substrate 202, a first switching active element 203, a second switching active element 204, first to third external terminals 221 to 223, a first conductive wire 231, a second conductive wire 232a, 232b, bonding wires 233a and 233b, bonding wire 234, resin mold 241 and heat sink 242 are provided.
- the first to third external terminals 221 to 223, the bonding wire 234, the resin mold 241 and the heat sink 242 are the first to third external terminals 121 to 123, the bonding wire 134, the resin mold 141 and the heat sink 242 in the semiconductor device 101.
- Each of the radiator plates 142 has the same function. Therefore, detailed description thereof is omitted here.
- the first switching active element 203 has two first source electrode pads 225a and 225b and two first drain electrode pads 224a and 224b.
- the first switching active element 203 includes a first control electrode 229.
- the first source electrode pads 225 a and 225 b are arranged symmetrically with respect to the center line A passing through the first external terminal 221.
- the first drain electrode pads 224a and 224b are arranged symmetrically with respect to the center line A between the first source electrode pads 225a and 225b.
- the first control electrode 229 is disposed on the side closer to the second switching active element 204 on the center line A.
- the second switching active element 204 includes a second drain electrode pad 226, a second source electrode pad 227, and a second control electrode 230.
- the second drain electrode pad 226 has a shape (rectangular shape) that is symmetric with respect to the center line A, and is disposed so as to occupy most of the surface of the second switching active element 204.
- the second source electrode pad 227 is disposed on the contact surface with the conductive substrate 202 (surface opposite to the surface). Further, the second control electrode 230 is disposed on the side of the surface of the second switching active element 204 close to the third external terminal 223.
- the bonding wires 233a and 233b are arranged in parallel with the center line A, and connect the first drain electrode pads 224a and 224b and the first external terminal 221 respectively.
- the bonding wire 234 connects the second control electrode 230 and the third external terminal 223.
- the first conductive wire 231 connects the first control electrode 229 and the conductive substrate 202.
- the second conductive wire 232a connects the first source electrode pad 225a and the second drain electrode pad 226.
- the second conductive wire 232b connects the first source electrode pad 225b and the second drain electrode pad 226.
- the first source electrode pad 225a, the second conductive wire 232a, the second drain electrode pad 226, the second source electrode pad 227, the conductive substrate 202, the first conductive wire 231 and the first is formed by one control electrode 229. Further, the first source electrode pad 225b, the second conductive wire 232b, the second drain electrode pad 226, the second source electrode pad 227, the conductive substrate 202, the first conductive wire 231 and the first control electrode 229 are the second. A current path is formed.
- the first source electrode pads 225a and 225b and the second drain electrode pad 226 are arranged close to each other. Thereby, the 2nd conductive wires 232a and 232b can be shortened.
- the interval between the first switching active element 203 and the second switching active element 204 is limited.
- the arrangement is as narrow as possible with the minimum distance that satisfies the conditions.
- the constraint conditions include bonding accuracy of a device (die bonder) for die-bonding the first and second switching active elements 203 and 204 to the conductive substrate 202, a die-bonding material (solder, silver paste, epoxy, etc.) after die-bonding. ) And the bonding accuracy (connection accuracy) of a device (wire bonder) for bonding the first conductive wire 231 to the conductive substrate 202.
- the minimum distance is a distance that can allow such a constraint condition, and is a minimum distance that should be satisfied as a distance (interval) between the first and second switching active elements 203 and 204.
- FIG. 10 shows a circuit diagram of the current path 240 formed in the semiconductor device 201.
- the current path 240 is formed as the two first current paths and the second current path as described above.
- the current path 240 is shown as one current path 240, but the current path 240 may be regarded as either the first current path or the second current path.
- the loop areas of these current paths are the same due to the symmetry of the wiring as described above.
- the first control electrode 229 is disposed at a position shifted from the center line A, the first current path and the second current path are asymmetric with respect to the center line A. In this case, since one of the first current path and the second current path has a loop area larger than the other, it is likely to be affected by the electrical characteristics due to the parasitic parameters.
- the first conductive wire 231 is not between the two second conductive wires 232a and 232b. It will be arranged outside.
- the first current path and the second current path are asymmetric with respect to the center line A, and the loop area is unbalanced.
- first conductive wire 231 shared by the first and second current paths is arranged on the center line A, even if a voltage is applied to the first conductive wire 231, There is no inconvenience.
- first and second current paths 240 are asymmetric with respect to the center line A as described above, when a voltage is applied to the first conductive wire 231, the first and second current paths 240 Unexpected vibration may occur due to the difference in resonance frequency.
- the semiconductor device 201 of the present embodiment has a configuration in which the symmetry of the wiring is ensured, so that the influence on the electrical characteristics due to the parasitic parameters of the package is suppressed.
- the semiconductor device 201 can have three or more current paths.
- the first switching active element 203 is provided with three or more first source electrode pads and three first drain electrode pads.
- the first switching active element 203 is also provided with the same number of second conductive wires as the first source electrode pads that connect the first source electrode pads and the second drain electrode pads.
- the second conductive wire is disposed symmetrically and parallel to the center line A. However, when there are an odd number of second conductive wires, one is arranged on the center line A.
- FIG. 11A is a plan view showing a configuration of a semiconductor device 401 according to an embodiment of the present invention.
- FIG. 11B is a side view showing the configuration of the semiconductor device 401.
- FIG. 12 is a circuit diagram illustrating a circuit configuration of the semiconductor device 401.
- the semiconductor device 401 is formed of a TO220 package having three external terminals.
- the semiconductor device 401 includes a conductive substrate 402, a first switching active element 403, a second switching active element 404, first and second conductive wires 431 and 432, bonding wires 433 and 434, a resin mold 441, and a heat dissipation plate 442. It has.
- the semiconductor device 401 includes first to third external terminals 421 to 423 as three external terminals.
- the first switching active element 403 is, for example, a field effect transistor (GaN field effect transistor) having a GaN layer, and is a normally-on type.
- the second switching active element 404 is, for example, a MOS field effect transistor (MOSFET) and is a normally-off type.
- the entire conductive substrate 402 and one end side of the first to third external terminals 421 to 423 are covered with a resin mold 441.
- the first external terminal 421 and the third external terminal 423 are not connected to the conductive substrate 402, and the surface on which the chip (die) 402 is mounted is downset.
- the second external terminal 422 is downset while being integrated with the conductive substrate 402.
- the heat sink 442 is formed integrally with the conductive substrate 402 and is provided so as to be exposed to the outside of the resin mold 441.
- the heat radiating plate 442 is provided to release the heat generated by the first switching active element 403 and the second switching active element 404 disposed on the conductive substrate 402 to the outside.
- a first switching active element 403 and a second switching active element 404 are disposed on the conductive substrate 402.
- the first switching active element 403 includes two first drain electrode pads 424 and the same number of first sources as the first drain electrode pads 424 on a surface opposite to the contact surface with the conductive substrate 402 (hereinafter referred to as a surface).
- An electrode pad 425 and a first control electrode 429 are formed.
- the second switching active element 404 has the same number as the second control electrode 430, the surface source electrode pad 428, and the first source electrode pad 425 on the surface opposite to the contact surface with the conductive substrate 402 (hereinafter referred to as a surface).
- (Two) second drain electrode pads 426 are formed.
- a second source electrode pad 427 is formed on the contact surface (hereinafter referred to as the back surface) as shown in FIG.
- the first source electrode pad 425 and the second drain electrode pad 426 are disposed on the conductive substrate 402 with their closest sides facing each other. Further, the first drain electrode pad 424 and the first external terminal 421 are connected by two bonding wires 433. Further, the second control electrode 430 and the third external terminal 423 are connected by a bonding wire 434. The second source electrode pad 427 and the surface source electrode pad 428 are electrically connected through the second switching active element 404.
- the first control electrode 429 and the surface source electrode pad 428 are connected via the first conductive wire 431.
- Two first source electrode pads 425 and two second drain electrode pads 426 are connected in line symmetry with the first conductive wire 431 as the central axis via the second conductive wire 432, respectively.
- first source electrode pad 425 and the second drain electrode pad 426 are arranged so as to have a line-symmetric configuration with the first conductive wire 431 as the axis of symmetry. Further, the first source electrode pad 425 and the second drain electrode pad 426 are connected by the second conductive wire 432 so as to have a line symmetric configuration with the first conductive wire 431 as the axis of symmetry.
- the first control electrode 429 and the surface source electrode pad 428 are connected via the first conductive wire 431.
- the first source electrode pad 425, the second conductive wire 432, the second drain electrode pad 426, the surface source electrode pad 428, the first conductive wire 431, and the first control electrode In the plan view of the first switching active element 403 and the second switching active element 404 in which two loop-shaped current paths (first and second current paths) passing through 429 are cascode-connected, the first conductive wire 431 Are symmetrically formed with respect to each other.
- the first switching active element 403 and the second switching active element 404 are arranged as much as possible so that the first source electrode pad 425 and the second drain electrode pad 426 are arranged as close as possible. It is mounted close. That is, they are mounted with a minimum distance satisfying the constraint condition.
- the constraint condition of the semiconductor device 401 is determined from the mounting accuracy of the first and second switching active elements 403 and 404 on the conductive substrate 402 by the die bonder.
- the second conductive wire 432 is wired as low as possible within the limits of wiring.
- the restriction of the wiring is a restriction on the height of the wiring in the semiconductor device 401, and is a restriction determined by the thickness of the resin mold 441, the performance of various wires, mounting conditions, and the like.
- the distance between the first switching active element 403 and the second switching active element 404 is narrowed to the limit of the above-mentioned constraint condition, and at the same time, the wiring height is reduced as much as possible.
- the length of the second conductive wire 432 is the shortest. As a result, the loop area of the current path is reduced, so that the influence of the parasitic parameters on the electrical characteristics can be minimized.
- FIG. 12 shows a circuit diagram of a current path 440 represented as the first and second current paths.
- the difference of the circuit of the current path 440 from the circuit of the current path 240 of the previous embodiment is that the conductive substrate 402 is not included in the circuit.
- the drain electrode (first drain electrode pad 424) of the first switching active element 403 is connected to the first external terminal 421.
- the source electrode (first source electrode pad 425) of the first switching active element 403 is connected to the drain electrode (second drain electrode pad 426) of the second switching active element 404.
- the gate electrode (first control electrode 429) of the first switching active element 403 is connected to the surface source electrode (surface source electrode pad 428) of the second switching active element 404.
- Another source electrode (second source electrode pad 427) of the second switching active element 404 is connected to the second external terminal 422 through the conductive substrate 402.
- the gate electrode (second control electrode 430) of the second switching active element 404 is connected to the third external terminal 423.
- the first control electrode 429 and the surface source electrode pad 428 are connected by a first conductive wire 431.
- the first source electrode pad 425 and the second drain electrode pad 426 are connected via the second conductive wire 432.
- the current source 440 includes the first source electrode pad 425, the second conductive wire 432, the second drain electrode pad 426, the surface source electrode pad 428, the first conductive wire 431, and the first conductive wire 431.
- Two loop-shaped current paths 440 that pass through one control electrode 429 are formed at positions that are line-symmetric with respect to each other about the first conductive wire 431 in the plan view of the semiconductor device 401. As a result, the loop areas and shapes of the two current paths 440 are equal.
- the loop area of the current path 440 is a projected area of the current path 440 in plan view or side view. If the loop areas of the two current paths 440 have different areas or shapes, the electric characteristics are easily affected by the parasitic parameters. In the present embodiment, since the current path 440 is formed so as to be line-symmetric with respect to the first conductive wire 431, these loop areas are equal and hardly affected by the electrical characteristics due to the parasitic parameters.
- one end of the first conductive wire 231 is connected to the first switching active element 203 as shown in FIGS. 8A and 8B in the previous embodiment.
- the first and second switching active elements 203 and 204 are made closer to each other as compared with the configuration in which the second switching active element 204 is dropped and connected on the conductive substrate 202 (hereinafter referred to as configuration X). be able to. Therefore, the loop area of the current path 440 can be made smaller than the loop area of the current path 240, and as a result, ringing can be further suppressed. The reason for this will be described below.
- between chips the area between the first switching active element and the second switching active element is referred to as “between chips”.
- the first and second switching active elements are connected (die-bonded) to the conductive substrate by a material (die-bonding material) such as solder, silver paste, or epoxy as an insulating material. Therefore, the above-mentioned constraints, that is, the bonding accuracy of the die bonding device (die bonder), the spread of the die bonding material after die bonding, and the bonding accuracy of the device (wire bonder) for bonding the first conductive wire between the chips ( The distance between chips must be designed in consideration of the connection accuracy).
- the bonding accuracy of the wire bonder includes the thickness of the first and second switching active elements, the thickness of the wire bonder tool, and the accuracy of the wire bonder itself.
- the semiconductor device 401 of this embodiment it is not necessary to consider the above matters. This is because the first conductive wire 431 having one end connected to the first control electrode 429 is connected to the surface source electrode pad 428 formed on the surface of the second switching active element 404 and the other end is connected to the first control electrode 429. This is because it is not connected to the substrate 402. Therefore, as compared with the configuration X, the above matters need not be considered (although the mounting accuracy of the first and second switching active elements 403 and 404 on the conductive substrate 402 by the die bonder needs to be considered). The distance between the chips can be reduced.
- the first conductive wire 431 is connected to the surface source electrode pad 428 so that the first conductive wire 431 is connected to the conductive substrate 402 between the chips. There is no need to connect. Therefore, the distance between chips, that is, the distance between the first and second switching active elements 403 and 404 can be reduced as compared with the configuration X in which the first conductive wire is connected to the conductive substrate. Further, there is an advantage that a manufacturing process for cleaning the surface of the conductive substrate 402 for wire bonding is not necessary. That is, the semiconductor device 401 has a simpler mounting process than that of the configuration X, and thus has a configuration that is easy to mount.
- FIG. 9 is a circuit diagram showing a configuration of the motor drive system 301 according to the present embodiment.
- the motor drive system 301 generates a three-phase AC voltage from the AC voltage of the AC power supply 302 by the three-phase AC voltage generation unit 303 and applies it to the motor 304 (three-phase AC motor). It is configured.
- the three-phase AC voltage generation unit 303 includes a coil 311, a rectifier 312, a smoothing capacitor 313, an inverter 314, a driver 315, and a control unit 316.
- the rectifier 312 performs full-wave rectification on the AC voltage received from the AC power supply 302 via the coil 311.
- the smoothing capacitor 313 smoothes the AC voltage rectified by the rectifier 312.
- the inverter 314 (electronic device) includes switching elements SW1 to SW6, switching elements SW1 and SW2, switching elements SW3 and SW4, and switching elements SW5 and SW6 connected in series between both ends of the smoothing capacitor 313, respectively. Yes.
- the diodes D1 to D6 are connected between both ends of the switching elements SW1 to SW6, respectively.
- the switching elements SW1 to SW6 are configured by any one of the semiconductor devices 101, 201, and 901 described above.
- the switching elements SW1 to SW6 in the inverter 314 convert the DC voltage smoothed by the smoothing capacitor 313 into a U-phase, V-phase, and W-phase three-phase AC voltage by switching based on the drive signal from the driver 315.
- the motor 304 To the motor 304. The motor 304 is rotated by this three-phase AC voltage.
- the control unit 316 outputs a control signal given to the driver 315 based on a three-phase AC voltage detected by an output voltage detector (not shown).
- the driver 315 outputs a drive signal based on the control signal.
- the semiconductor device is a semiconductor device that is mounted on a conductive substrate and sealed so that the first switching active element that is normally on and the second switching active element that is normally off are cascode-connected.
- the first switching active element has a first source electrode pad, a first drain electrode pad, and a first control electrode formed on a surface thereof, and the second switching active element is formed on a surface thereof.
- a second source electrode pad formed on the back surface of the second switching active element, which is a contact surface with the conductive substrate, and has the first drain electrode pad and the second control electrode.
- the control electrode is connected to the conductive substrate by a first conductive wire, and the first source electrode pad and the second drain electrode pad are connected. The de is disposed close positions, they are connected by a second conductive wires.
- the semiconductor device according to the present embodiment can be expressed as follows.
- the first semiconductor device of this embodiment is mounted and sealed on a conductive substrate so that a normally-on type first switching active element and a normally-off type second switching active element are cascode-connected.
- the first switching active element has a first source electrode pad, a first drain electrode pad, and a first control electrode formed on a surface thereof, and the second switching active element is And a second drain electrode pad and a second control electrode formed on the front surface, and a second source electrode pad formed on the back surface of the second switching active element, which is a contact surface with the conductive substrate.
- the first control electrode is connected to the conductive substrate by a first conductive wire, and the first source electrode pad and the second drain are connected.
- the electrode pad is the minimum that allows at least the mounting accuracy of mounting the first switching active element and the second switching active element on the conductive substrate and the connection accuracy of the first conductive wire to the conductive substrate. It arrange
- the first semiconductor device is preferably formed at a position where the first conductive wire is hidden under the second conductive wire in a plan view of the semiconductor device.
- the loop area (projected area) of the current path in the plan view is minimized (nearly zero).
- the influence of the parasitic parameters on the electrical characteristics of the semiconductor device can be suppressed.
- a plurality of the first source electrode pads are provided and arranged at positions symmetrical to the first conductive wire, and the second conductive wire is connected to the first source. It is preferable that the same number as the electrode pad is provided and arranged at a position symmetrical to the first conductive wire.
- the semiconductor device includes a plurality of current paths formed by using a plurality of first source electrode pads and a plurality of second conductive wires corresponding to the first source electrode pads. Moreover, these are arrange
- the second semiconductor device of the present embodiment is mounted on a conductive substrate so that the normally-on type first switching active element and the normally-off type second switching active element are cascode-connected.
- the first switching active element has a plurality of first source electrode pads, the same number of first drain electrode pads as the first source electrode pads, and a first switching element formed on a surface thereof.
- the second switching active element has a control electrode, and has the same number of second drain electrode pads, second control electrodes, and surface source electrode pads as the first source electrode pads formed on the surface thereof.
- the first source electrode pad and the second drain electrode pad include at least the first switching active element and the second switch on the conductive substrate.
- the first control electrode and the surface source electrode pad are connected to each other by a first conductive wire, and are arranged close to each other at a minimum distance that allows mounting accuracy for mounting the active element.
- the pad is arranged so as to have a line-symmetric configuration with the first conductive wire as the axis of symmetry, and the second conductive wire has a line-symmetric configuration with the first conductive wire as the axis of symmetry. It is connected.
- the first switching active element is a field effect transistor having a GaN layer
- the second switching active element is a MOS type field effect transistor.
- the first switching active element is a field effect transistor having a GaN layer having excellent properties such as high breakdown voltage, high speed operation, high heat resistance, and low on-resistance.
- the present invention can be particularly suitably used for electronic devices such as refrigerators and air conditioners.
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Abstract
Description
本発明の実施形態1に係る半導体装置を、図1~図7に従って説明する。
図1の(a)は、本発明の第1の実施形態に係る半導体装置101の構成を示す平面図である。図1の(b)は、半導体装置101の構成を示す側面図である。図2は、半導体装置101の回路構成を示す回路図である。
ここで、本実施形態の変形例について説明する。
続いて、本実施形態の比較例について説明する。
上記電流経路140におけるループ面積とリンギングの減衰との関係について説明する。
上記減衰係数ζが1以上であれば、電流経路140の発振は抑えられる。また、減衰係数ζの値が大きいほど、電流経路140に発生したリンギングが早く落ち着く(減衰する)ことが分かっている。
図7は、半導体装置101について、スイッチングオフ時における第1制御電極129の電圧の時間変化をシミュレーションした結果を示すグラフである。
前記のように、半導体装置101は、パッケージ(TO220パッケージ)の導電性基板102上に第1スイッチング能動素子103および第2スイッチング能動素子104を実装し、配線処理をすることによって作製される。
本発明の他の実施形態について、図8の(a)および(b)と図10とにしたがって説明する。
図10に、半導体装置201において形成される電流経路240の回路図を示す。
本発明の一実施形態に係る半導体装置を、図11の(a)および(b)と図12とに従って説明する。
図11の(a)は、本発明の一実施形態に係る半導体装置401の構成を示す平面図である。図11の(b)は、半導体装置401の構成を示す側面図である。また、図12は、半導体装置401の回路構成を示す回路図である。
図12に第1および第2電流経路として表される電流経路440の回路図を示す。前実施形態の電流経路240の回路に対する電流経路440の回路の差異は、導電性基板402が回路に含まれないことである。
本実施形態に係る半導体装置401の構成によれば、前実施形態で図8の(a)および(b)に示したような、第1導電性ワイヤー231の一端を第1スイッチング能動素子203と第2スイッチング能動素子204との間の導電性基板202上に落として接続する構成(以下、構成Xと呼ぶ)と比較して、上記第1および第2スイッチング能動素子203,204を互いにより近づけることができる。したがって、電流経路440のループ面積を電流経路240のループ面積よりも小さくでき、その結果リンギングをより抑えることができる。この理由について、以下に説明する。
本発明のさらに他の実施形態について、図9にしたがって説明する。
なお、本実施形態は、下記のようにも表現できる。
以上で実施形態の説明を終えるが、本発明は上述した各実施形態に限定されるものではなく、請求項に示した範囲で種々の変更が可能であり、異なる実施形態にそれぞれ開示された技術的手段を適宜組み合わせて得られる実施形態についても本発明の技術的範囲に含まれると考えられるべきである。
102 導電性基板
103 第1スイッチング能動素子
104 第2スイッチング能動素子
121 第1外部端子
122 第2外部端子
123 第3外部端子
124 第1ドレイン電極パッド
125 第1ソース電極パッド
126 第2ドレイン電極パッド
127 第2ソース電極パッド
129 第1制御電極
130 第2制御電極
131 第1導電性ワイヤー
132 第2導電性ワイヤー
133 ボンディングワイヤー
134 ボンディングワイヤー
140 電流経路
141 樹脂モールド
201 半導体装置
202 導電性基板
203 第1スイッチング能動素子
204 第2スイッチング能動素子
221 第1外部端子
222 第2外部端子
223 第3外部端子
224 第1ドレイン電極パッド
224a 第1ドレイン電極パッド
224b 第1ドレイン電極パッド
225a 第1ソース電極パッド
225b 第1ソース電極パッド
226 第2ドレイン電極パッド
227 第2ソース電極パッド
229 第1制御電極
230 第2制御電極
231 第1導電性ワイヤー
232a 第2導電性ワイヤー
232b 第2導電性ワイヤー
233a ボンディングワイヤー
233b ボンディングワイヤー
234 ボンディングワイヤー
240 電流経路
241 樹脂モールド
401 半導体装置
402 導電性基板
403 第1スイッチング能動素子
404 第2スイッチング能動素子
421 第1外部端子
422 第2外部端子
423 第3外部端子
424 第1ドレイン電極パッド
425 第1ソース電極パッド
426 第2ドレイン電極パッド
427 第2ソース電極パッド
428 表面ソース電極パッド
429 第1制御電極
430 第2制御電極
431 第1導電性ワイヤー
432 第2導電性ワイヤー
433 ボンディングワイヤー
434 ボンディングワイヤー
440 電流経路
441 樹脂モールド
301 モータ駆動システム
314 インバータ(電子機器)
901 半導体装置
902 導電性基板
903 第1スイッチング能動素子
904 第2スイッチング能動素子
921 第1外部端子
922 第2外部端子
923 第3外部端子
924 第1ドレイン電極パッド
925 第1ソース電極パッド
926 第2ドレイン電極パッド
927 第2ソース電極パッド
929 第1制御電極
930 第2制御電極
931 第1導電性ワイヤー
932 第2導電性ワイヤー
933 ボンディングワイヤー
934 ボンディングワイヤー
941 樹脂モールド
960 電流経路
SW1~SW6 スイッチング素子
Claims (6)
- ノーマリオン型である第1スイッチング能動素子とノーマリオフ型である第2スイッチング能動素子とがカスコード接続されるように導電性基板の上に実装されて封止された半導体装置であって、
上記第1スイッチング能動素子は、その表面に形成された、第1ソース電極パッド、第1ドレイン電極パッドおよび第1制御電極を有し、
上記第2スイッチング能動素子は、その表面に形成された第2ドレイン電極パッドおよび第2制御電極を有するとともに、上記第2スイッチング能動素子における上記導電性基板との接触面となる裏面に形成された第2ソース電極パッドを有し、
上記第1制御電極は、第1導電性ワイヤーによって上記導電性基板と接続され、
上記第1ソース電極パッドと上記第2ドレイン電極パッドとは、少なくとも上記導電性基板に上記第1スイッチング能動素子および上記第2スイッチング能動素子を搭載する搭載精度および上記第1導電性ワイヤーの上記導電性基板への接続精度を許容しうる最小距離で近接した位置に配置されており、第2導電性ワイヤーによって接続されていることを特徴とする半導体装置。 - 上記半導体装置の平面視において、上記第1導電性ワイヤーが上記第2導電性ワイヤーの真下に隠れる位置に形成されていることを特徴とする請求項1に記載の半導体装置。
- 上記第1ソース電極パッドは、複数設けられ、上記第1導電性ワイヤーに対して対称な位置に配置されており、
上記第2導電性ワイヤーは、上記第1ソース電極パッドと同数設けられ、上記第1導電性ワイヤーに対して対称な位置に配置されていることを特徴とする請求項1に記載の半導体装置。 - ノーマリオン型である第1スイッチング能動素子とノーマリオフ型である第2スイッチング能動素子とがカスコード接続されるように導電性基板の上に実装されて封止された半導体装置であって、
第1スイッチング能動素子は、その表面に形成された、複数の第1ソース電極パッド、上記第1ソース電極パッドと同数の第1ドレイン電極パッド、および第1制御電極を有し、
上記第2スイッチング能動素子は、その表面に形成された、上記第1ソース電極パッドと同数の第2ドレイン電極パッド、第2制御電極および表面ソース電極パッドを有し、
上記第1ソース電極パッドと上記第2ドレイン電極パッドとは、少なくとも上記導電性基板に上記第1スイッチング能動素子および上記第2スイッチング能動素子を搭載する搭載精度を許容しうる最小距離で近接した位置に配置され、
上記第1制御電極と上記表面ソース電極パッドとは、第1導電性ワイヤーによって接続され、
上記表面ソース電極パッドは、上記第2スイッチング能動素子において上記導電性基板との接触面となる裏面に形成された第2ソース電極パッドと電気的に接続され、
さらに、上記第1ソース電極パッドと上記第2ドレイン電極パッドとは、上記第1導電性ワイヤーを対称軸として線対称の構成となるように配置され、かつ上記第1導電性ワイヤーを対称軸として線対称の構成となるように第2導電性ワイヤーによって接続されていることを特徴とする半導体装置。 - 上記第1スイッチング能動素子はGaN層を有する電界効果トランジスタであり、
上記第2スイッチング能動素子はMOS型の電界効果トランジスタであることを特徴とする請求項1から4までのいずれか1項に記載の半導体装置。 - 請求項1から5までのいずれか1項に記載の半導体装置をスイッチング素子として備えていることを特徴とする電子機器。
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CN201280057121.9A CN103946978B (zh) | 2011-11-24 | 2012-09-27 | 半导体装置以及电子设备 |
US14/359,382 US9129838B2 (en) | 2011-11-24 | 2012-09-27 | Semiconductor device and electronic apparatus |
JP2013545832A JP5813781B2 (ja) | 2011-11-24 | 2012-09-27 | 半導体装置および電子機器 |
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JP2015008431A (ja) * | 2013-06-25 | 2015-01-15 | 株式会社東芝 | 半導体装置 |
WO2016002473A1 (ja) * | 2014-07-01 | 2016-01-07 | シャープ株式会社 | 半導体装置 |
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JP6406815B2 (ja) | 2013-11-29 | 2018-10-17 | 株式会社東芝 | 半導体装置 |
CN104716128B (zh) | 2013-12-16 | 2019-11-22 | 台达电子企业管理(上海)有限公司 | 功率模块、电源变换器以及功率模块的制造方法 |
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CN103946978A (zh) | 2014-07-23 |
JP5813781B2 (ja) | 2015-11-17 |
JPWO2013077081A1 (ja) | 2015-04-27 |
TW201324744A (zh) | 2013-06-16 |
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US20140306238A1 (en) | 2014-10-16 |
CN103946978B (zh) | 2017-03-01 |
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