WO2012147286A1 - Pfc信号生成回路、それを用いたpfc制御システム、及びpfc制御方法 - Google Patents
Pfc信号生成回路、それを用いたpfc制御システム、及びpfc制御方法 Download PDFInfo
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- WO2012147286A1 WO2012147286A1 PCT/JP2012/002416 JP2012002416W WO2012147286A1 WO 2012147286 A1 WO2012147286 A1 WO 2012147286A1 JP 2012002416 W JP2012002416 W JP 2012002416W WO 2012147286 A1 WO2012147286 A1 WO 2012147286A1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
- H02M1/4208—Arrangements for improving power factor of AC input
- H02M1/4225—Arrangements for improving power factor of AC input using a non-isolated boost converter
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
- H02M1/4208—Arrangements for improving power factor of AC input
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0067—Converter structures employing plural converter units, other than for parallel operation of the units on a single load
- H02M1/007—Plural converter units in cascade
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
- H02M3/1584—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load with a plurality of power processing stages connected in parallel
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
- H02M3/1584—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load with a plurality of power processing stages connected in parallel
- H02M3/1586—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load with a plurality of power processing stages connected in parallel switched with a phase shift, i.e. interleaved
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
- H05B45/30—Driver circuits
- H05B45/37—Converter circuits
- H05B45/3725—Switched mode power supply [SMPS]
- H05B45/375—Switched mode power supply [SMPS] using buck topology
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
- H05B45/30—Driver circuits
- H05B45/37—Converter circuits
- H05B45/3725—Switched mode power supply [SMPS]
- H05B45/38—Switched mode power supply [SMPS] using boost topology
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
- H05B45/30—Driver circuits
- H05B45/37—Converter circuits
- H05B45/3725—Switched mode power supply [SMPS]
- H05B45/385—Switched mode power supply [SMPS] using flyback topology
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Definitions
- the present invention relates to a PFC signal generation circuit, a PFC control system using the same, and a PFC control method.
- a so-called switching power supply using a switching circuit that is periodically turned on and off is frequently used due to demands for downsizing electronic devices and reducing power consumption.
- a switching power supply for example, by using PWM (Pulse Width ⁇ Modulation) control that adjusts the duty ratio of an input pulse signal, the output voltage can be adjusted according to the operating state of the electronic device.
- PWM Pulse Width ⁇ Modulation
- PFC control includes a single method and an interleave method.
- switching operations are complementarily performed by two PFC control pulse signals having a phase difference of ⁇ (180 °).
- ⁇ 180 °
- two coil currents having a phase difference ⁇ are generated. Therefore, the interleave method can obtain twice as much power as the single method. Further, since the ripple of the output current is small, the capacitance of the capacitor for reducing this can be reduced.
- Patent Document 1 discloses a switching power supply that employs critical mode interleaved PFC control.
- Patent Document 1 only a zero current in one coil current is detected, and a PFC control pulse signal having a phase difference of ⁇ is automatically generated, and a zero current in two coil currents is detected and two PFCs are detected.
- a technique for generating a control pulse signal is disclosed. In the latter case, since the critical mode can be guaranteed for both coil currents, the efficiency is improved.
- Patent Document 2 discloses a watchdog timer that detects that a clear signal is input within a certain period of time as the program is executed and outputs a reset signal to the computer to notify the abnormality. ing.
- the watchdog timer includes signal control means for permitting the input of the clear signal only for a set time before the end of the predetermined time.
- Patent Document 1 when the zero current in the coil current is detected, there is a possibility that the period of the PFC control pulse signal becomes too small due to noise or the like. Such an abnormal PFC control pulse signal may increase power loss and reduce the power factor.
- a PFC signal generation circuit generates a PFC signal that controls a PFC circuit having a first inductor connected to a first switch and a second inductor connected to a second switch. It is a PFC signal generation circuit. Based on the first timing at which the zero current of the first inductor is detected, and when the count value is cleared and the first timing falls below the cycle lower limit value, after waiting until the cycle lower limit value A counter clear control circuit that clears the count value, a first control signal output unit that outputs a first PFC signal that turns on the first switch at a timing when the count value is cleared, and a second inductor And a second control signal output unit that outputs a second PFC signal that turns on the second switch based on a second timing at which zero current is detected.
- the PFC control system is a PFC control system including a PFC circuit connected to an AC power source and a PFC signal generation circuit that generates a PFC signal for controlling the PFC circuit.
- the PFC circuit includes a first inductor connected to the first switch, and a second inductor connected to the second switch.
- the PFC signal generation circuit includes a counter that clears the count value based on the first timing at which the zero current of the first inductor is detected, and the first cycle timing lower than the cycle lower limit value.
- a counter clear control circuit that clears the counter value after waiting until the value, a first control signal output unit that outputs a first PFC signal that turns on the first switch at a timing when the count value is cleared, And a second control signal output unit that outputs a second PFC signal for turning on the second switch based on a second timing at which the zero current of the second inductor is detected.
- the PFC control method is a PFC control method for controlling a PFC circuit having a first inductor connected to a first switch and a second inductor connected to a second switch. Based on the first timing at which the zero current of the first inductor is detected, the count value of the counter is cleared, and at the timing when the count value is cleared, the first switch is turned on and the second inductor zero Based on the second timing at which the current is detected, when the second switch is turned on and the count value of the counter is cleared, if the first timing falls below the cycle lower limit value, it waits until the cycle lower limit value. Then clear the counter value.
- the count value of the counter when the count value of the counter is cleared, if the timing at which the zero current of the first inductor is detected falls below the cycle lower limit value, the counter value is cleared after waiting for the cycle lower limit value. .
- the cycle lower limit value of the first PFC signal serving as a reference is guaranteed. Therefore, the power factor improvement by the PFC circuit can be further improved.
- FIG. 1 It is the schematic of processor system MCU to which the PWM signal generation unit concerning this embodiment is applied. It is a circuit diagram of the power supply circuit which drives LED. It is a circuit diagram of the power supply circuit which drives LED. It is a circuit diagram which shows the other structural example of a DC / DC unit. It is a circuit diagram which shows the other structural example of a DC / DC unit. It is a circuit diagram which shows the other structural example of a PFC unit. It is a circuit diagram which shows the other structural example of the power supply circuit which drives LED. It is a circuit diagram which shows the other structural example of the power supply circuit which drives LED. 3 is a block diagram of a PFC signal generation unit PSG according to Embodiment 1. FIG.
- 2 is a circuit diagram showing an example of a specific circuit configuration of a counter clear control circuit 202.
- FIG. 6 is a timing chart for explaining the operation of the counter clear control circuit 202. It is a timing chart for demonstrating the production
- 5 is a flowchart showing a processing flow of an output timing correction circuit 113. It is a timing chart for demonstrating the production
- FIG. 1 is a schematic diagram of a processor system MCU to which a PWM signal generation unit according to the present embodiment is applied.
- the processor system MCU includes a memory MEM, a calculation core PE, a clock generation unit CG, a PWM signal generation unit PWM, a PFC signal generation unit PSG, a monitor unit MON, an IO unit IOU, and a peripheral circuit PERI. .
- FIG. 1 also shows a control target circuit PWR controlled by the processor system MCU.
- the control target circuit PWR is, for example, a power supply circuit.
- the power supply circuit generates a DC power supply voltage from the AC power supply voltage with high efficiency based on the PFC control pulse signal pfc generated by the PFC signal generation unit PSG (AC / DC conversion). Further, based on the PWM control pulse signal pwm generated by the PWM signal generation unit PWM, a DC power supply voltage obtained by boosting or lowering the DC power supply voltage is generated (DC / DC conversion) and supplied to another circuit.
- the memory MEM stores programs used by the processor system MCU, setting values used to operate the processor system MCU, and the like.
- the arithmetic core PE performs specific processing required for the processor system MCU based on a program stored in the memory MEM or a program read from the outside. Generally, it is a CPU (Central Processing Unit).
- the clock generation unit CG generates a clock signal used in each circuit block in the processor system MCU. The clock signal generated by the clock generation unit CG may be output to the outside.
- the clock signal used in the processor system MCU can be supplied from an external circuit.
- the PWM signal generation unit PWM generates a PWM control pulse signal pwm that is a pulse signal for PWM control of the control target circuit PWR.
- This PWM signal generation unit PWM can be realized, for example, by using the timer function of the processor system MCU.
- the PFC signal generation unit PSG generates a PFC control pulse signal pfc that is a pulse signal for performing PFC control on the control target circuit PWR.
- This PFC signal generation unit PSG can be realized, for example, by using the timer function of the processor system MCU, similarly to the PWM signal generation unit PWM.
- the monitor unit MON monitors the feedback signal mon from the control target circuit PWR for generating the PWM control pulse signal pwm and the PFC control pulse signal pfc.
- the monitor unit MON converts the feedback signal mon, which is an analog signal, into a digital signal and transmits the digital signal to, for example, the computation core PE.
- the feedback signal mon output from the control target circuit PWR provided outside is monitored, and a digital value corresponding to the feedback signal mon is taken into the processor system MCU.
- the monitor unit MON can be configured by a circuit capable of converting an analog value into a digital value, such as an analog-digital converter (ADC), a comparator circuit, and the like.
- ADC analog-digital converter
- the IO unit IOU communicates with an external circuit and receives a control signal to the processor system MCU or transmits a processing result of the processor system MCU.
- Specific examples of the IO unit IOU include an SPI unit and a UART unit.
- the SPI unit performs communication of SPI (System (Packet Interface) standard which is 3-wire or 4-wire serial communication.
- a UART (Universal Asynchronous Receiver Retransmitter) unit converts a serial signal according to an asynchronous method into a parallel signal and performs conversion in the opposite direction.
- the peripheral circuit PERI is a circuit other than the circuit blocks described above, and includes a circuit block used by the arithmetic core PE.
- a timer unit for example, a timer unit, a watchdog timer unit, a DMA (Direct Memory Access) unit, a low voltage detection unit, a power-on reset (POR) unit, or the like can be considered.
- DMA Direct Memory Access
- POR power-on reset
- the arithmetic core PE, the memory MEM, the PWM signal generation unit PWM, the PFC signal generation unit PSG, the monitor unit MON, the IO unit IOU, and the peripheral circuit PERI are mutually connected by a bus. It is the composition which becomes. Although not shown, power is supplied to the processor system MCU from another circuit.
- the processor system MCU described so far is an example of a processor system to which the present invention is applied.
- the program and data stored in the memory MEM can be appropriately changed according to the specifications of the system.
- the connection between the circuit blocks may be, for example, a configuration in which a plurality of buses are connected, and the arithmetic core PE and another circuit block are directly connected without via the bus. There may be.
- the processor system MCU generates a PWM control pulse signal pwm and a PFC control pulse signal pfc, and gives them to the control target circuit PWR. Then, the processor system MCU controls the duty of the PWM control pulse signal pwm and the PFC control pulse signal pfc, the generation timing of the PWM control pulse signal pwm, and the like from the feedback signal mon from the control target circuit PWR and other circuits. Control by signal etc.
- the power supply circuit described below drives an LED (Light Emitting Diode) as a load circuit, but the load circuit is not limited to an LED, and may be a general circuit.
- FIGS. 2A and 2B show an example of a power supply circuit for driving an LED.
- the power supply circuit is denoted by PWR.
- an NMOS transistor is used as an output transistor that performs a switching operation.
- this output transistor can also be composed of a PMOS transistor, or can be composed of a PNP transistor or an NPN transistor. You can also.
- Each of the power supply circuits PWR shown in FIGS. 2A and 2B includes an AC power supply AP, a full-wave rectifier circuit FWR, a PFC unit, and a DC / DC unit. 2A and 2B, the AC power supply AP, the full-wave rectifier circuit FWR, and the PFC unit are common.
- the full-wave rectifier circuit FWR generates a DC voltage V1 from the AC power supply AP.
- the full-wave rectifier circuit FWR is a bridge circuit including four diodes.
- the cathodes of the two diodes connected to the anode of the AC power supply AP are commonly connected to the output of the full-wave rectifier circuit FWR.
- the anodes of the two diodes connected to the cathode of the AC power supply AP are grounded in common.
- the PFC unit in FIG. 2A is a non-insulated boost converter.
- This PFC unit includes inductors L1, L2, Lm1, and Lm2, diodes D1 and D2, NMOS transistors NM1 and NM2, a smoothing capacitor C1, and resistors R1 and R2.
- the PFC unit is an interleaved PFC circuit, and the NMOS transistors NM1 and NM2 are complementarily switched by two PFC control pulse signals pfc1 and pfc2 having a phase difference of approximately ⁇ (180 °).
- the PFC unit generates a DC voltage V2 from the DC voltage V1.
- each of the inductors L1 and L2 is commonly connected to the output of the full-wave rectifier circuit FWR, and is given a voltage V1.
- the other end of the inductor L1 is connected to the anode of the diode D1.
- the other end of the inductor L2 is connected to the anode of the diode D2.
- One end of a smoothing capacitor C1 is commonly connected to the cathodes of the diodes D1 and D2. That is, the inductor L1 and the diode D1 connected in series and the inductor L2 and the diode D2 connected in series are connected in parallel. The other end of the smoothing capacitor C1 is grounded.
- the drain of the NMOS transistor NM1 is connected to a node between the inductor L1 and the diode D1 connected in series.
- the source of the NMOS transistor NM1 is grounded.
- the PFC control pulse signal pfc1 is input to the gate of the NMOS transistor NM1.
- the NMOS transistor NM1 performs a switching operation according to the voltage level of the PFC control pulse signal pfc1. Energy is stored in the inductor L1 when the NMOS transistor NM1 is on, and the smoothing capacitor C1 is charged via the diode D1 by the energy stored in the inductor L1 when the NMOS transistor NM1 is off.
- the drain of the NMOS transistor NM2 is connected to a node between the inductor L2 and the diode D2 connected in series.
- the source of the NMOS transistor NM2 is grounded.
- the PFC control pulse signal pfc2 is input to the gate of the NMOS transistor NM2.
- the NMOS transistor NM2 performs a switching operation according to the voltage level of the PFC control pulse signal pfc2. Energy is stored in the inductor L2 while the NMOS transistor NM2 is on, and the smoothing capacitor C1 is charged via the diode D2 by the energy stored in the inductor L2 while the NMOS transistor NM2 is off. An output voltage V2 corresponding to the charge charged in the smoothing capacitor C1 is output.
- the feedback signal mon1 corresponding to the current I1 flowing through the inductor L1 is generated by the monitoring inductor Lm1 electromagnetically coupled to the inductor L1 via the iron core.
- the feedback signal mon1 is fed back to the monitor unit MON.
- the feedback signal mon2 corresponding to the current I2 flowing through the inductor L2 is generated by the monitoring inductor Lm2 electromagnetically coupled to the inductor L2 via the iron core.
- the feedback signal mon2 is fed back to the monitor unit MON.
- resistors R1 and R2 are connected in series in parallel with the smoothing capacitor C1. That is, the output voltage V2 of the PFC unit is applied to both ends of the resistors R1 and R2.
- a feedback signal mon3 is output from a node between the resistors R1 and R2.
- the feedback signal mon3 is a monitor voltage obtained by dividing the output voltage V2 into the resistance ratio of the resistors R1 and R2.
- This feedback signal mon3 is fed back to the monitor unit MON of the processor system MCU.
- the duty ratio and pulse width of the PFC control pulse signals pfc1 and pfc2 are determined.
- the PFC unit in FIGS. 2A and 2B is a constant voltage control circuit.
- the DC / DC unit in FIGS. 2A and 2B will be described in order.
- the DC / DC unit in FIG. 2A is a step-down DC / DC converter.
- This DC / DC unit includes an NMOS transistor NM3, an inductor L3, a diode D3, a smoothing capacitor C2, and a resistor Rm.
- the drain of the NMOS transistor NM3 is connected to the output of the PFC unit, and the source is connected to the cathode of the diode D3. Further, the PWM control pulse signal pwm is given to the gate of the NMOS transistor NM3. Therefore, the NMOS transistor NM3 performs a switching operation according to the voltage level of the PWM control pulse signal pwm.
- the anode of the diode D3 is grounded.
- One end of an inductor L3 is connected to a node between the source of the NMOS transistor NM3 and the cathode of the diode D3.
- the other end of the inductor L3 is connected to one end of the smoothing capacitor C2.
- the other end of the smoothing capacitor C2 is grounded.
- an output voltage Vout corresponding to the charge accumulated in the smoothing capacitor C2 is output from a node between the smoothing capacitor C2 and the inductor L3. Further, the electric charge accumulated in the smoothing capacitor C2 is supplied to the LED as an output current Iout.
- a resistor Rm is provided between the cathode of the LED and the ground. An output current Iout flowing through the LED flows through the resistor Rm. That is, a voltage corresponding to the output current Iout and the resistance value of the resistor Rm is generated at both ends of the resistor Rm. This voltage is a monitor voltage for monitoring the output current Iout. This monitor voltage is fed back to the monitor unit MON as a feedback signal mon4.
- the PWM signal generation unit of the processor system MCU generates a PWM control pulse signal pwm having a duty ratio or a period that makes the voltage level of the monitor voltage constant.
- the DC / DC unit of FIG. 2A is a constant current control circuit.
- the DC / DC unit in FIG. 2B is a non-insulated step-up DC / DC converter.
- This DC / DC unit also includes an NMOS transistor NM3, an inductor L3, a diode D3, a smoothing capacitor C2, and a resistor Rm.
- One end of the inductor L3 is connected to the output of the PFC unit, and the other end is connected to the drain of the NMOS transistor NM3.
- the source of the NMOS transistor NM3 is grounded.
- the PWM control pulse signal pwm is given to the gate of the NMOS transistor NM3. Therefore, the NMOS transistor NM3 performs a switching operation according to the voltage level of the PWM control pulse signal pwm.
- the anode of the diode D3 is connected to a node between the drain of the NMOS transistor NM3 and the inductor L3.
- the cathode of the diode D3 is connected to one end of the smoothing capacitor C2. The other end of the smoothing capacitor C2 is grounded.
- an output voltage Vout corresponding to the electric charge accumulated in the smoothing capacitor C2 is output from a node between the smoothing capacitor C2 and the cathode of the diode D3. Further, the electric charge accumulated in the smoothing capacitor C2 is supplied to the LED as an output current Iout.
- a resistor Rm is provided between the cathode of the LED and the ground. An output current Iout flowing through the LED flows through the resistor Rm. That is, a voltage corresponding to the output current Iout and the resistance value of the resistor Rm is generated at both ends of the resistor Rm. This voltage is a monitor voltage for monitoring the output current Iout. This monitor voltage is fed back to the monitor unit MON as a feedback signal mon4.
- the PWM signal generation unit of the processor system MCU generates a PWM control pulse signal pwm having a duty ratio or a period that makes the voltage level of the monitor voltage constant.
- the DC / DC unit of FIG. 2B is also a constant current control circuit.
- the DC / DC unit in FIG. 3A is a non-insulated step-down DC / DC converter, similar to the DC / DC unit in FIG. 2A.
- a resistor Rm for generating the feedback signal mon4 is connected in series with the LED.
- resistors Rm1 and Rm2 for generating the feedback signal mon4 are connected in parallel with the LED.
- the output voltage Vout of the power supply circuit PWR is applied to both ends of the resistors Rm1 and Rm2.
- a feedback signal mon4 is output from a node between the resistors Rm1 and Rm2.
- the feedback signal mon4 is a monitor voltage obtained by dividing the output voltage Vout into the resistance ratio of the resistors Rm1 and Rm2.
- This feedback signal mon4 is fed back to the monitor unit MON of the processor system MCU.
- the PWM signal generation unit of the processor system MCU generates a PWM control pulse signal pwm having a duty ratio or a period that makes the voltage level of the monitor voltage constant.
- the DC / DC unit in FIG. 3A is a constant voltage control circuit.
- the other configuration is the same as that of the DC / DC unit of FIG.
- the DC / DC unit in FIG. 3B is a non-insulated step-up DC / DC converter, similar to the DC / DC unit in FIG. 2B.
- a resistor Rm for generating the feedback signal mon4 is connected in series with the LED.
- resistors Rm1 and Rm2 for generating the feedback signal mon4 are connected in parallel with the LED.
- the output voltage Vout of the power supply circuit PWR is applied to both ends of the resistors Rm1 and Rm2.
- a feedback signal mon4 is output from a node between the resistors Rm1 and Rm2.
- the feedback signal mon4 is a monitor voltage obtained by dividing the output voltage Vout into the resistance ratio of the resistors Rm1 and Rm2.
- This feedback signal mon4 is fed back to the monitor unit MON of the processor system MCU.
- the PWM signal generation unit of the processor system MCU generates a PWM control pulse signal pwm having a duty ratio or a period that makes the voltage level of the monitor voltage constant.
- the DC / DC unit of FIG. 3B is a constant voltage control circuit.
- the other configuration is the same as that of the DC / DC unit of FIG.
- the PFC unit in FIGS. 2A and 2B is a non-insulated boost converter, whereas the PFC unit in FIG. 4 is an isolated flyback converter. Although there is a difference between the non-insulating type and the insulating type, the operating principle is the same.
- the PFC unit of FIG. 4 includes inductors L11, L12, L21, L22, Lm1, Lm2, diodes D1, D2, NMOS transistors NM1, NM2, and a smoothing capacitor C1.
- each of the inductors L11 and L21 is commonly connected to the output of the full-wave rectifier circuit FWR, and is given a voltage V1.
- the other end of the inductor L11 is connected to the drain of the NMOS transistor NM1.
- the other end of the inductor L2 is connected to the drain of the NMOS transistor NM2.
- the sources of the NMOS transistors NM1 and NM2 are both grounded.
- the PFC control pulse signal pfc1 is input to the gate of the NMOS transistor NM1, and the PFC control pulse signal pfc2 is input to the gate of the NMOS transistor NM2.
- the inductor L12 is electromagnetically coupled to the inductor L11 via the core.
- the anode of the diode D1 is connected to the other end of the inductor L12 whose one end is grounded.
- the inductor L22 is electromagnetically coupled to the inductor L21 via the core.
- the other end of the inductor L22 whose one end is grounded is connected to the anode of the diode D2.
- One end of a smoothing capacitor C1 is commonly connected to the cathodes of the diodes D1 and D2. The other end of the smoothing capacitor C1 is grounded.
- the feedback signal mon1 corresponding to the current I1 flowing through the inductor L12 is generated by the monitoring inductor Lm1 electromagnetically coupled to the inductor L11 via the iron core.
- the feedback signal mon1 is fed back to the monitor unit MON.
- the feedback signal mon2 corresponding to the current I2 flowing through the inductor L2 is generated by the monitoring inductor Lm2 electromagnetically coupled to the inductor L2 via the iron core.
- the feedback signal mon2 is fed back to the monitor unit MON.
- resistors R1 and R2 are connected in series in parallel with the smoothing capacitor C1. That is, the output voltage V2 of the PFC unit is applied to both ends of the resistors R1 and R2.
- a feedback signal mon3 is output from a node between the resistors R1 and R2.
- the feedback signal mon3 is a monitor voltage obtained by dividing the output voltage V2 into the resistance ratio of the resistors R1 and R2.
- This feedback signal mon3 is fed back to the monitor unit MON of the processor system MCU.
- the duty ratio and pulse width of the PFC control pulse signals pfc1 and pfc2 are determined.
- the PFC unit in FIG. 4 is a constant voltage control circuit.
- the PFC unit is a non-insulated boost converter, as in the power supply circuit PWR in FIGS. 2A and 2B.
- resistors R1 and R2 for generating the feedback signal mon3 are connected in parallel with the smoothing capacitor C1.
- the resistor R for generating the feedback signal mon3 is connected in series with the LED. That is, this PFC unit is a constant current control circuit.
- the DC / DC unit can be omitted and the LED can be directly connected to the PFC unit. Therefore, the circuit can be reduced in size.
- the PFC unit is an insulating flyback converter, similarly to the power supply circuit PWR in FIG.
- resistors R1 and R2 for generating the feedback signal mon3 are connected in parallel with the smoothing capacitor C1.
- the resistor R for generating the feedback signal mon3 is connected in series with the LED. That is, this PFC unit is a constant current control circuit.
- the DC / DC unit can be omitted and the LED can be directly connected to the PFC unit. Therefore, the circuit can be reduced in size.
- FIG. 6 is a block diagram of the PFC signal generation unit PSG according to the first embodiment.
- the PFC signal generation unit PSG includes an up counter 101, a cycle upper limit comparator 104, a cycle lower limit comparator 201, a counter clear control circuit 202, a pulse width comparator 107, an OR gate 108, a first control pulse.
- An output circuit 109, a count value capture circuit 110, a shift circuit 111, a phase comparator 112, an output timing correction circuit 113, a down counter 116, a second control pulse output circuit 117, and an interrupt signal output circuit 118 are provided.
- the up counter 101 counts up the input clock signal clk.
- the up counter 101 clears the count value at the timing when the zero current detection signal cd1 of the current I1 flowing through the inductor L1 is input, and newly starts counting from zero.
- the zero current detection signal cd1 is generated by the monitor unit MON in FIG.
- the period upper limit comparator 104 is a digital comparator, and more specifically a coincidence circuit.
- the cycle upper limit comparator 104 outputs a clear signal clr when the count value cnt1 of the up counter 101 matches the cycle upper limit set value.
- the clear signal clr is input to the up counter 101, the count value of the up counter 101 is cleared. That is, if the zero current detection signal cd1 of the current I1 is not input before the count value of the up counter 101 reaches the set cycle upper limit set value, the count value of the up counter 101 is forcibly cleared.
- the clear signal clr is output exceptionally, and is indicated by a dotted line in FIG.
- the cycle upper limit set value is an upper limit value of the cycle that the PFC control pulse signal pfc1 can take, and is set by the computation core PE.
- the period of the PFC control pulse signal pfc1 is, in principle, an interval at which the zero current detection signal cd1 of the current I1 is input, and is not necessarily constant.
- the cycle upper limit set value is an auxiliary value used when the zero current detection signal cd1 of the current I1 is not input due to system startup or trouble.
- the period lower limit comparator 201 is a digital comparator, and more specifically a coincidence circuit.
- the cycle lower limit comparator 201 outputs a match signal cs2 when the count value cnt1 of the up counter 101 matches the cycle lower limit set value.
- the coincidence signal cs2 is input to the counter clear control circuit 202.
- the counter clear control circuit 202 determines the timing when the zero current detection signal cd1 of the current I1 is input based on the coincidence signal cs2 output from the cycle lower limit comparator 201, and outputs the clear signals cd1a and cd1b at appropriate timing. To do. Specifically, when the zero current detection signal cd1 of the current I1 is input at a timing equal to or lower than the cycle lower limit set value, the process waits until the cycle lower limit set value and clears the count value of the up counter 101. On the other hand, when the zero current detection signal cd1 of the current I1 is input at a timing exceeding the cycle lower limit set value, the count value of the up counter 101 is cleared at the timing as usual. Details of the configuration and operation of the counter clear control circuit 202 will be described later.
- the pulse width comparator 107 is a digital comparator, and more specifically a coincidence circuit.
- the pulse width comparator 107 outputs a reset signal rst1 when the count value cnt1 of the up counter 101 matches the pulse width setting value of the PFC control pulse signal pfc1.
- the pulse width setting value is calculated by the calculation core PE based on the duty ratio determined based on the feedback signal mon3 fed back from the PFC unit and the period of the PFC control pulse signal pfc1.
- the period is an interval at which the zero current detection signal cd1 of the current I1 is generated.
- the pulse width setting value is updated as needed by PFC control. For example, it is updated when the count value of the up counter 101 is cleared.
- the OR gate 108 receives the clear signals cd1a and cd1b output from the counter clear control circuit 202 and the clear signal clr output from the period upper limit comparator 104.
- the OR gate 108 outputs a set signal set1.
- the set signal set1 is a clear signal for clearing the count value of the up counter 101.
- the first control pulse output circuit 109 generates and outputs a PFC control pulse signal pfc1 based on the set signal set1 and the reset signal rst1.
- the PFC control pulse signal pfc1 is set from the inactive level to the active level at the timing when the set signal set1 is input.
- the active level is reset to the inactive level. That is, the PFC control pulse signal pfc1 is at the active level from the timing when the set signal set1 is input to the timing when the reset signal rst1 is input.
- the PFC control pulse signal pfc1 when the PFC control pulse signal pfc1 is input to the NMOS transistor, the PFC control pulse signal pfc1 becomes H (High) during this active level period.
- the PFC control pulse signal pfc1 when the PFC control pulse signal pfc1 is input to the PMOS transistor (not shown), the PFC control pulse signal pfc1 becomes L (Low) during this active level period.
- the count value capture circuit 110 captures the count value cnt1 of the up counter 101 at the timing when the zero current detection signal cd1 of the current I1 is input. That is, the count value cnt1 of the up counter 101 at the time of clearing, that is, the period value T of the “previous period” (hereinafter, T is the maximum count value of the “previous period”) is captured.
- the shift circuit 111 shifts the period value T captured by the count value capture circuit 110 by 1 bit to generate a 1 ⁇ 2 period value T / 2 that is a target phase difference.
- the phase comparator 112 is a digital comparator, and in detail is a coincidence circuit.
- the phase comparator 112 outputs a coincidence signal cs1 when the count value cnt1 of the up counter 101 coincides with the 1 ⁇ 2 period value T / 2 generated by the shift circuit 111.
- the output timing correction circuit 113 determines the timing when the zero current detection signal cd2 of the current I2 is input based on the set signal set1 and the coincidence signal cs1 output from the phase comparator 112, and sets the set signal at an appropriate timing. set2 is output. Details of the configuration and operation of the output timing correction circuit 113 will be described later.
- the down counter 116 starts counting down from the pulse width setting value of the PFC control pulse signal pfc2 at the timing when the set signal set2 is input.
- the down counter 116 counts down according to the clock signal clk, stops when the count value reaches 1 and outputs a reset signal rst2.
- a desired pulse width is obtained by outputting the reset signal rst2 when the count value reaches 1 instead of 0.
- the pulse width setting value is based on the duty ratio determined based on the feedback signal mon3 fed back from the PFC unit and the cycle of the PFC control pulse signal pfc1. It is calculated by the calculation core PE. That is, since the pulse width setting values of the PFC control pulse signals pfc1 and pfc2 are both generated from the same signal, they are approximately the same value. However, they need not be the same value.
- This pulse width setting value is updated as needed by PFC control. For example, it is updated at the timing when the count value of the up counter 101 is cleared.
- the second control pulse output circuit 117 generates and outputs a PFC control pulse signal pfc2 based on the set signal set2 and the reset signal rst2.
- the PFC control pulse signal pfc2 is set from the inactive level to the active level at the timing when the set signal set2 is input.
- the active level is reset to the inactive level. That is, the PFC control pulse signal pfc2 is at the active level from the timing when the set signal set2 is input until the timing when the reset signal rst2 is input.
- the interrupt signal output circuit 118 generates and outputs an interrupt signal int every time the count value cnt1 of the up counter 101 is cleared.
- the computation core PE updates the pulse width setting values of the PFC control pulse signals pfc1 and pfc2 every time this interrupt signal int is received.
- FIG. 7 is a timing chart for explaining a method of generating the PFC control pulse signal pfc1.
- a set signal set1, a reset signal rst1, a count value cnt1 of the up counter 101, and a PFC control pulse signal pfc1 are shown.
- the set signal set1 is in principle the zero current detection signal cd1 of the current I1. That is, as shown in FIG. 7, at the timing when the zero current detection signal cd1 of the current I1 is generated, the count value cnt1 of the up counter 101 is cleared and the PFC control pulse signal pfc1 is switched from the inactive level to the active level. Change.
- the pulse width setting value and the cycle upper limit setting value of the PFC control pulse signal pfc1 are values between 0000H and FFFFH.
- the relation of pulse width setting value ⁇ period upper limit setting value + 1 is established.
- FIG. 8 is a circuit diagram showing an example of a specific circuit configuration of the counter clear control circuit 202.
- the counter clear control circuit 202 includes holding circuits HC11 and HC12, AND gates A11 to A13, and a D flip-flop DF11.
- each holding circuit HC11, HC12 is composed of a D flip-flop.
- the SR in the previous stage indicates a set input and a reset input for the data input of the D flip-flop.
- a clock signal clk is input to the clock input of each D flip-flop.
- the coincidence signal cs2 output from the cycle lower limit comparator 201 is input to the set input S of the holding circuit HC11, and the set signal set1 is input to the reset input R.
- the output signal of the holding circuit HC11 is a period signal hs11 indicating a period exceeding the cycle lower limit set value.
- An inverted signal of the period signal hs11 is input to one input of the AND gate A11.
- the zero current detection signal cd1 of the current I1 is input to the other input of the AND gate A11.
- the output signal of the AND gate A11 is a detection signal s1 that is generated when the zero current detection signal cd1 of the current I1 is input below the cycle lower limit set value.
- This detection signal s1 is input to the set input S of the holding circuit HC12.
- the coincidence signal cs2 is input to the reset input R of the holding circuit HC12.
- the output signal of the holding circuit HC12 is a holding signal hs12 for holding up to the cycle lower limit set value when the zero current detection signal cd1 of the current I1 is input.
- the holding signal hs12 is input to one input of the AND gate A12.
- the coincidence signal cs2 is input to the other input of the AND gate A12.
- the output signal of the AND gate A12 is a clear signal cd1b that constitutes one of the set signals set1.
- the period signal hs11 output from the holding circuit HC11 is input to one input of the AND gate A13.
- the zero current detection signal cd1 of the current I1 is input to the other input of the AND gate A13.
- the output signal of the AND gate A13 is a clear signal cd1a that constitutes one of the set signals set1.
- the D flip-flop DF11 captures this and outputs an error flag ef2.
- FIG. 9 is a timing chart for explaining the operation of the counter clear control circuit 202.
- the zero current detection signal cd1 of the current I1, the coincidence signal cs2, the period signal hs11, the set signal set1, the count value cnt1 of the up counter 101, the coincidence signal cs2, the detection signal s1, the holding signal hs12, and the clear signal cd1a, clear signal cd1b, set signal set1, PFC control pulse signal pfc1, and error flag ef2 are shown.
- the zero current detection signal cd1 of the current I1 is input after exceeding the cycle lower limit set value. Therefore, as usual, the clear signal cd1a is output at the timing.
- the zero current detection signal cd1 of the current I1 is input below the cycle lower limit set value. Therefore, the zero current detection signal cd1 of the current I1 is input while the period signal hs11 indicating the period exceeding the cycle lower limit set value remains L. At that timing, the detection signal s1 is generated, and the hold signal hs12 is changed from L to H and held. Then, at the timing when the coincidence signal cs2 indicating the passage of the cycle lower limit set value is input, the holding signal hs12 is changed from H to L, and the clear signal cd1b is output.
- the cycle lower limit set value and guaranteeing the cycle lower limit of the PFC control pulse signal pfc1 it is possible to generate a PFC control pulse signal that further improves the power factor improvement by the PFC circuit.
- FIG. 10 is a timing chart for explaining a method of generating the PFC control pulse signal pfc2.
- the set signal set2 (zero current detection signal cd2 of current I2) is 1/2 cycle value T / 2 from the generation timing of the set signal set1 (zero current detection signal cd1 of current I1). It occurs at the timing deviated.
- the pulse width setting value and the cycle upper limit setting value of the PFC control pulse signal pfc1 are values between 0000H and FFFFH.
- the relation of pulse width setting value ⁇ period upper limit setting value + 1 is established.
- the zero current detection signal cd1 of the current I1, that is, the set signal set1 is generated.
- the count value cnt1 of the up counter 101 is cleared.
- a zero current detection signal cd2 of current I2 is generated.
- the set signal set2 is generated simultaneously with the zero current detection signal cd2 of the current I2. Therefore, at this timing, the PFC control pulse signal pfc2 is switched from the inactive level to the active level.
- the reset signal rst2 is generated.
- the PFC control pulse signal pfc2 is switched from the active level to the inactive level.
- the zero current detection signal cd1 of the current I1 that is, the set signal set1 is generated again.
- the count value cnt1 of the up counter 101 is cleared.
- the cycle starting from time t1 ends.
- the interval of the zero current detection signal cd1 of the adjacent current I1 is a cycle. This period value is b.
- a zero current detection signal cd2 of current I2 is generated.
- the set signal set2 is generated simultaneously with the zero current detection signal cd2 of the current I2. Therefore, at this timing, the PFC control pulse signal pfc2 is switched from the inactive level to the active level.
- the reset signal rst2 is generated.
- the PFC control pulse signal pfc2 is switched from the active level to the inactive level.
- the zero current detection signal cd1 of the current I1 that is, the set signal set1 is generated again.
- the count value cnt1 of the up counter 101 is cleared.
- the cycle started from time t4 ends.
- This period value is c.
- the PFC control pulse signal pfc2 as shown in FIG. 10 is generated.
- the zero current detection signal cd2 of the current I2 does not necessarily occur at a timing that is shifted from the generation timing of the zero current detection signal cd1 of the current I1 by a half cycle value T / 2. Therefore, in order to balance high efficiency by detecting zero current of the current I2 and high efficiency by setting the phase difference between the PFC control pulse signals pfc1 and pfc2 to ⁇ , the PFC signal generation unit PSG according to the present embodiment is used. Then, an output timing correction circuit 113 is provided.
- the output timing correction circuit 113 corrects the output timing of the set signal set2 according to the generation timing of the zero current detection signal cd2 of the current I2 with respect to the generation timing of the zero current detection signal cd1 of the current I1.
- the output of the set signal set2 switches the PFC control pulse signal pfc2 from the inactive level to the active level.
- FIG. 11 is a flowchart showing a processing flow of the output timing correction circuit 113.
- the output timing correction circuit 113 generates the zero current detection signal cd2 of the current I2 until the time of 1/2 cycle value T / 2 (T is the cycle value of the previous cycle) elapses from the start in each cycle. It is determined whether or not (step ST1).
- the output timing correction circuit 113 waits until the 1/2 cycle value T / 2.
- the set signal set2 is output (step ST2).
- T / 2 is most preferable as the target phase difference, but it may be 3 / 8T to 5 / 8T. 7 / 16T to 9 / 16T is more preferable from the viewpoint of improving efficiency.
- step ST1 when the zero current detection signal cd2 of the current I2 is not generated during the period from the start until the time of the 1/2 cycle value T / 2 has elapsed (NO in step ST1), the predetermined value from the 1/2 cycle value T / 2 is determined. It is determined whether or not the zero current detection signal cd2 of the current I2 is generated within the allowable period (step ST3).
- step ST3 When the zero current detection signal cd2 of the current I2 is generated within the allowable period (step ST3 YES), the output timing correction circuit 113 outputs the set signal set2 at the timing when the zero current detection signal cd2 of the current I2 is generated. (Step ST4).
- the PFC control pulse signal pfc2 is switched from the inactive level to the active level.
- the width of the allowable period is preferably T / 64 to T / 8. If the width of the allowable period is less than T / 64, the frequency of error occurrence increases, which is not preferable for system operation. On the other hand, if the allowable period exceeds T / 8, it does not contribute to power factor improvement in the PFC circuit.
- step ST5 when the zero current detection signal cd2 of the current I2 does not occur within the allowable period (step ST3 NO), the output timing correction circuit 113 determines that an error has occurred (step ST5). Then, the output timing correction circuit 113 does not output the set signal set2 in the cycle, but forcibly outputs the set signal set2 at the timing when the time of the 1/2 cycle value T / 2 has elapsed from the start of the next cycle ( Step ST6).
- the above processing is repeatedly executed every cycle.
- FIGS. 12 to 14 are timing charts for explaining a method of generating the PFC control pulse signal pfc2, as in FIG. 12 to 14, in order from the top of the figure, the set signal set1, the zero current detection signal cd2 of the current I2, the set signal set2, the count value cnt1 of the up counter 101, the count value cnt2 of the down counter 116, and the reset signal rst2 , PFC control pulse signal pfc1 and PFC control pulse signal pfc2 are shown. In FIG. 14, an error flag ef1 is also shown at the bottom.
- FIG. 12 will be described.
- the first cycle starting from time t1 is the ideal state.
- the zero current detection signal cd2 of the current I2 is generated between the start and the half cycle value T / 2.
- the output timing correction circuit 113 does not output the set signal set2 at the generation timing of the zero current detection signal cd2, but outputs the set signal set2 after waiting until time t5.
- the PFC control pulse signal pfc2 is switched from the inactive level to the active level.
- the down counter 116 starts counting down from the pulse width setting value of the PFC control pulse signal pfc2.
- the reset signal rst2 is generated.
- the PFC control pulse signal pfc2 is switched from the active level to the inactive level.
- the zero current detection signal cd1 of the current I1, that is, the set signal set1 is generated again.
- the count value cnt1 of the up counter 101 is cleared.
- the cycle started from time t4 ends.
- the first cycle starting from time t1 is the ideal state.
- the zero current detection signal cd2 of the current I2 is generated during the allowable period TR from the 1/2 cycle value T / 2.
- the zero current detection signal cd2 of the current I2 is generated.
- the output timing correction circuit 113 outputs the set signal set2 at time t5, which is the generation timing of the zero current detection signal cd2.
- the PFC control pulse signal pfc2 is switched from the inactive level to the active level.
- the down counter 116 starts counting down from the pulse width setting value of the PFC control pulse signal pfc2.
- the reset signal rst2 is generated.
- the PFC control pulse signal pfc2 is switched from the active level to the inactive level.
- the zero current detection signal cd1 of the current I1, that is, the set signal set1 is generated again.
- the count value cnt1 of the up counter 101 is cleared.
- the cycle started from time t4 ends.
- the output timing correction circuit 113 outputs the set signal set2 at time t8, which is the generation timing of the zero current detection signal cd2.
- the first cycle starting from time t1 is the ideal state.
- the zero current detection signal cd2 of the current I2 is generated after the allowable period TR from the time T / 2 is exceeded.
- the output timing correction circuit 113 does not output the set signal set2 in the cycle, and forcibly outputs the set signal set2 in the 1/2 cycle value T / 2 from the start of the next cycle. become.
- the error flag ef1 is switched from L to H at a timing exceeding the allowable period TR.
- the zero current detection signal cd1 of the current I1, that is, the set signal set1 is generated again.
- the count value cnt1 of the up counter 101 is cleared.
- the cycle started from time t4 ends.
- the PFC signal generation unit PSG sets the PFC control pulse signal that further improves the power factor improvement by the PFC circuit by setting the cycle lower limit set value and guaranteeing the cycle lower limit of the PFC control pulse signal pfc1. Can be generated.
- the output timing correction circuit 113 receives the zero current detection signal cd2 of the current I2 based on the set signal set1 for setting the PFC control pulse signal pfc1 to the active level and the coincidence signal cs1 output from the phase comparator 112. The set timing is determined, and the set signal set2 for setting the PFC control pulse signal pfc2 to the active level is output at an appropriate timing.
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Abstract
Description
特許文献1において、コイル電流におけるゼロ電流を検出する場合、ノイズなどが原因で、PFC制御パルス信号の周期が小さくなり過ぎるおそれがあった。そして、このような異常なPFC制御パルス信号により、電力ロスが増大し、力率が低下するおそれがあった。
まず、本実施の形態に係るPFC信号生成ユニットが適用されるプロセッサシステムの概要について説明する。なお、本実施の形態に係るPFC信号生成ユニットは、以下で説明するプロセッサシステムに適用されるものではあるが、説明するプロセッサシステムは一例であり、他のプロセッサシステムに本発明を適用することも可能である。
演算コアPEは、メモリMEMに格納されたプログラム又は外部から読み込んだプログラムに基づくプロセッサシステムMCUに求められる具体的な処理を行う。一般的には、CPU(Central Processing Unit)である。
クロック生成ユニットCGは、プロセッサシステムMCU内の各回路ブロックで利用されるクロック信号を生成する。また、クロック生成ユニットCGで生成されたクロック信号は、外部に出力されてもよい。
なお、プロセッサシステムMCU内で利用されるクロック信号は、外部の回路から供給することも可能である。
位相比較器112は、デジタルコンパレータであって、詳細には一致回路である。位相比較器112は、アップカウンタ101のカウント値cnt1と、シフト回路111が生成した1/2周期値T/2とが一致した場合、一致信号cs1を出力する。
まず、出力タイミング補正回路113は、各周期において、スタートから1/2周期値T/2(Tは前周期の周期値)の時間が経過するまでに、電流I2のゼロ電流検出信号cd2が発生したか否かを判定する(ステップST1)。スタートから1/2周期値T/2までの間に、電流I2のゼロ電流検出信号cd2が発生した場合(ステップST1YES)、出力タイミング補正回路113は、1/2周期値T/2まで待機して、セット信号set2を出力する(ステップST2)。ここで、目標位相差としては、T/2が最も好ましいのはいうまでもないが、3/8T~5/8Tであればよい。7/16T~9/16Tであれば、効率向上の観点から更に好ましい。
104 周期上限比較器
107 パルス幅比較器
108 ORゲート
109 第1制御パルス出力回路
110 カウント値キャプチャ回路
111 シフト回路
112 位相比較器
113 出力タイミング補正回路
116 ダウンカウンタ
117 第2制御パルス出力回路
118 割込信号出力回路
201 周期下限比較器
202 カウンタクリア制御回路
A11-A13 ANDゲート
AP 交流電源
C1、C2 平滑コンデンサ
cd1、cd2 ゼロ電流検出信号
clr、cd1a、cd1b クリア信号
CG クロック生成ユニット
clk クロック信号
cnt1、cnt2 カウント値
cs1、cs2 一致信号
D1-D3 ダイオード
DF11 Dフリップフロップ
ef1、ef2 エラーフラグ
FWR 全波整流回路
HC11、HC12 保持回路
hs11 期間信号
hs12 保持信号
int 割込信号
IOU ユニット
L1、L11、L12、L2、L21、L22、L3 インダクタ
LED LED
Lm1、Lm2 モニタ用インダクタ
MCU プロセッサシステム
MEM メモリ
MON モニタユニット
mon、mon1-mon4 フィードバック信号
NM1-NM3 NMOSトランジスタ
O1、O2 ORゲート
PE 演算コア
PERI 周辺回路
pfc、pfc1、pfc2 PFC制御パルス信号
PSG PFC信号生成ユニット
PWM PWM信号生成ユニット
pwm PWM制御パルス信号
PWR 電源回路(制御対象回路)
R、R1、R2、Rm、Rm1、Rm2 抵抗
Claims (7)
- 第1のスイッチに接続された第1のインダクタと、第2のスイッチに接続された第2のインダクタと、を有するPFC回路を制御するPFC信号を生成するPFC信号生成回路であって、
前記第1のインダクタのゼロ電流が検出される第1のタイミングに基づいて、カウント値がクリアされるカウンタと、
前記第1のタイミングが、周期下限値を下回る場合、当該周期下限値まで待機してから前記カウンタ値をクリアするカウンタクリア制御回路と、
前記カウント値がクリアされるタイミングで、前記第1のスイッチをオンにする第1のPFC信号を出力する第1の制御信号出力部と、
前記第2のインダクタのゼロ電流が検出される第2のタイミングに基づいて、前記第2のスイッチをオンにする第2のPFC信号を出力する第2の制御信号出力部と、を備えるPFC信号生成回路。 - 前記周期下限値の設定値と、前記カウンタのカウント値とを比較する第1のデジタル比較器を更に備え、
前記カウンタクリア制御回路は、前記第1のデジタル比較器の比較結果に基づいて、前記第1のタイミングが、周期下限値を下回っているか否かを判断することを特徴とする請求項1に記載のPFC信号生成回路。 - 前記PFC回路からのフィードバック信号に基づいて決定される前記第1のPFC信号のパルス幅の設定値と、前記カウンタのカウント値を比較する第2のデジタル比較器を更に備えることを特徴とする請求項1又は2に記載のPFC信号生成回路。
- 前記PFC回路からのフィードバック信号に基づいて決定される前記第2のPFC信号のパルス幅の設定値をカウントダウンするダウンカウンタを更に備えることを特徴とする請求項1~3のいずれか一項に記載のPFC信号生成回路。
- 前記フィードバック信号に基づいて決定される前記第1のPFC信号のパルス幅の設定値と、前記カウンタのカウント値を比較する第2のデジタル比較器を更に備えることを特徴とする請求項4に記載のPFC信号生成回路。
- 交流電源に接続されたPFC回路と、
前記PFC回路を制御するPFC信号を生成するPFC信号生成回路と、を備えたPFC制御システムであって、
前記PFC回路は、
第1のスイッチに接続された第1のインダクタと、
第2のスイッチに接続された第2のインダクタと、を備え、
前記PFC信号生成回路は、
前記第1のインダクタのゼロ電流が検出される第1のタイミングに基づいて、カウント値がクリアされるカウンタと、
前記第1のタイミングが、周期下限値を下回る場合、当該周期下限値まで待機してから前記カウンタ値をクリアするカウンタクリア制御回路と、
前記カウント値がクリアされるタイミングで、前記第1のスイッチをオンにする第1のPFC信号を出力する第1の制御信号出力部と、
前記第2のインダクタのゼロ電流が検出される第2のタイミングに基づいて、前記第2のスイッチをオンにする第2のPFC信号を出力する第2の制御信号出力部と、を備えるPFC制御システム。 - 第1のスイッチに接続された第1のインダクタと、第2のスイッチに接続された第2のインダクタと、を有するPFC回路を制御するPFC制御方法であって、
前記第1のインダクタのゼロ電流が検出される第1のタイミングに基づいて、カウンタのカウント値をクリアし、
前記カウント値がクリアされるタイミングで、前記第1のスイッチをオンにし、
前記第2のインダクタのゼロ電流が検出される第2のタイミングに基づいて、前記第2のスイッチをオンにし、
前記カウンタのカウント値をクリアする際、
前記第1のタイミングが、周期下限値を下回る場合、当該周期下限値まで待機してから前記カウンタ値をクリアするPFC制御方法。
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CN201280020387.6A CN103503296B (zh) | 2011-04-26 | 2012-04-06 | Pfc信号生成电路、使用pfc信号生成电路的pfc控制***、以及pfc控制方法 |
JP2013511900A JP5584827B2 (ja) | 2011-04-26 | 2012-04-06 | Pfc信号生成回路、それを用いたpfc制御システム、及びpfc制御方法 |
US15/612,468 US10158283B2 (en) | 2011-04-26 | 2017-06-02 | PFC signal generation circuit, PFC control system using the same, and PFC control method |
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