WO2012120796A1 - Semiconductor device and method for manufacturing same - Google Patents

Semiconductor device and method for manufacturing same Download PDF

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Publication number
WO2012120796A1
WO2012120796A1 PCT/JP2012/001088 JP2012001088W WO2012120796A1 WO 2012120796 A1 WO2012120796 A1 WO 2012120796A1 JP 2012001088 W JP2012001088 W JP 2012001088W WO 2012120796 A1 WO2012120796 A1 WO 2012120796A1
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layer
base
base layer
region
semiconductor device
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PCT/JP2012/001088
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French (fr)
Japanese (ja)
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賢一 宮島
村山　啓一
昌宏 前田
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パナソニック株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/6631—Bipolar junction transistors [BJT] with an active layer made of a group 13/15 material
    • H01L29/66318—Heterojunction transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV

Definitions

  • the present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a heterojunction bipolar transistor and a manufacturing method thereof.
  • GaAs-MESFET Metal Semiconductor Field Effect Transistor
  • GaAs-HEMT High Electron Mobility Transistor
  • HBT HeteroTransistor
  • a heterojunction bipolar transistor does not require a negative power supply, as compared with a GaAs-MESFET.
  • a single positive power supply operation is possible.
  • the collector current density can be increased. Therefore, HBT has an advantage that the chip size can be reduced as compared with GaAs-MESFET.
  • a base ballast resistor connected to the base of the bipolar transistor and giving negative feedback to the voltage between the base and the emitter with respect to the temperature rise of the element is used.
  • the HBT was formed in an island shape on the subcollector layer 11, the collector layer 12 and the base layer 13 formed in an island shape on the subcollector layer 11, and the base layer 13. And an emitter layer 14.
  • the HBT further includes a collector electrode 15 formed on the subcollector layer 11 and an emitter electrode 18 formed on the emitter layer 14.
  • a DC terminal to which a DC bias is applied is connected to the first base electrode 16 formed on the base layer 13.
  • An RF terminal to which a high-frequency signal is input is connected to the second base electrode 17 formed on the base layer 13.
  • a ballast resistor element 19 for suppressing thermal runaway is connected (externally connected) to the DC terminal between the first base electrode 16.
  • FIG. 6 shows a cross-sectional configuration of an HBT according to a second conventional example in which no ballast resistor element is provided outside the transistor element.
  • the distance between the first base electrode 16 connected to the DC terminal and the end of the emitter layer 14 facing the base electrode 16 is the second base electrode 17 connected to the RF terminal. And the distance between the end of the emitter layer 14 facing the base electrode 16 is larger. Therefore, the first base electrode 16 side uses the internal resistance component 13a of the base layer 13 as a ballast resistor.
  • the ballast resistor element 19 connected to the DC terminal is connected to the outside of the transistor element.
  • a plurality of amplifying elements used for a mobile communication power amplifier are required.
  • one resistance element is required for one element, and there is a problem that the chip size increases as the amplification factor increases.
  • the HBT according to the second conventional example uses the internal resistance of the base layer as a ballast resistor by increasing the distance between the first base electrode connected to the DC terminal and the end of the emitter layer. For this reason, there is a problem that the cell size increases.
  • a semiconductor device having a ballast resistor having a desired resistance value can be realized without increasing the chip size and the cell size.
  • the semiconductor device has a high resistance region in a region between the base electrode to which a DC bias is applied in the base layer and the emitter layer.
  • a semiconductor device includes a collector layer made of a first conductivity type semiconductor, a base layer made of a second conductivity type semiconductor formed on the collector layer, and a base on the base layer. And an emitter layer made of a first conductivity type semiconductor selectively formed so as to expose the layer.
  • the semiconductor device further includes a first base electrode formed on the base layer and applied with a DC bias voltage, and a second base electrode formed on the base layer and input with a high-frequency signal.
  • the base layer has a high resistance region, and the high resistance region includes a peripheral region of the first base electrode in the lower portion of the first base electrode and is formed so as not to reach the lower portion of the emitter layer. The resistance value is higher than that of other regions.
  • the high resistance region of the base layer includes the peripheral region of the first base electrode in the lower portion of the first base electrode to which the DC bias voltage is applied, and the lower side of the emitter layer. It is formed so as not to reach the portion, and has a higher resistance value than other regions. Therefore, a ballast resistor effective for thermal runaway can be formed without providing a ballast resistor element outside the cell or increasing the distance between the first base electrode and the emitter layer.
  • a desired ballast resistance value can be obtained by controlling the dose amount and acceleration voltage of ion implantation regardless of the sheet resistance of the base layer. Therefore, the desired ballast resistance value can be controlled independently of the carrier concentration. Thereby, a high ballast resistance value can be realized without affecting the RF characteristics.
  • the emitter layer preferably includes a semiconductor layer having a band gap larger than that of the base layer at a portion in contact with the base layer.
  • HBT heterojunction bipolar transistor
  • the high resistance region may be formed by implanting ions.
  • the ions may be helium ions or boron ions.
  • the method of manufacturing a semiconductor device includes a step of forming a collector layer made of a first conductivity type semiconductor on a substrate, and a base layer made of a second conductivity type semiconductor on the collector layer. And a step of forming an emitter layer made of a first conductivity type semiconductor on the base layer. Further, the method for manufacturing a semiconductor device includes a step of forming the emitter layer in an island shape by selectively etching the emitter layer. Furthermore, the semiconductor device manufacturing method includes a step of forming the base layer and the collector layer in an island shape by selectively etching the base layer and the collector layer so as to include the island-shaped emitter layer. .
  • the method for manufacturing a semiconductor device includes a step of forming a high resistance region in the base layer by implanting ions at a distance from the emitter layer into a lateral region of the island-shaped emitter layer in the base layer. Furthermore, the method for manufacturing a semiconductor device includes a step of forming a base electrode to which a DC bias voltage is applied on a high resistance region.
  • a step of forming a high resistance region in the base layer by implanting ions into the side region of the island-shaped emitter layer in the base layer at a distance from the emitter layer It has. Therefore, a ballast resistor effective for thermal runaway can be formed without providing a ballast resistor element outside the cell or increasing the distance between the base electrode to which the DC bias voltage is applied and the emitter layer.
  • a desired ballast resistance value can be obtained by controlling the dose amount and acceleration voltage of ion implantation regardless of the sheet resistance of the base layer. Therefore, the desired ballast resistance value can be controlled independently of the carrier concentration. Thereby, a high ballast resistance value can be realized without affecting the RF characteristics.
  • the step of forming the emitter layer it is preferable to form a semiconductor layer having a band gap larger than that of the base layer in a portion in contact with the base layer in the emitter layer.
  • HBT heterojunction bipolar transistor
  • the ions in the step of forming the high resistance region, may be helium ions or boron ions.
  • the step of forming the high resistance region may be performed simultaneously with the formation of the element isolation region by ion implantation.
  • a semiconductor device having a ballast resistor having a desired resistance value can be realized without increasing the chip size and the cell size.
  • FIG. 1A is a plan view schematically showing a semiconductor device according to an embodiment of the present invention.
  • 1B is a cross-sectional view taken along line 1b-1b in FIG. 1A.
  • FIG. 2 is a graph comparing current-voltage characteristics of a high resistance base region implanted with helium ions with a conventional base layer in a semiconductor device according to an embodiment of the present invention.
  • FIG. 3 is a graph showing the dose dependency of the sheet resistance value in the high resistance base region of the semiconductor device according to the embodiment of the present invention.
  • FIG. 4A is a cross-sectional view in the order of steps showing the method for manufacturing the semiconductor device according to one embodiment of the present invention.
  • FIG. 4B is a cross-sectional view in the order of steps showing the method for manufacturing the semiconductor device according to the embodiment of the present invention.
  • FIG. 4C is a cross-sectional view in the order of steps showing the method for manufacturing the semiconductor device according to the embodiment of the present invention.
  • FIG. 4D is a cross-sectional view in the order of steps showing the method for manufacturing the semiconductor device according to the embodiment of the present invention.
  • FIG. 5 is a schematic cross-sectional view showing a heterojunction bipolar transistor to which a base ballast resistor according to a first conventional example is externally connected.
  • FIG. 6 is a cross-sectional view showing a heterojunction bipolar transistor having a base ballast resistor formed therein according to a second conventional example.
  • the heterojunction bipolar transistor (HBT) 100 includes a sub-collector layer made of n-type GaAs doped with impurities at a high concentration of about 5 ⁇ 10 18 cm ⁇ 3. 101. Also, the collector layer 102 made of n-type GaAs doped with impurities at a low concentration of about 1 ⁇ 10 16 m ⁇ 3 and p-type GaAs doped with impurities at a high concentration of about 4 ⁇ 10 19 cm ⁇ 3. And a base layer 103.
  • the emitter layer 104 has a stacked structure including a plurality of semiconductor layers containing n-type InGaP doped with an impurity concentration of about 1 ⁇ 10 17 cm ⁇ 3 .
  • the semiconductor layer in contact with the base layer 103 in the emitter layer 104 is made of a semiconductor layer having a larger band gap than that of the base layer 103, for example, InGaP.
  • the collector layer 102 and the base layer 103 are processed into a convex shape on the subcollector layer 101 to form a base island region.
  • the emitter layer 104 is processed into a convex shape on the base layer 103 to form an emitter island region.
  • collector electrodes 9 On the upper surface of the subcollector layer 101 exposed from the collector layer 102, for example, a plurality of collector electrodes 9 each formed by laminating gold germanium (AuGe) / nickel (Ni) / gold (Au) or the like are formed. A collector terminal 4 for applying a voltage to the collector layer 102 is connected to each of the collector electrodes 9.
  • a first base electrode 7 and a second base electrode 8 formed by thermal diffusion are formed on the upper surface of the base layer 103 exposed from the emitter layer 104 so as to be in ohmic contact with the base layer 103, respectively.
  • a metal laminated film such as platinum (Pt) / titanium (Ti) / platinum (Pt) / gold (Au) can be used.
  • a DC terminal 2 to which a direct current (DC) bias is applied is connected to the first base electrode 7.
  • the second base electrode 8 is connected to an RF terminal 3 to which high frequency (RF) power is supplied.
  • an emitter electrode 6 formed by laminating Pt / Ti / Pt / Au or the like is formed on the upper surface of the emitter layer 104.
  • An emitter terminal 1 is connected to the emitter electrode 6.
  • a high resistance base in which helium ions (He +) or the like are ion-implanted into the lower portion of the first base electrode 7 connected to the DC terminal 2 in the base layer 103 to increase the resistance.
  • Region 150 is formed.
  • the high resistance base region 150 is formed in a region larger than the plane area of the first base electrode 7. That is, the base layer 103 is formed so as to include the peripheral region of the first base electrode 7. However, the end of the high resistance base region 150 on the emitter layer 104 side does not reach the lower portion of the emitter layer 104.
  • the high resistance base region 150 preferably has a resistance value of about twice or more the resistance value before ion implantation in the base layer 103.
  • FIG. 2 shows current-voltage characteristics when helium ions (He +) or the like are implanted into the base layer (marked with ⁇ ) and when ions are not implanted (marked with ⁇ ). It can be seen that the graph of the base layer 103 implanted with helium ions according to the present embodiment has a smaller inclination than the graph of the conventional base layer into which helium ions are not implanted, that is, the resistance value is increased.
  • the high resistance base region 150 is ohmically connected to the first base electrode 7 and can be used as a resistance layer.
  • FIG. 3 shows a sheet when helium ions are implanted into a base layer made of p-type GaAs doped at a high concentration of about 4 ⁇ 10 19 cm ⁇ 3 at an acceleration voltage of 100 keV and a dose amount in three ways.
  • the measurement result of the resistance value (dependence on the He dose) is shown.
  • the resistance value can be changed by adjusting the dose during ion implantation. Therefore, it can be understood that an arbitrary resistance value can be realized by appropriately combining the base sheet resistance value and the ion implantation conditions (acceleration voltage and dose amount).
  • the high resistance base region 150 is formed in the region between the first base electrode 7 to which the DC bias voltage is applied in the base layer 103 and the emitter layer 104.
  • a ballast resistor effective for thermal runaway can be formed without providing a ballast resistor element outside the cell or increasing the distance between the first base electrode and the emitter layer as in the prior art. it can.
  • the high resistance base region 150 is formed by ion implantation, a desired ballast resistance value can be obtained by controlling (adjusting) the dose amount and acceleration voltage of ion implantation regardless of the sheet resistance value of the base layer 103. Obtainable. Therefore, the desired ballast resistance value can be controlled independently of the carrier concentration. Thereby, a high ballast resistance value can be realized without affecting the RF characteristics. That is, an HBT including a ballast resistor having a desired resistance value can be realized without increasing the chip size and the cell size.
  • a substrate (not shown) made of n-type GaAs is formed by a crystal growth method such as a molecular beam epitaxy method or a metal organic chemical vapor deposition method. ), An n-type GaAs layer 101A, an n-type GaAs layer 102A, a p-type GaAs layer 103A, and a laminated structure 104A are sequentially formed.
  • the n-type GaAs layer 101A is doped with an impurity at a high concentration of about 5 ⁇ 10 18 cm ⁇ 3
  • the n-type GaAs layer 102A is doped with an impurity at a low concentration of about 1 ⁇ 10 16 m ⁇ 3. Yes.
  • the p-type GaAs layer 103A is doped with an impurity at a high concentration of about 4 ⁇ 10 19 cm ⁇ 3
  • the stacked structure 104A is an n-type InGaP doped with an impurity of about 1 ⁇ 10 17 cm ⁇ 3. It consists of a plurality of semiconductor layers including layers.
  • a first resist mask 201 is formed by a lithography method so as to cover the emitter layer formation region, that is, the emitter island region in the stacked structure 104A including the n-type InGaP layer. Subsequently, in a state where the emitter island region is covered with the first resist mask 201, wet etching or dry etching is performed on the stacked structure body 104A, and as shown in FIG. An emitter layer 104 is formed.
  • the first resist mask 201 is removed.
  • the second resist mask 202 is formed by lithography again so as to cover the base layer and collector layer forming regions in the p-type GaAs layer 103A and the n-type GaAs layer 102A, that is, the base island region. Form.
  • wet etching or dry etching is performed on the p-type GaAs layer 103A and the n-type GaAs layer 102A in a state where the base island region is covered with the second resist mask 202.
  • an island-shaped base layer 103 and a collector layer 102 are formed from the p-type GaAs layer 103A and the n-type GaAs layer 102A.
  • a third resist mask 203 is formed on the n-type GaAs layer 101A so as to cover the emitter layer 104, the base layer 103, and the collector layer.
  • an opening pattern 203a is formed in the third resist mask 203 by lithography.
  • the opening pattern 203 a a region on one side of the emitter layer 104 in the base layer 103 and a region spaced from the emitter layer 104 is exposed. Ions are implanted into the base layer 103 through the third resist mask 203 having the opening pattern 203a.
  • helium ions He + having an acceleration voltage of about 100 keV and a dose of about 7.2 ⁇ 10 13 cm ⁇ 2 are implanted into the base layer 103.
  • helium ions are implanted into a region of the base layer 103 including the first base electrode formation region, so that the high resistance base region 150 is formed.
  • helium ions are selectively implanted into a region away from the base island region in the n-type GaAs layer 101A to form an element isolation region. Form. Thereby, the subcollector layer 101 is formed from the n-type GaAs layer 101A.
  • a resist mask having an opening pattern exposing the emitter electrode formation region is formed on the emitter layer 104.
  • a predetermined metal laminated film is formed by a sputtering method or a vacuum deposition method so that the opening pattern is filled on the resist mask.
  • the emitter electrode 6 is formed by a so-called lift-off method that removes the resist mask.
  • the first base electrode 7 made of a predetermined metal laminated film is formed on the high resistance base region 150 on the base layer 103 by a lift-off method.
  • a second base electrode 8 having the same composition as that of the first base electrode 7 is formed on the base layer 103 in a region opposite to the first base electrode 7 with respect to the emitter layer 104. .
  • a collector electrode 9 made of a predetermined metal laminated film is formed on the subcollector layer 101 by a lift-off method.
  • the order of formation of the emitter electrode 6, the first base electrode 7, the second base electrode 8, and the collector electrode 9 is not particularly limited.
  • the HBT 100 shown in FIGS. 1A and 1B can be obtained.
  • the helium ion implantation conditions are an acceleration voltage of about 100 keV and a dose amount of about 7.2 ⁇ 10 13 cm ⁇ 2 .
  • a desired resistance value can be given to the high resistance base region 150 by appropriately changing these implantation conditions.
  • helium ion ion implantation used for forming the high resistance base region 150 and helium ion ion implantation used for forming the element isolation region can be performed simultaneously. . Thereby, the process of implanting helium ions can be reduced.
  • helium ions are used to form the high resistance base region 150.
  • the ion species used for ion implantation is not limited to helium ions.
  • boron ions (B +) have the same effect. It goes without saying that it can be obtained.
  • hydrogen ions (H +) can be used in addition to helium ions and boron ions.
  • heterojunction bipolar transistor HBT
  • BT homojunction bipolar transistor
  • the semiconductor device and the manufacturing method thereof according to the present invention can realize a semiconductor device having a ballast resistor having a desired resistance value without increasing the chip size and the cell size.
  • a semiconductor device having a heterojunction bipolar transistor, such as a power amplifier is useful for a semiconductor device having a heterojunction bipolar transistor, such as a power amplifier.

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Abstract

This semiconductor device is provided with: a first conductivity type collector layer (102); a second conductivity type base layer (103), which is formed on the collector layer; a first conductivity type emitter layer (104), which is selectively formed on the base layer such that the base layer is exposed; a first base electrode (7), which is formed on the base layer, and has a direct current bias voltage applied thereto; and a second base electrode (8), which is formed on the base layer, and has high frequency signals inputted thereto. The base layer (103) has a high-resistance base region (150), which has a resistance value higher than the resistance values of other regions, and which is formed in a region below the first base electrode (7) such that the high-resistance base region includes the peripheral region of the first base electrode (7) and that the high-resistance base region does not reach a portion below the emitter layer (104).

Description

半導体装置及びその製造方法Semiconductor device and manufacturing method thereof
　本発明は、半導体装置及びその製造方法に関し、特にヘテロ接合バイポーラトランジスタを有する半導体装置及びその製造方法に関する。 The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a heterojunction bipolar transistor and a manufacturing method thereof.
　現在、移動体通信用電力増幅器には、増幅素子として、ＧａＡｓ―ＭＥＳＦＥＴ（Ｍｅｔａｌ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　Ｆｉｅｌｄ　Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ）、ＧａＡｓ―ＨＥＭＴ（Ｈｉｇｈ　Ｅｌｅｃｔｒｏｎ　Ｍｏｂｉｌｉｔｙ　Ｔｒａｎｓｉｓｔｏｒ）及びヘテロ接合バイポーラトランジスタ（ＨＢＴ：Ｈｅｔｅｒｏ―ｊｕｎｃｔｉｏｎ　Ｂｉｐｏｌａｒ　Ｔｒａｎｓｉｓｔｏｒ）等が用いられている。特に、ヘテロ接合バイポーラトランジスタ（以下、ＨＢＴと略称する。）は、ＧａＡｓ―ＭＥＳＦＥＴと比較して、第１に、負電源を必要としないため、単一の正電源動作が可能である、第２に、コレクタ電流密度を大きくできる。そのため、ＨＢＴはＧａＡｓ－ＭＥＳＦＥＴよりもチップサイズの小型化が可能である、という利点を有している。 Currently, in power amplifiers for mobile communications, GaAs-MESFET (Metal Semiconductor Field Effect Transistor), GaAs-HEMT (High Electron Mobility Transistor), and heterojunction bipolar transistor (HBT: HeteroTransistor) are used as amplifying elements. Is used. In particular, a heterojunction bipolar transistor (hereinafter abbreviated as HBT) does not require a negative power supply, as compared with a GaAs-MESFET. First, a single positive power supply operation is possible. In addition, the collector current density can be increased. Therefore, HBT has an advantage that the chip size can be reduced as compared with GaAs-MESFET.
　一般に、バイポーラトランジスタは、素子の温度が上昇すると、ベース－エミッタ間のオン電圧が低下するために、コレクタ電流が増加することが知られている。このため、複数のトランジスタを有する高周波電力増幅器において、コレクタ電流の集中が生じると、消費電力の増加により局所的な素子の温度上昇が発生する。これにより、さらに局所的な素子でコレクタ電流が増加するという悪循環に陥る。従って、各トランジスタ間の電流が不均一になると、電力増幅器の性能及び寿命に悪影響を与えるだけでなく、電流の集中がさらに進むことから、トランジスタが熱暴走の状態に陥り、破壊に至ることがある。 In general, it is known that in the bipolar transistor, when the temperature of the element rises, the on-voltage between the base and the emitter decreases, so that the collector current increases. For this reason, in the high-frequency power amplifier having a plurality of transistors, when the collector current is concentrated, a local temperature rise of the element occurs due to an increase in power consumption. This causes a vicious circle in which the collector current increases in more local elements. Therefore, if the current between the transistors becomes uneven, it not only adversely affects the performance and life of the power amplifier, but the current concentration further increases, so that the transistor falls into a state of thermal runaway and may be destroyed. is there.
　このような問題に対して、バイポーラトランジスタのベースと接続され、素子の温度上昇に対してベース－エミッタ間の電圧に負帰還を与えるベースバラスト抵抗が用いられている。このベース－エミッタ間の電圧の負帰還により、温度上昇によるコレクタ電流の増加を相殺して、熱暴走を防ぐことが可能となる。 For this problem, a base ballast resistor connected to the base of the bipolar transistor and giving negative feedback to the voltage between the base and the emitter with respect to the temperature rise of the element is used. By this negative feedback of the voltage between the base and the emitter, an increase in the collector current due to a temperature rise can be offset and thermal runaway can be prevented.
　以下に、第１の従来例に係る、ベースバラスト抵抗を用いたＨＢＴの断面構成を説明する（例えば、特許文献１を参照。）。 Hereinafter, a cross-sectional configuration of the HBT using the base ballast resistor according to the first conventional example will be described (for example, see Patent Document 1).
　図５に示すように、ＨＢＴは、サブコレクタ層１１と、サブコレクタ層１１の上に島状に形成されたコレクタ層１２及びベース層１３と、ベース層１３の上に島状に形成されたエミッタ層１４とを有している。さらにＨＢＴは、サブコレクタ層１１の上に形成されたコレクタ電極１５と、エミッタ層１４の上に形成されたエミッタ電極１８とを有している。 As shown in FIG. 5, the HBT was formed in an island shape on the subcollector layer 11, the collector layer 12 and the base layer 13 formed in an island shape on the subcollector layer 11, and the base layer 13. And an emitter layer 14. The HBT further includes a collector electrode 15 formed on the subcollector layer 11 and an emitter electrode 18 formed on the emitter layer 14.
　ベース層１３の上に形成された第１のベース電極１６には、直流バイアスが印加されるＤＣ端子が接続されている。ベース層１３の上に形成された第２のベース電極１７には、高周波信号が入力されるＲＦ端子が接続されている。また、ＤＣ端子には熱暴走を抑止するためのバラスト抵抗素子１９が第１のベース電極１６との間に接続（外部接続）されている。 A DC terminal to which a DC bias is applied is connected to the first base electrode 16 formed on the base layer 13. An RF terminal to which a high-frequency signal is input is connected to the second base electrode 17 formed on the base layer 13. In addition, a ballast resistor element 19 for suppressing thermal runaway is connected (externally connected) to the DC terminal between the first base electrode 16.
　図６は、バラスト抵抗素子をトランジスタ素子の外部に設けない、第２の従来例に係るＨＢＴの断面構成を示す。 FIG. 6 shows a cross-sectional configuration of an HBT according to a second conventional example in which no ballast resistor element is provided outside the transistor element.
　第２の従来例においては、ＤＣ端子と接続された第１のベース電極１６とエミッタ層１４のベース電極１６に対向する端部との距離が、ＲＦ端子と接続された第２のベース電極１７とエミッタ層１４のベース電極１６に対向する端部との距離よりも大きい。従って、第１のベース電極１６側はベース層１３の内部抵抗成分１３ａをバラスト抵抗として利用している。 In the second conventional example, the distance between the first base electrode 16 connected to the DC terminal and the end of the emitter layer 14 facing the base electrode 16 is the second base electrode 17 connected to the RF terminal. And the distance between the end of the emitter layer 14 facing the base electrode 16 is larger. Therefore, the first base electrode 16 side uses the internal resistance component 13a of the base layer 13 as a ballast resistor.
特許第４５０４３２６号Patent No. 4504326
　しかしながら、第１の従来例に係るＨＢＴは、ＤＣ端子と接続されたバラスト抵抗素子１９がトランジスタ素子の外部に接続されている。一般に、移動体通信用電力増幅器に用いられる増幅素子は複数個が必要である。第１の従来例の場合は、１つの素子に対して１個の抵抗素子が必要となり、増幅率を大きくすればするほど、チップサイズが大きくなってしまうという問題がある。 However, in the HBT according to the first conventional example, the ballast resistor element 19 connected to the DC terminal is connected to the outside of the transistor element. In general, a plurality of amplifying elements used for a mobile communication power amplifier are required. In the case of the first conventional example, one resistance element is required for one element, and there is a problem that the chip size increases as the amplification factor increases.
　第２の従来例に係るＨＢＴは、ＤＣ端子と接続された第１のベース電極とエミッタ層の端部までの距離を大きくすることにより、ベース層の内部抵抗をバラスト抵抗として用いている。このため、セルサイズが拡大してしまうという問題がある。 The HBT according to the second conventional example uses the internal resistance of the base layer as a ballast resistor by increasing the distance between the first base electrode connected to the DC terminal and the end of the emitter layer. For this reason, there is a problem that the cell size increases.
　また、より大きい抵抗値を得ようとすると、この距離を延長してセルサイズをより大きくするか、ベース層のキャリア濃度を下げてベース層のシート抵抗値を上げる必要がある。しかしながら、ベース層のキャリア濃度を下げてしまうと、ＲＦ端子と接続されたベース層の抵抗値も増大して、ＲＦ特性が劣化してしまう。 In order to obtain a larger resistance value, it is necessary to increase the cell size by extending this distance, or to lower the carrier concentration of the base layer to increase the sheet resistance value of the base layer. However, if the carrier concentration of the base layer is lowered, the resistance value of the base layer connected to the RF terminal also increases, and the RF characteristics deteriorate.
　かかる問題に鑑み、チップサイズ及びセルサイズを大きくすることなく、所望の抵抗値を持つバラスト抵抗を備えた半導体装置を実現できるようにする。 In view of such problems, a semiconductor device having a ballast resistor having a desired resistance value can be realized without increasing the chip size and the cell size.
　半導体装置は、ベース層における直流バイアスが印加されるベース電極とエミッタ層との間の領域に高抵抗領域を有する。 The semiconductor device has a high resistance region in a region between the base electrode to which a DC bias is applied in the base layer and the emitter layer.
　具体的に、本発明に係る半導体装置は、第１導電型の半導体からなるコレクタ層と、コレクタ層の上に形成された第２導電型の半導体からなるベース層と、ベース層の上にベース層を露出するように選択的に形成された第１導電型の半導体からなるエミッタ層とを有する。さらに、半導体装置は、ベース層の上に形成され、直流バイアス電圧が印加される第１のベース電極と、ベース層の上に形成され、高周波信号が入力される第２のベース電極とを有する。さらに、ベース層は高抵抗領域を有し、高抵抗領域は、第１のベース電極の下側部分に第１のベース電極の周辺領域を含むと共にエミッタ層の下側部分に達しないように形成され、他の領域と比べて抵抗値が高い。 Specifically, a semiconductor device according to the present invention includes a collector layer made of a first conductivity type semiconductor, a base layer made of a second conductivity type semiconductor formed on the collector layer, and a base on the base layer. And an emitter layer made of a first conductivity type semiconductor selectively formed so as to expose the layer. The semiconductor device further includes a first base electrode formed on the base layer and applied with a DC bias voltage, and a second base electrode formed on the base layer and input with a high-frequency signal. . Further, the base layer has a high resistance region, and the high resistance region includes a peripheral region of the first base electrode in the lower portion of the first base electrode and is formed so as not to reach the lower portion of the emitter layer. The resistance value is higher than that of other regions.
　本発明の半導体装置によると、ベース層が有する高抵抗領域は、直流バイアス電圧が印加される第１のベース電極の下側部分に第１のベース電極の周辺領域を含むと共にエミッタ層の下側部分に達しないように形成され、他の領域と比べて抵抗値が高い。このため、バラスト抵抗素子をセルの外部に設けたり、第１のベース電極とエミッタ層との距離を拡大したりすることなく、熱暴走に有効なバラスト抵抗を形成することができる。その上、高抵抗領域をイオン注入により形成する場合には、ベース層のシート抵抗によらず、イオン注入のドーズ量及び加速電圧を制御することにより、所望のバラスト抵抗値を得ることができる。従って、所望のバラスト抵抗値をキャリア濃度とは独立して制御可能である。これにより、ＲＦ特性に影響を与えることなく、高いバラスト抵抗値を実現できる。 According to the semiconductor device of the present invention, the high resistance region of the base layer includes the peripheral region of the first base electrode in the lower portion of the first base electrode to which the DC bias voltage is applied, and the lower side of the emitter layer. It is formed so as not to reach the portion, and has a higher resistance value than other regions. Therefore, a ballast resistor effective for thermal runaway can be formed without providing a ballast resistor element outside the cell or increasing the distance between the first base electrode and the emitter layer. In addition, when the high resistance region is formed by ion implantation, a desired ballast resistance value can be obtained by controlling the dose amount and acceleration voltage of ion implantation regardless of the sheet resistance of the base layer. Therefore, the desired ballast resistance value can be controlled independently of the carrier concentration. Thereby, a high ballast resistance value can be realized without affecting the RF characteristics.
　本発明に係る半導体装置は、エミッタ層が、ベース層と接する部分にベース層と比べてバンドギャップが大きい半導体層を含むことが好ましい。 In the semiconductor device according to the present invention, the emitter layer preferably includes a semiconductor layer having a band gap larger than that of the base layer at a portion in contact with the base layer.
　このようにすると、ヘテロ接合バイポーラトランジスタ（ＨＢＴ）を形成することができる。 In this way, a heterojunction bipolar transistor (HBT) can be formed.
　本発明に係る半導体装置は、高抵抗領域はイオンが注入されることにより形成されていてもよい。 In the semiconductor device according to the present invention, the high resistance region may be formed by implanting ions.
　この場合に、イオンは、ヘリウムイオン又はボロンイオンであってもよい。 In this case, the ions may be helium ions or boron ions.
　本発明に係る半導体装置の製造方法は、基板の上に、第１導電型の半導体からなるコレクタ層を形成する工程と、コレクタ層の上に第２導電型の半導体からなるベース層を形成する工程と、ベース層の上に第１導電型の半導体からなるエミッタ層を形成する工程とを有する。さらに半導体装置の製造方法は、エミッタ層に対して選択的にエッチングを行うことにより、エミッタ層を島状に形成する工程を有する。さらに、半導体装置の製造方法は、ベース層及びコレクタ層に対して、島状のエミッタ層を含むように選択的にエッチングを行うことにより、ベース層及びコレクタ層を島状に形成する工程を有する。さらに半導体装置の製造方法は、ベース層における島状のエミッタ層の側方領域に対してエミッタ層から間隔をおいてイオンを注入することにより、ベース層に高抵抗領域を形成する工程を有する。さらに半導体装置の製造方法は、高抵抗領域の上に、直流バイアス電圧が印加されるベース電極を形成する工程を有する。 The method of manufacturing a semiconductor device according to the present invention includes a step of forming a collector layer made of a first conductivity type semiconductor on a substrate, and a base layer made of a second conductivity type semiconductor on the collector layer. And a step of forming an emitter layer made of a first conductivity type semiconductor on the base layer. Further, the method for manufacturing a semiconductor device includes a step of forming the emitter layer in an island shape by selectively etching the emitter layer. Furthermore, the semiconductor device manufacturing method includes a step of forming the base layer and the collector layer in an island shape by selectively etching the base layer and the collector layer so as to include the island-shaped emitter layer. . Further, the method for manufacturing a semiconductor device includes a step of forming a high resistance region in the base layer by implanting ions at a distance from the emitter layer into a lateral region of the island-shaped emitter layer in the base layer. Furthermore, the method for manufacturing a semiconductor device includes a step of forming a base electrode to which a DC bias voltage is applied on a high resistance region.
　本発明の半導体装置の製造方法によると、ベース層における島状のエミッタ層の側方領域に対してエミッタ層から間隔をおいてイオンを注入することにより、ベース層に高抵抗領域を形成する工程を備えている。このため、バラスト抵抗素子をセルの外部に設けたり、直流バイアス電圧が印加されるベース電極とエミッタ層との距離を拡大したりすることなく、熱暴走に有効なバラスト抵抗を形成することができる。その上、高抵抗領域をイオン注入により形成するため、ベース層のシート抵抗によらず、イオン注入のドーズ量及び加速電圧を制御することにより、所望のバラスト抵抗値を得ることができる。従って、所望のバラスト抵抗値をキャリア濃度とは独立して制御可能である。これにより、ＲＦ特性に影響を与えることなく、高いバラスト抵抗値を実現できる。 According to the method for manufacturing a semiconductor device of the present invention, a step of forming a high resistance region in the base layer by implanting ions into the side region of the island-shaped emitter layer in the base layer at a distance from the emitter layer. It has. Therefore, a ballast resistor effective for thermal runaway can be formed without providing a ballast resistor element outside the cell or increasing the distance between the base electrode to which the DC bias voltage is applied and the emitter layer. . In addition, since the high resistance region is formed by ion implantation, a desired ballast resistance value can be obtained by controlling the dose amount and acceleration voltage of ion implantation regardless of the sheet resistance of the base layer. Therefore, the desired ballast resistance value can be controlled independently of the carrier concentration. Thereby, a high ballast resistance value can be realized without affecting the RF characteristics.
　本発明の半導体装置の製造方法は、エミッタ層を形成する工程において、エミッタ層におけるベース層と接する部分に、ベース層と比べてバンドギャップが大きい半導体層を形成することが好ましい。 In the method of manufacturing a semiconductor device according to the present invention, in the step of forming the emitter layer, it is preferable to form a semiconductor layer having a band gap larger than that of the base layer in a portion in contact with the base layer in the emitter layer.
　このようにすると、ヘテロ接合バイポーラトランジスタ（ＨＢＴ）を形成することができる。 In this way, a heterojunction bipolar transistor (HBT) can be formed.
　本発明の半導体装置の製造方法は、高抵抗領域を形成する工程において、イオンはヘリウムイオン又はボロンイオンであってもよい。 In the method for manufacturing a semiconductor device of the present invention, in the step of forming the high resistance region, the ions may be helium ions or boron ions.
　本発明の半導体装置の製造方法において、高抵抗領域を形成する工程は、イオン注入による素子分離領域の形成と同時に行ってもよい。 In the method of manufacturing a semiconductor device of the present invention, the step of forming the high resistance region may be performed simultaneously with the formation of the element isolation region by ion implantation.
　本発明に係る半導体装置及びその製造方法によると、チップサイズ及びセルサイズを大きくすることなく、所望の抵抗値を持つバラスト抵抗を備えた半導体装置を実現することができる。 According to the semiconductor device and the manufacturing method thereof according to the present invention, a semiconductor device having a ballast resistor having a desired resistance value can be realized without increasing the chip size and the cell size.
図１Ａは、本発明の一実施形態に係る半導体装置を模式的に示した平面図である。FIG. 1A is a plan view schematically showing a semiconductor device according to an embodiment of the present invention. 図１Ｂは、図１Ａの１ｂ－１ｂ線における断面図である。1B is a cross-sectional view taken along line 1b-1b in FIG. 1A. 図２は、本発明の一実施形態に係る半導体装置における、ヘリウムイオンを注入された高抵抗ベース領域の電流－電圧特性を従来のベース層と比較したグラフである。FIG. 2 is a graph comparing current-voltage characteristics of a high resistance base region implanted with helium ions with a conventional base layer in a semiconductor device according to an embodiment of the present invention. 図３は、本発明の一実施形態に係る半導体装置の高抵抗ベース領域におけるシート抵抗値のドーズ量依存性を示すグラフである。FIG. 3 is a graph showing the dose dependency of the sheet resistance value in the high resistance base region of the semiconductor device according to the embodiment of the present invention. 図４Ａは、本発明の一実施形態に係る半導体装置の製造方法を示す工程順の断面図である。FIG. 4A is a cross-sectional view in the order of steps showing the method for manufacturing the semiconductor device according to one embodiment of the present invention. 図４Ｂは、本発明の一実施形態に係る半導体装置の製造方法を示す工程順の断面図である。FIG. 4B is a cross-sectional view in the order of steps showing the method for manufacturing the semiconductor device according to the embodiment of the present invention. 図４Ｃは、本発明の一実施形態に係る半導体装置の製造方法を示す工程順の断面図である。FIG. 4C is a cross-sectional view in the order of steps showing the method for manufacturing the semiconductor device according to the embodiment of the present invention. 図４Ｄは、本発明の一実施形態に係る半導体装置の製造方法を示す工程順の断面図である。FIG. 4D is a cross-sectional view in the order of steps showing the method for manufacturing the semiconductor device according to the embodiment of the present invention. 図５は、第１の従来例に係るベースバラスト抵抗が外部接続されたヘテロ接合バイポーラトランジスタを示す模式的な断面図である。FIG. 5 is a schematic cross-sectional view showing a heterojunction bipolar transistor to which a base ballast resistor according to a first conventional example is externally connected. 図６は、第２の従来例に係るベースバラスト抵抗が内部形成されたヘテロ接合バイポーラトランジスタを示す断面図である。FIG. 6 is a cross-sectional view showing a heterojunction bipolar transistor having a base ballast resistor formed therein according to a second conventional example.
　（一実施形態）
　本発明の一実施形態について図１Ａおよび図１Ｂを参照しながら説明する。 (One embodiment)
An embodiment of the present invention will be described with reference to FIGS. 1A and 1B.
　図１Ａ及び図１Ｂに示すように、本実施形態に係るヘテロ接合バイポーラトランジスタ（ＨＢＴ）１００は、不純物が５×１０１８ｃｍ－３程度の高濃度にドープされたｎ型ＧａＡｓからなるサブコレクタ層１０１を有する。また、不純物が１×１０１６ｍ－３程度の低濃度にドープされたｎ型ＧａＡｓからなるコレクタ層１０２と、不純物が４×１０１９ｃｍ－３程度の高濃度にドープされたｐ型ＧａＡｓからなるベース層１０３とを有する。また、不純物濃度が１×１０１７ｃｍ－３程度にドープされたｎ型ＩｎＧａＰを含む複数の半導体層からなる積層構造を有するエミッタ層１０４を有する。 As shown in FIGS. 1A and 1B, the heterojunction bipolar transistor (HBT) 100 according to the present embodiment includes a sub-collector layer made of n-type GaAs doped with impurities at a high concentration of about 5 × 10 18 cm −3. 101. Also, the collector layer 102 made of n-type GaAs doped with impurities at a low concentration of about 1 × 10 16 m −3 and p-type GaAs doped with impurities at a high concentration of about 4 × 10 19 cm −3. And a base layer 103. The emitter layer 104 has a stacked structure including a plurality of semiconductor layers containing n-type InGaP doped with an impurity concentration of about 1 × 10 17 cm −3 .
　ここで、エミッタ層１０４におけるベース層１０３と接する半導体層は、ベース層１０３と比べてバンドギャップが大きい半導体層、例えばＩｎＧａＰにより構成されている。 Here, the semiconductor layer in contact with the base layer 103 in the emitter layer 104 is made of a semiconductor layer having a larger band gap than that of the base layer 103, for example, InGaP.
　コレクタ層１０２及びベース層１０３は、サブコレクタ層１０１上に凸型形状に加工されており、ベース島領域を形成している。また、エミッタ層１０４は、ベース層１０３上に凸型形状に加工されており、エミッタ島領域を形成している。 The collector layer 102 and the base layer 103 are processed into a convex shape on the subcollector layer 101 to form a base island region. The emitter layer 104 is processed into a convex shape on the base layer 103 to form an emitter island region.
　サブコレクタ層１０１のコレクタ層１０２から露出した上面には、例えば、それぞれ金ゲルマニウム（ＡｕＧｅ）／ニッケル（Ｎｉ）／金（Ａｕ）等が積層されてなる複数のコレクタ電極９が形成されている。複数のコレクタ電極９には、コレクタ層１０２に電圧を印加するコレクタ端子４がそれぞれ接続されている。 On the upper surface of the subcollector layer 101 exposed from the collector layer 102, for example, a plurality of collector electrodes 9 each formed by laminating gold germanium (AuGe) / nickel (Ni) / gold (Au) or the like are formed. A collector terminal 4 for applying a voltage to the collector layer 102 is connected to each of the collector electrodes 9.
　ベース層１０３のエミッタ層１０４から露出した上面には、ベース層１０３とオーミック接触するように熱拡散により形成された第１のベース電極７及び第２のベース電極８がそれぞれ形成されている。第１のベース電極７及び第２のベース電極８には、例えば、白金（Ｐｔ）／チタン（Ｔｉ）／白金（Ｐｔ）／金（Ａｕ）等の金属積層膜を用いることができる。 A first base electrode 7 and a second base electrode 8 formed by thermal diffusion are formed on the upper surface of the base layer 103 exposed from the emitter layer 104 so as to be in ohmic contact with the base layer 103, respectively. For the first base electrode 7 and the second base electrode 8, for example, a metal laminated film such as platinum (Pt) / titanium (Ti) / platinum (Pt) / gold (Au) can be used.
　第１のベース電極７には、直流（ＤＣ）バイアスが印加されるＤＣ端子２が接続されている。一方、第２のベース電極８には、高周波（ＲＦ）電力が供給されるＲＦ端子３が接続されている。 A DC terminal 2 to which a direct current (DC) bias is applied is connected to the first base electrode 7. On the other hand, the second base electrode 8 is connected to an RF terminal 3 to which high frequency (RF) power is supplied.
　エミッタ層１０４の上面には、Ｐｔ／Ｔｉ／Ｐｔ／Ａｕ等が積層されてなるエミッタ電極６が形成されている。エミッタ電極６には、エミッタ端子１が接続されている。 On the upper surface of the emitter layer 104, an emitter electrode 6 formed by laminating Pt / Ti / Pt / Au or the like is formed. An emitter terminal 1 is connected to the emitter electrode 6.
　本実施形態の特徴として、ベース層１０３におけるＤＣ端子２と接続された第１のベース電極７の下側部分には、ヘリウムイオン（Ｈｅ＋）等をイオン注入して高抵抗化された高抵抗ベース領域１５０が形成されている。高抵抗ベース領域１５０は、第１のベース電極７の平面積よりも大きい領域で形成されている。すなわち、ベース層１０３における第１のベース電極７の周辺領域を含むように形成されている。但し、高抵抗ベース領域１５０のエミッタ層１０４側の端部は、エミッタ層１０４の下側部分にまでは達していない。 As a feature of the present embodiment, a high resistance base in which helium ions (He +) or the like are ion-implanted into the lower portion of the first base electrode 7 connected to the DC terminal 2 in the base layer 103 to increase the resistance. Region 150 is formed. The high resistance base region 150 is formed in a region larger than the plane area of the first base electrode 7. That is, the base layer 103 is formed so as to include the peripheral region of the first base electrode 7. However, the end of the high resistance base region 150 on the emitter layer 104 side does not reach the lower portion of the emitter layer 104.
　また、高抵抗ベース領域１５０は、ベース層１０３におけるイオン注入前の抵抗値の２倍以上程度の抵抗値を有することが好ましい。 Further, the high resistance base region 150 preferably has a resistance value of about twice or more the resistance value before ion implantation in the base layer 103.
　以下、ベース層にヘリウムイオン（Ｈｅ＋）等をイオン注入した場合の電流－電圧特性と、シート抵抗値のドーズ量依存性との実験結果を示す。 Hereinafter, experimental results of current-voltage characteristics when helium ions (He +) or the like are ion-implanted into the base layer and the dose dependency of the sheet resistance value are shown.
　図２は、ベース層にヘリウムイオン（Ｈｅ＋）等をイオン注入を行った場合（▲印）と、イオン注入を行わない場合（■印）との電流－電圧特性を示している。本実施形態に係るヘリウムイオンを注入されたベース層１０３のグラフは、ヘリウムイオンを注入されない従来のベース層のグラフと比べて傾きが小さく、すなわち抵抗値が上昇していることが分かる。 FIG. 2 shows current-voltage characteristics when helium ions (He +) or the like are implanted into the base layer (marked with ▲) and when ions are not implanted (marked with ■). It can be seen that the graph of the base layer 103 implanted with helium ions according to the present embodiment has a smaller inclination than the graph of the conventional base layer into which helium ions are not implanted, that is, the resistance value is increased.
　また、低電圧領域においても高電圧領域においても、良好な線形性を示している。このことから、高抵抗ベース領域１５０は第１のベース電極７とオーミック接続されており、抵抗層として使用可能であるといえる。 Also, good linearity is shown both in the low voltage region and in the high voltage region. From this, it can be said that the high resistance base region 150 is ohmically connected to the first base electrode 7 and can be used as a resistance layer.
　図３は、４×１０１９ｃｍ－３程度の高濃度にドープされたｐ型ＧａＡｓからなるベース層に、ヘリウムイオンを１００ｋｅＶの加速電圧で、ドーズ量を３通りに変えて注入したときのシート抵抗値の測定結果（Ｈｅドーズ量による依存性）を示している。図３に示すように、イオン注入の際のドーズ量を調節すれば抵抗値を変えることができる。従って、ベースシート抵抗値とイオン注入条件（加速電圧及びドーズ量）とを適当に組み合わせれば、任意の抵抗値を実現できることが分かる。 FIG. 3 shows a sheet when helium ions are implanted into a base layer made of p-type GaAs doped at a high concentration of about 4 × 10 19 cm −3 at an acceleration voltage of 100 keV and a dose amount in three ways. The measurement result of the resistance value (dependence on the He dose) is shown. As shown in FIG. 3, the resistance value can be changed by adjusting the dose during ion implantation. Therefore, it can be understood that an arbitrary resistance value can be realized by appropriately combining the base sheet resistance value and the ion implantation conditions (acceleration voltage and dose amount).
　このように、本実施形態によると、ベース層１０３におけるＤＣバイアス電圧が印加される第１のベース電極７とエミッタ層１０４との間の領域に高抵抗ベース領域１５０を形成する。これにより、従来のように、バラスト抵抗素子をセルの外部に設けたり、第１のベース電極とエミッタ層との距離を拡大したりすることなく、熱暴走に有効なバラスト抵抗を形成することができる。その上、高抵抗ベース領域１５０をイオン注入により形成するため、ベース層１０３のシート抵抗値によらず、イオン注入のドーズ量及び加速電圧を制御（調節）することにより、所望のバラスト抵抗値を得ることができる。従って、所望のバラスト抵抗値をキャリア濃度とは独立して制御が可能となる。これにより、ＲＦ特性に影響を与えることなく、高いバラスト抵抗値を実現できる。すなわち、チップサイズ及びセルサイズを大きくすることなく、所望の抵抗値を持つバラスト抵抗を備えたＨＢＴを実現できる。 As described above, according to the present embodiment, the high resistance base region 150 is formed in the region between the first base electrode 7 to which the DC bias voltage is applied in the base layer 103 and the emitter layer 104. As a result, a ballast resistor effective for thermal runaway can be formed without providing a ballast resistor element outside the cell or increasing the distance between the first base electrode and the emitter layer as in the prior art. it can. In addition, since the high resistance base region 150 is formed by ion implantation, a desired ballast resistance value can be obtained by controlling (adjusting) the dose amount and acceleration voltage of ion implantation regardless of the sheet resistance value of the base layer 103. Obtainable. Therefore, the desired ballast resistance value can be controlled independently of the carrier concentration. Thereby, a high ballast resistance value can be realized without affecting the RF characteristics. That is, an HBT including a ballast resistor having a desired resistance value can be realized without increasing the chip size and the cell size.
　以下、前記のような構成を有する半導体装置の製造方法について図４Ａ～図４Ｄを参照しながら説明する。 Hereinafter, a method for manufacturing a semiconductor device having the above-described configuration will be described with reference to FIGS. 4A to 4D.
　まず、図４Ａに示すように、分子線エピタキシ（Ｍｏｌｅｃｕｌａｒ　Ｂｅａｍ　Ｅｐｉｔａｘｙ）法又は有機金属化学気相成長（Ｍｅｔａｌ　Ｏｒｇａｎｉｃ　Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）法等の結晶成長法により、ｎ型ＧａＡｓからなる基板（図示せず）の主面上に、ｎ型ＧａＡｓ層１０１Ａと、ｎ型ＧａＡｓ層１０２Ａと、ｐ型ＧａＡｓ層１０３Ａと、積層構造体１０４Ａとを順次形成する。ｎ型ＧａＡｓ層１０１Ａには、不純物が５×１０１８ｃｍ－３程度の高濃度にドープされ、ｎ型ＧａＡｓ層１０２Ａには、不純物が１×１０１６ｍ－３程度の低濃度にドープされている。また、ｐ型ＧａＡｓ層１０３Ａには、不純物が４×１０１９ｃｍ－３程度の高濃度にドープされ、積層構造体１０４Ａは、不純物が１×１０１７ｃｍ－３程度にドープされたｎ型ＩｎＧａＰ層を含む複数の半導体層からなる。 First, as shown in FIG. 4A, a substrate (not shown) made of n-type GaAs is formed by a crystal growth method such as a molecular beam epitaxy method or a metal organic chemical vapor deposition method. ), An n-type GaAs layer 101A, an n-type GaAs layer 102A, a p-type GaAs layer 103A, and a laminated structure 104A are sequentially formed. The n-type GaAs layer 101A is doped with an impurity at a high concentration of about 5 × 10 18 cm −3 , and the n-type GaAs layer 102A is doped with an impurity at a low concentration of about 1 × 10 16 m −3. Yes. The p-type GaAs layer 103A is doped with an impurity at a high concentration of about 4 × 10 19 cm −3 , and the stacked structure 104A is an n-type InGaP doped with an impurity of about 1 × 10 17 cm −3. It consists of a plurality of semiconductor layers including layers.
　次に、リソグラフィ法により、ｎ型ＩｎＧａＰ層を含む積層構造体１０４Ａにおけるエミッタ層形成領域、すなわちエミッタ島領域を覆うように第１のレジストマスク２０１を形成する。続いて、第１のレジストマスク２０１によりエミッタ島領域を覆った状態で、積層構造体１０４Ａに対してウェットエッチング又はドライエッチングを行って、図４Ｂに示すように、積層構造体１０４Ａから島状のエミッタ層１０４を形成する。 Next, a first resist mask 201 is formed by a lithography method so as to cover the emitter layer formation region, that is, the emitter island region in the stacked structure 104A including the n-type InGaP layer. Subsequently, in a state where the emitter island region is covered with the first resist mask 201, wet etching or dry etching is performed on the stacked structure body 104A, and as shown in FIG. An emitter layer 104 is formed.
　次に、第１のレジストマスク２０１を除去する。その後、再度リソグラフィ法により、エミッタ層１０４を含み、且つ、ｐ型ＧａＡｓ層１０３Ａ及びｎ型ＧａＡｓ層１０２Ａにおけるベース層及びコレクタ層形成領域、すなわちベース島領域を覆うように第２のレジストマスク２０２を形成する。続いて、第２のレジストマスク２０２によりベース島領域を覆った状態で、ｐ型ＧａＡｓ層１０３Ａ及びｎ型ＧａＡｓ層１０２Ａに対してウェットエッチング又はドライエッチングを行う。そして、図４Ｃに示すように、ｐ型ＧａＡｓ層１０３Ａ及びｎ型ＧａＡｓ層１０２Ａから島状のベース層１０３及びコレクタ層１０２を形成する。 Next, the first resist mask 201 is removed. Thereafter, the second resist mask 202 is formed by lithography again so as to cover the base layer and collector layer forming regions in the p-type GaAs layer 103A and the n-type GaAs layer 102A, that is, the base island region. Form. Subsequently, wet etching or dry etching is performed on the p-type GaAs layer 103A and the n-type GaAs layer 102A in a state where the base island region is covered with the second resist mask 202. Then, as shown in FIG. 4C, an island-shaped base layer 103 and a collector layer 102 are formed from the p-type GaAs layer 103A and the n-type GaAs layer 102A.
　次に、第２のレジストマスク２０２を除去した後、ｎ型ＧａＡｓ層１０１Ａの上に、エミッタ層１０４、ベース層１０３及びコレクタ層１０２を覆うように、第３のレジストマスク２０３を形成する。続いて、図４Ｄに示すように、リソグラフィ法により、第３のレジストマスク２０３に、開口パターン２０３ａを形成する。開口パターン２０３ａによって、ベース層１０３におけるエミッタ層１０４の一方の側方領域で、且つエミッタ層１０４から間隔をおいた領域が露出される。この開口パターン２０３ａを有する第３のレジストマスク２０３を介した状態で、ベース層１０３にイオン注入する。具体的には、ベース層１０３に、加速電圧が１００ｋｅＶ程度で、ドーズ量が７．２×１０１３ｃｍ－２程度のヘリウムイオン（Ｈｅ＋）を注入する。これにより、ベース層１０３の第１のベース電極形成領域を含む領域にヘリウムイオンが注入されて、高抵抗ベース領域１５０が形成される。 Next, after removing the second resist mask 202, a third resist mask 203 is formed on the n-type GaAs layer 101A so as to cover the emitter layer 104, the base layer 103, and the collector layer. Subsequently, as shown in FIG. 4D, an opening pattern 203a is formed in the third resist mask 203 by lithography. By the opening pattern 203 a, a region on one side of the emitter layer 104 in the base layer 103 and a region spaced from the emitter layer 104 is exposed. Ions are implanted into the base layer 103 through the third resist mask 203 having the opening pattern 203a. Specifically, helium ions (He +) having an acceleration voltage of about 100 keV and a dose of about 7.2 × 10 13 cm −2 are implanted into the base layer 103. As a result, helium ions are implanted into a region of the base layer 103 including the first base electrode formation region, so that the high resistance base region 150 is formed.
　次に、図示はしていないが、第３のレジストマスク２０３を除去した後、ｎ型ＧａＡｓ層１０１Ａにおけるベース島領域から離れた領域に、ヘリウムイオンを選択的に注入して、素子分離領域を形成する。これにより、ｎ型ＧａＡｓ層１０１Ａからサブコレクタ層１０１が形成される。 Next, although not shown, after removing the third resist mask 203, helium ions are selectively implanted into a region away from the base island region in the n-type GaAs layer 101A to form an element isolation region. Form. Thereby, the subcollector layer 101 is formed from the n-type GaAs layer 101A.
　続いて、図示はしていないが、エミッタ層１０４の上に、エミッタ電極形成領域を露出する開口パターンを有するレジストマスクを形成する。その後、スパッタ法又は真空蒸着法等により、レジストマスクの上に開口パターンが埋まるように所定の金属積層膜を形成する。その後、レジストマスクを除去する、いわゆるリフトオフ法により、エミッタ電極６を形成する。 Subsequently, although not shown, a resist mask having an opening pattern exposing the emitter electrode formation region is formed on the emitter layer 104. Thereafter, a predetermined metal laminated film is formed by a sputtering method or a vacuum deposition method so that the opening pattern is filled on the resist mask. Thereafter, the emitter electrode 6 is formed by a so-called lift-off method that removes the resist mask.
　続いて、リフトオフ法により、ベース層１０３の上の高抵抗ベース領域１５０の上に、所定の金属積層膜からなる第１のベース電極７を形成する。同時に、ベース層１０３の上であって、エミッタ層１０４に対して第１のベース電極７と反対側の領域に、第１のベース電極７と組成が同一の第２のベース電極８を形成する。 Subsequently, the first base electrode 7 made of a predetermined metal laminated film is formed on the high resistance base region 150 on the base layer 103 by a lift-off method. At the same time, a second base electrode 8 having the same composition as that of the first base electrode 7 is formed on the base layer 103 in a region opposite to the first base electrode 7 with respect to the emitter layer 104. .
　続いて、リフトオフ法により、サブコレクタ層１０１の上に、所定の金属積層膜からなるコレクタ電極９を形成する。 Subsequently, a collector electrode 9 made of a predetermined metal laminated film is formed on the subcollector layer 101 by a lift-off method.
　なお、エミッタ電極６、第１のベース電極７、第２のベース電極８及びコレクタ電極９における形成の順序は特に問われない。 The order of formation of the emitter electrode 6, the first base electrode 7, the second base electrode 8, and the collector electrode 9 is not particularly limited.
　続いて、オーミックコンタクト及び注入イオンの活性化のための熱処理を行うことにより、図１Ａ及び図１Ｂに示すＨＢＴ１００を得ることができる。 Subsequently, by performing a heat treatment for activating ohmic contacts and implanted ions, the HBT 100 shown in FIGS. 1A and 1B can be obtained.
　なお、本実施形態においては、ヘリウムイオンの注入条件を、加速電圧が１００ｋｅＶ程度で、ドーズ量が７．２×１０１３ｃｍ－２程度としている。しかし、これらの注入条件を適宜変更することにより、高抵抗ベース領域１５０に所望の抵抗値を与えることができる。 In this embodiment, the helium ion implantation conditions are an acceleration voltage of about 100 keV and a dose amount of about 7.2 × 10 13 cm −2 . However, a desired resistance value can be given to the high resistance base region 150 by appropriately changing these implantation conditions.
　また、高抵抗ベース領域１５０に設定する抵抗値によっては、高抵抗ベース領域１５０の形成に用いるヘリウムイオンのイオン注入と、素子分離領域の形成に用いるヘリウムイオンのイオン注入とを同時に行うことができる。これにより、ヘリウムイオンの注入工程を削減することができる。 Further, depending on the resistance value set in the high resistance base region 150, helium ion ion implantation used for forming the high resistance base region 150 and helium ion ion implantation used for forming the element isolation region can be performed simultaneously. . Thereby, the process of implanting helium ions can be reduced.
　また、本実施形態においては、高抵抗ベース領域１５０の形成にヘリウムイオンを用いたが、イオン注入に供されるイオン種はヘリウムイオンに限られず、例えばボロンイオン（Ｂ＋）等でも同様の効果を得られることはいうまでもない。さらには、ヘリウムイオン及びボロンイオン以外にも、水素イオン（Ｈ＋）を用いることができる。 In this embodiment, helium ions are used to form the high resistance base region 150. However, the ion species used for ion implantation is not limited to helium ions. For example, boron ions (B +) have the same effect. It goes without saying that it can be obtained. Furthermore, hydrogen ions (H +) can be used in addition to helium ions and boron ions.
　また、本実施形態においては、ヘテロ接合バイポーラトランジスタ（ＨＢＴ）について説明したが、本発明は、ＨＢＴに限られず、例えば、ホモ接合のバイポーラトランジスタ（ＢＴ）でもよい。 In this embodiment, the heterojunction bipolar transistor (HBT) has been described. However, the present invention is not limited to the HBT, and may be a homojunction bipolar transistor (BT), for example.
　また、本発明の要旨を逸脱しない範囲で当業者が思いつく各種変形を施したものも本発明の範囲内に含まれる。 In addition, the present invention includes various modifications made by those skilled in the art without departing from the scope of the present invention.
　本発明に係る半導体装置及びその製造方法は、チップサイズ及びセルサイズを大きくすることなく所望の抵抗値を持つバラスト抵抗を備えた半導体装置を実現できる。特にヘテロ接合バイポーラトランジスタを有する半導体装置、例えば電力増幅器等に有用である。 The semiconductor device and the manufacturing method thereof according to the present invention can realize a semiconductor device having a ballast resistor having a desired resistance value without increasing the chip size and the cell size. In particular, it is useful for a semiconductor device having a heterojunction bipolar transistor, such as a power amplifier.
１　　エミッタ端子
２　　ＤＣ端子
３　　ＲＦ端子
４　　コレクタ端子
６，１８　　エミッタ電極
７，１６　　第１のベース電極
８，１７　　第２のベース電極
９，１５　　コレクタ電極
１３ａ　　内部抵抗成分
１００　　ヘテロ接合バイポーラトランジスタ（ＨＢＴ）
１１，１０１　　サブコレクタ層
１０１Ａ　　ｎ型ＧａＡｓ層
１２，１０２　　コレクタ層
１０２Ａ　　ｎ型ＧａＡｓ層
１３，１０３　　ベース層
１０３Ａ　　ｐ型ＧａＡｓ層
１４，１０４　　エミッタ層
１０４Ａ　　積層構造体
１５０　　高抵抗ベース領域（高抵抗領域）
２０１　　第１のレジストマスク
２０２　　第２のレジストマスク
２０３　　第３のレジストマスク
２０３ａ　　開口パターン DESCRIPTION OF SYMBOLS 1 Emitter terminal 2 DC terminal 3 RF terminal 4 Collector terminal 6,18 Emitter electrode 7,16 1st base electrode 8,17 2nd base electrode 9,15 Collector electrode 13a Internal resistance component 100 Heterojunction bipolar transistor (HBT)
11, 101 Subcollector layer 101A n- type GaAs layer 12, 102 collector layer 102A n- type GaAs layer 13, 103 base layer 103A p- type GaAs layer 14, 104 emitter layer 104A laminated structure 150 high resistance base region (high resistance region)
201 First resist mask 202 Second resist mask 203 Third resist mask 203a Opening pattern

Claims (8)

  1. 　第１導電型の半導体からなるコレクタ層と、
    　前記コレクタ層の上に形成された第２導電型の半導体からなるベース層と、
    　前記ベース層の上に前記ベース層を露出するように選択的に形成された第１導電型の半導体からなるエミッタ層と、
    　前記ベース層の上に形成され、直流バイアス電圧が印加される第１のベース電極と、
    　前記ベース層の上に形成され、高周波信号が入力される第２のベース電極とを備え、
    　前記ベース層は、前記第１のベース電極の下側部分に前記第１のベース電極の周辺領域を含むと共に前記エミッタ層の下側部分に達しないように形成され、他の領域と比べて抵抗値が高い高抵抗領域を有している半導体装置。     A collector layer made of a semiconductor of the first conductivity type;
    A base layer made of a second conductivity type semiconductor formed on the collector layer;
    An emitter layer made of a first conductivity type semiconductor selectively formed on the base layer to expose the base layer;
    A first base electrode formed on the base layer and applied with a DC bias voltage;
    A second base electrode formed on the base layer and receiving a high-frequency signal;
    The base layer includes a peripheral region of the first base electrode in a lower portion of the first base electrode and is formed so as not to reach a lower portion of the emitter layer, and has a resistance higher than that of other regions. A semiconductor device having a high resistance region having a high value.
  2. 　前記エミッタ層は、前記ベース層と接する部分に、前記ベース層と比べてバンドギャップが大きい半導体層を含む請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the emitter layer includes a semiconductor layer having a band gap larger than that of the base layer at a portion in contact with the base layer.
  3. 　前記高抵抗領域は、イオンが注入されることにより形成されている請求項１又は２に記載の半導体装置。 3. The semiconductor device according to claim 1, wherein the high resistance region is formed by ion implantation.
  4. 　前記イオンは、ヘリウムイオン又はボロンイオンである請求項３に記載の半導体装置。 4. The semiconductor device according to claim 3, wherein the ions are helium ions or boron ions.
  5. 　基板の上に、第１導電型の半導体からなるコレクタ層を形成する工程と、
    　前記コレクタ層の上に第２導電型の半導体からなるベース層を形成する工程と、
    　前記ベース層の上に第１導電型の半導体からなるエミッタ層を形成する工程と、
    　前記エミッタ層に対して選択的にエッチングを行うことにより、前記エミッタ層を島状に形成する工程と、
    　前記ベース層及びコレクタ層に対して、前記島状のエミッタ層を含むように選択的にエッチングを行うことにより、前記ベース層及びコレクタ層を島状に形成する工程と、
    　前記ベース層における前記島状のエミッタ層の側方領域に対して、前記エミッタ層から間隔をおいてイオンを注入することにより、前記ベース層に高抵抗領域を形成する工程と、
    　前記高抵抗領域の上に、直流バイアス電圧が印加されるベース電極を形成する工程とを備えている半導体装置の製造方法。     Forming a collector layer made of a first conductivity type semiconductor on a substrate;
    Forming a base layer made of a second conductivity type semiconductor on the collector layer;
    Forming an emitter layer made of a first conductivity type semiconductor on the base layer;
    Forming the emitter layer in an island shape by selectively etching the emitter layer;
    Forming the base layer and the collector layer in an island shape by selectively etching the base layer and the collector layer so as to include the island-shaped emitter layer;
    Forming a high resistance region in the base layer by implanting ions spaced from the emitter layer into a lateral region of the island-shaped emitter layer in the base layer;
    Forming a base electrode to which a DC bias voltage is applied on the high resistance region.
  6. 　前記エミッタ層を形成する工程において、前記エミッタ層における前記ベース層と接する部分に、前記ベース層と比べてバンドギャップが大きい半導体層を形成する請求項５に記載の半導体装置の製造方法。 6. The method of manufacturing a semiconductor device according to claim 5, wherein in the step of forming the emitter layer, a semiconductor layer having a band gap larger than that of the base layer is formed in a portion of the emitter layer in contact with the base layer.
  7. 　前記高抵抗領域を形成する工程において、前記イオンは、ヘリウムイオン又はボロンイオンである請求項５又は６に記載の半導体装置の製造方法。 7. The method of manufacturing a semiconductor device according to claim 5, wherein in the step of forming the high resistance region, the ions are helium ions or boron ions.
  8. 　前記高抵抗領域を形成する工程は、前記イオンを用いたイオン注入による素子分離領域の形成と同時に行う請求項５～７のいずれかに記載の半導体装置の製造方法。 8. The method of manufacturing a semiconductor device according to claim 5, wherein the step of forming the high resistance region is performed simultaneously with the formation of an element isolation region by ion implantation using the ions.
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TWI754492B (en) * 2020-02-19 2022-02-01 日商村田製作所股份有限公司 Radio-frequency power-amplifying element
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