WO2012096070A1 - 炭化珪素半導体装置の製造方法 - Google Patents
炭化珪素半導体装置の製造方法 Download PDFInfo
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- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 91
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 68
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- 229910052710 silicon Chemical group 0.000 claims abstract description 7
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 7
- 238000000137 annealing Methods 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 238000004544 sputter deposition Methods 0.000 claims description 6
- 239000011229 interlayer Substances 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
- H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/048—Making electrodes
- H01L21/0485—Ohmic electrodes
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66893—Unipolar field-effect transistors with a PN junction gate, i.e. JFET
- H01L29/66901—Unipolar field-effect transistors with a PN junction gate, i.e. JFET with a PN homojunction gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
Definitions
- the present invention relates to a method of manufacturing a silicon carbide semiconductor device, and more particularly to a method of manufacturing a silicon carbide semiconductor device having a contact electrode containing Al atoms.
- Patent Document 1 titanium (Ti) and aluminum (Al) are contained as a material of the ohmic contact electrode disposed in contact with the SiC wafer (silicon carbide substrate) Is disclosed. According to this publication, it is supposed that the contact resistance can be reduced to the SiC wafer by the application of the above-mentioned material.
- an object of the present invention is to provide a method of manufacturing a silicon carbide semiconductor device capable of improving the insulation reliability of an insulating film when a contact electrode having Al atoms is used.
- the method for manufacturing a silicon carbide semiconductor device of the present invention has the following steps.
- a silicon carbide substrate having a substrate surface is prepared.
- An insulating film is formed to cover a part of the substrate surface.
- a contact electrode is formed on the substrate surface to be in contact with the insulating film.
- the contact electrode contains Al, Ti and Si atoms.
- the contact electrode includes an alloy film made of an alloy containing at least one of Si atoms and Ti atoms and Al atoms.
- the contact electrode is annealed such that the silicon carbide substrate and the contact electrode are ohmically connected.
- the Al atoms contained in the contact electrode are present not as elements but as an alloy with at least one of Si atoms and Ti atoms. This suppresses the diffusion of Al atoms to the outside of the contact electrode during annealing. Thus, the diffusion of Al atoms into the insulating film is suppressed, so that the insulation reliability of the insulating film can be enhanced.
- the alloy film is formed by sputtering using a target made of an alloy. This can prevent the formation of a region where the Al element is present without being alloyed.
- the alloy film contains Si atoms. More preferably, the alloy film contains Ti atoms. This more reliably suppresses the diffusion of Al atoms to the outside of the contact electrode during annealing.
- the insulating film includes at least one of a silicon oxide film and a silicon nitride film.
- the silicon oxide film is, for example, a SiO 2 film.
- the silicon nitride film is, for example, a SiN film.
- the manufacturing method may further include the step of forming a gate electrode on the insulating film.
- the insulating film is used as a gate insulating film, current leakage between the gate electrode and the silicon carbide substrate can be suppressed.
- the insulating film may be an interlayer insulating film. In this case, the occurrence of current leak in the interlayer insulating film can be suppressed.
- the insulation reliability of the insulating film can be improved.
- FIG. 7 is a schematic cross-sectional view showing a first step of a method of manufacturing the MOSFET of FIG. 1; It is a schematic sectional drawing which shows the 2nd process of the manufacturing method of MOSFET of FIG. It is a schematic sectional drawing which shows the 3rd process of the manufacturing method of MOSFET of FIG. It is a schematic sectional drawing which shows the 4th process of the manufacturing method of MOSFET of FIG.
- FIG. 11 is a schematic cross-sectional view showing a first step of a method of manufacturing the JFET of FIG. 10;
- FIG. 11 is a schematic cross-sectional view showing a second step of the method of manufacturing the JFET of FIG. 10.
- FIG. 11 is a schematic cross-sectional view showing a third step of the method of manufacturing the JFET of FIG. 10.
- FIG. 11 is a schematic cross-sectional view showing a fourth step of the method of manufacturing the JFET of FIG. 10.
- FIG. 11 is a schematic cross-sectional view showing a fifth step of the method of manufacturing the JFET of FIG. 10.
- FIG. 11 is a schematic cross-sectional view showing a sixth step of the method of manufacturing the JFET in FIG. 10.
- It is a flowchart which shows the ohmic electrode formation process in the manufacturing method of MOSFET in Embodiment 3 of this invention.
- FIG. 17 is a schematic cross-sectional view showing a first step of a method of manufacturing the MOSFET in the third embodiment of the present invention.
- FIG. 17 is a schematic cross-sectional view showing a second step of the method of manufacturing the MOSFET in the third embodiment of the present invention.
- FIG. 21 is a schematic cross-sectional view showing a third step of the method of manufacturing the MOSFET in the third embodiment of the present invention.
- FIG. 21 is a schematic cross-sectional view showing a first step of a method of manufacturing JFET in the fourth embodiment of the present invention.
- FIG. 21 is a schematic cross-sectional view showing a second step of the method of manufacturing JFET in the fourth embodiment of the present invention.
- Embodiment 1 First, the configuration of a MOSFET (oxide film field effect transistor) in the present embodiment will be described.
- MOSFET oxide film field effect transistor
- MOSFET 1 silicon carbide semiconductor device
- Silicon carbide substrate 10 has an n + substrate 11, an n ⁇ SiC layer 12, a p body 13, an n + source region 14 and a p + region 18.
- the n + substrate 11 is a substrate made of silicon carbide (SiC) and having n conductivity type.
- the n + substrate 11 contains a high concentration n-type impurity (an impurity whose conductivity type is n-type), for example, N (nitrogen).
- the n ⁇ SiC layer 12 is a semiconductor layer made of SiC and having a conductivity type of n type.
- the n ⁇ SiC layer 12 is formed on one main surface 11 A of the n + substrate 11 with a thickness of, for example, about 10 ⁇ m.
- the n-type impurity contained in n - SiC layer 12 is, for example, N (nitrogen), and is contained at a lower concentration than the n-type impurity contained in n + substrate 11, for example, at a concentration of 5 ⁇ 10 15 cm -3. There is.
- the pair of p bodies 13 have p type conductivity.
- the pair of p bodies 13 has a second main surface 12B (substrate surface) which is a main surface opposite to the first main surface 12A which is the main surface on the n + substrate 11 side in the n ⁇ SiC layer 12 It is formed separately from each other to be included.
- the p-type impurity contained in p body 13 is, for example, Al (aluminum), B (boron) or the like, and has a concentration lower than that of the n-type impurity contained in n + substrate 11, eg, 1 ⁇ 10 17 cm ⁇ 3 . Is included.
- the n + source region 14 has n type conductivity.
- the n + source region 14 is formed in each of the pair of p bodies 13 so as to include the second major surface 12 B and be surrounded by the p bodies 13.
- the n + source region 14 contains an n-type impurity such as P (phosphorus) at a concentration higher than that of the n-type impurity contained in the n ⁇ SiC layer 12, for example, 1 ⁇ 10 20 cm ⁇ 3 .
- the p + region 18 has p type conductivity.
- the p + region 18 contains a p-type impurity such as Al or B at a concentration higher than that of the p-type impurity contained in the p body 13, for example, 1 ⁇ 10 20 cm ⁇ 3 .
- the MOSFET 1 further includes a gate oxide film 15 (insulating film) as a gate insulating film, a gate electrode 17, a pair of source contact electrodes 16, a source wiring 19, a drain electrode 20, and a passivation film 21. .
- a gate oxide film 15 is in contact with second main surface 12B, n so as to extend from the upper surface of one n + source region 14 to the top surface of the other n + source regions 14 - SiC layer 12 It is formed on the second major surface 12B.
- Gate oxide film 15 preferably includes at least one of a silicon oxide film and a silicon nitride film, and is made of, for example, silicon dioxide (SiO 2 ).
- Gate electrode 17 is disposed in contact with gate oxide film 15 so as to extend from above one n + source region 14 to above the other n + source region 14.
- the gate electrode 17 is made of a conductor such as polysilicon or Al.
- Source contact electrode 16 extends from on each of the pair of n + source regions 14 to p + region 18 in a direction away from gate oxide film 15 and is disposed in contact with second major surface 12 B ing.
- the source contact electrode 16 contains titanium (Ti) atoms, aluminum (Al) atoms, silicon (Si) atoms and carbon (C) atoms, with the balance being unavoidable impurities.
- the unavoidable impurities include oxygen (O) atoms which are inevitably mixed in the manufacturing process.
- the source contact electrode 16 contains aluminum atoms and titanium atoms in a region including the interface with the n ⁇ SiC layer 12 in which the source region 14 and the p + region 18 are formed.
- Source interconnection 19 is formed in contact with source contact electrode 16 and made of a conductor such as Al. Source interconnection 19 is electrically connected to n + source region 14 via source contact electrode 16. Source interconnection 19 and source contact electrode 16 constitute source electrode 22.
- Drain electrode 20 is formed in contact with the other main surface 11B which is the main surface on the opposite side to one main surface 11A which is the main surface on the side where n - SiC layer 12 is formed in n + substrate 11 ing.
- the drain electrode 20 may have, for example, the same configuration as that of the source contact electrode 16 described above, or may be made of another material such as Ni, which can be in ohmic contact with the n + substrate 11. Thus, the drain electrode 20 is electrically connected to the n + substrate 11.
- the passivation film 21 is formed to extend from above the one source wiring 19 to above the gate electrode 17 and onto the other source wiring 19.
- Passivation film 21 is made of, for example, SiO 2 and has functions of electrically insulating source interconnection 19 and gate electrode 17 from the outside and protecting MOSFET 1.
- Ni is often employed as a material of the electrode in contact with the n-type SiC region.
- a vertical MOSFET of DMOS (Double-diffused MOSFET) type using SiC as a material a structure in which an electrode made of Ni is in contact with both a p-type SiC region and an n-type SiC region is adopted.
- DMOS type vertical MOSFET requires an electrode in contact with both the p-type region and the n-type region, and an electrode made of Ni is about 10 ⁇ 2 ⁇ ⁇ cm 2 in both the p-type SiC region It is because contact is possible with the contact resistivity of.
- the contact resistivity of 10 -2 ⁇ ⁇ cm 2 is a value that can be used as an ohmic contact electrode
- the contact made of Ti / Al is in contact with the p-type SiC region and about 10 -3 ⁇ ⁇ cm 2 It is not sufficiently low considering that it can be contacted by resistivity.
- the contact resistance with the p-type SiC region is sufficiently suppressed, but the contact resistivity with the n-type SiC region is about 10 ⁇ 3 ⁇ ⁇ cm 2 .
- the contact resistivity of 10 -3 ⁇ ⁇ cm 2 is also a value that can be used as an ohmic contact electrode, the electrode made of Ni contacts the n-type SiC region at a contact resistivity of about 10 -6 ⁇ ⁇ cm 2.
- the contact resistance between the electrode made of Ti / Al and the n-type SiC region is not sufficiently low.
- source contact electrode 16 is an ohmic contact electrode containing Ti atoms, Al atoms, and Si atoms, so that the contact resistance is sufficiently sufficient for both p-type SiC region and n-type SiC region. Low.
- the source contact electrode 16 is arranged to extend from the region in contact with the n + source region 14 to the region in contact with the p + region 18.
- the MOSFET 1 is a semiconductor device capable of reducing the number of manufacturing processes and improving the degree of integration.
- n + source region 14 and p body 13 need to be held at the same potential. Therefore, source contact electrode 16 is required to be electrically connected to both n + source region 14 and p body 13 while reducing the contact resistance. Furthermore, in the MOSFET 1, in order to reduce the on resistance, it is necessary to electrically connect the n + source region 14 and the source contact electrode 16 while suppressing the contact resistance. In order to achieve the reduction of the number of steps of the manufacturing process and the improvement of the degree of integration while meeting these requirements, the contact resistance is reduced and the region contacting the n + source region 14 to the region contacting the p body 13 The source contact electrode 16 extending to the top is required.
- Source contact electrode 16 is in contact with both n + source region 14 and p + region 18 (p body 13) with low contact resistance by having the above configuration.
- the MOSFET 1 is a semiconductor device capable of reducing the number of manufacturing steps and improving the degree of integration while achieving high efficiency.
- silicon carbide substrate 10 is prepared by substrate preparation step S10 (FIG. 2).
- the first epitaxial growth on n + SiC substrate 11, n on one main surface 11A of n + SiC substrate 11 - SiC layer 12 is formed.
- the epitaxial growth can be performed, for example, using a mixed gas of SiH 4 (silane) and C 3 H 8 (propane) as a source gas.
- SiH 4 silane
- C 3 H 8 propane
- N is introduced as an n-type impurity.
- n including n-type impurity of lower concentration than the n-type impurity contained in n + SiC substrate 11 - it is possible to form a SiC layer 12.
- an oxide film made of SiO 2 is formed on second main surface 12B, for example, by CVD (Chemical Vapor Deposition; chemical vapor deposition). Then, after a resist is applied on the oxide film, exposure and development are performed, and a resist film having an opening in a region corresponding to the desired shape of the p body 13 is formed. Then, using the resist film as a mask, the oxide film is partially removed by, for example, RIE (Reactive Ion Etching; reactive ion etching), whereby an oxide film having an opening pattern on n ⁇ SiC layer 12 is obtained. Mask layer is formed.
- RIE reactive Ion Etching
- reactive ion etching reactive ion etching
- the p-type impurity such as Al n - by implanting ions into the SiC layer 12, n - p body 13 in the SiC layer 12 is formed Be done.
- a mask layer having an opening in a region corresponding to the shape of the desired n + source region 14 is formed.
- an n + source region 14 is formed by introducing an n type impurity such as P into the n ⁇ SiC layer 12 by ion implantation.
- a mask layer having an opening in a region corresponding to the shape of the desired p + region 18 is formed, and using this as a mask, p-type impurities such as Al and B are ion-implanted into n ⁇ SiC layer 12 By being introduced, p + region 18 is formed.
- n - SiC layer 12 subjected to ion implantation is heated, for example, to about 1700 ° C. in an Ar (argon) atmosphere, and held for about 30 minutes.
- Ar argon
- silicon carbide substrate 10 (FIG. 5) having second main surface 12B is prepared.
- gate oxide film 15 (insulating film) is formed in gate insulating film forming step S70 (FIG. 2). Specifically, first, the above process is performed to thermally oxidize the n + substrate 11 on which the n ⁇ SiC layer 12 including the desired ion implantation region is formed. Thermal oxidation can be performed, for example, by heating to about 1300 ° C. in an oxygen atmosphere and holding for about 40 minutes. Thereby, a thermal oxide film 15A (about 50 nm thick, for example) made of silicon dioxide (SiO 2 ) is formed on the second major surface 12B.
- the thermal oxide film 15A After the resist is applied on the thermal oxide film 15A, exposure and development are performed to form a resist film 91 having an opening 91A corresponding to the area where the source contact electrode 16 (see FIG. 1) is to be formed. Then, using the resist film 91 as a mask, the thermal oxide film 15A is partially removed by RIE, for example. Thereby, the gate oxide film 15 which covers a part of 2nd main surface 12B is formed.
- ohmic electrode formation step S80 (FIG. 2) is performed. Specifically, an alloy film 50 made of an alloy containing Si atoms, Ti atoms, and Al atoms is formed by the alloy film forming step S81 (FIG. 3). That is, the alloy film 50 is formed on the second major surface 12 B and on the major surface of the n + substrate 11 opposite to the n ⁇ SiC layer 12.
- the formation of the alloy film is preferably performed by sputtering using a sputtering target 90.
- the sputtering target 90 is made of an alloy containing Al atoms, Si atoms, and Ti atoms.
- Source contacts extending from on each of the pair of n + source regions 14 to over p + regions 18 in a direction away from gate oxide film 15 and in contact with second main surface 12 B
- the electrode 16 and the n + substrate 11 are disposed in contact with the other main surface 11B which is the main surface opposite to the one main surface 11A which is the main surface on which the n ⁇ SiC layer 12 is formed
- the drain electrode 20 is formed.
- Source contact electrode 16 is formed on second major surface 12 B to be in contact with gate oxide film 15.
- the electrical connection between the alloy film 50 and the silicon carbide substrate 10 is made ohmic by annealing. Specifically, it is heated to a temperature of 550 ° C. to 1200 ° C., preferably 900 ° C. to 1100 ° C., for example 1000 ° C. in an inert gas atmosphere such as Ar, for a time of 10 minutes or less, eg 2 An anneal that is held for a minute is performed. Thereby, Ti atoms, Al atoms, Si atoms contained in the alloy film 50, and Si atoms and C atoms contained in the silicon carbide substrate 10 are alloyed.
- n + substrate 11 be heated in a mixed gas of an inert gas, particularly Ar or / and N 2 , and hydrogen.
- source contact electrode 16 can be manufactured with the contact resistance to n + source region 14 and p body 13 (p + region 18) reduced more reliably while suppressing the manufacturing cost.
- gate electrode 17 is formed by gate electrode formation step S100 (FIG. 2).
- a gate electrode 17 made of Al is, as well as extending over one n + source region 14 to above the other n + source regions 14, the gate oxide film 15 Formed to be in contact.
- the polysilicon can be contained at a high concentration of P exceeding 1 ⁇ 10 20 cm ⁇ 3 .
- source wiring 19 is formed by source wiring formation step S110 (FIG. 2).
- source interconnection 19 made of Al, which is a conductor, is formed on the upper surface of source contact electrode 16 by, for example, vapor deposition.
- the source electrode 22 is completed.
- the passivation film 21 is formed by the passivation film forming step S120.
- passivation film 21 made of, for example, SiO 2 is formed to extend from above one source line 19 to above gate electrode 17 and onto the other source line 19.
- Passivation film 21 can be formed, for example, by the CVD method.
- the MOSFET 1 is completed.
- the Al atoms contained in the source contact electrode 16 exist not as an element but as an alloy with Si atoms and Ti atoms before the source contact electrode 16 is annealed. This suppresses the diffusion of Al atoms to the outside of source contact electrode 16 during annealing. Thus, the diffusion of Al atoms into the gate oxide film 15 is suppressed, and the reliability of the gate oxide film 15 can be enhanced.
- the alloy film 50 is formed by sputtering using a sputtering target 90 made of an alloy. Thereby, it is possible to suppress the formation of a region in which Al element is present without being alloyed in the formed film.
- an insulating film made of another material may be formed instead of thermal oxide film 15A.
- a silicon nitride film may be formed.
- JFET 3 silicon carbide semiconductor device
- JFET 3 has the same configuration as that of MOSFET 1 in the first embodiment in the configuration of the ohmic contact electrode, and exhibits the same effect.
- JFET 3 has silicon carbide substrate 30.
- Silicon carbide substrate 30 has an n-type substrate 31, a first p-type layer 32, an n-type layer 33, and a second p-type layer 34.
- the n-type substrate 31 is made of SiC and has n-type conductivity.
- the first p-type layer 32 is formed on the n-type substrate 31.
- the n-type layer 33 is formed on the first p-type layer 32.
- the p-type layer 34 is formed on the n-type layer 33.
- the first p-type layer 32 has, for example, a thickness of about 10 ⁇ m, the concentration of p-type impurities is about 7.5 ⁇ 10 15 cm ⁇ 3 , the n-type layer 33 has, for example, a thickness of about 0.45 ⁇ m, and the concentration of n-type impurities 2 ⁇ 10 17 cm -3 or so, the second p-type layer 34 may be, for example, thickness 0.25 ⁇ m approximately, the concentration of approximately 2 ⁇ 10 17 cm -3 of p-type impurity.
- Second p-type layer 34 and n-type layer 33 contain an impurity (n-type impurity) whose conductivity type is higher than n-type layer 33 (for example, about 1 ⁇ 10 20 cm ⁇ 3 )
- the first p-type layer 32 and the first p-type layer 32 are formed so as to be sandwiched between the first n-type region 35 and the second n-type region 37 while the first n-type region 35 and the second n-type region 37 are formed.
- a first p-type region 36 is formed (for example, about 1 ⁇ 10 18 cm ⁇ 3 ) containing an impurity (p-type impurity) whose conductivity type is higher than that of the second p-type layer 34 (p type). .
- the first n-type region 35, the first p-type region 36, and the second n-type region 37 are formed to penetrate the second p-type layer 34 and reach the n-type layer 33, respectively.
- the bottoms of the first n-type region 35, the first p-type region 36 and the second n-type region 37 are the upper surface of the first p-type layer 32 (the first p-type layer 32 and the n-type It is spaced apart from the boundary with the layer 33).
- the upper surface 34A of the second p-type layer 34 (a main surface on the opposite side to the n-type layer 33 side)
- a groove 71 is formed so as to penetrate the second p-type layer 34 from the surface) to the n-type layer 33.
- the bottom surface 71A of the groove 71 is located inside the n-type layer 33 at a distance from the interface between the first p-type layer 32 and the n-type layer 33.
- a second p-type region 43 containing impurities (for example, about 1 ⁇ 10 18 cm ⁇ 3 ) is formed. The bottom of the second p-type region 43 is spaced from the top surface of the n-type substrate 31 (the boundary between the n-type substrate 31 and the first p-type layer 32).
- a source contact electrode as an ohmic contact electrode is brought into contact with the upper surfaces of first n-type region 35, first p-type region 36, second n-type region 37 and second p-type region 43.
- 39, a gate contact electrode 41, a drain contact electrode 42, and a potential holding contact electrode 44 are formed.
- the source contact electrode 39, the gate contact electrode 41, the drain contact electrode 42, and the potential holding contact electrode 44 have features similar to those of the source contact electrode 16 in the first embodiment.
- oxide film 38 (insulating film as an interlayer insulating film ) Is formed. More specifically, oxide film 38 as an interlayer insulating film is formed on source contact electrode 39, gate contact electrode 41, and drain contact on upper surface 34A of second p-type layer 34 and bottom surface 71A and sidewall 71B of groove 71. It is formed to cover the entire area other than the area where the electrode 42 and the potential holding contact electrode 44 are formed. Thereby, the adjacent ohmic contact electrodes are insulated.
- source interconnection 45, gate interconnection 46 and drain interconnection 47 are respectively formed to be in contact with the upper surfaces of source contact electrode 39, gate contact electrode 41 and drain contact electrode 42, and are electrically connected to each ohmic contact electrode It is done.
- Source interconnection 45 is also in contact with the upper surface of potential holding contact electrode 44 and is also electrically connected to potential holding contact electrode 44. That is, source interconnection 45 is formed to extend from the upper surface of source contact electrode 39 to the upper surface of potential holding contact electrode 44, whereby potential holding contact electrode 44 is a source contact electrode. It is held at the same potential as 39.
- Source interconnection 45, gate interconnection 46 and drain interconnection 47 are made of a conductor such as Al.
- Source contact electrode 39 and source interconnection 45 constitute source electrode 61
- gate contact electrode 41 and gate interconnection 46 constitute gate electrode 62
- drain contact electrode 42 and drain interconnection 47 constitute drain electrode 63.
- a passivation film 64 is formed to cover the upper surfaces of the source electrode 61, the gate electrode 62, the drain electrode 63, and the oxide film 38.
- the passivation film 64 is made of, for example, SiO 2 and has functions of electrically insulating the source electrode 61, the gate electrode 62 and the drain electrode 63 from the outside and protecting the JFET 3.
- JFET 3 is arranged in contact with silicon carbide substrate 30 and silicon carbide substrate 30, contains Ti, Al, Si and C, and source contact electrode 39 as an ohmic contact electrode composed of the remaining unavoidable impurities, and gate contact An electrode 41, a drain contact electrode 42, and a potential holding contact electrode 44 are provided.
- Silicon carbide substrate 30 includes first n-type region 35 and second n-type region 37 having n-type conductivity, and first p-type region 36 and second p-type having p-type conductivity. And a region 43.
- source contact electrode 39 and drain contact electrode 42 are in contact with first n-type region 35 and second n-type region 37, respectively, and gate contact electrode 41 and potential holding contact
- the electrode 44 is in contact with the first p-type region 36 and the second p-type region 43, respectively.
- the source contact electrode 39, the gate contact electrode 41, the drain contact electrode 42, and the potential holding contact electrode 44 have features similar to those of the source contact electrode 16 in the first embodiment.
- source contact electrode 39 and drain contact electrode 42 having features similar to those of source contact electrode 16 in the first embodiment are a first n-type region 35 and a second n-type region as n-type regions, respectively. 37 and made of the same material as the source contact electrode 39 and the drain contact electrode 42 is in contact with the first p-type region 36 and the second p-type region 43 as p-type regions. It is arranged.
- the JFET 3 is a semiconductor device capable of reducing the number of steps in the manufacturing process and improving the degree of integration.
- the material forming the source contact electrode 39 and the drain contact electrode 42 disposed in contact with the first n-type region 35 and the second n-type region 37 is Ni, and the first p-type region 36 is in contact
- Ti / Al is used as the material of the gate contact electrode 41 to be disposed
- the following problems occur. That is, under this assumption, after forming a mask for forming the source contact electrode 39 and the drain contact electrode 42, these electrodes are formed by vapor deposition or the like. Thereafter, after the mask is removed, it is necessary to form a mask for forming the gate contact electrode 41 and to form the electrode by vapor deposition or the like.
- source contact electrode 39, gate contact electrode 41 and drain contact electrode 42 can be formed of the same material, so these electrodes are collectively formed by one mask formation. Can be formed. As a result, according to the JFET 3 in the present embodiment, it is possible to reduce the number of manufacturing steps and improve the degree of integration.
- n-type layer 33 in a state where the voltage of gate electrode 62 is 0 V, in n-type layer 33, a region sandwiched by first p-type region 36 and second n-type region 37 and the region A region (drift region) sandwiched between the region and the first p-type layer 32, and a region (channel region) sandwiched between the first p-type region 36 and the first p-type layer 32 are depleted.
- the first n-type region 35 and the second n-type region 37 are electrically connected to each other through the n-type layer 33. Therefore, a current flows by moving electrons from the first n-type region 35 toward the second n-type region 37.
- first n-type region 35 and second n-type region 37 are electrically connected. It is blocked by the Therefore, electrons can not move from the first n-type region 35 toward the second n-type region 37, and no current flows.
- silicon carbide substrate 30 is prepared by substrate preparation step S210 (FIG. 11).
- a first p-type layer 32, an n-type layer 33 and a second p-type layer 34 made of SiC are sequentially It is formed.
- a vapor phase epitaxial growth method is used for this formation.
- silane (SiH 4 ) gas and propane (C 3 H 8 ) gas can be used as a material gas
- hydrogen (H 2 ) gas can be employed as a carrier gas.
- a p-type impurity source for forming a p-type layer for example, diborane (B 2 H 6 ) or trimethylaluminum (TMA), and for an n-type impurity for forming an n-type layer, for example N 2
- B 2 H 6 diborane
- TMA trimethylaluminum
- N 2 n-type impurity for forming an n-type layer
- the first p-type layer 32 and the second p-type layer 34 containing p-type impurities such as Al and B, and the n-type layer 33 containing n-type impurities such as N are formed.
- a groove 71 is formed so as to penetrate the second p-type layer 34 from the upper surface 34A of the second p-type layer 34 to reach the n-type layer 33.
- the groove portion 71 has a bottom surface 71A and a side wall 71B.
- the formation of groove 71 is performed by dry etching using SF 6 gas, for example, after forming a mask layer having an opening at the desired formation position of groove 71 on upper surface 34 A of second p-type layer 34. Can.
- ion implantation is performed. Specifically, first, on the upper surface 34A of the second p-type layer 34 and the bottom of the groove 71, an oxide film made of SiO 2 is formed by CVD, for example. Then, after a resist is applied on the oxide film, exposure and development are performed, and a resist film having an opening in a region corresponding to the shape of the desired first n-type region 35 and second n-type region 37 Is formed. Then, using the resist film as a mask, the oxide film is partially removed by RIE, for example, to form a mask layer made of an oxide film having an opening pattern on the upper surface 34A of the second p-type layer 34. It is formed.
- the resist film is removed, and ion implantation is performed on the n-type layer 33 and the second p-type layer 34 using the mask layer as a mask.
- the ion species to be implanted can be, for example, P, N or the like. As a result, a first n-type region 35 and a second n-type region 37 which penetrate the second p-type layer 34 and reach the n-type layer 33 are formed.
- the upper surface 34A of the second p-type layer 34 and the groove are similarly processed.
- a mask layer having an opening in a region corresponding to the shape of the desired first p-type region 36 and second p-type region 43 is formed.
- ion implantation is performed on the first p-type layer 32, the n-type layer 33 and the second p-type layer 34 using the mask layer as a mask.
- the ion species to be implanted can be, for example, Al, B or the like.
- the second p-type region 43 is formed.
- the n-type substrate 31 having the first p-type layer 32, the n-type layer 33, and the second p-type layer 34 completed with the above ion implantation is, for example, 1700 in an inert gas atmosphere such as argon. Heat to ° C and hold for 30 minutes.
- the impurity is activated and can function as an n-type impurity or a p-type impurity.
- silicon carbide substrate 30 (FIG. 14) having substrate surface 80 having upper surface 34A, bottom surface 71A and side wall 71B is prepared.
- oxide film 38 is formed by an oxide film forming step S260 (FIG. 11).
- thermal oxidation treatment is first performed, for example, by heating to about 1300 ° C. in an oxygen atmosphere and holding for about 90 minutes, whereby the upper surface 34 A of the second p-type layer 34 and the groove 71 are formed.
- An oxide film 38 (field oxide film) is formed as an insulating film covering the bottom surface 71A and the side wall 71B.
- the thickness of oxide film 38 is, for example, about 0.1 ⁇ m.
- oxide film 38 After a resist is applied on oxide film 38, exposure and development are performed to form source contact electrode 39, gate contact electrode 41, drain contact electrode 42 and potential holding contact electrode 44 (see FIG. 10). A resist film 91 having an opening 91A corresponding to the region is formed. Then, oxide film 38 is partially removed, for example, by RIE using resist film 91 as a mask.
- step S270 (FIG. 11) is performed.
- This step (S270) can be performed in the same manner as the step (S80) in the first embodiment. Specifically, first, as in step S81 (FIG. 3) of the first embodiment, the alloy film 50 is formed on the resist film 91 and a region exposed from the resist film 91.
- the alloy film 50 on the resist film 91 is removed (lifted off), and the first n-type region 35, the first p-type region 36, and the second n-type region The alloy film 50 remains so as to be in contact on the 37 and the second p-type region 43.
- the electrical connection between alloy film 50 and silicon carbide substrate 10 is made ohmic by annealing. Specifically, heating is performed at a temperature of 550 ° C. to 1200 ° C., preferably 900 ° C. to 1100 ° C., for example 1000 ° C. in an inert gas atmosphere such as Ar, for a time of 10 minutes or less, for example 2 Annealing to hold for a minute is performed.
- the source contact as an ohmic contact electrode is brought into contact with the upper surfaces of first n-type region 35, first p-type region 36, second n-type region 37 and second p-type region 43.
- An electrode 39, a gate contact electrode 41, a drain contact electrode 42, and a potential holding contact electrode 44 are formed, respectively.
- the annealing is preferably performed in a mixed gas of an inert gas, in particular Ar or / and N 2 and hydrogen.
- the source contact electrode 39, the gate contact electrode 41 and the drain contact electrode 42 in which the contact resistance is suppressed can be manufactured while suppressing the manufacturing cost.
- a wiring formation step S280 (FIG. 11) is performed. Specifically, source interconnection 45, gate interconnection 46 and drain interconnection 47 in contact with the upper surfaces of source contact electrode 39, gate contact electrode 41 and drain contact electrode 42 are formed. Source interconnection 45, gate interconnection 46 and drain interconnection 47 are formed, for example, of a resist layer having an opening in a desired region where source interconnection 45, gate interconnection 46 and drain interconnection 47 are to be formed, Al is deposited, and then resist layer It can form by removing Al on a resist layer (lift off).
- passivation film formation step S290 (FIG. 11) is performed.
- passivation film 64 made of, for example, SiO 2 is formed to cover the upper surfaces of source electrode 61, gate electrode 62, drain electrode 63, and oxide film 38.
- the formation of passivation film 64 can be performed, for example, by CVD.
- JFET 3 is completed.
- source contact electrode 39, gate contact electrode 41 and drain contact electrode 42 can be formed of the same material, so a single mask can be used. The formation can simultaneously form these electrodes.
- the Al atoms contained in each of the source contact electrode 39, the gate contact electrode 41 and the drain contact electrode 42 are not elements but Si atoms before these electrodes are annealed. And as an alloy with Ti atoms. This suppresses the diffusion of Al atoms to the outside of these electrodes during annealing. Thus, the diffusion of Al atoms into the oxide film 38 is suppressed, and the reliability of the oxide film 38 can be enhanced.
- an insulating film made of another material may be formed instead of oxide film 38.
- a silicon nitride film may be formed.
- MOSFET 1 substantially the same as that of the first embodiment is manufactured.
- the gate oxide film 15 (insulating film) is formed by the gate insulating film forming step S70 (FIG. 2).
- an Al--Si alloy film forming step S82 (FIG. 18) forms an alloy film 59 made of an alloy containing Al atoms and Si atoms. That is, the alloy film 59 is formed on the second major surface 12 B and on the major surface of the n + substrate 11 opposite to the n ⁇ SiC layer 12.
- the formation of the alloy film is preferably performed by sputtering using a sputtering target 99.
- the sputtering target 99 is made of an alloy containing Al atoms and Si atoms.
- Ti film 53 is formed on alloy film 59 by a Ti film forming step S83 (FIG. 18). Thereby, a laminated film 50V having the alloy film 59 and the Ti film 53 is formed.
- laminated film 50 V on resist film 91 is removed (lifted off), and on second main surface 12 B exposed from gate oxide film 15.
- the laminated film 50 V remains on the main surface of the n + substrate 11 opposite to the n ⁇ SiC layer 12. As a result, as shown in FIG. 1, it extends from above each of the pair of n + source regions 14 to above p + region 18 in a direction away from gate oxide film 15 and contacts second main surface 12B.
- Source contact electrode 16 to be arranged, and the other main surface 11B which is the main surface on the opposite side to one main surface 11A which is the main surface on the side where n - SiC layer 12 is formed in n + substrate 11
- a drain electrode 20 is formed to be disposed in contact with.
- Source contact electrode 16 is formed on second major surface 12 B to be in contact with gate oxide film 15.
- the electrical connection between the laminated film 50V and the silicon carbide substrate 10 is made ohmic by annealing. Specifically, it is heated to a temperature of 550 ° C. to 1200 ° C., preferably 900 ° C. to 1100 ° C., for example 1000 ° C. in an inert gas atmosphere such as Ar, for a time of 10 minutes or less, eg 2 An anneal that is held for a minute is performed. Thereby, Ti atoms, Al atoms, Si atoms contained in the laminated film 50V, and Si atoms and C atoms contained in the silicon carbide substrate 10 are alloyed.
- n + substrate 11 be heated in a mixed gas of an inert gas, particularly Ar or / and N 2 , and hydrogen.
- source contact electrode 16 can be manufactured with the contact resistance to n + source region 14 and p body 13 (p + region 18) reduced more reliably while suppressing the manufacturing cost.
- substantially the same effect as that of the first embodiment can be obtained. Furthermore, according to the present embodiment, by covering the alloy film 59 with the Ti film 53, oxidation of Al atoms in the alloy film 59 can be prevented. This can further enhance the above effect.
- Al—Si alloy film 59 and the Ti film 53 instead of each of the Al—Si alloy film 59 and the Ti film 53, an Al—Ti alloy film and a Si film may be used.
- Embodiment 4 Also in this embodiment, a JFET 3 substantially similar to that of the second embodiment (FIG. 10) is manufactured.
- the oxide film 38 is formed in the oxide film forming step S260 (FIG. 11) as in the second embodiment.
- the alloy film 59 is formed by sputtering using the same sputtering target 99 as that of the third embodiment.
- Ti film 53 is formed on alloy film 59, whereby laminated film 50V having alloy film 59 and Ti film 53 is formed.
- the laminated film 50V on the resist film 91 is removed (lifted off), and the first n-type region 35, the first p-type region 36, and the second n-type region
- the laminated film 50V remains so as to be in contact on the 37 and the second p-type region 43.
- the electrical connection between laminated film 50V and silicon carbide substrate 30 is made ohmic by annealing. Specifically, it is heated to a temperature of 550 ° C. to 1200 ° C., preferably 900 ° C. to 1100 ° C., for example 1000 ° C. in an inert gas atmosphere such as Ar, for a time of 10 minutes or less, eg 2 An anneal that is held for a minute is performed. Thereby, Ti atoms, Al atoms, Si atoms contained in the laminated film 50 V, and Si atoms and C atoms contained in the silicon carbide substrate 30 are alloyed.
- the annealing is preferably performed in a mixed gas of an inert gas, in particular Ar or / and N 2 and hydrogen.
- an inert gas in particular Ar or / and N 2 and hydrogen.
- JFET 3 is completed. Also in the present embodiment, substantially the same effect as in the second embodiment can be obtained.
- the alloy film 59 by covering the alloy film 59 with the Ti film 53, oxidation of Al atoms in the alloy film 59 can be prevented. This can further enhance the above effect.
- Al—Si alloy film 59 and the Ti film 53 instead of each of the Al—Si alloy film 59 and the Ti film 53, an Al—Ti alloy film and a Si film may be used.
- a configuration in which the n-type and the p-type in each of the above embodiments are interchanged may be used.
- MOSFETs and JFETs have been described above as an example of the semiconductor device of the present invention, other semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors, Insulated Gate Bipolar Transistors), bipolar transistors, etc. may be manufactured.
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Abstract
Description
基板面を有する炭化珪素基板が準備される。基板面の一部を覆うように絶縁膜が形成される。絶縁膜に接触するように基板面上にコンタクト電極が形成される。コンタクト電極はAl、TiおよびSi原子を含有する。コンタクト電極は、Si原子およびTi原子の少なくともいずれかと、Al原子とを含有する合金から作られた合金膜を含む。炭化珪素基板とコンタクト電極とがオーミックに接続されるようにコンタクト電極がアニールされる。
まず本実施の形態におけるMOSFET(酸化膜電界効果トランジスタ)の構成について説明する。
図4および図5を参照して、まず基板準備工程S10(図2)によって炭化珪素基板10が準備される。
図6および図7を参照して、ゲート絶縁膜形成工程S70(図2)によって、ゲート酸化膜15(絶縁膜)が形成される。具体的には、まず、上記工程が実施されて所望のイオン注入領域を含むn-SiC層12が形成されたn+基板11が熱酸化される。熱酸化は、たとえば酸素雰囲気中で1300℃程度に加熱し、40分間程度保持することにより実施することができる。これにより第2の主面12B上に、二酸化珪素(SiO2)からなる熱酸化膜15A(たとえば厚み50nm程度)が形成される。熱酸化膜15A上にレジストが塗布された後、露光および現像が行なわれ、ソースコンタクト電極16(図1参照)を形成すべき領域に応じた開口91Aを有するレジスト膜91が形成される。そして、当該レジスト膜91をマスクとして用いて、たとえばRIEにより熱酸化膜15Aが部分的に除去される。これにより、第2の主面12Bの一部を覆うゲート酸化膜15が形成される。
具体的には、合金膜形成工程S81(図3)によって、Si原子、Ti原子、およびAl原子とを含有する合金から作られた合金膜50が形成される。すなわち、第2の主面12B上およびn+基板11のn-SiC層12とは反対側の主面上に、合金膜50が形成される。合金膜の形成は、好ましくは、スパッタリングターゲット90を用いたスパッタ法によって行なわれる。スパッタリングターゲット90は、Al原子、Si原子、およびTi原子を含有する合金から作られている。次にレジスト膜91が除去されることにより、レジスト膜91上の合金膜50が除去(リフトオフ)されて、図8に示すように、ゲート酸化膜15から露出する第2の主面12B上およびn+基板11のn-SiC層12とは反対側の主面上に、合金膜50が残存する。これにより、一対のn+ソース領域14上のそれぞれから、ゲート酸化膜15から離れる向きにp+領域18上にまで延在するとともに、第2の主面12Bに接触して配置されるソースコンタクト電極16、およびn+基板11においてn-SiC層12が形成される側の主面である一方の主面11Aとは反対側の主面である他方の主面11Bに接触して配置されるドレイン電極20が形成される。ソースコンタクト電極16は、ゲート酸化膜15に接触するように第2の主面12B上に形成される。
本実施の形態の製造方法によれば、ソースコンタクト電極16が含むAl原子は、ソースコンタクト電極16がアニールされる前に、元素としてではなく、Si原子およびTi原子との合金として存在する。これにより、アニール中にAl原子がソースコンタクト電極16の外部へ拡散することが抑制される。よってAl原子がゲート酸化膜15中に拡散することが抑制されるので、ゲート酸化膜15の信頼性を高めることができる。
まず本実施の形態におけるJFET(接合型電界効果トランジスタ)の構成について説明する。
図12~図14を参照して、まず基板準備工程S210(図11)によって炭化珪素基板30が準備される。
次にオーミック電極形成工程S270(図11)が行われる。この工程(S270)は、実施の形態1における工程(S80)と同様に実施することができる。具体的には、まず実施の形態1の工程S81(図3)と同様に、合金膜50が、レジスト膜91上および当該レジスト膜91から露出する領域に形成される。さらに、レジスト膜91が除去されることにより、レジスト膜91上の合金膜50が除去(リフトオフ)されて、第1のn型領域35、第1のp型領域36、第2のn型領域37および第2のp型領域43上に接触するように、合金膜50が残存する。
本実施の形態においても実施の形態1とほぼ同様のMOSFET1が製造される。まず実施の形態1と同様にゲート絶縁膜形成工程S70(図2)によってゲート酸化膜15(絶縁膜)が形成される。
さらに本実施の形態によれば、合金膜59をTi膜53が被覆することによって、合金膜59中のAl原子が酸化されることを防止することができる。これにより上記効果をより高めることができる。
本実施の形態においても実施の形態2(図10)とほぼ同様のJFET3が製造される。
本実施の形態によっても実施の形態2とほぼ同様の効果が得られる。
Claims (7)
- 基板面(12B)を有する炭化珪素基板(10)を準備する工程と、
前記基板面の一部を覆うように絶縁膜(15)を形成する工程と、
前記絶縁膜に接触するように前記基板面上にコンタクト電極(16)を形成する工程とを備え、
前記コンタクト電極はAl、TiおよびSi原子を含有し、前記コンタクト電極は、Si原子およびTi原子の少なくともいずれかと、Al原子とを含有する合金から作られた合金膜(50)を含み、さらに
前記炭化珪素基板と前記コンタクト電極とがオーミックに接続されるように前記コンタクト電極をアニールする工程とを備える、炭化珪素半導体装置(1)の製造方法。 - 前記合金膜は、前記合金から作られたターゲット(90)を用いたスパッタ法によって形成される、請求項1に記載の炭化珪素半導体装置の製造方法。
- 前記合金膜はSi原子を含有する、請求項1に記載の炭化珪素半導体装置の製造方法。
- 前記合金膜はTi原子を含有する、請求項3に記載の炭化珪素半導体装置の製造方法。
- 前記絶縁膜は酸化珪素膜および窒化珪素膜の少なくともいずれかを含む、請求項1に記載の炭化珪素半導体装置の製造方法。
- 前記絶縁膜上にゲート電極(17)を形成する工程をさらに備える、請求項1に記載の炭化珪素半導体装置の製造方法。
- 前記絶縁膜は層間絶縁膜(38)である、請求項1に記載の炭化珪素半導体装置の製造方法。
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JP5961563B2 (ja) | 2013-01-25 | 2016-08-02 | 株式会社豊田中央研究所 | 半導体装置の製造方法 |
JP6075185B2 (ja) * | 2013-04-26 | 2017-02-08 | 住友電気工業株式会社 | 炭化珪素半導体装置の製造方法 |
JP2015015352A (ja) | 2013-07-04 | 2015-01-22 | 住友電気工業株式会社 | 炭化珪素半導体装置の製造方法 |
JP2015032615A (ja) | 2013-07-31 | 2015-02-16 | 住友電気工業株式会社 | 炭化珪素半導体装置の製造方法 |
JP2015032614A (ja) | 2013-07-31 | 2015-02-16 | 住友電気工業株式会社 | 炭化珪素半導体装置およびその製造方法 |
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