WO2011121979A1 - 位相調整回路、位相調整方法 - Google Patents
位相調整回路、位相調整方法 Download PDFInfo
- Publication number
- WO2011121979A1 WO2011121979A1 PCT/JP2011/001827 JP2011001827W WO2011121979A1 WO 2011121979 A1 WO2011121979 A1 WO 2011121979A1 JP 2011001827 W JP2011001827 W JP 2011001827W WO 2011121979 A1 WO2011121979 A1 WO 2011121979A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- local signal
- signal
- phase adjustment
- circuit
- local
- Prior art date
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
- H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
- H04L27/36—Modulator circuits; Transmitter circuits
- H04L27/366—Arrangements for compensating undesirable properties of the transmission path between the modulator and the demodulator
Definitions
- the present invention relates to a phase adjustment circuit and a phase adjustment method, and more particularly to a phase adjustment circuit and a phase adjustment method for generating an IQ orthogonal local signal used in a reception circuit that performs quadrature demodulation or a transmission circuit that performs quadrature modulation.
- the digital modulation mainly includes PSK (Phase Shift Keying) modulation, QPSK (Quadrature Shift PSK) modulation, QAM (Quadrature Amplitude Modulation), OFDM (Orthogonal Frequency Shift Division Multiplexing), and the like.
- PSK Phase Shift Keying
- QPSK Quadratture Shift PSK
- QAM Quadrature Amplitude Modulation
- OFDM Orthogonal Frequency Shift Division Multiplexing
- the following method is simple and effective as one of the means. That is, using IQ orthogonal local signals with two carrier frequencies of 90 degrees in phase, a baseband signal expressed by IQ is directly modulated by a mixer circuit, or a high frequency signal subjected to IQ orthogonal modulation is directly demodulated.
- the method is simple and effective.
- direct modulation or direct demodulation if the phase difference between the I local signal and the Q local signal deviates from the ideal phase difference of 90 degrees, the orthogonality of the IQ is impaired, and the communication quality is reduced. It is well known that degradation occurs.
- the phase difference of IQ quadrature local deviates from an accurate 90 degrees, the IQ constellation of the modulated signal and demodulated signal is distorted, and EVM (Error Vector Magnitude) is degraded. Bring. For this reason, it is important to suppress the IQ orthogonal local phase error to achieve better communication quality.
- the IQ orthogonal local phase error is caused by various factors such as imperfection of the 90-degree phase shift circuit for generating the I local signal and the Q local signal, and imbalance on the I side Q side of the transmission path of the local signal. Occurs. For this reason, in order to realize a very small phase error, it is necessary to correct the phase of the IQ local signal.
- Patent Document 1 A means for adjusting the phase error of the IQ local signal is described in Patent Document 1, for example.
- a phase error is suppressed by adjusting a phase difference of an IQ local signal using a circuit as shown in FIG.
- a local signal is input to a single input terminal, and a local signal whose phase is adjusted is obtained from a differential output port.
- the capacitors C1 and C2 or the resistors R1 and R2 are used as variable elements to adjust the capacitance value and the resistance value, respectively, thereby changing the phase of the signal appearing at the differential output port according to the value.
- the phase difference of the IQ quadrature local signal deviates from 90 degrees due to various factors. For example, there is a difference in the propagation delay of the IQ local signal due to a mismatch between the resistance component and the capacitance component on the propagation path from the IQ orthogonal local signal generation circuit to the mixer circuit, or between IQs of the IQ orthogonal local signal generation circuit itself. There is a case where the waveform of the local signal has a difference between IQs due to mismatch, and as a result, the switching timing in the mixer circuit is shifted between IQs, resulting in a phase error. Therefore, in order to improve the communication quality, an IQ phase adjustment circuit that corrects the phase difference of the IQ orthogonal local signal to 90 degrees after manufacturing the transmitter and the receiver is necessary.
- the phase is adjusted by utilizing the frequency characteristics of the phase fluctuation caused by the combination of the resistor and the capacitor. For this reason, in order to adjust the phase of a local signal having a wide frequency range from a low frequency to a high frequency, it is necessary to be able to largely adjust the resistance value and the capacitance value. On the other hand, in order to ensure the phase adjustment accuracy, extremely fine adjustment is necessary. Therefore, a large resistance adjustment width and a large capacitance adjustment width are required, and it is necessary to be able to finely adjust them. Therefore, applying to a local signal in a wide frequency range while maintaining high accuracy increases the scale of element value switching, and is not easy to realize.
- the transmitter and receiver may be realized in a semiconductor integrated circuit.
- a semiconductor integrated circuit in order to adopt the circuit described in Patent Document 1 and switch between a resistance value and a capacitance value with high accuracy, it is general that an element having a very large size is required. For this reason, in order to realize the IQ phase adjustment circuit including the circuit described in Patent Document 1 in the semiconductor integrated circuit, there is a problem that the circuit area scale becomes very large.
- the present invention has been made in view of this point, and an object of the present invention is to easily realize an accurate phase adjustment for an IQ local signal in a wide frequency range and to have a very small area even in a semiconductor integrated circuit. It is to provide a phase adjustment circuit and a phase adjustment method that can be realized.
- a phase adjustment circuit includes a first I local signal and a first Q local signal having a phase different from that of the first I local signal at the same frequency.
- a first addition / subtraction unit that outputs a second Q local signal when it is an I local signal and outputs a second I local signal when the one local signal is the first Q local signal; Is provided.
- a second amplification unit to which the other local signal is input; Adding or subtracting the one local signal and the output signal from the second amplification unit, and outputting the second I local signal when the one local signal is the first I local signal;
- a second adder / subtractor that outputs a second Q local signal when one local signal is the first Q local signal; May be further provided. According to such a configuration, precise phase adjustment of the IQ local signal used in the quadrature modulation / demodulation circuit can be realized.
- the gains of the first amplifying unit and the second amplifying unit are variable. Since the gain can be changed, the phase of the IQ local signal can be precisely adjusted. Further, the gain of each of the first amplifying unit and the second amplifying unit may be fixed. It is preferable that the gains of the first amplifying unit and the second amplifying unit are adjusted by changing a bias current. By adjusting the gain by changing the bias current, the phase of the IQ local signal can be precisely adjusted.
- a load resistor may be connected to each of the first amplification unit and the second amplification unit, and the bias current may be supplied to each of the load resistors.
- the first I local signal and the first Q local signal may be output in accordance with the sign of the phase error value, which is an error in which the phase difference is shifted from 90 degrees.
- the gain of one of the amplifying unit and the second amplifying unit may be set to zero. According to such a configuration, the phase adjustment circuit can be realized with a simple configuration in which only one amplifier operates.
- One of the first addition / subtraction unit and the second addition / subtraction unit performs addition and the other performs subtraction. According to such a configuration, precise phase adjustment of the IQ local signal used in the quadrature modulation / demodulation circuit can be realized with a simpler configuration.
- the one local signal is input to the second adder / subtractor via a third amplifier,
- the other local signal is input to the first addition / subtraction unit via a fourth amplification unit.
- precise phase adjustment of the IQ local signal used in the quadrature modulation / demodulation circuit can be realized.
- the first addition / subtraction unit is realized by connecting the output of the first amplification unit and the output of the fourth amplification unit
- the second addition / subtraction unit is realized by connecting the output of the second amplification unit and the output of the third amplification unit. According to such a configuration, the adder / subtracter can be realized by connecting the outputs, so that the phase adjustment circuit can be realized with a simple configuration.
- a local signal generator for generating the first I local signal and the first Q local signal.
- the local signal generator receives the fifth local signal and divides the signal by a predetermined frequency division ratio. It is desirable to have a frequency divider that generates the first I local signal and the first Q local signal. By configuring the IQ phase adjustment circuit using the frequency divider, the IQ phase adjustment circuit can be realized with a simpler circuit configuration.
- a local signal generation unit configured to generate the first I local signal and the first Q local signal, wherein the local signal generation unit inputs a fifth local signal and shifts a phase thereof; It is desirable to have a phase divider that generates an I local signal and the first Q local signal. According to such a configuration, the phase adjustment can be performed so that the phase error becomes zero.
- a phase adjustment method amplifies one local signal of a first I local signal and a first Q local signal having a phase different from that of the first I local signal.
- the IQ phase adjustment circuit can be realized in a wide local frequency range. Further, when realizing the IQ phase adjustment circuit in the semiconductor integrated circuit, the IQ phase adjustment circuit can be realized with a very small area scale.
- FIG. 1 shows the specific circuit structural example of the phase adjustment circuit implement
- FIG. 1 is an example of a quadrature modulation circuit using the IQ phase adjustment circuit according to the present embodiment
- FIG. 2 is an example of a quadrature demodulation circuit using the IQ phase adjustment circuit according to the present embodiment.
- the quadrature mixer 20 includes an I mixer 20a having the local signal A2 as one input and a Q mixer 20b having the local signal B2 as one input.
- the IQ transmission baseband signal is frequency-converted by the I mixer 20a and the Q mixer 20b, respectively, and IQ-combined and output as a transmission RF (Radio-Frequency) signal.
- the received RF signal is frequency-converted by the I mixer 20a and the Q mixer 20b, respectively, and becomes an IQ reception baseband signal.
- FIG. 3 is a block diagram showing a configuration example of the IQ phase adjustment circuit according to the present embodiment.
- the local signal B is input to a variable amplifier AMP2 (second amplification unit) whose gain, that is, gain can be adjusted, and the output is added or subtracted from the local signal A by an addition / subtraction circuit (addition / subtraction unit) 5 to be output as a local signal A2. Is done.
- the local signal B is output as it is as the local signal B2.
- the local signal A2 and the local signal B2 become IQ local signals used for the orthogonal mixer.
- the local signal A is an I local signal (first I local signal) input to the IQ phase adjustment circuit
- the local signal B is a Q local signal (first output) input to the IQ phase adjustment circuit.
- Q local signal the local signal A2 becomes an I local signal (second I local signal) output from the IQ phase adjustment circuit
- the local signal B2 is output from the IQ phase adjustment circuit. (Second Q local signal).
- the local signal A is a Q local signal (first Q local signal) input to the IQ phase adjustment circuit
- the local signal B is an I local signal (first I local signal) input to the IQ phase adjustment circuit.
- Local signal the local signal A2 becomes the Q local signal (second Q local signal) output from the IQ phase adjustment circuit
- the local signal B2 becomes the I local signal (output from the IQ phase adjustment circuit).
- Second I local signal Second I local signal
- the local signal A2 if the phase error between the local signal A and the local signal B (that is, the deviation of the phase difference from 90 degrees) is ⁇ ( ⁇ > 0), the local signal A is sin ( ⁇ t ⁇ ), The local signal B can be expressed by cos ⁇ t. Assuming that the gain of the variable amplifier AMP2 is k, the local signal A2 is expressed by Expression (1).
- Equation (2) ⁇ that satisfies Equation (2).
- the phase adjustment circuit of the present embodiment is not limited to the phase error due to the IQ mismatch of the IQ orthogonal local signal generation circuit itself as described above, but also the phase error due to the mismatch between IQs generated in the subsequent circuit such as the propagation path and the quadrature mixer. Can also be eliminated.
- ⁇ is set to ⁇ 1 degree (that is, the phase difference between the local signal A2 and the local signal B2 is 89 degrees).
- the phase error of the quadrature modulation circuit and the quadrature demodulation circuit as a whole can be set to 0 (zero).
- ⁇ 0 (zero)
- k tan ⁇ .
- the subsequent circuit has a positive phase error
- ⁇ has a negative value
- the absolute value of tan ⁇ may be applied by the variable amplifier AMP2 and the addition / subtraction circuit 5 may perform subtraction, or tan ⁇ itself may be applied by the variable amplifier AMP2 and the addition may be performed by the addition / subtraction circuit 5.
- tan ⁇ is multiplied by the variable amplifier AMP2, and addition is performed by the adder / subtractor circuit 5.
- phase adjustment is possible. If the gain k is constant, the amount of phase adjustment will be constant regardless of the frequency. For example, it is possible to adjust the local signal in a wide frequency range operating from several MHz to several GHz with very high accuracy. It becomes. In particular, it occurs due to mismatch between IQs due to mismatch of resistance and capacitance components on the propagation path from IQ orthogonal local signal generation circuit to mixer circuit, mismatch between IQs of IQ orthogonal local signal generation circuit itself, and variation of orthogonal mixers. The phase adjustment can be performed so that the phase error caused by the IQ mismatch becomes zero.
- IQ local signals that is, local signals A2 and B2 have sufficiently large amplitudes, and the mixer is used in a state where the local amplitude dependency is saturated. This is a typical circuit and quadrature demodulation circuit.
- the phase difference between the local signal A1 and the local signal B1 exceeds 90 degrees has been described.
- the phase error is expressed as ⁇ ( ⁇ > 0)
- the gain of the variable amplifier AMP2 is expressed as k
- the local signal A is expressed as sin ( ⁇ t + ⁇ )
- the local signal B is expressed as cos ⁇ t.
- the signal A2 is as shown in Equation (3).
- phase difference can be similarly corrected to 90 degrees in this case.
- this addition and subtraction can be performed in the reverse configuration. That is, it may be configured as shown in FIG. That is, the local signal A is input to the variable amplifier AMP1 (first amplification unit), and the output is added or subtracted from the local signal B in the addition / subtraction circuit (addition / subtraction unit) 5 to be output as the local signal B2.
- the signal A may be directly output as the local signal A2.
- the local signal A is an I local signal (first I local signal) input to the IQ phase adjustment circuit
- the local signal B is a Q local signal (first output) input to the IQ phase adjustment circuit.
- Q local signal the local signal A2 becomes an I local signal (second I local signal) output from the IQ phase adjustment circuit
- the local signal B2 is output from the IQ phase adjustment circuit. (Second Q local signal).
- the local signal A is a Q local signal (first Q local signal) input to the IQ phase adjustment circuit
- the local signal B is an I local signal (first I local signal) input to the IQ phase adjustment circuit.
- Local signal the local signal A2 becomes the Q local signal (second Q local signal) output from the IQ phase adjustment circuit
- the local signal B2 becomes the I local signal (output from the IQ phase adjustment circuit).
- Second I local signal Second I local signal
- phase adjustment circuit shown in FIG. 4 is similar to the phase adjustment circuit shown in FIG. 3, the same effect as the phase adjustment circuit shown in FIG. 3 can be obtained. That is, by making it possible to finely adjust the gain k, it is possible to perform precise phase adjustment. If the gain k is constant, the amount of phase adjustment will be constant regardless of the frequency. For example, it is possible to adjust the local signal in a wide frequency range operating from several MHz to several GHz with very high accuracy. It becomes.
- phase adjustment can be performed so that the phase error caused by the IQ mismatch becomes zero.
- FIG. 5 is a block diagram showing another configuration example of the IQ phase adjustment circuit according to the present embodiment.
- the local signal A is input to the variable amplifier AMP1 whose gain, that is, the gain can be adjusted, and the output is subtracted from the local signal B by the subtractor 4 and output as the local signal B2.
- the local signal B is input to the variable amplifier AMP2 whose gain can be adjusted, and the output of the local signal B is added to the local signal A by the adder 3 and output as the local signal A2.
- the local signal A2 and the local signal B2 become IQ local signals used for the orthogonal mixer.
- the local signal A is an I local signal (first I local signal) input to the IQ phase adjustment circuit
- the local signal B is a Q local signal (first output) input to the IQ phase adjustment circuit.
- Q local signal the local signal A2 becomes an I local signal (second I local signal) output from the IQ phase adjustment circuit
- the local signal B2 is output from the IQ phase adjustment circuit. (Second Q local signal).
- the local signal A is a Q local signal (first Q local signal) input to the IQ phase adjustment circuit
- the local signal B is an I local signal (first I local signal) input to the IQ phase adjustment circuit.
- Local signal the local signal A2 becomes the Q local signal (second Q local signal) output from the IQ phase adjustment circuit
- the local signal B2 becomes the I local signal (output from the IQ phase adjustment circuit).
- Second I local signal Second I local signal
- the local signal A2 is expressed by the above-described equation (1). In this case as well, by setting ⁇ to 0 (zero), the local signal A2 has a phase error with respect to the local signal B. 0 (zero).
- k sin ⁇
- the local signal A is not combined with the local signal B (that is, the gain of the variable amplifier AMP2 is set to 0 (zero)) so that the local signal B is used as it is as the local signal B2.
- the phase error between the local signal A2 and the local signal B2 can be eliminated.
- the IQ phase adjustment circuit of the present embodiment is not limited to the phase error caused by the IQ mismatch of the IQ orthogonal local signal generation circuit itself as described above, but also the phase caused by the IQ mismatch generated in the subsequent circuit such as the propagation path or the quadrature mixer. Errors can be eliminated.
- the gain k is set so that ⁇ is 1 degree (that is, the phase difference between the local signal A2 and the local signal B2 is 91 degrees). By determining this value, the phase error of the quadrature modulation circuit and the quadrature demodulation circuit as a whole can be set to 0 (zero).
- the phase difference between the local signal A1 and the local signal B1 exceeds 90 degrees has been described.
- the phase error is represented by ⁇ ( ⁇ > 0)
- the gain of the variable amplifier AMP2 is represented by k
- the local signal A is represented by sin ⁇ t
- the local signal B is represented by cos ( ⁇ t ⁇ ).
- the local signal B2 is expressed by Equation (5).
- the gain of the variable amplifier AMP1 is set to 0 (zero)
- the local signal A is used as it is as the local signal A2.
- the phase difference can be similarly corrected to 90 degrees.
- the phase adjustment circuit of the present embodiment is not limited to the phase error due to the IQ mismatch of the IQ orthogonal local signal generation circuit itself as described above, but also the phase error due to the mismatch between IQs generated in the subsequent circuit such as the propagation path and the quadrature mixer. Can also be eliminated.
- ⁇ is set to ⁇ 1 degree (that is, the phase difference between the local signal A2 and the local signal B2 is 89 degrees).
- the phase error of the quadrature modulation circuit and the quadrature demodulation circuit as a whole can be set to 0 (zero).
- phase error can be set to 0 (zero).
- the phase error of the IQ orthogonal local signal can be either a positive value or a negative value.
- the configuration of FIG. 5 is used in this example. That is, the output of the variable amplifier AMP1 is subtracted from the local signal B, and the output of the other variable amplifier AMP2 is added to the local signal A.
- the variable amplifier AMP1 or the variable amplifier AMP2 for both the case where the phase difference is large with respect to 90 degrees and the case where the phase difference is small (that is, depending on whether the phase error value is positive or negative) Correction to a phase difference of 90 degrees can be realized.
- the output of the variable amplifier AMP1 may be added to the local signal B, and the output of the other variable amplifier AMP2 may be subtracted from the local signal A.
- the local signal A is an I local signal (first I local signal) input to the IQ phase adjustment circuit
- the local signal B is a Q local signal (first output) input to the IQ phase adjustment circuit.
- Q local signal the local signal A2 becomes an I local signal (second I local signal) output from the IQ phase adjustment circuit
- the local signal B2 is output from the IQ phase adjustment circuit. (Second Q local signal).
- the local signal A is a Q local signal (first Q local signal) input to the IQ phase adjustment circuit
- the local signal B is an I local signal (first I local signal) input to the IQ phase adjustment circuit.
- Local signal the local signal A2 becomes the Q local signal (second Q local signal) output from the IQ phase adjustment circuit
- the local signal B2 becomes the I local signal (output from the IQ phase adjustment circuit).
- Second I local signal Second I local signal
- the phase error can be both positive and negative. That is, the gain of one of the variable amplifier AMP1 and the variable amplifier AMP2 is set to zero according to the sign of the phase error value, which is an error in which the phase difference between the local signal A and the local signal B is shifted from 90 degrees.
- phase adjustment circuit shown in FIG. 6 is similar to the phase adjustment circuit shown in FIG. 5, the same effect as the phase adjustment circuit shown in FIG. 5 can be obtained. That is, by making it possible to finely adjust the gain k, it is possible to perform precise phase adjustment. If the gain k is constant, the amount of phase adjustment will be constant regardless of the frequency. For example, it is possible to adjust the local signal in a wide frequency range operating from several MHz to several GHz with very high accuracy. It becomes.
- phase adjustment can be performed so that the phase error caused by the IQ mismatch becomes zero.
- the phase adjustment circuit illustrated in FIGS. 5 and 6 includes the variable amplifier AMP1 and the variable amplifier. It is possible to give both AMP2 gains. That is, the phase adjustment can be performed by providing both the variable amplifier AMP1 and the variable amplifier AMP2 with gain and distributing the correction amount of the phase error to the local signal A2 and the local signal B2. In particular, by distributing evenly, the amplitudes of the local signal A2 and the local signal B2 can be made equal in addition to the effects described above.
- the gains of the variable amplifier AMP1 and the variable amplifier AMP2 shown in FIGS. 3 to 6 are obtained by measuring the phase error in advance from the output signal of the subsequent circuit including the quadrature mixer in the quadrature modulation circuit or the quadrature demodulation circuit.
- the phase error can be set to be zero. That is, the variable amplifier AMP1 and the variable amplifier AMP2 function as a fixed gain amplifying unit after the gain is set.
- the phase error obtained from the output signal of the subsequent circuit including the quadrature mixer in the quadrature modulation circuit or the quadrature demodulation circuit can be fed back to the variable amplifier AMP1 and the variable amplifier AMP2 to automatically set the gain. That is, the variable amplifier AMP1 and the variable amplifier AMP2 function as a variable gain amplifying unit.
- variable amplifier AMP1 and the variable amplifier 2 function as a fixed amplifying unit after the gain is set or when they function as a variable gain amplifying unit, the gain k can be finely adjusted so that precise phase adjustment is possible. Is possible. If the gain k is constant, the amount of phase adjustment will be constant regardless of the frequency. For example, it is possible to adjust the local signal in a wide frequency range operating from several MHz to several GHz with very high accuracy. It becomes.
- phase adjustment can be performed so that the phase error caused by the IQ mismatch becomes zero.
- FIG. 7 is a diagram illustrating a configuration using a differential circuit as an example of a specific circuit for realizing the variable amplifier.
- the gain of the amplifier composed of the transistors M12a and M12b and the load resistors R2a and R2b is adjusted by finely adjusting the current amount of the current source VRI1.
- the current from the current source VRI1 is supplied to the transistors M12a and M12b and the load resistors R2a and R2b.
- the gain of the variable amplifier is represented by the product of the mutual conductance values of the transistors M12a and M12b and the load resistors R2a and R2b. Therefore, the gain of the amplifier can be finely adjusted by finely adjusting the current amount of the current source VRI1 that determines the mutual conductance value.
- FIG. 8 is a block diagram showing another configuration example of the IQ phase adjustment circuit according to the present embodiment.
- the local signal A is input to a variable amplifier AMP1 whose gain, that is, gain can be adjusted, and to an amplifier AMP3 having an arbitrary gain.
- the local signal B is input to the variable amplifier AMP2 whose gain, that is, the gain can be adjusted, and to the amplifier AMP4 having an arbitrary gain.
- the output of the variable amplifier AMP1 is subtracted from the output of the amplifier AMP4 in the subtractor 4 and output as the local signal B2.
- the output of the variable amplifier AMP2 is added to the output of the amplifier AMP3 in the adder 3 and output as the local signal A2.
- the local signal A is an I local signal (first I local signal) input to the IQ phase adjustment circuit
- the local signal B is a Q local signal (first output) input to the IQ phase adjustment circuit.
- Q local signal the local signal A2 becomes an I local signal (second I local signal) output from the IQ phase adjustment circuit
- the local signal B2 is output from the IQ phase adjustment circuit. (Second Q local signal).
- the local signal A is a Q local signal (first Q local signal) input to the IQ phase adjustment circuit
- the local signal B is an I local signal (first I local signal) input to the IQ phase adjustment circuit.
- Local signal the local signal A2 becomes the Q local signal (second Q local signal) output from the IQ phase adjustment circuit
- the local signal B2 becomes the I local signal (output from the IQ phase adjustment circuit).
- Second I local signal Second I local signal
- this addition and subtraction can be performed in the reverse configuration. That is, it may be configured as shown in FIG. That is, in FIG. 9, the local signal A is input to the variable amplifier AMP1 whose gain, that is, the gain can be adjusted, and to the amplifier AMP3 having an arbitrary gain. Similarly, the local signal B is input to the variable amplifier AMP2 whose gain, that is, the gain can be adjusted, and to the amplifier AMP4 having an arbitrary gain. Then, the output of the variable amplifier AMP1 is added to the output of the amplifier AMP4 in the adder 3, and is output as a local signal B2. At the same time, the output of the variable amplifier AMP2 is subtracted from the output of the amplifier AMP3 in the subtractor 4 and output as the local signal A2.
- the local signal A is an I local signal (first I local signal) input to the IQ phase adjustment circuit
- the local signal B is a Q local signal (first output) input to the IQ phase adjustment circuit.
- Q local signal the local signal A2 becomes an I local signal (second I local signal) output from the IQ phase adjustment circuit
- the local signal B2 is output from the IQ phase adjustment circuit. (Second Q local signal).
- the local signal A is a Q local signal (first Q local signal) input to the IQ phase adjustment circuit
- the local signal B is an I local signal (first I local signal) input to the IQ phase adjustment circuit.
- Local signal the local signal A2 becomes the Q local signal (second Q local signal) output from the IQ phase adjustment circuit
- the local signal B2 becomes the I local signal (output from the IQ phase adjustment circuit).
- Second I local signal Second I local signal
- the output signals of the variable amplifier AMP1 and the variable amplifier AMP2 are respectively output from the amplifier AMP3 and the amplifier AMP4.
- the amplitude becomes relatively small. Therefore, precise phase adjustment is possible without finely adjusting the gain k of the variable amplifier AMP1 and the variable amplifier AMP2.
- the phase adjustment amount is constant regardless of the frequency.
- the local signal in a wide frequency range operating from several MHz to several GHz is adjusted with very high accuracy. Is easily possible. In particular, it occurs due to mismatch between IQs due to mismatch of resistance and capacitance components on the propagation path from IQ orthogonal local signal generation circuit to mixer circuit, mismatch between IQs of IQ orthogonal local signal generation circuit itself, and variation of orthogonal mixers.
- the phase adjustment can be performed so that the phase error caused by the IQ mismatch becomes zero.
- FIG. 10 is a diagram showing a configuration using a differential circuit as an example of a specific circuit for realizing the IQ phase adjustment circuit of the example shown in FIGS.
- an IQ local signal used for an orthogonal mixer is often used after being amplified by an amplifier. This is because it is used in a state where the frequency conversion efficiency is saturated in order to suppress a gain difference between IQs in a quadrature mixer and a gain variation between individual manufacturing differences.
- This circuit example focuses on this point, and easily adjusts the phase of the IQ local signal by utilizing an amplifier necessary for signal amplification.
- the main amplifiers 11A (corresponding to AMP3 in FIGS. 8 and 9) and 11B (corresponding to AMP4 in FIGS. 8 and 9) in the broken line portion of FIG. Part.
- the main amplifier 11A includes a transistor M2a and a resistor R2a to which the local signal A positive signal (positive signal) AP is applied to the gate, a transistor M1a and a resistor R1a to which the local signal A negative signal (negative signal) AN is applied to the gate, and
- the current source I11a is configured to output a local signal A2 positive signal A2P and a local signal A2 negative signal A2N.
- the main amplifier 11B includes a transistor M1b and a resistor R1b to which the local signal B positive signal BP is applied to the gate, a transistor M2b and a resistor R2b to which the local signal B negative signal BN is applied to the gate, and a current source I11b.
- the signal B2 positive signal B2P and the local signal B2 negative signal B2N are output.
- sub amplifiers 12A and 12B in addition to the main amplifiers 11A and 11B, sub amplifiers 12A (corresponding to AMP1 in FIGS. 8 and 9) and 12B (corresponding to AMP2 in FIGS. 8 and 9) having the same configuration as these main amplifiers. ).
- These sub-amplifiers 12A and 12B have the functions of the adder 3 and the subtracter 4 in FIGS.
- the transistor M12b to which the local signal A positive signal (positive signal) is input is output to the positive signal output of the local signal B2, and the local signal A negative signal (negative signal). Is input to the negative signal output of the local signal B2, respectively.
- the transistor M1b to which the local signal B positive signal is input is the negative signal output of the local signal A2
- the transistor M2b to which the local signal B negative signal is input is The output is connected to the positive signal output of the local signal A2.
- the phase adjustment circuit can be realized with a simple configuration. Further, the gains of the sub-amplifiers 12A and 12B can be adjusted by adjusting the bias currents with the variable current sources VRI1 and VRI2 of the sub-amplifiers 12A and 12B, respectively. As a result, the IQ phase adjustment circuit can be easily realized simply by adding the sub-amplifiers 12A and 12B to the amplification amplifier that was originally necessary.
- transistors having the same mutual conductance per size as the transistors used for the main amplifiers 11A and 11B are used for the sub amplifiers 12A and 12B, and the current sources I11a and A11b of the main amplifiers 11A and 11B and the variable current source VRI1 of the sub amplifier are used.
- VRI2 are matched so that the amount of current is linked, so that even if the gains of the main amplifiers 11A and 11B fluctuate due to temperature, power supply voltage, etc., the gains of the sub-amplifiers 12A and 12B change in conjunction with each other. It is easy to make the amount constant.
- the local signal in a wide frequency range operating at several MHz to several GHz with very high accuracy.
- the phase adjustment can be performed so that the phase error caused by the IQ mismatch becomes zero.
- FIG. 11 is an image diagram showing an example of circuit arrangement when the circuit of FIG. 5 is realized in a semiconductor integrated circuit.
- the transistors M12a, M12b, M12c, and M12d constituting the sub-amplifiers 12A and 12B are arranged along with the main amplifier transistors M1a, M2a, M1b, and M2b, and only a simple wiring shown by a broken line is added. It is a feature of this circuit arrangement that an adder circuit and a subtractor circuit can be configured.
- the sub-amplifier can be realized with a smaller transistor than the main amplifier. From this, it can be seen that the circuit of FIG. 10 can be realized on a very small scale when realized in a semiconductor integrated circuit.
- the IQ phase adjustment circuit of this example can be easily realized.
- a high-frequency signal C having a frequency twice the desired local frequency is input to the divider circuit 30, and the local signal A2 and the local signal having a desired frequency that are 90 degrees different from each other.
- Signal B2 is obtained.
- the frequency dividing circuit 30 is a frequency dividing circuit 30, a high frequency signal C having a frequency four times the desired local frequency is input to the frequency dividing circuit 30, and the local signal A 2 and the local signal having a desired frequency that are 90 degrees different from each other.
- Signal B2 is obtained.
- FIG. 14 is a diagram illustrating a specific circuit configuration example of an IQ phase adjustment circuit realized by using a divide-by-2 circuit used in the quadrature modulation circuit of FIG. 12 and the quadrature demodulation circuit of FIG.
- a broken line portion in FIG. 2 is a divide-by-2 circuit 30 that is originally necessary for generating an IQ local signal.
- This divide-by-2 circuit 30 has a configuration in which two stages of well-known differential D latch circuits are combined. In other words, in FIG. 14, the divide-by-2 circuit 30 is configured by the differential D latch circuits 31 and 32 combined in two stages.
- the differential D latch circuit 31 includes a hold unit composed of transistors M01 and M02 and resistors R11 and R12, a latch unit composed of transistors M03 and M04, a transistor M05 having a high frequency signal C positive input CP applied to the gate,
- the signal C negative input CN includes a transistor M06 having a gate applied thereto, and a constant current source I1.
- the differential D latch circuit 32 includes a hold unit composed of transistors M09 and M10 and resistors R13 and R14, a latch unit composed of transistors M07 and M08, a transistor M11 having a high frequency signal C positive input CP applied to the gate, and a high frequency
- the signal C negative input CN includes a transistor M12 having a gate applied thereto, and a constant current source I2.
- differential D latch circuit 31 and the differential D latch circuit 32 one output is an input to the other.
- the differential D latch circuits 31 and 32 operate as a D-type latch circuit using the high frequency signal C positive input CP and the high frequency signal C negative input CN as clocks, respectively, and operate as a divide-by-2 circuit.
- two sub-amplifiers 12A and 12B are prepared.
- the output of the transistor M41 to which the local signal A2 positive signal A2P is input to the gate, is output to the positive signal B2P of the local signal B2, and the local signal A2 negative signal A2N is input to the gate.
- the output of the transistor M42 is connected to the output of the negative signal B2N of the local signal B2.
- the output of the transistor M43 to which the local signal B2 positive signal B2P is input to the gate is the output of the negative signal A2N of the local signal A2, and the local signal B2 negative signal B2N is input to the gate
- the output of the transistor being connected is connected to the output of the positive signal A2P of the local signal A2.
- the gain of the sub-amplifier can be adjusted by adjusting the variable current sources I1 and I2 of the sub-amplifiers 12A and 12B, and the phase adjustment circuit can be easily realized. it can. Further, the phase error due to the IQ mismatch in the frequency divider can be made zero. Also in this case, it is possible to easily adjust the local signal in a wide frequency range that operates at, for example, several MHz to several GHz with very high accuracy.
- phase adjustment can be performed so that the phase error caused by the IQ mismatch becomes zero.
- FIG. 15 is a specific circuit configuration example of the divide-by-4 circuit used in the quadrature modulation circuit of FIG. 12 and the quadrature demodulation circuit of FIG.
- a broken line portion in FIG. 4 is a divide-by-4 circuit 30 which is originally necessary for generating an IQ local signal.
- the divide-by-4 circuit 30 is configured by combining two divide-by-2 circuits described with reference to FIG. That is, in FIG. 15, the four-frequency divider 30 is configured by the differential D latch circuits 31, 32, 33, and 34 combined in four stages.
- the differential D latch circuit 31 includes a hold unit composed of transistors M01 and M02 and resistors R11 and R12, a latch unit composed of transistors M03 and M04, a transistor M05 having a high frequency signal C positive input CP applied to the gate,
- the signal C negative input CN includes a transistor M06 having a gate applied thereto, and a constant current source I1.
- the differential D latch circuit 32 includes a hold unit composed of transistors M09 and M10 and resistors R13 and R14, a latch unit composed of transistors M07 and M08, a transistor M11 having a high frequency signal C positive input CP applied to the gate, and a high frequency
- the signal C negative input CN includes a transistor M12 having a gate applied thereto, and a constant current source I2.
- the differential D latch circuit 33 includes a hold unit composed of transistors M21 and M22 and resistors R21 and R22, a latch unit composed of transistors M23 and M24, a transistor M25 having a high frequency signal C positive input CP applied to the gate,
- the signal C negative input CN includes a transistor M26 having a gate applied thereto, and a constant current source I3.
- the differential D latch circuit 34 includes a hold unit composed of transistors M29 and M30 and resistors R23 and R24, a latch unit composed of transistors M27 and M28, a transistor M31 having a high frequency signal C positive input CP applied to the gate,
- the signal C negative input CN includes a transistor M32 having a gate applied thereto and a constant current source I4.
- two sub-amplifiers 12A and 12B are prepared, and currents are added and subtracted from outputs of the sub-amplifiers 12A and 12B.
- the gain of the sub-amplifier can be adjusted by adjusting the variable current sources I1 and I2 of the sub-amplifiers 12A and 12B, and the IQ phase adjustment circuit can be easily realized. .
- the circuit is not limited to the divide-by-2 circuit and the divide-by-4 circuit, and if necessary, an divide-by-8 circuit, a divide-by-16 circuit, or the like may be used.
- the phase adjustment circuit can be easily realized. Further, the phase error due to the IQ mismatch in the frequency divider can be made zero. Also in this case, it is possible to easily adjust the local signal in a wide frequency range that operates at, for example, several MHz to several GHz with very high accuracy.
- phase adjustment can be performed so that the phase error caused by the IQ mismatch becomes zero.
- IQ local signals having a phase difference of about 90 degrees are prepared using a polyphase filter (phase division unit) that prepares a signal of a desired local frequency and shifts the phase of the signal. May be generated.
- FIG. 16 is a diagram showing a configuration of a quadrature modulation circuit having a polyphase filter
- FIG. 17 is a diagram showing a configuration of a quadrature demodulation circuit having a polyphase filter. 16 and 17, the 0 ° / 90 ° division polyphase filter 40 receives the high-frequency signal C and outputs local signals A and B, which are IQ local signals having a phase difference of 90 degrees.
- the local signals A2 and B2 obtained by the IQ phase adjustment circuit 10 that receives the local signals A and B output from the polyphase filter 40 are as follows:
- the signals are input to the mixers 20 a and 20 b in the orthogonal mixer 20.
- the time constant deviates from an ideal value due to variations in accuracy of elements constituting the filter.
- the phase difference deviates from 90 degrees.
- the correction to the phase difference of 90 degrees can be realized by using the IQ phase adjustment circuit 10 as shown in FIGS.
- the IQ mismatch due to the mismatch of the resistance component and the capacitance component on the propagation path from the IQ orthogonal local signal generation circuit to the mixer circuit, and the IQ mismatch of the IQ orthogonal local signal generation circuit itself are orthogonal.
- the phase adjustment can be performed so that the phase error caused by the mismatch between IQs caused by the variation of the mixer becomes zero.
- phase adjustment method According to the phase adjustment circuit described above, the following phase adjustment method is realized. That is, a first step of amplifying one local signal among a first I local signal and a first Q local signal having a phase different from that of the first I local signal, Of the first I local signal and the first Q local signal, the other local signal and a signal obtained by amplifying the one local signal are added or subtracted, and the one local signal becomes the first I signal. A second step of outputting a second Q local signal when the signal is a local signal and outputting a second I local signal when the one local signal is the first Q local signal. An adjustment method is realized. According to this method, precise phase adjustment of the IQ local signal used in the quadrature modulation / demodulation circuit can be realized.
- an IQ phase adjustment circuit can be realized in a wide local frequency range. Further, when realizing the IQ phase adjustment circuit in the semiconductor integrated circuit, the IQ phase adjustment circuit can be realized with a very small area scale. Further, an IQ phase adjustment circuit is configured by using a frequency dividing circuit, and a signal having a frequency twice the local frequency is divided by two, or a signal having a frequency four times the local frequency is divided by four to obtain an IQ local signal. In the case of generation, an IQ phase adjustment circuit can be realized with a simpler circuit configuration.
- the present invention can be applied to an IQ phase adjustment circuit that generates an IQ orthogonal local signal used in a reception circuit that performs quadrature demodulation or a transmission circuit that performs quadrature modulation.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Superheterodyne Receivers (AREA)
- Transmitters (AREA)
Abstract
Description
前記第1のIローカル信号および前記第1のQローカル信号のうち、他方のローカル信号と前記第1の増幅部からの出力信号とを加算もしくは減算し、前記一方のローカル信号が前記第1のIローカル信号であるとき第2のQローカル信号を出力し、前記一方のローカル信号が前記第1のQローカル信号であるとき第2のIローカル信号を出力する第1の加減算部と、
を備える。このような構成によれば、直交変復調回路に用いるIQローカル信号の精密な位相調整を、実現することができる。
前記一方のローカル信号と前記第2の増幅部からの出力信号とを加算もしくは減算し、前記一方のローカル信号が前記第1のIローカル信号であるとき第2のIローカル信号を出力し、前記一方のローカル信号が前記第1のQローカル信号であるとき第2のQローカル信号を出力する第2の加減算部と、
を更に備えていてもよい。このような構成によれば、直交変復調回路に用いるIQローカル信号の精密な位相調整を、実現することができる。
また、前記第1の増幅部及び前記第2の増幅部は、それぞれの利得が固定であってもよい。
前記第1の増幅部及び前記第2の増幅部は、バイアス電流を変化させることにより、それぞれの利得が調整されることが望ましい。バイアス電流を変化させて利得が調整されることにより、IQローカル信号の位相調整を精密に行うことができる。
前記第2の加減算部には、第3の増幅部を介して、前記一方のローカル信号が入力され、
前記第1の加減算部には、第4の増幅部を介して、前記他方のローカル信号が入力されることを特徴とする。このような構成によれば、直交変復調回路に用いるIQローカル信号の精密な位相調整を、実現することができる。
前記第2の加減算部は、前記第2の増幅部の出力と前記第3の増幅部の出力との結線によって実現されることを特徴とする。このような構成によれば、出力を結線することで加減算部を実現できるため、位相調整回路を簡易な構成で実現することができる。
前記第1のIローカル信号および前記第1のQローカル信号のうち、他方のローカル信号と前記一方のローカル信号を増幅した信号とを加算もしくは減算し、前記一方のローカル信号が前記第1のIローカル信号であるとき第2のQローカル信号を出力し、前記一方のローカル信号が前記第1のQローカル信号であるとき第2のIローカル信号を出力する第2のステップと、
を備える。この方法によれば、直交変復調回路に用いるIQローカル信号の精密な位相調整を、実現することができる。
(直交変調回路、直交復調回路)
図1は本実施形態によるIQ位相調整回路を用いた直交変調回路の例であり、図2は本実施形態によるIQ位相調整回路を用いた直交復調回路の例である。図1の直交変調回路、図2の直交復調回路のいずれにおいても、位相誤差を持ったローカル信号として、互いに位相がおよそ90度異なるローカル信号Aおよびローカル信号BがIQ位相調整回路10に入力され、このIQ位相調整回路10において位相誤差を抑えたローカル信号A2およびローカル信号B2が直交ミキサ20に入力される。直交ミキサ20は、ローカル信号A2を入力の一方とするIミキサ20aと、ローカル信号B2を入力の一方とするQミキサ20bとを備えている。
図3は本実施形態によるIQ位相調整回路の構成例を示すブロック図である。ローカル信号Bは、利得すなわちゲインが調整できる可変アンプAMP2(第2の増幅部)に入力され、その出力が加減算回路(加減算部)5においてローカル信号Aから加算もしくは減算され、ローカル信号A2として出力される。同時に、ローカル信号Bはそのままローカル信号B2として出力される。このローカル信号A2およびローカル信号B2が直交ミキサに使用するIQローカル信号となる。
特に、IQ直交ローカル信号生成回路からミキサ回路への伝播経路につく抵抗成分、容量成分のミスマッチによるIQ間ミスマッチと、IQ直交ローカル信号生成回路そのものがもつIQ間ミスマッチと、直交ミキサのばらつきで生じるIQ間ミスマッチと、に起因する位相誤差が零になるように位相調整を行うことができる。
図5は本実施形態によるIQ位相調整回路の他の構成例を示すブロック図である。ローカル信号Aは、利得すなわちゲインが調整できる可変アンプAMP1に入力され、その出力が減算器4においてローカル信号Bから減算され、ローカル信号B2として出力される。同様に、ローカル信号Bは、利得が調整できる可変アンプAMP2に入力され、その出力が加算器3においてローカル信号Aと加算され、ローカル信号A2として出力される。このローカル信号A2およびローカル信号B2が直交ミキサに使用するIQローカル信号となる。
ここで、ローカル信号Aが、IQ位相調整回路に入力されるIローカル信号(第1のIローカル信号)であり、ローカル信号Bが、IQ位相調整回路に入力されるQローカル信号(第1のQローカル信号)であるとき、ローカル信号A2が、IQ位相調整回路から出力されるIローカル信号(第2のIローカル信号)となり、ローカル信号B2が、IQ位相調整回路から出力されるQローカル信号(第2のQローカル信号)となる。
図7は、可変アンプを実現する具体的な回路の一例として、差動回路を用いた構成を示す図である。この構成では、電流源VRI1の電流量を細かく調整することで、トランジスタM12aおよびM12bとロード抵抗R2aおよびR2bで構成されるアンプの利得を調整するものである。図7においては、電流源VRI1の電流が、トランジスタM12aおよびM12bとロード抵抗R2aおよびR2bとに供給される。この可変アンプの利得は、トランジスタM12aおよびM12bの相互コンダクタンス値と、ロード抵抗R2aおよびR2bとの積で表される。このため、相互コンダクタンス値を決める電流源VRI1の電流量を細かく調整することで、アンプの利得を細かく調整することができる。
図8は、本実施形態によるIQ位相調整回路の他の構成例を示すブロック図である。図8において、ローカル信号Aは、利得すなわちゲインが調整できる可変アンプAMP1に入力されるとともに、任意のゲインをもつアンプAMP3に入力される。同様に、ローカル信号Bは、利得すなわちゲインが調整できる可変アンプAMP2に入力されるとともに、任意のゲインをもつアンプAMP4に入力される。そして、可変アンプAMP1の出力が減算器4においてアンプAMP4の出力から減算され、ローカル信号B2として出力される。同時に、可変アンプAMP2の出力が加算器3においてアンプAMP3の出力に加算され、ローカル信号A2として出力される。
特に、IQ直交ローカル信号生成回路からミキサ回路への伝播経路につく抵抗成分、容量成分のミスマッチによるIQ間ミスマッチと、IQ直交ローカル信号生成回路そのものがもつIQ間ミスマッチと、直交ミキサのばらつきで生じるIQ間ミスマッチと、に起因する位相誤差が零になるように位相調整を行うことができる。
図10は、図8および図9に示した例のIQ位相調整回路を実現する具体的な回路の一例として、差動回路を用いた構成を示す図である。一般に、直交ミキサに用いるIQローカル信号は、アンプで増幅して使用されることが多い。これは、直交ミキサにおけるIQ間のゲイン差や製造個体差間でのゲインばらつきを小さく抑えるために、周波数変換効率が飽和した状態で使用するためである。この回路例ではこの点に着眼し、信号増幅のために必要となるアンプを活用して容易にIQローカル信号の位相調整を行うものである。
このように接続された構成とすることで、主アンプ11Aおよび11Bとサブアンプ12A、12Bとの出力を電流加算および電流減算することができる。
また、サブアンプ12A、12Bの可変電流源VRI1、VRI2によりバイアス電流を調整することで、サブアンプ12A、12Bのゲインをそれぞれ調整することができる。これにより、従来からもともと必要であった増幅アンプにサブアンプ12A、12Bを付加するだけで、IQ位相調整回路を容易に実現することができる。
特に、IQ直交ローカル信号生成回路からミキサ回路への伝播経路につく抵抗成分、容量成分のミスマッチによるIQ間ミスマッチと、IQ直交ローカル信号生成回路そのものがもつIQ間ミスマッチと、直交ミキサのばらつきで生じるIQ間ミスマッチと、に起因する位相誤差が零になるように位相調整を行うことができる。
図11は、半導体集積回路内で図5の回路を実現した場合の回路配置例を示すイメージ図である。図11において、サブアンプ12A、12Bを構成するトランジスタM12a、M12b、M12c、M12dは、主アンプのトランジスタM1a、M2a、M1b、M2bに付随して配置され、また破線で示した単純な配線の追加のみで加算回路、減算回路を構成できることが本回路配置の特徴である。一般に、サブアンプの利得は主アンプの利得に対してcosα倍(αは位相誤差量)で済むため、サブアンプは主アンプにくらべて小さいトランジスタで実現可能である。このことから、図10の回路は、半導体集積回路内で実現する場合、非常に小面積規模で実現できることがわかる。図11のコア回路構成に、電流源回路を、通常行われる方法で付加することで、本例のIQ位相調整回路が容易に実現可能である。
一般に、直交変調器および直交復調器においては、所望のローカル周波数の2倍または4倍の周波数の信号を用意し、その信号を2分周または4分周して90度位相の異なるIQローカル信号を生成することが多い。この場合の直交変調回路を図12に、直交復調回路を図13に、それぞれ示す。図12の直交変調回路、図13の直交復調回路のいずれにおいても、分周回路(分周部)30によって得られるローカル信号A2、B2が、直交ミキサ20内のミキサ20a、20bに入力されている。
図14は、図12の直交変調回路、図13の直交復調回路において用いられる、2分周回路を用いて実現したIQ位相調整回路の具体的な回路構成例を示す図である。同図の破線部分が本来IQローカル信号の生成に必要となる2分周回路30である。この2分周回路30は、周知の差動Dラッチ回路を2段組み合わせた構成になっている。すなわち、図14において、2段に組み合わされた差動Dラッチ回路31、32によって、2分周回路30が構成されている。
この場合も、たとえば数MHzから数GHzで動作するような広い周波数範囲のローカル信号について非常に精度よく調整を行うことが容易に可能となる。
図15は、図12の直交変調回路、図13の直交復調回路において用いられる、4分周回路の具体的な回路構成例である。同図の破線部分が本来IQローカル信号の生成に必要となる4分周回路30である。この4分周回路30は、図14を参照して説明した2分周回路を2段組み合わせた構成になっている。すなわち、図15において、4段に組み合わされた差動Dラッチ回路31、32、33、34によって、4分周回路30が構成されている。
この場合も、たとえば数MHzから数GHzで動作するような広い周波数範囲のローカル信号について非常に精度よく調整を行うことが容易に可能となる。
一般に、直交変調器および直交復調器においては、所望のローカル周波数の信号を用意し、その信号の位相をシフトするポリフェーズフィルタ(位相分割部)などを用いておよそ90度位相の異なるIQローカル信号を生成することもある。図16はポリフェーズフィルタを有する直交変調回路の構成を示す図、図17はポリフェーズフィルタを有する直交復調回路の構成を示す図である。図16および図17において、0°/90°分割ポリフェーズフィルタ40は、高周波信号Cを入力とし、90度位相の異なるIQローカル信号である、ローカル信号A、Bを出力する。
一般に、ポリフェーズフィルタなどを用いて90度位相の異なるIQローカル信号を生成する場合、そのフィルタを構成する素子の精度ばらつきなどの理由で時定数が理想値からずれるために、IQローカル信号の位相差が90度からずれてしまう。しかしながら、そのような場合においても、図5および図6に示すようなIQ位相調整回路10を用いることで、位相差90度への補正を実現することが可能となる。
上述した位相調整回路によれば、以下のような位相調整方法が実現されている。すなわち、第1のIローカル信号、および前記第1のIローカル信号と同一の周波数で位相が異なる第1のQローカル信号のうち、一方のローカル信号を増幅する第1のステップと、
前記第1のIローカル信号および前記第1のQローカル信号のうち、他方のローカル信号と前記一方のローカル信号を増幅した信号とを加算もしくは減算し、前記一方のローカル信号が前記第1のIローカル信号であるとき第2のQローカル信号を出力し、前記一方のローカル信号が前記第1のQローカル信号であるとき第2のIローカル信号を出力する第2のステップと、を備えた位相調整方法が実現されている。この方法によれば、直交変復調回路に用いるIQローカル信号の精密な位相調整を、実現することができる。
本発明により、直交変復調回路に用いるIQローカル信号の精密な位相調整を広いローカル周波数範囲で実現することができる。また、半導体集積回路内でIQ位相調整回路を実現する上で、非常に小さい面積規模でIQ位相調整回路を実現することができる。
さらに、分周回路を用いてIQ位相調整回路を構成し、ローカル周波数の2倍の周波数の信号を2分周、またはローカル周波数の4倍の周波数の信号を4分周してIQローカル信号を生成する場合には、より簡便な回路構成によって、IQ位相調整回路を実現することができる。
4 減算器
5 加減算器
10 IQ位相調整回路
11A、11B 主アンプ
12A、12B サブアンプ
20 直交ミキサ
20a、20b ミキサ
30 分周回路
31~34 差動Dラッチ回路
40 ポリフェーズフィルタ
AMP1、AMP2 可変アンプ
AMP3、AMP4 アンプ
VRI1 可変電流源
M12a、M12b トランジスタ
R2a、R2b 抵抗
Claims (13)
- 第1のIローカル信号、および前記第1のIローカル信号と同一の周波数で位相が異なる第1のQローカル信号のうち、一方のローカル信号が入力される第1の増幅部と、
前記第1のIローカル信号および前記第1のQローカル信号のうち、他方のローカル信号と前記第1の増幅部からの出力信号とを加算もしくは減算し、前記一方のローカル信号が前記第1のIローカル信号であるとき第2のQローカル信号を出力し、前記一方のローカル信号が前記第1のQローカル信号であるとき第2のIローカル信号を出力する第1の加減算部と、
を備えることを特徴とする位相調整回路。 - 前記他方のローカル信号が入力される第2の増幅部と、
前記一方のローカル信号と前記第2の増幅部からの出力信号とを加算もしくは減算し、前記一方のローカル信号が前記第1のIローカル信号であるとき第2のIローカル信号を出力し、前記一方のローカル信号が前記第1のQローカル信号であるとき第2のQローカル信号を出力する第2の加減算部と、
を更に備えることを特徴とする請求項1に記載の位相調整回路。 - 前記第1の増幅部及び前記第2の増幅部は、それぞれの利得が変化可能であることを特徴とする請求項1または請求項2に記載の位相調整回路。
- 前記第1の増幅部及び前記第2の増幅部は、それぞれの利得が固定であることを特徴とする請求項1または請求項2に記載の位相調整回路。
- 前記第1の増幅部及び前記第2の増幅部は、バイアス電流を変化させることにより、それぞれの利得が調整されることを特徴とする請求項1から請求項4のいずれか1項に記載の位相調整回路。
- 前記第1の増幅部及び前記第2の増幅部には、それぞれロード抵抗が接続されており、前記ロード抵抗それぞれに前記バイアス電流が供給されることを特徴とする請求項5に記載の位相調整回路。
- 前記第1のIローカル信号と前記第1のQローカル信号との位相差が90度からずれた誤差である位相誤差の値の正負に応じて、前記第1の増幅部及び前記第2の増幅部の一方の利得が零に設定されることを特徴とする請求項2に記載の位相調整回路。
- 前記第1の加減算部及び前記第2の加減算部は、一方が加算を行い、他方が減算を行うことを特徴とする請求項2から請求項7のいずれか1項に記載の位相調整回路。
- 前記第2の加減算部には、第3の増幅部を介して、前記一方のローカル信号が入力され、
前記第1の加減算部には、第4の増幅部を介して、前記他方のローカル信号が入力されることを特徴とする請求項2に記載の位相調整回路。 - 前記第1の加減算部は、前記第1の増幅部の出力と前記第4の増幅部の出力との結線によって実現され、
前記第2の加減算部は、前記第2の増幅部の出力と前記第3の増幅部の出力との結線によって実現されることを特徴とする請求項9に記載の位相調整回路。 - 前記第1のIローカル信号及び前記第1のQローカル信号を生成するローカル信号生成部を更に備え、前記ローカル信号生成部は、第5のローカル信号を入力し所定の分周比で分周して前記第1のIローカル信号及び前記第1のQローカル信号を生成する分周部を有することを特徴とする請求項1から請求項10のいずれか1項に記載の位相調整回路。
- 前記第1のIローカル信号及び前記第1のQローカル信号を生成するローカル信号生成部を更に備え、前記ローカル信号生成部は、第5のローカル信号を入力し位相をシフトさせて前記第1のIローカル信号及び前記第1のQローカル信号を生成する位相分割部を有することを特徴とする請求項1から請求項10のいずれか1項に記載の位相調整回路。
- 第1のIローカル信号、および前記第1のIローカル信号と同一の周波数で位相が異なる第1のQローカル信号のうち、一方のローカル信号を増幅する第1のステップと、
前記第1のIローカル信号および前記第1のQローカル信号のうち、他方のローカル信号と前記一方のローカル信号を増幅した信号とを加算もしくは減算し、前記一方のローカル信号が前記第1のIローカル信号であるとき第2のQローカル信号を出力し、前記一方のローカル信号が前記第1のQローカル信号であるとき第2のIローカル信号を出力する第2のステップと、
を備えることを特徴とする位相調整方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201180003591.2A CN102484633B (zh) | 2010-03-29 | 2011-03-28 | 相位调整电路、相位调整方法 |
EP11762227.4A EP2555483A4 (en) | 2010-03-29 | 2011-03-28 | Phase adjustment circuit and phase adjustment method |
JP2012508080A JP5216162B2 (ja) | 2010-03-29 | 2011-03-28 | 位相調整回路、位相調整方法 |
US13/518,031 US8942621B2 (en) | 2010-03-29 | 2011-03-28 | Phase adjustment circuit and phase adjustment method |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010075414 | 2010-03-29 | ||
JP2010-075414 | 2010-03-29 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2011121979A1 true WO2011121979A1 (ja) | 2011-10-06 |
Family
ID=44711742
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2011/001827 WO2011121979A1 (ja) | 2010-03-29 | 2011-03-28 | 位相調整回路、位相調整方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US8942621B2 (ja) |
EP (1) | EP2555483A4 (ja) |
JP (1) | JP5216162B2 (ja) |
CN (1) | CN102484633B (ja) |
WO (1) | WO2011121979A1 (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9614664B2 (en) | 2015-05-25 | 2017-04-04 | Panasonic Intellectual Property Management Co., Ltd. | Wireless communication apparatus and method |
JP2019161651A (ja) * | 2018-03-15 | 2019-09-19 | 三星ディスプレイ株式會社Samsung Display Co.,Ltd. | 直交位相クロック生成回路および方法 |
US10998627B2 (en) | 2017-10-23 | 2021-05-04 | Nec Corporation | Phase adjustment circuit and array antenna device |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5890852B2 (ja) * | 2014-01-29 | 2016-03-22 | アンリツ株式会社 | 移動体端末試験装置および試験方法 |
US9685931B2 (en) | 2014-08-28 | 2017-06-20 | Qualcomm Incorporated | High accuracy millimeter wave/radio frequency wideband in-phase and quadrature generation |
US9438463B2 (en) * | 2014-09-25 | 2016-09-06 | Stmicroelectronics S.R.L. | System for the correction of amplitude and phase errors of in-quadrature signals, corresponding receiver and method |
US9729378B1 (en) * | 2015-04-13 | 2017-08-08 | The United States Of America As Represented By The Secretary Of The Navy | Receiver architecture for constant envelope OFDM |
WO2019008743A1 (ja) * | 2017-07-07 | 2019-01-10 | 株式会社島津製作所 | 電気伝導度検出器及び位相調整値を求めるための方法 |
CN107883589A (zh) * | 2017-12-29 | 2018-04-06 | 广州帝胜智能科技有限公司 | 一种快热式热水器出厂校正的调试*** |
CN109039467A (zh) * | 2018-06-26 | 2018-12-18 | 天津师范大学 | 基于iq调制器的准恒包络光ofdm信号调制解调***及其调制解调方法 |
US10965331B2 (en) * | 2019-04-22 | 2021-03-30 | Semiconductor Components Industries, Llc | Broad range voltage-controlled oscillator |
CN115765722B (zh) * | 2022-12-26 | 2023-04-14 | 深圳市华普微电子股份有限公司 | 一种正交六分频电路 |
Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04275746A (ja) * | 1991-03-01 | 1992-10-01 | Toshiba Corp | 直交変調器 |
JPH05130156A (ja) * | 1991-11-08 | 1993-05-25 | Nec Corp | 直交変調器 |
JPH07303028A (ja) * | 1994-05-09 | 1995-11-14 | Hitachi Ltd | 90度移相回路 |
JPH1117757A (ja) * | 1997-06-26 | 1999-01-22 | Nec Ic Microcomput Syst Ltd | 90度移相回路 |
JPH1198212A (ja) * | 1997-09-19 | 1999-04-09 | Yokogawa Electric Corp | 直交変調器 |
JPH11284490A (ja) * | 1998-03-31 | 1999-10-15 | Texas Instr Japan Ltd | 位相変換回路 |
JP2002535924A (ja) * | 1999-01-19 | 2002-10-22 | インターデイジタル テクノロジー コーポレーション | 位相偏移変調受信装置における振幅および位相の不平衡の補正 |
JP2003218649A (ja) * | 2002-01-28 | 2003-07-31 | Hitachi Ltd | 通信用半導体集積回路および無線通信装置 |
JP2004222259A (ja) * | 2002-12-24 | 2004-08-05 | Hitachi Kokusai Electric Inc | 送信機の負帰還増幅器、送信機、及び負帰還増幅器の誤差補正方法 |
JP2005252931A (ja) * | 2004-03-08 | 2005-09-15 | Matsushita Electric Ind Co Ltd | 直交変調器 |
JP2005252861A (ja) * | 2004-03-05 | 2005-09-15 | Toshiba Corp | 複数の無線システムに対応可能な無線通信装置 |
JP2008022243A (ja) * | 2006-07-12 | 2008-01-31 | Toshiba Corp | 通信装置、直交誤差補償の設定値算出方法および直交誤差補償プログラム |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3660764A (en) * | 1969-11-26 | 1972-05-02 | Bell Telephone Labor Inc | Non-coherent differential phase detection |
JPH06283966A (ja) * | 1993-03-30 | 1994-10-07 | Toshiba Corp | π/2位相制御回路 |
US5406629A (en) * | 1993-12-20 | 1995-04-11 | Motorola, Inc. | Apparatus and method for digitally processing signals in a radio frequency communication system |
JPH09153741A (ja) * | 1995-09-13 | 1997-06-10 | Fujitsu Ltd | 変調器、間接変調型変調器、及び周波数逓倍器 |
JP3561184B2 (ja) | 1998-09-03 | 2004-09-02 | テクトロニクス・インターナショナル・セールス・ゲーエムベーハー | Iqスプリッタ装置 |
DE19946669C2 (de) * | 1999-09-29 | 2001-09-27 | Rohde & Schwarz | Verfahren zum Einstellen eines Phasenwinkels eines Phasenschiebers einer Sendeeinrichtung |
US6674998B2 (en) * | 2000-10-02 | 2004-01-06 | Intersil Americas Inc. | System and method for detecting and correcting phase error between differential signals |
US7133649B2 (en) | 2002-12-24 | 2006-11-07 | Hitachi Kokusai Electric, Inc. | Negative feedback amplifier for transmitter, transmitter, and method of correcting error in the negative feedback amplifier |
JP3926324B2 (ja) | 2003-12-19 | 2007-06-06 | 埼玉日本電気株式会社 | ディジタル変調回路 |
JP4246166B2 (ja) * | 2004-03-04 | 2009-04-02 | パナソニック株式会社 | 分周回路及びそれを用いたマルチモード無線機 |
EP1594221A1 (en) * | 2004-05-05 | 2005-11-09 | Deutsche Thomson-Brandt Gmbh | Single conversion tuner |
CN1835489B (zh) * | 2005-03-16 | 2010-04-21 | 联发科技股份有限公司 | 一种可补偿同相/正交相不平衡的装置及其方法 |
JP2008544619A (ja) | 2005-06-13 | 2008-12-04 | エヌエックスピー ビー ヴィ | 高い直線性を有する直交発振器 |
JP2007104007A (ja) | 2005-09-30 | 2007-04-19 | Toshiba Corp | 直交変調器及び直交変調器におけるベクトル補正方法 |
TWI311855B (en) * | 2006-04-17 | 2009-07-01 | Via Tech Inc | Harmonic-rejection modulating devices and methods |
JP4830898B2 (ja) | 2007-02-20 | 2011-12-07 | パナソニック電工株式会社 | ダイレクトコンバージョン方式の無線送受信装置 |
KR100847801B1 (ko) * | 2007-02-21 | 2008-07-23 | 지씨티 세미컨덕터 인코포레이티드 | Iq 불일치 측정 장치 및 방법 |
CN101316112A (zh) | 2007-05-28 | 2008-12-03 | 安国国际科技股份有限公司 | 应用于跳频***的频率合成器 |
-
2011
- 2011-03-28 CN CN201180003591.2A patent/CN102484633B/zh active Active
- 2011-03-28 US US13/518,031 patent/US8942621B2/en active Active
- 2011-03-28 JP JP2012508080A patent/JP5216162B2/ja active Active
- 2011-03-28 EP EP11762227.4A patent/EP2555483A4/en not_active Withdrawn
- 2011-03-28 WO PCT/JP2011/001827 patent/WO2011121979A1/ja active Application Filing
Patent Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04275746A (ja) * | 1991-03-01 | 1992-10-01 | Toshiba Corp | 直交変調器 |
JPH05130156A (ja) * | 1991-11-08 | 1993-05-25 | Nec Corp | 直交変調器 |
JPH07303028A (ja) * | 1994-05-09 | 1995-11-14 | Hitachi Ltd | 90度移相回路 |
JPH1117757A (ja) * | 1997-06-26 | 1999-01-22 | Nec Ic Microcomput Syst Ltd | 90度移相回路 |
JPH1198212A (ja) * | 1997-09-19 | 1999-04-09 | Yokogawa Electric Corp | 直交変調器 |
JPH11284490A (ja) * | 1998-03-31 | 1999-10-15 | Texas Instr Japan Ltd | 位相変換回路 |
JP2002535924A (ja) * | 1999-01-19 | 2002-10-22 | インターデイジタル テクノロジー コーポレーション | 位相偏移変調受信装置における振幅および位相の不平衡の補正 |
JP2003218649A (ja) * | 2002-01-28 | 2003-07-31 | Hitachi Ltd | 通信用半導体集積回路および無線通信装置 |
JP2004222259A (ja) * | 2002-12-24 | 2004-08-05 | Hitachi Kokusai Electric Inc | 送信機の負帰還増幅器、送信機、及び負帰還増幅器の誤差補正方法 |
JP2005252861A (ja) * | 2004-03-05 | 2005-09-15 | Toshiba Corp | 複数の無線システムに対応可能な無線通信装置 |
JP2005252931A (ja) * | 2004-03-08 | 2005-09-15 | Matsushita Electric Ind Co Ltd | 直交変調器 |
JP2008022243A (ja) * | 2006-07-12 | 2008-01-31 | Toshiba Corp | 通信装置、直交誤差補償の設定値算出方法および直交誤差補償プログラム |
Non-Patent Citations (1)
Title |
---|
See also references of EP2555483A4 * |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9614664B2 (en) | 2015-05-25 | 2017-04-04 | Panasonic Intellectual Property Management Co., Ltd. | Wireless communication apparatus and method |
US10998627B2 (en) | 2017-10-23 | 2021-05-04 | Nec Corporation | Phase adjustment circuit and array antenna device |
JP2019161651A (ja) * | 2018-03-15 | 2019-09-19 | 三星ディスプレイ株式會社Samsung Display Co.,Ltd. | 直交位相クロック生成回路および方法 |
Also Published As
Publication number | Publication date |
---|---|
JPWO2011121979A1 (ja) | 2013-07-04 |
US20120256673A1 (en) | 2012-10-11 |
JP5216162B2 (ja) | 2013-06-19 |
EP2555483A4 (en) | 2017-06-28 |
US8942621B2 (en) | 2015-01-27 |
CN102484633A (zh) | 2012-05-30 |
CN102484633B (zh) | 2014-11-26 |
EP2555483A1 (en) | 2013-02-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5216162B2 (ja) | 位相調整回路、位相調整方法 | |
JP4616093B2 (ja) | Rf受信器ミスマッチ校正システム及び方法 | |
US9749172B2 (en) | Calibration method and calibration apparatus for calibrating mismatch between first signal path and second signal path of transmitter/receiver | |
EP1829202B1 (en) | Direct conversion device with compensation means for a transmission path of a wireless communication equipment | |
US9344302B2 (en) | Loopback technique for IQ imbalance estimation for calibration in OFDM systems | |
US20070026821A1 (en) | Systems and methods of RF power transmission, modulation, and amplification, including Multiple Input Single Output (MISO) amplifiers | |
US7023292B2 (en) | Polar modulation using amplitude modulated quadrature signals | |
US8112047B2 (en) | Configurable RF transmitter | |
JPWO2006051776A1 (ja) | 増幅回路、無線通信回路、無線基地局装置、および無線端末装置 | |
WO2006101094A1 (ja) | 送信装置、通信機器、及び移動無線機 | |
WO2005039043A1 (ja) | 増幅回路 | |
US7545856B2 (en) | Current mode phase shifter, mixer and amplifier | |
JP5151785B2 (ja) | 送信機及び送受信装置 | |
US20050152471A1 (en) | Transmitting device | |
JP2007104007A (ja) | 直交変調器及び直交変調器におけるベクトル補正方法 | |
JP2006135422A (ja) | 送信回路 | |
Oveisi et al. | A study of a millimeter-wave transmitter architecture realizing QAM directly in RF domain | |
Shabardin et al. | The development of quadrature modulators and demodulators 1800 MHz–6 GHz with digital correction of parameters | |
JP2016220134A (ja) | 無線通信装置および無線通信方法 | |
US7773969B2 (en) | Current converter, frequency mixer, radiofrequency transmission system and method for frequency mixing | |
US7243037B2 (en) | Signal processing device, use of the signal processing device and method for signal processing | |
WO2011004737A1 (ja) | 直交ミキサ | |
Gueorguiev et al. | A 5.2 GHz CMOS I/Q modulator with integrated phase shifter for beamforming | |
WO2024028679A1 (en) | Method, device and apparatus for generating in-phase (i) and quadrature-phase (q) local oscillator signals | |
JPH08340363A (ja) | 変調回路 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 201180003591.2 Country of ref document: CN |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2012508080 Country of ref document: JP |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 11762227 Country of ref document: EP Kind code of ref document: A1 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2011762227 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 13518031 Country of ref document: US |
|
NENP | Non-entry into the national phase |
Ref country code: DE |