WO2009078215A1 - 半導体装置の製造方法及び半導体装置 - Google Patents

半導体装置の製造方法及び半導体装置 Download PDF

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Publication number
WO2009078215A1
WO2009078215A1 PCT/JP2008/068596 JP2008068596W WO2009078215A1 WO 2009078215 A1 WO2009078215 A1 WO 2009078215A1 JP 2008068596 W JP2008068596 W JP 2008068596W WO 2009078215 A1 WO2009078215 A1 WO 2009078215A1
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WO
WIPO (PCT)
Prior art keywords
film
semiconductor device
substrate
semiconductor
insulating
Prior art date
Application number
PCT/JP2008/068596
Other languages
English (en)
French (fr)
Inventor
Michiko Takei
Yutaka Takafuji
Yasumori Fukushima
Kazuhide Tomiyasu
Steven Roy Droes
Original Assignee
Sharp Kabushiki Kaisha
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Kabushiki Kaisha filed Critical Sharp Kabushiki Kaisha
Priority to US12/741,852 priority Critical patent/US8288184B2/en
Priority to CN2008801135899A priority patent/CN101842871B/zh
Publication of WO2009078215A1 publication Critical patent/WO2009078215A1/ja

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H01L27/1266—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本発明は、半導体基板に形成される半導体チップの表面平坦性を向上させ、表面に絶縁性を有する基板上に移動させた半導体チップの電気的特性のばらつきを抑制し、更に製造歩留りを改善することができる半導体装置の製造方法を提供する。本発明の半導体装置の製造方法は、表面に絶縁性を有する基板上に、導電パターン膜を含む半導体チップが配置された半導体装置の製造方法であって、上記製造方法は、半導体基板上、及び、半導体基板上の導電パターン膜上に第一絶縁膜を形成し、第一絶縁膜をパターニングして導電パターン膜と重畳する領域の第一絶縁膜を除去することで、平坦な第一絶縁パターン膜を形成する工程と、第二絶縁膜を形成し、上記第二絶縁膜を研磨することで平坦化膜を形成する工程と、上記平坦化膜を介して半導体基板に剥離用物質を注入し剥離層を形成する工程と、上記半導体チップを半導体基板とは反対側から上記表面に絶縁性を有する基板に転写する工程と、該半導体チップを剥離層に沿って分離する工程とをこの順に含む半導体装置の製造方法、及び、上記製造方法によって作製された半導体装置である。
PCT/JP2008/068596 2007-12-18 2008-10-14 半導体装置の製造方法及び半導体装置 WO2009078215A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US12/741,852 US8288184B2 (en) 2007-12-18 2008-10-14 Production method of semiconductor device and semiconductor device
CN2008801135899A CN101842871B (zh) 2007-12-18 2008-10-14 半导体装置的制造方法以及半导体装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007326420 2007-12-18
JP2007-326420 2007-12-18

Publications (1)

Publication Number Publication Date
WO2009078215A1 true WO2009078215A1 (ja) 2009-06-25

Family

ID=40795334

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/068596 WO2009078215A1 (ja) 2007-12-18 2008-10-14 半導体装置の製造方法及び半導体装置

Country Status (3)

Country Link
US (1) US8288184B2 (ja)
CN (1) CN101842871B (ja)
WO (1) WO2009078215A1 (ja)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103377911B (zh) 2012-04-16 2016-09-21 中国科学院微电子研究所 提高化学机械平坦化工艺均匀性的方法
JP5939184B2 (ja) * 2013-03-22 2016-06-22 ソニー株式会社 半導体装置の製造方法
KR102647695B1 (ko) 2016-08-12 2024-03-14 삼성디스플레이 주식회사 트랜지스터 표시판 및 그 제조 방법
KR101939462B1 (ko) * 2017-05-19 2019-01-16 경희대학교 산학협력단 스트레처블 전자 소자 및 그의 제조 방법
JP6525046B1 (ja) * 2017-12-19 2019-06-05 株式会社Sumco 半導体ウェーハの製造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08288295A (ja) * 1995-04-18 1996-11-01 Sony Corp 半導体装置の製造方法
JP2000340567A (ja) * 1999-05-31 2000-12-08 Seiko Epson Corp 基板平坦化方法、電気光学装置の製造方法及び半導体装置の製造方法
JP2003163194A (ja) * 2001-11-28 2003-06-06 Semiconductor Energy Lab Co Ltd 研磨方法及び半導体装置の作製方法
JP2005039244A (ja) * 2003-06-27 2005-02-10 Hitachi Ltd 電子デバイスとその多層配線の形成方法
JP2006066591A (ja) * 2004-08-26 2006-03-09 Sharp Corp 半導体装置の製造方法、及び半導体装置

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DE69232432T2 (de) * 1991-11-20 2002-07-18 Canon Kk Verfahren zur Herstellung einer Halbleiteranordnung
CN1132223C (zh) * 1995-10-06 2003-12-24 佳能株式会社 半导体衬底及其制造方法
US5807783A (en) * 1996-10-07 1998-09-15 Harris Corporation Surface mount die by handle replacement
JPH11186186A (ja) 1997-12-18 1999-07-09 Denso Corp 半導体基板の製造方法
US6191007B1 (en) * 1997-04-28 2001-02-20 Denso Corporation Method for manufacturing a semiconductor substrate
US7081417B2 (en) * 2003-06-27 2006-07-25 Hitachi, Ltd. Manufacturing method for electronic device and multiple layer circuits thereof
JP4943663B2 (ja) 2005-04-06 2012-05-30 シャープ株式会社 半導体装置の製造方法及び半導体装置並びに液晶表示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08288295A (ja) * 1995-04-18 1996-11-01 Sony Corp 半導体装置の製造方法
JP2000340567A (ja) * 1999-05-31 2000-12-08 Seiko Epson Corp 基板平坦化方法、電気光学装置の製造方法及び半導体装置の製造方法
JP2003163194A (ja) * 2001-11-28 2003-06-06 Semiconductor Energy Lab Co Ltd 研磨方法及び半導体装置の作製方法
JP2005039244A (ja) * 2003-06-27 2005-02-10 Hitachi Ltd 電子デバイスとその多層配線の形成方法
JP2006066591A (ja) * 2004-08-26 2006-03-09 Sharp Corp 半導体装置の製造方法、及び半導体装置

Also Published As

Publication number Publication date
CN101842871A (zh) 2010-09-22
US8288184B2 (en) 2012-10-16
CN101842871B (zh) 2013-01-09
US20100270618A1 (en) 2010-10-28

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