WO2008108383A1 - グラフェンを用いる半導体装置及びその製造方法 - Google Patents
グラフェンを用いる半導体装置及びその製造方法 Download PDFInfo
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- WO2008108383A1 WO2008108383A1 PCT/JP2008/053899 JP2008053899W WO2008108383A1 WO 2008108383 A1 WO2008108383 A1 WO 2008108383A1 JP 2008053899 W JP2008053899 W JP 2008053899W WO 2008108383 A1 WO2008108383 A1 WO 2008108383A1
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- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 title claims abstract description 168
- 229910021389 graphene Inorganic materials 0.000 title claims abstract description 145
- 239000004065 semiconductor Substances 0.000 title claims abstract description 142
- 238000000034 method Methods 0.000 title claims description 50
- 229910052751 metal Inorganic materials 0.000 claims abstract description 49
- 239000002184 metal Substances 0.000 claims abstract description 49
- 108091006146 Channels Proteins 0.000 claims description 73
- 238000004519 manufacturing process Methods 0.000 claims description 48
- 108090000699 N-Type Calcium Channels Proteins 0.000 claims description 34
- 102000004129 N-Type Calcium Channels Human genes 0.000 claims description 34
- 108010075750 P-Type Calcium Channels Proteins 0.000 claims description 31
- 239000000758 substrate Substances 0.000 claims description 31
- 230000005669 field effect Effects 0.000 claims description 26
- 230000008569 process Effects 0.000 claims description 18
- 229910002804 graphite Inorganic materials 0.000 claims description 17
- 239000010439 graphite Substances 0.000 claims description 17
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 10
- 229910052799 carbon Inorganic materials 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 8
- 238000001459 lithography Methods 0.000 claims description 8
- 238000006467 substitution reaction Methods 0.000 claims description 8
- 230000006870 function Effects 0.000 claims description 7
- 238000012545 processing Methods 0.000 claims description 7
- 239000000470 constituent Substances 0.000 claims description 6
- 230000001747 exhibiting effect Effects 0.000 claims description 6
- 238000006722 reduction reaction Methods 0.000 claims description 6
- 238000012546 transfer Methods 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 5
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052787 antimony Inorganic materials 0.000 claims description 5
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 5
- 229910052785 arsenic Inorganic materials 0.000 claims description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 5
- 229910052796 boron Inorganic materials 0.000 claims description 5
- 229910052733 gallium Inorganic materials 0.000 claims description 5
- 229910052738 indium Inorganic materials 0.000 claims description 5
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 5
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 229910052698 phosphorus Inorganic materials 0.000 claims description 5
- 239000011574 phosphorus Substances 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000005979 thermal decomposition reaction Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 32
- 230000000295 complement effect Effects 0.000 description 30
- 238000010586 diagram Methods 0.000 description 23
- 239000000463 material Substances 0.000 description 17
- 239000002356 single layer Substances 0.000 description 11
- 230000005684 electric field Effects 0.000 description 10
- 230000005476 size effect Effects 0.000 description 10
- 230000010355 oscillation Effects 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 230000008901 benefit Effects 0.000 description 7
- 239000002772 conduction electron Substances 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 239000002041 carbon nanotube Substances 0.000 description 4
- 229910021393 carbon nanotube Inorganic materials 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- 239000002390 adhesive tape Substances 0.000 description 2
- 239000012298 atmosphere Substances 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000004299 exfoliation Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 208000019901 Anxiety disease Diseases 0.000 description 1
- 230000005355 Hall effect Effects 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000002547 anomalous effect Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 125000004432 carbon atom Chemical group C* 0.000 description 1
- CREMABGTGYGIQB-UHFFFAOYSA-N carbon carbon Chemical compound C.C CREMABGTGYGIQB-UHFFFAOYSA-N 0.000 description 1
- 239000011203 carbon fibre reinforced carbon Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000005685 electric field effect Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- OYFJQPXVCSSHAI-QFPUQLAESA-N enalapril maleate Chemical compound OC(=O)\C=C/C(O)=O.C([C@@H](C(=O)OCC)N[C@@H](C)C(=O)N1[C@@H](CCC1)C(O)=O)CC1=CC=CC=C1 OYFJQPXVCSSHAI-QFPUQLAESA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 238000000197 pyrolysis Methods 0.000 description 1
- 238000010791 quenching Methods 0.000 description 1
- 230000000171 quenching effect Effects 0.000 description 1
- 230000035484 reaction time Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000002791 soaking Methods 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/8213—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using SiC technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8221—Three dimensional integrated circuits stacked in different levels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H—ELECTRICITY
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- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
- H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1606—Graphene
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7781—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
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- H10B—ELECTRONIC MEMORY DEVICES
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/70—Nanostructure
- Y10S977/755—Nanosheet or quantum barrier/well, i.e. layer structure having one dimension or thickness of 100 nm or less
Definitions
- the present invention relates to a semiconductor device and a manufacturing method thereof, and in particular, a P-type capable of operating at high speed with low power consumption, in which element elements such as channels, gates, sources, drain electrodes, and wiring are all composed of graphene. Or a field effect transistor having an n-type channel, and
- Semiconductor devices such as logic circuits and memory element circuits, and their manufacturing methods
- CMOS complementary metal oxide semiconductor
- silicon semiconductor industry has achieved miniaturization by continuously reducing the application range of microfabrication technologies such as lithography technology, etching technology, and film formation technology from micrometers to several tens of nanometers, resulting in higher integration. High performance has been achieved at the same time.
- device dimensions will inevitably reach the atomic and molecular level, and physical limitations of semiconductor materials such as silicon and existing device structures are pointed out.
- Darafen is a stable monoatomic planar material obtained by extracting only one layer of graphite, which is a layered material composed only of sp 2 hybridized carbon.
- graphene may include one that has two or more force layers indicating one graphite layer.
- the size of the graphene plane can be assumed to vary from a molecular size with a piece length of nanometer order to theoretically infinite.
- the graphene is derived from this honeycomb structure, and has a three-fold symmetry axis in the plane. Therefore, if the graph is rotated 120 degrees in the plane around a certain point, it overlaps the original structure.
- the graphon has two characteristic end structures, one on the armchair end and the other on the zigzag end. Since the graphene plane is symmetrical three times, the armchair direction and zigzag direction appear at every 120 rotations in the plane, and they are orthogonal to each other.
- Non-Patent Document 2 A method for producing graphene having a size of sub-micrometer order with an atomic force microscope (AFM) is disclosed in Japanese Patent No. 2541091 (page 6-8, Fig. 3-10) (Patent Document 1) USP No. 5,925,465 (July 20, 1999), Sheet 2 to 8, Fig.3 to 8.
- Patent Document 1 USP No. 5,925,465 (July 20, 1999), Sheet 2 to 8, Fig.3 to 8.
- STM scanning tunneling microscope
- Patent Document 2 For sub-micrometer geometry holes with characteristic end structures due to heating of darafen, see, for example, Journal of Materials Research, 16 (5) 12, 12 87–1292, 2001 (Journal of Materials Research, 16 (5), 1287- 1292, 2001) (non-patent document 3).
- Japanese Patent No. 3447492 (column 7, line 43 to column 10, line 30, Fig. 3-11) shows a method for obtaining a graph piece having a geometric shape by arranging such holes regularly.
- Patent Document 2 USP No. 6,540,972 B1 (A pril 1, 2003), Line 16 in Column 5 to Line 19 in Column 9, disclosed in Fig. 3 to 11. It has been done.
- Non-Patent Document 4 the field effect of semi-metallic graphene is reported in Science Journal, 306, 666-669, 2004 ⁇ (Science, March 06, 666-669, 2004) (Non-Patent Document 4).
- metal graphene pieces acting as channels are arranged on a highly doped silicon substrate through silicon oxide, and are connected to two gold electrodes at both ends of the metal graphene pieces.
- a source-drain electrode is provided, and a field effect transistor having a high-dop silicon as a back gate electrode is formed.
- Semi-metallic darafen pieces can be obtained by cutting darafen from a highly oriented pyrolytic graphite (HO PG) surface using standard lithography and etching.
- the graphene channel of this device is at least 80 nanometers in width and is the same metal as in the macro bulk state, and the quantum size effect derived from the edge structure does not appear.
- the electric field effect occurs in the graphene metal that is not in the semiconductor.
- the electric field due to the gate electrode that is extremely thin in the thickness direction from one to several layers of metal daraphene exceeds the shielding by carriers in the darafen channel. Because it is possible.
- Non-Patent Document 4 A report using a metal daraphene element with almost the same structure as Non-Patent Document 4 includes Nichiya, pp. 28, 197-200, 2005 (Nature, 428, 197-200, 2005) (Non-Patent Document 5) ), Nichiya, 428, 201-204, 2005 (Nature, 428, 201-204, 2005) (Non-patent Document 6).
- Non-Patent Documents 5 and 6 measurements such as massless electrons and anomalous integer quantum Hall effects not found in ordinary metals have been made. In recent years, relativistic quantum mechanical effects have been reported, which greatly contributes to the deepening of human wisdom and the development of science.
- Non-Patent Documents 4, 5, and 6 the graphene is only used for the channel, and there is a drawback that the contact resistance between the channel and the electrode is large. This is due to the use of metal such as gold for the source and drain electrodes and the gate electrode. The reason is that if a device that takes advantage of the characteristics of semiconductor graphene and metal darafen is constructed, the viewpoint will be lost.
- Non-Patent Document 7 there is a problem that a field effect transistor that uses dalafen for the source and drain electrodes and gate electrode in addition to the channel is only shown in its structure, and does not operate as an actual device. It is. This is because the graphene width of the channel is as large as lOOntn. The reason for this is that the darafen used is not so small that the quantum size effect appears remarkably, and that the edge structure defining the electronic properties of Grafyun is controlled.
- the field effect transistor has a problem of high manufacturing cost. This is due to the fact that other materials are used for the electrode material and wiring besides the graphene of the channel. The reason for this is that the use of graphene for electrodes and wiring has adopted a technique that unifies the types of materials and reduces the number of manufacturing processes.
- the first object of the present invention is to use a dalaphen having a width of 20 nm or less and a controlled end structure, in which the quantum size effect is remarkable, so that it can be compared in a two-dimensional plane.
- the second object of the present invention is to reduce the material cost by unifying all the components of the semiconductor device such as channels, electrodes, and wiring with graphene, and to manufacture without using materials other than graphene as much as possible.
- the object is to provide a semiconductor device and a method for manufacturing the semiconductor device in which the manufacturing cost is reduced by simplifying the process.
- a channel layer made of semiconductor graphene, a source electrode, a drain electrode, and a gate electrode layer also serving as wiring made of metal graphene, and a gate insulating layer that insulates the channel layer from the gate electrode layer are provided.
- a semiconductor device using a field effect characterized in that the channel layer and each electrode layer are in the same plane can be obtained.
- the step of producing darafen on the substrate, the step of processing graphene into a desired element structure by lithography and etching, and the end structure of dalafen by an oxidation reaction or a reduction reaction, a zigzag edge is formed.
- a method of manufacturing a semiconductor device which includes a step of processing an armchair end, a step of doping semiconductor graphene, and a step of forming an insulating film.
- the invention's effect by using dalaphen having a width of 20 nm or less in which the quantum size effect becomes remarkable and at the same time, the end structure is controlled, it is compactly integrated in a two-dimensional plane, and the speed is increased.
- a semiconductor device with reduced power consumption and a method for manufacturing the semiconductor device can be provided.
- FIG. 1 is a diagram showing an example of an all-graphene basic element of the present invention.
- FIG. 2A is a diagram showing the transport characteristics of the all-darafen basic element of the present invention, and is a case of a field effect transistor having a multilayer graphon with several graphene layers as a channel in bulk size.
- FIG. 2B is a diagram showing the transport characteristics of all graphene basic elements of the present invention, in the case of a field effect transistor having a bulk single-layer darafen having a width of lOOnm or more as a channel.
- FIG. 2C is a diagram showing the transport characteristics of the all-graphene basic element of the present invention, which is a case of a field effect transistor having a single layer graphene as a channel with a width of 20 to 100 nm and a quantum size effect starting to appear.
- FIG. 2D is a diagram showing the transport characteristics of the all-graphene basic element of the present invention, and a field effect transistor having a single-layer graphon with a quantum size of 20 nm or less and an end structure controlled to an armchair edge as a channel. This is the case.
- FIG. 2E is a diagram showing the transport characteristics of the all-graphene basic element of the present invention, and is a case of a field effect transistor having p-type doped single layer graphene as a channel in the case of FIG. 2D.
- FIG. 2F is a diagram showing the transport characteristics of all graphene basic elements of the present invention.
- FIG. 2D it is a case of a field effect transistor having n-type doped single layer graphene as a channel.
- FIG. 3A to FIG. 3H are process diagrams showing a processing method of the HOPG surface in the manufacturing method of the all graphene element according to the embodiment of the present invention.
- FIG. 4A to FIG. 4F are process diagrams showing a method for producing graphene pieces in the method for producing all graphene elements according to the embodiment of the present invention.
- FIG. 5A to FIG. 5D are process diagrams showing a method for manufacturing the all-darafen element according to the embodiment of the present invention.
- FIG. 6 is a diagram showing a double-gate all-darafen element according to Example 1 of the present invention.
- FIG. 7A is a diagram showing an all-graphene complementary inverter according to Example 2 of the present invention, in which a p-type channel and an n-type channel are controlled by two independent gate electrodes.
- FIG. 7B is a diagram showing an all-graphene complementary inverter according to Example 2 of the present invention, in which the p-type and n-type channels are collinear, and both channels are controlled by a single gate electrode.
- FIG. 7C is a diagram showing an all-darafen complementary inverter according to Example 2 of the present invention, in which the p-type and n-type channels are parallel, and both channels are controlled by one gate electrode.
- 8A to 8C are diagrams showing all-darafen NOR gates according to Embodiment 3 of the present invention.
- 9A to 9C are diagrams showing an all-graphene NAND gate according to Embodiment 4 of the present invention.
- 10A to 10B are diagrams showing a ring oscillation circuit according to Embodiment 5 of the present invention.
- FIG. 11 is a diagram showing an all graph N AND gate having a flip-flop circuit according to Embodiment 6 of the present invention.
- FIG. 12 shows the structure of graphene. Best Mode for Carrying Out the Invention:
- Graphene is a quasi-two-dimensional material composed of one to several monolayer graphites. Graphene is an ideal two-dimensional gas system. In the case of single-layer dalafen, its mobility is almost independent of temperature and is about lO ⁇ n ⁇ V- s— 1. In the case of several layers of multilayer graphon, its mobility is 300K (Kelvin) 1. 5 X 10 4 cm 2 'V- 1 ⁇ s- 1 mm, the 4K 6 X 10 4 cm 2' V- 1 ⁇ s one about one And it has a very large value of several times to ten times or more compared with the mobility of silicon.
- the size of the graphene plane can be assumed to be various sizes, from a molecular size with a piece length of nanometer order to a theoretically infinite size. Expresses completely different electronic properties. This is called the so-called quantum size effect.
- Darafen is a metal similar to normal graphite when it is macroscopic, but when it comes to nanometer size, depending on the edge structure, Properties or properties as a semiconductor with a band gap.
- the zigzag end 27 there are two types of characteristic end structures: one is the zigzag end 27 and the other is the armchair end 26.
- the end structure of the long side is a zigzag shape
- the end structure of the long side is a zigzag shape
- it is metal in the direction and the end structure of the long side is an armchair type
- it is a semiconductor.
- the band gap of the armchair type Darafen ribbon depends on the length of the short side, and the shorter the short side length, the larger the gap tends to be.
- the structure-dependent electronic properties seen in such graphs are reminiscent of carbon nanotubes.
- carbon nanotubes are obtained by wrapping a graph ribbon along the long side and connecting the two long sides to each other, and conversely, a carbon nanotube is cut along the long axis and flattened to make a flat surface. Given this, it is possible to intuitively understand the similarity in electronic properties between darafen ribbons and carbon nanotubes.
- graphene is always a metal when the bulk size is larger than 20 nm, and it is always a metal, and when the quantum size is about 20 nm or less, the edge structure has a zigzag edge. It is a metal. These metal grains can be used as electrodes and wiring materials.
- darafen has a quantum size of 20 nm or less
- the armchair edge is a semiconductor, and this semiconductor darafen can be used as a channel material.
- Darafen exhibits bipolar conduction unless special operations such as doping are performed.
- Bipolar refers to a conduction type in which a carrier is induced, regardless of the polarity of the electric field. Holes are conducted in the positive electric field, and conduction electrons are conducted in the negative electric field. This is due to the fact that there are the same number of holes and conduction electrons in the graphon without electric field. In metal darafen, holes or conduction electrons cannot be completely depleted by electric field action. Therefore, when a transistor is configured with a metal darafen channel, it can be completely turned off. This is not possible and power consumption increases. A way to avoid this problem is to use the semiconductor darafen.
- Darafen is less than 20nm wide and has a finite band gap in the case of darafen at the end of the armchair, so it can be turned off and part of the reduction in power consumption is achieved.
- a complementary inverter with low power consumption cannot be constructed. Therefore, when a logic circuit or a memory element is configured, it is not possible to sufficiently reduce power consumption. In order to avoid this problem, it is necessary to dope semiconductor graphene. For the doping, lattice substitution doping or charge transfer doping can be used.
- the Group IV carbon constituting the graphene is changed to an impurity element belonging to Group III such as boron, aluminum, gallium or indium or an impurity element belonging to Group VI such as nitrogen, phosphorus, arsenic or antimony. Replace with. Then, p-type is obtained in the former and n-type graphene semiconductor is obtained in the latter.
- a donor having an appropriate ionization energy and an acceptor having an appropriate electron affinity are arranged on the surface of semiconductor graphene.
- the ionization energy of the donor is smaller than the effective work function of the semiconductor graph, electrons move from the donor to the semiconductor graphene, and conduction electrons are electrostatically induced in the semiconductor graphin. Also, if the electron affinity of the acceptor is greater than the effective work function of semiconductor darafen, the acceptor draws electrons from the semiconductor darafen and holes are electrostatically induced in the semiconductor graphene.
- the ionization energy of the donor should be 6.4 eV or less, and the electron affinity of the acceptor should be 2.3 eV or more.
- a graphene that acts as a p-type semiconductor or an n-type semiconductor can be obtained by doping semiconductor graphene at the armchair edge with a width of 20 nm or less.
- the desired carrier density and gate voltage threshold can be defined.
- Figure 1 is the most basic structure, and is a schematic plan view of an all-darafen field effect transistor.
- the basic element 20 of the all-graph field-effect transistor of the present invention is composed only of graph elements.
- the gate electrode 24 is formed between the source electrode 21 and the drain electrode 22, and the same end facing the source electrode 21 and the drain electrode 22 is connected by the channel 23.
- the long axis end structure of the channel 23 to be connected is At the air end 26 is semiconductor graphing.
- the source electrode 21, the drain electrode 22, and the gate electrode 24 are formed by integrating wirings, and the long-axis end structure is a metal graphene at a zigzag end 27.
- the integration of the source electrode 21, the drain electrode 22, and the gate electrode 24 with the wiring is the second feature of all graphene elements, and has the advantage that the element configuration is greatly simplified.
- each element element is cut out from one graph sheet. Therefore, the Schottky barrier free and the contact resistance free are provided between the electrode and the channel and between the electrode wiring. That is, heat generation due to resistance is suppressed to the limit. Moreover, the mobility of Gurafuwen operate at extremely high speed because also lO ⁇ m ⁇ V- ⁇ s one 1 about a minimum. Furthermore, as described above, p-type and n-type conduction channels can be obtained separately by doping. Therefore, this means that the all-daraphen element shown in the present invention is the ultimate ideal transistor with both p-type and n-type channels.
- Figures 2A to 2F show the transport characteristics (drain current vs. gate voltage characteristics) of all graphene field effect transistors of the present invention.
- Figure 2A is a multilayer graphene with a bulk size and several layers of darafen layers. Balta-sized single-layer graphene with a width of lOOnm or more,
- Fig. 2C is a single-layer graphene with a width of 20-100 nm, and quantum size effects begin to appear, Fig.
- FIG. 2D is a quantum size with a width of 20 nm or less, and the edge structure is controlled to the armchair edge
- Figure 2E shows a p-doped single-layer dalaphen in the case of Figure 2D
- Figure 2F shows a drain current of a gate of a field-effect transistor having an n-type doped single-layer graph as a channel in Figure 2D. The voltage characteristics are shown.
- the metal darafen channel is a low-performance transistor.
- the graphene width size control when applied, it turns off as shown in Fig. 2C and below.
- the force is still large and incomplete.
- the size is small enough.
- the edge structure is controlled, the channel behaves as a complete semiconductor graph.
- the practical use is limited in the case of Fig. 2C and Fig. 2D due to the bipolar conduction channel.
- pn conduction control of the semiconductor graphene channel is performed as shown in Fig. 2E and Fig. 2F, ideal transistor operation is realized as p-type and n-type graphene channels, respectively.
- the latter HOPG exfoliation method has the advantage of being able to prepare uniform and large graphene, and requires a process of transferring the exfoliated darafen to an appropriate substrate.
- the latter HOPG stripping method will be explained in detail.
- a silicon (Si) film 2 is deposited on the clean surface by sputtering.
- Si silicon
- SiO 2 or the like may be used, and vapor deposition may be performed by CVD instead of sputtering.
- a resist 3 is spin-coated on the surface of the silicon (Si) film 2.
- the resist 3 is exposed with a mesh-like mask 4.
- the exposed resist 3 is developed with an appropriate developer.
- a mesh-like resist mask 3a is obtained.
- the Si film 2 is dry-etched with hexafluoride (SiF 6 ) or the like using the mesh-like resist mask 3a.
- SiF 6 hexafluoride
- Na us, in the case of Si0 2 film is wet-etched with hydrofluoric acid (HF).
- the mesh-like Si film mask 2a is transferred. Then, with a mesh Si film mask 2a, dry etching, etc. 0 2 a HOPG surface.
- a mesh Si film mask 2a dry etching, etc. 0 2 a HOPG surface.
- the Si0 2 film mask 2a of mesh-like mask is transferred to Doraietsu quenching the HOPG surface 0 2 or the like.
- HOPG with a mesh mesh pattern notch la is obtained with the surface covered with a mesh-like Si film mask 2a.
- the Si film mask 2a is removed from the HOPG surface by dry etching using SiF 6 or the like.
- SiO 2 film mask it is removed from the HOPG surface by wet etching with HF.
- HO PG with a mesh pattern cut la on the surface is finally obtained.
- FIGS. 4A to 4F a process of dispersing graphene pieces on a substrate will be described with reference to FIGS. 4A to 4F.
- Fig. 4A use the method shown in Fig. 3 to prepare HOPG1 with a mesh-like pattern with cuts la, and peel off the top surface extremely thinly to get a clean surface.
- a suitable substrate 9 such as glass is coated with resist 6 or the like, and the surface of HOPG1 containing the mesh pattern is pressed against the surface as shown by arrow 8.
- the resist-coated substrate 9 with one to several layers of graphene pieces 7 formed in FIG. By soaking, the resist 6 is dissolved, and at the same time, one to several layers of graphene pieces 7 are dispersed in a solvent to obtain a suspension of one to several layers of graphene pieces 7.
- Substrate 12 such as Si0 2 Si substrate 1 to several layers of graphene pieces 7 are developed on the substrate 12 by immersing as shown by arrows l ib.
- an appropriate graphene is selected on the darafen substrate 10 described in FIG. 4F or the graphene piece-coated substrate 10.
- an element having a desired layout is finely processed by lithography and etching with the metal direction 14 and the semiconductor direction 15 as the basic axes.
- a resist is spin-coated on the substrate 10, exposed with a mask having a desired layout, and developed.
- the resist pattern as a mask, the entire graph of row-,, quantum size dry etching using 0 2 - cut out down element, the resist is removed.
- reference numeral 17 denotes an all-daraphen element obtained by lithography and etching. Therefore, a process for precisely manufacturing the end structure is required.
- the reaction temperature is 500 to 700 ° C, and the reaction time is about 10 seconds to 10 minutes.
- a reduction reaction under heating in an H 2 atmosphere may be used.
- the graphene undergoes an oxidation reaction or a reduction reaction from the edge, the structural disorder is removed, and a smooth zigzag edge and armchair edge are obtained at the atomic level, as shown in FIG. 5C.
- p-type or n-type doping is performed to obtain all graphene elements 18 with controlled end structures.
- an appropriate oxide film 19 such as SiO 2 , A1 2 0 3 , Hf0 2 , ZrO 2 or the like is formed on all the graphite elements and used as a gate insulating layer.
- FIG. 6 is a diagram showing a double-gate all-darafen field effect transistor fabricated using the manufacturing method of FIGS. 5A to 5D.
- a double-gate all-graphene field effect transistor 20 includes a source electrode 21 made of metal graphene with integrated wiring and a drain electrode 22 made of metal graphene with integrated wiring. It has a structure in which two gate electrodes 24 and 25 are opposed to each other with the formed channel 23 interposed therebetween. There are two advantages of this structure.
- the first is that the electric field generated by the two gate electrodes 24 and 25 can be applied symmetrically to the channel, so that the gate controllability is excellent and it is easy to turn off.
- the two gate electrodes 24 and 25 are asymmetric in size, so that the larger one can be used as a normal gate electrode for on / off, and the smaller one can be used as an electrode for shifting the threshold of the gate voltage. is there.
- This double gate method makes it possible to precisely control the threshold of the gate voltage.
- FIGS. 7A to 7C are diagrams showing phase-inverter 30a, 30b, and 30c made of all graphon elements manufactured using the same manufacturing method as that shown in FIG. 5, and FIG. 7A shows p-type and n-type inverters.
- the type channel is controlled by two independent gate electrodes
- Fig. 7B is a type in which the p-type and n-type channels are collinear, and both channels are controlled by one gate electrode
- Fig. 7C is the p-type and n type Each type is parallel, and both channels are controlled by a single gate electrode.
- the p-type channel 31 and the n-type channel 32 are semiconductor graphs, and the electrodes such as the gate electrode 33 that also serves as wiring are metal graphons.
- Reference 34 is the output voltage V. ut and 35 are the input voltage V in , 37 is the power supply voltage V DD , and 36 is the ground potential V GND .
- the important point here is that the zigzag end direction, which is a metal, and the armchair end, which is a semiconductor, are perpendicular to each other.
- the p-type channel 31 and the n-type channel 32 are semiconductor graphene, and the electrodes such as the gate electrode 33 also serving as wiring are metal graphene.
- Symbol 34 is the output voltage V. ut and 35 are the input voltage V in , 37 is the power supply voltage V DD , and 36 is the ground potential V GND .
- the important point here is that, like the complementary inverter 30a in Fig. 7A, the zigzag end direction of the metal and the armchair end of the semiconductor are orthogonal to each other. It is.
- the p-type channel 31 and the n-type channel 32 are semiconductor darafen, and the electrodes such as the gate electrode 33 that also serves as wiring are metal darafen.
- Symbol 34 is the output voltage V. ut and 35 are the input voltage V in , 37 is the power supply voltage V DD , and 36 is the ground potential V GND .
- the important point here is that, like the complementary inverter 30a in FIG. 7A and the complementary inverter 30b in FIG. 7 (B), the zigzag edge direction of the metal and the armchair edge of the semiconductor are perpendicular to each other. That is.
- the zigzag edge appears in the vertical direction (metal direction 14) of the paper, and electrodes and wiring are used, while the armchair edge appears in the left and right direction (semiconductor direction 15) and is used for the channel.
- the gate electrode 33 of the phase-inverter 30b in FIG. 7B and the complementary inverter 30c in FIG. 7C has an armchair end in the major axis direction, but acts as a metal because it is sufficiently wide.
- the complementary inverter 30a in Fig. 7A has two gate electrodes, and the complementary inverter 30b in Fig. 7B and the complementary type in Fig. 7C. Since there is one type inverter 30c, the complementary inverter 30b in FIG. 7B and the complementary inverter 30c in FIG. 7C have the advantage that the number of element components can be reduced compared to the complementary inverter 30a in FIG. 7A.
- the long structure of the gate electrode 33 has a zigzag end structure.
- the complementary inverter 30b in FIG. 7B is more concise than the complementary inverter 30c in FIG. There are certain advantages.
- the complementary inverter 30b in FIG. 7B has a disadvantage that the gate electrode becomes larger than the complementary inverter 30c in FIG. 7C.
- each element structure has advantages and disadvantages.
- the Darafen element has a high degree of freedom in layout design. In other words, it is one of the features of the present invention that free circuit design is possible depending on the application and purpose.
- Example 3 are diagrams respectively showing NOR gates 40a, 40b, and 40c made of complementary inverters manufactured using the manufacturing method of FIG.
- the number of gate electrodes is two in the NOR gate 40a in FIG. 8A, four in the NOR gate 40b in FIG. 8B, and three in the NOR gate 40c in FIG. 8C.
- Reference numeral 41 indicates three equivalent directions of the semiconductor graph, and reference numeral 42 indicates three equivalent directions of the metal graph, which are common in FIGS. 8A, 8B, and 8C.
- the gate having the smallest number of gate electrodes needs to extract the output (V. ut ) 34 through the via 38 out of the plane.
- Reference numerals 31a and 31b denote first and second p-type channels made of semiconductor graphene, and reference numerals 32a and 32b denote first and second n-type channels which are semiconductor graph processors.
- Reference numerals 33a and 33b denote the first and second gate electrodes having metal darafen force.
- Reference 34 is the output voltage V.
- reference numeral 35a, 35b is input voltages a, b iV ⁇ , V in b) are shown respectively, reference numeral 36 is a ground potential V GND, reference numeral 37 is shows the power supply voltage VDD, respectively.
- the NOR gate 40b shown in FIG. 8B has first and second p-type channels 3la and 3 lb which are semiconductor graphers, and first and second n-type channels 32a and 32b made of semiconductor graphene. .
- the source electrode on the second p-type channel 31b side is connected between the first and second n-type channel 32a and 32b.
- First and second gate electrodes 33a and 33b made of metal graphons are provided adjacent to the p-type and n-type channels, respectively.
- Reference 34 is the output voltage V.
- ut and symbols 35a and 35b represent input voltages a, b CV ⁇ and V ⁇ , respectively
- symbol 36 represents a ground potential V GND
- symbol 37 represents a power supply voltage V DD .
- the NOR gate 40c shown in FIG. 8C has first and second p-type channels 3la and 3lb made of semiconductor graphene, and first and second n-type channels 32a and 32b made of semiconductor graphene. Yes.
- the source electrode on the side of the second p-type channel 3 lb is connected between the first and second n-type channels 32a and 32b.
- Two first gate electrodes 33a and a second gate electrode 33b are provided adjacent to each of the p-type and n-type channels.
- Reference 34 is the output voltage V.
- Symbols ut and 35a and 35b represent input voltages a and b (V ta a and V in b )
- symbol 36 represents a ground potential V GND
- symbol 37 represents a power supply voltage V DD .
- the NOR gate 40b in FIG. 8B and the NOR gate 40c in FIG. 8C can include the concept elements in the plane including the wiring.
- the NOR gate 40c in FIG. The gate electrode is reduced by one by introducing a 120 degree rotation into the wiring between the pole 33b and the input 35a. In this way, the layout can be simplified by introducing 120 degree rotation.
- FIGS. 9A to 9C are diagrams respectively showing schematic configurations of NAND gates 50a, 50b, and 50c having complementary inverter force manufactured using the manufacturing method of FIG. 9A to 9C, the number of gate electrodes is two in the NAND gate 50a in FIG. 9A, four in the NAND gate 50b in FIG. 9B, and three in the NAND gate 50c in FIG. 9C.
- Reference numeral 41 denotes three equivalent directions of semiconductor graphene
- reference numeral 42 denotes three equivalent directions of metal graphene, which are common in FIGS. 9A to 9C.
- the relationship between the wiring routing and the number of gate electrodes is the same as the NOR gate in Fig. 8.
- the NAND gate 50a shown in FIG. 9A has the smallest number of gate electrodes 33a and 33b, and it is necessary to draw the output ( V.ut ) 34 through the via 38 out of the plane.
- Reference numerals 31a and 31b denote first and second p-type channels made of semiconductor graphs
- reference numerals 32a and 32b denote first and second n-type channels made of semiconductor graphs.
- Reference numerals 33a and 33b denote first and second gate electrodes made of metal darafen.
- Reference 34 is the output voltage V.
- Symbols ut and 35a and 35b indicate input voltages a and b (V in a and V in b )
- symbol 36 indicates a ground potential V GND
- symbol 37 indicates a power supply voltage VDD .
- the NAND gate 50b shown in FIG. 9B has first and second p-type channels 31a and 31b made of semiconductor graphene, and first and second n-type channels 32a and 32b made of semiconductor graphene.
- First and second gate electrodes 33a and 33b made of metal darafen are provided adjacent to the p-type and n-type channels, respectively.
- This NAND gate 50b is different from the NOR gate 40b shown in FIG. 8B in that the drain electrode force on the second n-type channel 32b side is connected between the first and second p-type channels 31a and 31b.
- Reference 34 is the output voltage V.
- Symbols ut and 35a and 35b denote input voltages a and b (V in a and V in b ), symbol 36 denotes a ground potential V CND , and symbol 37 denotes a power supply voltage V DD .
- the NAND gate 50c shown in FIG. 9C has first and second p-type channels 31a and 31b made of semiconductor graphene, and first and second n-type channels 32a and 32b made of semiconductor graphene.
- the Two first gate electrodes 33a made of metal darafen and one second gate electrode 33b are provided adjacent to each p-type and n-type channel.
- This NAND gate 50c is different from the NOR gate 40c shown in FIG. 8C in that the drain electrode on the second n-type channel 32b side is connected between the first and second p-type channels 31a and 31b. It is different.
- Reference 34 is the output voltage V.
- Symbols ut and 35a and 35b denote input voltages a and b (V in a and V in b ), symbol 36 denotes a ground potential V GND , and symbol 37 denotes a power supply voltage V DD .
- the components can be arranged in the plane.
- the gate electrode is reduced by one by introducing a 120 degree rotation into the wiring between the first gate electrode 33a and the input 35a.
- Fig. 10 shows a ring oscillation circuit that combines an odd number of all-graphin complementary inverters fabricated using the manufacturing method of Fig. 5.
- Fig. 10A is a series-type ring oscillation circuit 60a
- Fig. 10B is a series-type oscillation circuit.
- a ring oscillation circuit 60b is shown.
- Reference numeral 41 indicates three equivalent directions of the semiconductor graphene
- reference numeral 42 indicates three equivalent directions of the metal graph process, which are common in FIGS. 10A and 10B.
- the ring oscillation circuit 60a is formed by arranging a plurality of channels in which a p-type channel 31 and an n-type channel 32 are connected in series with one end aligned in parallel. The other end of each of the n-type channel 32 and the source electrode 21 and the drain electrode 22 are connected to form a ladder shape.
- a gate electrode 33 is formed in a region surrounded by the source electrode 21, the drain electrode 22, and the channel. Except for the lowermost gate electrode, the upper gate electrode is connected to the connection between the p-type channel and the n-type channel.
- the bottom gate electrode is connected to the p-type channel and n-type channel of the top channel by via wiring via each via.
- the ring oscillation circuit 60b is formed by arranging a plurality of channels in which a p-type channel 31 and an n-type channel 32 are connected in series with one end aligned in the circumferential direction, and the p-type channel 31 And the n-type channel 32, the other end of each is a source
- the electrode 21 and the drain electrode 22 formed in the hexagon inside are connected to each other to form a substantially hexagonal shape.
- a gate electrode 33 is formed in a region surrounded by the source electrode 21, the drain electrode 22, and the channel. The gate electrode 33 is connected to the connection between the p-type channel 31 and the n-type channel 32.
- FIG. 11 shows an entire graph SRA 70 having a flip-flop circuit manufactured by using the above manufacturing method.
- the SRAM 70 functions as a storage element.
- semiconductor darafen is used for the ⁇ -type and ⁇ -type channels 31 and 32 joined at 120.
- Metal darafen is used for the electrodes such as the gate electrode 33 at the junction of the ⁇ -type and ⁇ -type channels 31 and 32.
- the word line 43 and the bit line 44 are made of metal darafen. With the introduction of 120 degree rotation, the components can be placed in a plane.
- the channel layer made of semiconductor graphene, the source, drain, and gate electrode layers that also serve as wiring made of metal graphene, and the channel layer and the gate electrode layer are insulated.
- the channel is a graphene having an armchair end with a width of 20 nm or less
- the electrode is a graphene with a width greater than 20 nm and an arbitrary end structure, or a width
- a semiconductor device characterized in that it is darafen with a zigzag edge at a thickness of 20 nm or less can be obtained.
- the channel is graphene exhibiting p-type or n-type conduction by being driven.
- the channel may include any one of boron, aluminum, gallium, and indium, or a part of the constituent carbon.
- a force that is a graphene that exhibits P-type conduction by substitution with these combinations of elements, or a part of the constituent carbon is one of nitrogen, phosphorus, arsenic, antimony, or a combination thereof
- a semiconductor device characterized by being graphene exhibiting n-type conduction can be obtained.
- the channel may have a force that is graphene exhibiting p-type conduction or a donor by arranging an acceptor on a surface thereof.
- a semiconductor device characterized by being graphene exhibiting n-type conduction can be obtained.
- the semiconductor device in the semiconductor device, there is provided a semiconductor device characterized in that the acceptor has an electron affinity larger than the intrinsic work function of the semiconductor graphon and the donor has an ionization energy smaller than the intrinsic work function of the semiconductor graphin. can get.
- an acceptor has an electron affinity greater than 2.3 eV and a donor has an ionization energy smaller than 6.4 eV.
- any one of the semiconductor devices is an inverter in which p-type and n-type channels are complementarily combined.
- the semiconductor device is a memory element or a logic circuit having an inverter in which a p-type and an n-type channel are complementarily combined as a basic circuit. Is obtained.
- the step of producing graphene on the substrate the step of processing the graphene into a desired element structure by lithography and etching, and the end structure of dalafen by an oxidation reaction or a reduction reaction, a zigzag edge
- a method of manufacturing a semiconductor device which includes a step of processing an armchair end, a step of doping semiconductor graphene, and a step of forming an insulating film.
- the step of producing darafen on an appropriate substrate is a graphene forming method by pyrolysis on a SiC substrate. The manufacturing method is obtained.
- the process power for producing dalafen on a suitable substrate is processed on the surface of a graphite such as highly oriented pyrolytic graphite (HOPG),
- HOPG highly oriented pyrolytic graphite
- the step of doping the semiconductor graphene may include a step of boron, aluminum, gallium, indium in a part of carbon constituting the semiconductor darafen.
- P-type lattice substitution doping that substitutes with any one of these elements, or a combination thereof, or a part of the constituent carbon is one of nitrogen, phosphorus, arsenic, antimony, or a combination thereof
- a method for manufacturing a semiconductor device is obtained, which is characterized by n-type lattice-substitution doping with substitution by an element.
- the process force S for doping semiconductor graphene is charge transfer doping for obtaining a p-type by arranging an acceptor on the surface of the semiconductor graphene.
- a method of manufacturing a semiconductor device is obtained, which is charge transfer doping that obtains n-type by arranging force or a donor.
- highly integrated logic circuits and memory elements can be manufactured using the above manufacturing method.
- Examples of utilization of the present invention include semiconductor devices such as field effect transistors, logic circuits, and memory element circuits, which are characterized by low power consumption and ultrahigh-speed operation.
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Abstract
Description
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---|---|---|---|---|
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Families Citing this family (68)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090174435A1 (en) * | 2007-10-01 | 2009-07-09 | University Of Virginia | Monolithically-Integrated Graphene-Nano-Ribbon (GNR) Devices, Interconnects and Circuits |
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US8278643B2 (en) * | 2010-02-02 | 2012-10-02 | Searete Llc | Doped graphene electronic materials |
US20140021444A1 (en) * | 2010-05-31 | 2014-01-23 | Snu R&Db Foundation | Electronic device and manufacturing method thereof |
US20120038429A1 (en) * | 2010-08-13 | 2012-02-16 | International Business Machines Corporation | Oscillator Circuits Including Graphene FET |
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WO2012036537A2 (ko) * | 2010-09-17 | 2012-03-22 | 한국과학기술원 | 플래쉬 램프 또는 레이저 빔을 이용한 그래핀 제조장치, 제조방법 및 이를 이용하여 제조된 그래핀 |
KR101462539B1 (ko) * | 2010-12-20 | 2014-11-18 | 삼성디스플레이 주식회사 | 그라펜을 이용한 유기발광표시장치 |
US9608101B2 (en) | 2011-01-04 | 2017-03-28 | Ecole Polytechnique Federale De Lausanne (Epfl) | Semiconductor device |
CA2827793A1 (en) * | 2011-01-20 | 2012-07-26 | William Marsh Rice University | Graphene-based thin films in heat circuits and methods of making the same |
US8513773B2 (en) * | 2011-02-02 | 2013-08-20 | Semiconductor Energy Laboratory Co., Ltd. | Capacitor and semiconductor device including dielectric and N-type semiconductor |
KR101469450B1 (ko) * | 2011-03-02 | 2014-12-05 | 그래핀스퀘어 주식회사 | 그래핀의 n-도핑 방법 |
KR20120120514A (ko) * | 2011-04-22 | 2012-11-02 | 한국과학기술원 | 도핑 탄소나노구조체를 이용한 소자 제어방법 및 도핑 탄소나노구조체를 포함하는 소자 |
KR20120134220A (ko) | 2011-06-01 | 2012-12-12 | 삼성전자주식회사 | 강자성 그래핀 및 그를 구비한 스핀밸브 소자 |
WO2013011399A1 (en) * | 2011-07-20 | 2013-01-24 | Koninklijke Philips Electronics N.V. | Vaccum nano electronic switching and circuit elements. |
US8394682B2 (en) * | 2011-07-26 | 2013-03-12 | Micron Technology, Inc. | Methods of forming graphene-containing switches |
KR101813181B1 (ko) | 2011-08-26 | 2017-12-29 | 삼성전자주식회사 | 튜너블 배리어를 포함하는 그래핀 전계효과 트랜지스터를 구비한 인버터 논리소자 |
US9087691B2 (en) | 2011-09-16 | 2015-07-21 | Institute of Microelectronics, Chinese Academy of Sciences | Method for manufacturing graphene nano-ribbon, mosfet and method for manufacturing the same |
CN103000498B (zh) * | 2011-09-16 | 2015-06-24 | 中国科学院微电子研究所 | 石墨烯纳米带的制造方法、mosfet及其制造方法 |
US8940576B1 (en) * | 2011-09-22 | 2015-01-27 | Hrl Laboratories, Llc | Methods for n-type doping of graphene, and n-type-doped graphene compositions |
WO2013049144A1 (en) * | 2011-09-27 | 2013-04-04 | Georgia Tech Research Corporation | Graphene transistor |
US9368581B2 (en) | 2012-02-20 | 2016-06-14 | Micron Technology, Inc. | Integrated circuitry components, switches, and memory cells |
CN102655146B (zh) * | 2012-02-27 | 2013-06-12 | 京东方科技集团股份有限公司 | 阵列基板、阵列基板的制备方法及显示装置 |
CN103296071B (zh) * | 2012-02-29 | 2016-08-03 | 中国科学院微电子研究所 | 石墨烯器件 |
DE102012204539B4 (de) | 2012-03-21 | 2023-12-07 | Robert Bosch Gmbh | Leistungstransistor und Verfahren zur Herstellung eines Leistungstransistors |
US9196766B1 (en) | 2012-04-25 | 2015-11-24 | Magnolia Optical Technologies, Inc. | Thermal detectors using graphene and oxides of graphene and methods of making the same |
CN103378238B (zh) * | 2012-04-25 | 2016-01-20 | 清华大学 | 发光二极管 |
CN102694030B (zh) * | 2012-06-01 | 2015-02-25 | 北京大学 | 具有石墨烯纳米带异质结构的隧穿场效应晶体管 |
US8623717B2 (en) * | 2012-06-12 | 2014-01-07 | International Business Machines Corporation | Side-gate defined tunable nanoconstriction in double-gated graphene multilayers |
US9236488B2 (en) * | 2012-08-23 | 2016-01-12 | Chubu University Educational Foundation | Thin film transistor and method for producing same |
KR101430140B1 (ko) * | 2012-11-28 | 2014-08-13 | 성균관대학교산학협력단 | 인-도핑된 그래핀을 이용한 전계효과 트랜지스터, 그의 제조 방법, 인-도핑된 그래핀, 및 그의 제조 방법 |
KR101423925B1 (ko) * | 2012-12-21 | 2014-07-28 | 광주과학기술원 | 그래핀 다치 로직 소자, 이의 동작방법 및 이의 제조방법 |
US20140272309A1 (en) * | 2013-03-15 | 2014-09-18 | Solan, LLC | Non-Planar Graphite Based Devices and Fabrication Methods |
KR20140115198A (ko) * | 2013-03-20 | 2014-09-30 | 한국과학기술연구원 | 산화그래핀의 환원 방법, 상기 방법으로 얻어진 환원 산화그래핀 및 상기 환원 산화그래핀을 포함하는 박막 트랜지스터 |
WO2015156877A2 (en) | 2014-01-17 | 2015-10-15 | Graphene 3D Lab Inc. | Fused filament fabrication using multi-segment filament |
JP6169023B2 (ja) * | 2014-03-13 | 2017-07-26 | 株式会社東芝 | 不揮発性メモリ |
US9570559B2 (en) * | 2014-03-14 | 2017-02-14 | University Of Virginia Patent Foundation | Graphene device including angular split gate |
US9252155B2 (en) * | 2014-06-20 | 2016-02-02 | Macronix International Co., Ltd. | Memory device and method for manufacturing the same |
CA2959163C (en) | 2014-09-02 | 2023-02-14 | Graphene 3D Lab Inc. | Electrochemical devices comprising nanoscopic carbon materials made by additive manufacturing |
US20170358658A1 (en) * | 2014-09-26 | 2017-12-14 | Intel Corporation | Metal oxide metal field effect transistors (momfets) |
US10396175B2 (en) * | 2014-11-25 | 2019-08-27 | University Of Kentucky Research Foundation | Nanogaps on atomically thin materials as non-volatile read/writable memory devices |
US9859513B2 (en) * | 2014-11-25 | 2018-01-02 | University Of Kentucky Research Foundation | Integrated multi-terminal devices consisting of carbon nanotube, few-layer graphene nanogaps and few-layer graphene nanoribbons having crystallographically controlled interfaces |
FR3030887B1 (fr) * | 2014-12-23 | 2018-01-26 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Transistor comprenant un canal mis sous contrainte en cisaillement et procede de fabrication |
CN104538438A (zh) * | 2015-01-06 | 2015-04-22 | 京东方科技集团股份有限公司 | 石墨烯掺杂材料及其制备方法、电极、像素结构、显示装置 |
US9634245B2 (en) | 2015-01-09 | 2017-04-25 | Micron Technology, Inc. | Structures incorporating and methods of forming metal lines including carbon |
CA2978556C (en) | 2015-03-02 | 2022-02-15 | Graphene 3D Lab Inc. | Thermoplastic composites comprising water-soluble peo graft polymers useful for 3-dimensional additive manufacturing |
KR101696539B1 (ko) * | 2015-03-09 | 2017-01-16 | 한양대학교 산학협력단 | 박막, 그 제조 방법, 및 그 제조 장치 |
JP6522777B2 (ja) | 2015-03-23 | 2019-05-29 | ガーマー インク.Garmor, Inc. | 酸化グラフェンを用いた設計複合構造体 |
KR102335772B1 (ko) * | 2015-04-07 | 2021-12-06 | 삼성전자주식회사 | 측면 게이트와 2차원 물질 채널을 포함하는 전자소자와 그 제조방법 |
JP6563029B2 (ja) | 2015-04-13 | 2019-08-21 | ガーマー インク.Garmor, Inc. | コンクリート又はアスファルトなどのホスト中の酸化グラファイト強化繊維 |
US11482348B2 (en) | 2015-06-09 | 2022-10-25 | Asbury Graphite Of North Carolina, Inc. | Graphite oxide and polyacrylonitrile based composite |
CA2993799C (en) | 2015-07-29 | 2023-10-03 | Graphene 3D Lab Inc. | Thermoplastic polymer composites and methods for preparing, collecting, and tempering 3d printable materials and articles from same |
EP4234204A3 (en) | 2015-09-21 | 2024-01-03 | Asbury Graphite of North Carolina, Inc. | Low-cost, high-performance composite bipolar plate |
KR102465353B1 (ko) | 2015-12-02 | 2022-11-10 | 삼성전자주식회사 | 전계 효과 트랜지스터 및 이를 포함하는 반도체 소자 |
JP6659956B2 (ja) * | 2016-05-31 | 2020-03-04 | 富士通株式会社 | ショットキーバリアダイオード及び電子装置 |
JP6994028B2 (ja) | 2016-10-26 | 2022-01-14 | ガーマー インク. | 低コスト高性能材料のための添加剤被覆粒子 |
US11661346B2 (en) * | 2018-02-01 | 2023-05-30 | The University Of Toledo | Functionally graded all-graphene based free-standing materials, methods of making and uses thereof |
DE102018107922A1 (de) * | 2018-04-04 | 2019-10-10 | Infineon Technologies Ag | Verfahren zum Verarbeiten eines Siliciumcarbid enthaltenden kristallinen Substrats, Siliciumcarbidchip und Verarbeitungskammer |
US10756205B1 (en) | 2019-02-13 | 2020-08-25 | International Business Machines Corporation | Double gate two-dimensional material transistor |
US11791061B2 (en) | 2019-09-12 | 2023-10-17 | Asbury Graphite North Carolina, Inc. | Conductive high strength extrudable ultra high molecular weight polymer graphene oxide composite |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007335532A (ja) * | 2006-06-13 | 2007-12-27 | Hokkaido Univ | グラフェン集積回路 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2541091B2 (ja) | 1993-02-26 | 1996-10-09 | 日本電気株式会社 | 炭素材料とその製造方法 |
JP3447492B2 (ja) | 1996-11-12 | 2003-09-16 | 日本電気株式会社 | 炭素材料とその製造方法 |
SE0104452D0 (sv) * | 2001-12-28 | 2001-12-28 | Forskarpatent I Vaest Ab | Metod för framställning av nanostrukturer in-situ, och in-situ framställda nanostrukturer |
EP1636829B1 (en) * | 2003-06-12 | 2016-11-23 | Georgia Tech Research Corporation | Patterned thin film graphite devices |
US7619257B2 (en) * | 2006-02-16 | 2009-11-17 | Alcatel-Lucent Usa Inc. | Devices including graphene layers epitaxially grown on single crystal substrates |
-
2008
- 2008-02-27 US US12/529,501 patent/US8168964B2/en not_active Expired - Fee Related
- 2008-02-27 WO PCT/JP2008/053899 patent/WO2008108383A1/ja active Application Filing
- 2008-02-27 JP JP2009502594A patent/JP4669957B2/ja not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007335532A (ja) * | 2006-06-13 | 2007-12-27 | Hokkaido Univ | グラフェン集積回路 |
Non-Patent Citations (1)
Title |
---|
SCIENCE, vol. 312, 26 March 2006 (2006-03-26), pages 1191 - 1196 * |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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US8227794B2 (en) | 2008-07-25 | 2012-07-24 | Taiichi Otsuji | Complementary logic gate device |
WO2010010944A1 (ja) * | 2008-07-25 | 2010-01-28 | 国立大学法人東北大学 | 相補型論理ゲート装置 |
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WO2010113518A1 (ja) | 2009-04-01 | 2010-10-07 | 国立大学法人北海道大学 | 電界効果トランジスタ |
US10020365B2 (en) | 2009-06-30 | 2018-07-10 | Nokia Technologies Oy | Graphene device and method of fabricating a graphene device |
US9035281B2 (en) | 2009-06-30 | 2015-05-19 | Nokia Technologies Oy | Graphene device and method of fabricating a graphene device |
WO2011001240A1 (en) | 2009-06-30 | 2011-01-06 | Nokia Corporation | Graphene device and method of fabricating a graphene device |
EP2448863A1 (en) * | 2009-06-30 | 2012-05-09 | Nokia Corp. | Graphene device and method of fabricating a graphene device |
EP2448863A4 (en) * | 2009-06-30 | 2014-07-16 | Nokia Corp | GRAPHENE DEVICE AND METHOD FOR MANUFACTURING THE SAME |
US10167572B2 (en) | 2009-08-07 | 2019-01-01 | Guardian Glass, LLC | Large area deposition of graphene via hetero-epitaxial growth, and products including the same |
US10164135B2 (en) | 2009-08-07 | 2018-12-25 | Guardian Glass, LLC | Electronic device including graphene-based layer(s), and/or method or making the same |
CN102656702A (zh) * | 2009-08-07 | 2012-09-05 | 格尔德殿工业公司 | 包含石墨烯基层的电子装置和/或其制造方法 |
WO2011016832A3 (en) * | 2009-08-07 | 2011-03-31 | Guardian Industries Corp. | Electronic device including graphene-based layer(s),and/or method of making the same |
US20130309475A1 (en) * | 2009-08-07 | 2013-11-21 | Guardian Industries Corp. | Large area deposition and doping of graphene, and products including the same |
US9418770B2 (en) * | 2009-08-07 | 2016-08-16 | Guardian Industries Corp. | Large area deposition and doping of graphene, and products including the same |
JP2013502049A (ja) * | 2009-08-07 | 2013-01-17 | ガーディアン・インダストリーズ・コーポレーション | グラフェンベースの層を含む電子デバイスおよび/またはその製造方法 |
JP2011045944A (ja) * | 2009-08-26 | 2011-03-10 | National Institute For Materials Science | ナノリボン及びその製造方法、ナノリボンを用いたfet及びその製造方法、ナノリボンを用いた塩基配列決定方法およびその装置 |
JP2011061046A (ja) * | 2009-09-10 | 2011-03-24 | Sony Corp | 3端子型電子デバイス及び2端子型電子デバイス |
US8916057B2 (en) | 2009-10-16 | 2014-12-23 | Graphene Square, Inc. | Roll-to-roll transfer method of graphene, graphene roll produced by the method, and roll-to-roll transfer equipment for graphene |
US9782963B2 (en) | 2009-10-16 | 2017-10-10 | Graphene Square, Inc. | Roll-to-roll transfer method of graphene, graphene roll produced by the method, and roll-to-roll transfer equipment for graphene |
WO2011046415A3 (ko) * | 2009-10-16 | 2011-10-27 | 성균관대학교산학협력단 | 그래핀의 롤투롤 전사 방법, 그에 의한 그래핀 롤, 및 그래핀의 롤투롤 전사 장치 |
US8492747B2 (en) | 2009-10-26 | 2013-07-23 | Samsung Electronics Co., Ltd. | Transistor and flat panel display including thin film transistor |
US8926854B2 (en) | 2009-12-30 | 2015-01-06 | Graphene Square, Inc. | Roll-to-roll doping method of graphene film, and doped graphene film |
US9728605B2 (en) | 2009-12-30 | 2017-08-08 | Graphene Square, Inc. | Roll-to-roll doping method of graphene film, and doped graphene film |
WO2011081440A2 (ko) * | 2009-12-30 | 2011-07-07 | 성균관대학교산학협력단 | 그래핀 필름의 롤투롤 도핑 방법 및 도핑된 그래핀 필름 |
WO2011081440A3 (ko) * | 2009-12-30 | 2011-12-01 | 성균관대학교산학협력단 | 그래핀 필름의 롤투롤 도핑 방법 및 도핑된 그래핀 필름 |
WO2011081473A3 (ko) * | 2009-12-31 | 2011-11-17 | 성균관대학교산학협력단 | 그래핀 투명 전극 및 이를 포함하는 플렉시블 실리콘 박막 반도체 소자 |
WO2011081473A2 (ko) * | 2009-12-31 | 2011-07-07 | 성균관대학교산학협력단 | 그래핀 투명 전극 및 이를 포함하는 플렉시블 실리콘 박막 반도체 소자 |
US10886501B2 (en) | 2010-01-15 | 2021-01-05 | Graphene Square, Inc. | Graphene protective film serving as a gas and moisture barrier, method for forming same, and use thereof |
JP2011192667A (ja) * | 2010-03-11 | 2011-09-29 | Toshiba Corp | トランジスタおよびその製造方法 |
KR101144588B1 (ko) * | 2010-04-16 | 2012-05-08 | 성균관대학교산학협력단 | 그라핀 시트를 포함하는 가요성 투명 전도층을 구비하는 유기 전자 소자 및 이의 제조 방법 |
JP2013537700A (ja) * | 2010-05-05 | 2013-10-03 | ナショナル ユニヴァーシティー オブ シンガポール | グラフェンの正孔ドーピング |
JP2013531878A (ja) * | 2010-05-20 | 2013-08-08 | インターナショナル・ビジネス・マシーンズ・コーポレーション | グラフェン・チャネルに基づく装置およびその製作方法 |
KR101781552B1 (ko) | 2010-06-21 | 2017-09-27 | 삼성전자주식회사 | 보론 및 질소로 치환된 그라핀 및 제조방법과, 이를 구비한 트랜지스터 |
JP2012001431A (ja) * | 2010-06-21 | 2012-01-05 | Samsung Electronics Co Ltd | ホウ素及び窒素で置換されたグラフェン及びその製造方法、並びにそれを具備したトランジスタ |
US8999201B2 (en) | 2010-06-21 | 2015-04-07 | Samsung Electronics Co., Ltd. | Graphene substituted with boron and nitrogen, method of fabricating the same, and transistor having the same |
JP2012060010A (ja) * | 2010-09-10 | 2012-03-22 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US9166099B2 (en) | 2010-09-16 | 2015-10-20 | Samsung Electronics Co., Ltd. | Graphene light-emitting device and method of manufacturing the same |
JP2012064944A (ja) * | 2010-09-16 | 2012-03-29 | Samsung Led Co Ltd | グラフェン発光素子及びその製造方法 |
JP2012089786A (ja) * | 2010-10-22 | 2012-05-10 | Toshiba Corp | 光電変換素子およびその製造方法 |
US8907352B2 (en) | 2010-10-22 | 2014-12-09 | Kabushiki Kaisha Toshiba | Photoelectric conversion element and manufacturing method thereof |
KR101813173B1 (ko) * | 2011-03-30 | 2017-12-29 | 삼성전자주식회사 | 반도체소자와 그 제조방법 및 반도체소자를 포함하는 전자장치 |
JP2012227520A (ja) * | 2011-04-07 | 2012-11-15 | Nippon Telegr & Teleph Corp <Ntt> | 電界効果トランジスタ、製造用基板、およびその製造方法 |
JPWO2012160663A1 (ja) * | 2011-05-25 | 2014-07-31 | 富士通株式会社 | スピンフィルタ及びその駆動方法 |
WO2012160663A1 (ja) * | 2011-05-25 | 2012-11-29 | 富士通株式会社 | スピンフィルタ及びその駆動方法 |
JP5610072B2 (ja) * | 2011-05-25 | 2014-10-22 | 富士通株式会社 | スピンフィルタ及びその駆動方法 |
US8860106B2 (en) | 2011-05-25 | 2014-10-14 | Fujitsu Limited | Spin filter and driving method thereof |
JP2013004972A (ja) * | 2011-06-10 | 2013-01-07 | Samsung Electronics Co Ltd | 複層のゲート絶縁層を備えたグラフェン電子素子 |
JP2013012611A (ja) * | 2011-06-29 | 2013-01-17 | Fujitsu Ltd | 半導体デバイス及びその製造方法 |
JP2013016641A (ja) * | 2011-07-04 | 2013-01-24 | Fujitsu Ltd | 電子装置およびその製造方法 |
US10002935B2 (en) | 2011-08-23 | 2018-06-19 | Micron Technology, Inc. | Semiconductor devices and structures and methods of formation |
US11652173B2 (en) | 2011-08-23 | 2023-05-16 | Micron Technology, Inc. | Methods of forming a semiconductor device comprising a channel material |
US9356155B2 (en) | 2011-08-23 | 2016-05-31 | Micron Technology, Inc. | Semiconductor device structures and arrays of vertical transistor devices |
JP2014524672A (ja) * | 2011-08-23 | 2014-09-22 | マイクロン テクノロジー, インク. | 縦型トランジスタ素子、縦型トランジスタ素子のアレイを含む半導体素子構造体、および製造方法 |
US11011647B2 (en) | 2011-08-23 | 2021-05-18 | Micron Technology, Inc. | Semiconductor devices comprising channel materials |
US10446692B2 (en) | 2011-08-23 | 2019-10-15 | Micron Technology, Inc. | Semiconductor devices and structures |
JP2013074208A (ja) * | 2011-09-28 | 2013-04-22 | Fujitsu Ltd | 電子装置およびその製造方法 |
US9951436B2 (en) | 2011-10-27 | 2018-04-24 | Garmor Inc. | Composite graphene structures |
JP2013253010A (ja) * | 2011-12-01 | 2013-12-19 | Tohoku Univ | グラフェン構造体及びそれを用いた半導体装置並びにそれらの製造方法 |
JP2017200873A (ja) * | 2012-01-19 | 2017-11-09 | ジェームズ ダーリング、マイケル | グラフェンナノ構造のdna画定エッチング法 |
JP2015528198A (ja) * | 2012-06-21 | 2015-09-24 | モナッシュ ユニバーシティMonash University | 絶縁材料の導電部 |
KR102081669B1 (ko) | 2012-06-21 | 2020-02-26 | 모나쉬 유니버시티 | 절연재 내의 전도부 |
KR20150037763A (ko) * | 2012-06-21 | 2015-04-08 | 모나쉬 유니버시티 | 절연재 내의 전도부 |
US9758379B2 (en) | 2013-03-08 | 2017-09-12 | University Of Central Florida Research Foundation, Inc. | Large scale oxidized graphene production for industrial applications |
JP2016517382A (ja) * | 2013-03-08 | 2016-06-16 | ガーマー, インク.Garmor, Inc. | ホストにおけるグラフェン同伴 |
US10535443B2 (en) | 2013-03-08 | 2020-01-14 | Garmor Inc. | Graphene entrainment in a host |
JP2014240340A (ja) * | 2013-06-12 | 2014-12-25 | 住友電気工業株式会社 | 基板、基板の製造方法、及び電子装置 |
US9768372B2 (en) | 2013-09-18 | 2017-09-19 | Kabushiki Kaisha Toshiba | Semiconductor device, superconducting device, and manufacturing method of semiconductor device |
JP2015060908A (ja) * | 2013-09-18 | 2015-03-30 | 株式会社東芝 | 半導体装置、超伝導装置およびその製造方法 |
US10079209B2 (en) | 2014-02-28 | 2018-09-18 | Fujitsu Limited | Graphene film manufacturing method and semiconductor device manufacturing method |
JP2015191975A (ja) * | 2014-03-27 | 2015-11-02 | 富士通株式会社 | 電子デバイス及びその製造方法 |
US9525072B2 (en) | 2014-08-11 | 2016-12-20 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor device and method of formation |
KR101716938B1 (ko) | 2014-08-11 | 2017-03-15 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | 반도체 디바이스 및 반도체 디바이스 형성 방법 |
KR20160019345A (ko) * | 2014-08-11 | 2016-02-19 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | 반도체 디바이스 및 반도체 디바이스 형성 방법 |
US11171212B2 (en) | 2014-08-11 | 2021-11-09 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor device and method of formation |
US10269902B2 (en) | 2014-08-11 | 2019-04-23 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor device and method of formation |
US9828290B2 (en) | 2014-08-18 | 2017-11-28 | Garmor Inc. | Graphite oxide entrainment in cement and asphalt composite |
US10145005B2 (en) | 2015-08-19 | 2018-12-04 | Guardian Glass, LLC | Techniques for low temperature direct graphene growth on glass |
JP2017050424A (ja) * | 2015-09-02 | 2017-03-09 | 富士通株式会社 | 電子デバイス及びその製造方法 |
JP2018160540A (ja) * | 2017-03-22 | 2018-10-11 | 株式会社東芝 | グラフェン配線構造、半導体装置、グラフェン配線構造の作製方法、配線構造の作製方法 |
JP7002850B2 (ja) | 2017-03-22 | 2022-02-04 | 株式会社東芝 | グラフェン配線構造の作製方法、配線構造の作製方法 |
JP2021155329A (ja) * | 2017-09-12 | 2021-10-07 | 富士通株式会社 | グラフェンナノリボン、半導体装置、化合物の製造方法及びグラフェンナノリボンの製造方法 |
JP2022517129A (ja) * | 2019-01-22 | 2022-03-04 | ノースロップ グラマン システムズ コーポレーション | 絶縁体と金属相変化材料を用いた半導体デバイス、及び半導体デバイスの製造方法 |
KR20200101714A (ko) * | 2019-02-20 | 2020-08-28 | 충남대학교산학협력단 | 질소-도핑된 그래핀층을 활성층으로 포함하는 그래핀 기반의 tft |
KR102212999B1 (ko) * | 2019-02-20 | 2021-02-05 | 충남대학교산학협력단 | 질소-도핑된 그래핀층을 활성층으로 포함하는 그래핀 기반의 tft |
US11869945B2 (en) | 2019-02-20 | 2024-01-09 | The Industry & Academic Cooperation In Chungnam National University (Iac) | Graphene-based TFT comprising nitrogen-doped graphene layer as active layer |
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US8168964B2 (en) | 2012-05-01 |
US20100102292A1 (en) | 2010-04-29 |
JP4669957B2 (ja) | 2011-04-13 |
JPWO2008108383A1 (ja) | 2010-06-17 |
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