WO2007083381A1 - Élément de circuit, circuit de balayage, circuit de balayage de limites, procédé de test de balayage et procédé pour détecter l'emplacement d'un défaut dans un circuit de balayage - Google Patents

Élément de circuit, circuit de balayage, circuit de balayage de limites, procédé de test de balayage et procédé pour détecter l'emplacement d'un défaut dans un circuit de balayage Download PDF

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Publication number
WO2007083381A1
WO2007083381A1 PCT/JP2006/300812 JP2006300812W WO2007083381A1 WO 2007083381 A1 WO2007083381 A1 WO 2007083381A1 JP 2006300812 W JP2006300812 W JP 2006300812W WO 2007083381 A1 WO2007083381 A1 WO 2007083381A1
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WO
WIPO (PCT)
Prior art keywords
circuit
signal
register
input
scan
Prior art date
Application number
PCT/JP2006/300812
Other languages
English (en)
Japanese (ja)
Inventor
Masahiro Yanagida
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2006/300812 priority Critical patent/WO2007083381A1/fr
Publication of WO2007083381A1 publication Critical patent/WO2007083381A1/fr

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318566—Comparators; Diagnosing the device under test

Definitions

  • Circuit element scan circuit, boundary scan circuit, scan test method, scan circuit abnormal point detection method
  • the present invention relates to a scan circuit provided in, for example, an LSI, and in particular, a circuit element, a scan circuit, a noise scan circuit, and a scan test method capable of easily analyzing a failure location of the scan circuit.
  • the present invention also relates to a method for detecting an abnormal part of a scan circuit.
  • a scan circuit based on a serial scan method is used to set a value in an LSI internal register and read the value.
  • the LSI's internal registers register block consisting of one or more registers 1-1 to 1-n are connected in a daisy chain to form one shift register, and the set value is By shifting in and shifting out the output, and observing the output, a single unit test of the LSI is performed.
  • the register is composed of one or a plurality of flip-flops.
  • the failure detection rate can be set so that the logic state setting and the observation can be performed for more nodes of the user circuit to be tested while suppressing the decrease in the degree of integration due to the increase in the number of test circuits.
  • the following boundary scan register is known as an example of a technique for improving the test efficiency by improving the design defect rate and shortening the test pattern (see, for example, Patent Document 1 below).
  • Patent Document 1 JP-A-11 281710
  • the failure location is specified as follows.
  • the present invention has been made to solve the above-described problems, and can easily identify a failure of a scan circuit and a failure portion thereof, so that a circuit test of an LSI or the like can be performed on the scan circuit.
  • the purpose is to provide a circuit element, a scan circuit, a boundary scan circuit, a scan test method, and a method for detecting an abnormal part of the scan circuit, which can easily distinguish and diagnose faulty power.
  • a circuit element of the present invention includes a first register, a second register, a first input terminal to which the first register output is input, a control signal And a buffer circuit for outputting a signal corresponding to the control signal to the second register.
  • the circuit element of the present invention provides a plurality of registers connected in a column, a buffer circuit provided between the registers connected adjacent to each other, and an instruction signal to the buffer circuit
  • An instruction signal generation unit that outputs a register output connected upstream to a register connected downstream according to the instruction signal, or a signal generated by a buffer circuit. Output to a downstream connected register
  • the present invention is a scan circuit that scans data, and includes a plurality of registers (or register blocks) provided in cascade in a chain shape, and at least a part of the plurality of registers.
  • An input signal setting circuit is connected to the data input terminal of the register, and is switched to input a low signal and a high signal in place of the input data signal to which the previous register power of the register is input.
  • the input signal setting circuit includes a combination of two signal generators that selectively generate a low signal and a high signal, and a signal generated by the signal generator, so that the input data
  • a gate circuit that switches between a low signal and a high signal instead of a signal and inputs the signal to a data input terminal is provided.
  • the plurality of registers are divided into a plurality of blocks each including a plurality of registers, a buffer is inserted between the blocks, and the input signal setting circuit uses the buffer as an input terminal. It is provided.
  • the present invention is a boundary scan circuit provided for performing diagnostic analysis of the internal circuit with respect to the internal circuit, and includes a plurality of registers provided in tandem in a chain shape; An input signal that is connected to the data input terminal of at least some of these registers and that switches between a low signal and a high signal instead of the input data signal that is input at the previous stage of the register. And a setting circuit.
  • the present invention provides a scan test method for shifting information set in the first register to the second register, and is provided between the first register and the second register.
  • the present invention provides a circuit that sequentially scans information in a plurality of registers connected in a column. A step of outputting circuit force information connected between the upstream side register and the downstream side register, and a step of sequentially shifting the outputted information to the downstream side. And determining whether or not the output information is a normal output of the circuit force.
  • the present invention is a method for detecting an abnormal part of a scan circuit for detecting an abnormal part of a scan circuit that scans data by cascading a plurality of registers in a chain, and among the plurality of registers A forcible signal input step for causing a data input terminal of at least one of the registers to switch between a low signal and a high signal instead of an input data signal to which the register power of the previous stage of the register is also input, and the register And an abnormal point determination step for determining an abnormal point in the scan circuit in correspondence with the input low signal and high signal.
  • FIG. 1 is a block diagram of a scan circuit showing a first embodiment of the present invention.
  • FIG. 2 is a block diagram showing an outline of the present invention.
  • FIG. 3 is a block diagram showing an input signal setting circuit in the embodiment of the present invention. [4] This is a diagram showing the relationship between the output values of the first and second signal generation circuits and the output value of the input signal setting circuit.
  • FIG. 5 is a diagram showing an example of a faulty part of the scan circuit in order to show the operation of the first embodiment.
  • FIG. 6 is a flowchart showing the operation of the first embodiment.
  • FIG. 7 is a block diagram showing a boundary scan circuit according to a second embodiment of the present invention.
  • FIG. 8 is a block diagram showing a conventional scan circuit.
  • FIG. 1 is a block diagram showing an overall configuration in Embodiment 1 of the present invention
  • FIG. 2 is a block diagram showing an outline of the present invention
  • FIG. 3 is a block diagram showing an input signal setting circuit in the embodiment of the present invention. is there.
  • a set value shift-in circuit 10 that is connected to the input terminal of the first stage register block 1-1 of the scan circuit 100 and shifts the set value of the scan circuit 100 is provided outside the LSI, for example. It is done.
  • an observation (determination) circuit or device 20 for observing and judging the output value shifted out is provided.
  • FIG. 2 showing the outline of the present invention
  • a buffer constituting the input signal setting circuit is inserted between two registers (a front-stage register and a rear-stage register), and a buffer output is generated by a control signal of this buffer. Show that “1”, “0”, “input value (output of previous register)” is output to the subsequent register! /
  • Each of the input signal setting circuits P1 to P8 is, as shown in FIG. 3, a first signal generating circuit that can generate a binary signal of either low (0) or high (1) ( (First signal generator) 5 and second signal generator circuit (second signal generator) 6, and generated signal instruction circuit 7 for indicating and setting the generated signals by the first signal generator circuit 5 and the second signal generator circuit 6 With.
  • the generation signal indicating circuit 7 can be configured in cooperation with the set value shift-in circuit or can be configured separately.
  • Each of the input signal setting circuits P1 to P8 is an AND circuit 8 having two input terminals as a gate circuit, and one input terminal of the input signal setting circuits P1 to P8 is an output terminal of the previous stage register block (of the previous stage scan FF). Output) 12 is connected, the AND circuit 8 is input to the other input terminal with the signal from the first signal generation circuit 5 being negated (via the knot circuit), and the OR circuit 9 having two input terminals 9 And one of the input terminals is connected to the output terminal of the AND circuit 8. And an OR circuit 9 to which the signal from the second signal generating circuit 6 is input to the other input terminal.
  • the configuration of the gate circuit is merely an example in the embodiment, and of course.
  • the output terminal of the OR circuit 9 is connected to the input terminal (input of the next-stage scan FF) 13 of the next-stage register block.
  • the generation signal instruction circuit should be configured outside the force that is configured inside the LSI.
  • the output of the input signal setting circuit based on the combination of the signals generated by the first signal generating circuit 5 and the second signal generating circuit 6 in the input signal setting circuit is as shown in the table of FIG.
  • the generation signals of the generation circuit 5 and the second signal generation circuit 6 are both low, the output signal of the previous register block is directly used as the input signal to the next register block.
  • the low signal is forcibly sent to the register block of the next stage (the register block of the previous stage). Input) regardless of the output signal.
  • the input signal setting circuit P8 closest to the output side generates a 0 (low) fixed value as an output to the next stage and shifts it.
  • the number of bits in the register from the input signal setting circuit P8 to the final output terminal of the scan circuit The output value when shifted by the minute is judged by the judgment circuit 20 and observed.
  • Step S3 If the output value is 0, go to (Step S3), and if the output value is 1 (High), It can be seen that a fault exists between the signal setting circuit P8 and the final output terminal.
  • This output value can be automatically determined by the determination circuit 20 in accordance with the input signal. The result can then be displayed as shown in step S10 in FIG.
  • the set value shift-in circuit 10 the generated signal instruction circuit 7 and the determination circuit 20 cooperate with each other, and in this embodiment, as can be understood from the description of the operation, the set value shift-in circuit
  • the generated signal instruction circuit 7 of each input signal setting circuit is set to the set value shift-in circuit 10 so that the input signal setting circuit P8 on the most downstream side is operated sequentially from the input signal setting circuit P8 on the most downstream side to P1 on the first stage side.
  • the first signal generation circuit 5 and the second signal generation circuit 6 of each input signal setting circuit are instructed so that the description of the operation is established based on the measured value.
  • the judgment circuit 20 measures the signal pulse from the set value shift-in circuit 10 in conjunction with the operation of the set value shift-in circuit 10, and selects which input signal setting among the plurality of input signal setting circuits P1 to P8. It is configured to recognize whether the circuit outputs a fixed value of 0 and to recognize the determination value to be determined corresponding to the number of shifts.
  • the decision value 20 determines the output value when the input signal setting circuit P8 closest to the final output terminal generates and shifts the fixed value 1 and shifts by the number of register bits from the input signal setting circuit P8 to the final output terminal. And observe it.
  • Step S5 If the output value is ⁇ , go to (Step S5). If the output value is 0, it can be seen that a fault exists between the input signal setting circuit P8 and the final output terminal of the scan circuit. This determination can be automatically determined and displayed by the determination circuit 20 as described above (step S10).
  • the second input signal setting circuit P7 from the final output end generates a fixed value of 0 and shifts, and the output when shifting by the number of register bits from the input signal setting circuit P7 to the final output end
  • the force value is judged by the judgment circuit 20 and observed.
  • Step S7 If the output value is ⁇ , go to (Step S7). If the output value is 1, there is a failure between the input signal setting circuit P7 and the input signal setting circuit P8. This can also be automatically determined and displayed as described above (step S11).
  • the second input signal setting circuit P7 from the final output end generates a fixed value 1 and shifts, and the output value when the input signal setting circuit P7 shifts by the number of register bits from the final output end is judged 20 Judgment and observe it.
  • Step S9 If the output value is ⁇ , go to (Step S9). If the output value is 0, it can be seen that there is a fault between the input signal setting circuit P7 and the input signal setting circuit P8. This result is displayed in (Step S11).
  • the position of the failure can be detected by sequentially moving the position of the input signal setting circuit that generates the fixed value 0 or 1 toward P1.
  • the test decision to shift by generating a fixed value of 0 in the input signal setting circuit P6 is affirmative, but the test to shift by generating 1 is fixed at 0 at the location of X, so 1 is The test judgment is denied because it cannot be observed. This indicates that the fault is between the input signal setting circuit P6 and the input signal setting circuit P7.
  • FIG. 7 is a block diagram showing an application example to the boundary scan circuit as the second embodiment of the present invention.
  • the present invention can also be applied to boundary scans that are not limited to internal scans.
  • a register (boundary) is provided around the internal circuit 30 of the LSI.
  • a boundary scan circuit that can easily detect an abnormal location by providing input signal setting circuits P1 to P7 that generate low, noise, or noise at appropriate locations in the middle of the BS. can do.
  • This input signal setting circuit can have the same configuration as that described in the first embodiment.
  • the present invention it is possible to easily identify the failure of the scan circuit and the location of the failure, and to easily diagnose the circuit test of the LSI etc. by distinguishing the failure power of the scan circuit! /, Has an effect.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

Selon l'invention, afin d'identifier facilement un défaut et son emplacement dans un circuit de balayage, et de distinguer facilement un test de circuit, tel que sur un circuit d'intégration LSI, d'un défaut dans le circuit de balayage à diagnostiquer un procédé permettant de détecter l'emplacement d'un défaut dans un circuit de balayage comprend une étape d'entrée forcée de signal consistant à forcer l'application en entrée d'un signal de niveau bas et d'un signal de niveau haut sur des bornes d'entrée de données d'au moins une partie d'une pluralité de registres à la place d'un signal de données d'entrée appliqué en entrée depuis le registre d'étage précédent en effectuant une commutation entre ceux-ci, et une étape de détermination d'emplacement de défaut consistant à déterminer l'emplacement d'un défaut dans le circuit de balayage en établissant une relation entre un signal de sortie provenant du registre d'étage suivant et le signal de niveau bas et le signal de niveau haut appliqués en entrée.
PCT/JP2006/300812 2006-01-20 2006-01-20 Élément de circuit, circuit de balayage, circuit de balayage de limites, procédé de test de balayage et procédé pour détecter l'emplacement d'un défaut dans un circuit de balayage WO2007083381A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2006/300812 WO2007083381A1 (fr) 2006-01-20 2006-01-20 Élément de circuit, circuit de balayage, circuit de balayage de limites, procédé de test de balayage et procédé pour détecter l'emplacement d'un défaut dans un circuit de balayage

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2006/300812 WO2007083381A1 (fr) 2006-01-20 2006-01-20 Élément de circuit, circuit de balayage, circuit de balayage de limites, procédé de test de balayage et procédé pour détecter l'emplacement d'un défaut dans un circuit de balayage

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000009800A (ja) * 1998-06-19 2000-01-14 Sharp Corp スキャンテスト回路およびそれを備えた半導体装置ならびにスキャンテスト方法
JP2004361351A (ja) * 2003-06-06 2004-12-24 Sharp Corp スキャンパス回路およびそれを備える論理回路ならびに集積回路のテスト方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000009800A (ja) * 1998-06-19 2000-01-14 Sharp Corp スキャンテスト回路およびそれを備えた半導体装置ならびにスキャンテスト方法
JP2004361351A (ja) * 2003-06-06 2004-12-24 Sharp Corp スキャンパス回路およびそれを備える論理回路ならびに集積回路のテスト方法

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