WO2007083381A1 - Circuit element, scan circuit, boundary scan circuit, scan test method and method for detecting fault location in scan circuit - Google Patents

Circuit element, scan circuit, boundary scan circuit, scan test method and method for detecting fault location in scan circuit Download PDF

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Publication number
WO2007083381A1
WO2007083381A1 PCT/JP2006/300812 JP2006300812W WO2007083381A1 WO 2007083381 A1 WO2007083381 A1 WO 2007083381A1 JP 2006300812 W JP2006300812 W JP 2006300812W WO 2007083381 A1 WO2007083381 A1 WO 2007083381A1
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Prior art keywords
circuit
signal
register
input
scan
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PCT/JP2006/300812
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French (fr)
Japanese (ja)
Inventor
Masahiro Yanagida
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Fujitsu Limited
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Priority to PCT/JP2006/300812 priority Critical patent/WO2007083381A1/en
Publication of WO2007083381A1 publication Critical patent/WO2007083381A1/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318566—Comparators; Diagnosing the device under test

Definitions

  • Circuit element scan circuit, boundary scan circuit, scan test method, scan circuit abnormal point detection method
  • the present invention relates to a scan circuit provided in, for example, an LSI, and in particular, a circuit element, a scan circuit, a noise scan circuit, and a scan test method capable of easily analyzing a failure location of the scan circuit.
  • the present invention also relates to a method for detecting an abnormal part of a scan circuit.
  • a scan circuit based on a serial scan method is used to set a value in an LSI internal register and read the value.
  • the LSI's internal registers register block consisting of one or more registers 1-1 to 1-n are connected in a daisy chain to form one shift register, and the set value is By shifting in and shifting out the output, and observing the output, a single unit test of the LSI is performed.
  • the register is composed of one or a plurality of flip-flops.
  • the failure detection rate can be set so that the logic state setting and the observation can be performed for more nodes of the user circuit to be tested while suppressing the decrease in the degree of integration due to the increase in the number of test circuits.
  • the following boundary scan register is known as an example of a technique for improving the test efficiency by improving the design defect rate and shortening the test pattern (see, for example, Patent Document 1 below).
  • Patent Document 1 JP-A-11 281710
  • the failure location is specified as follows.
  • the present invention has been made to solve the above-described problems, and can easily identify a failure of a scan circuit and a failure portion thereof, so that a circuit test of an LSI or the like can be performed on the scan circuit.
  • the purpose is to provide a circuit element, a scan circuit, a boundary scan circuit, a scan test method, and a method for detecting an abnormal part of the scan circuit, which can easily distinguish and diagnose faulty power.
  • a circuit element of the present invention includes a first register, a second register, a first input terminal to which the first register output is input, a control signal And a buffer circuit for outputting a signal corresponding to the control signal to the second register.
  • the circuit element of the present invention provides a plurality of registers connected in a column, a buffer circuit provided between the registers connected adjacent to each other, and an instruction signal to the buffer circuit
  • An instruction signal generation unit that outputs a register output connected upstream to a register connected downstream according to the instruction signal, or a signal generated by a buffer circuit. Output to a downstream connected register
  • the present invention is a scan circuit that scans data, and includes a plurality of registers (or register blocks) provided in cascade in a chain shape, and at least a part of the plurality of registers.
  • An input signal setting circuit is connected to the data input terminal of the register, and is switched to input a low signal and a high signal in place of the input data signal to which the previous register power of the register is input.
  • the input signal setting circuit includes a combination of two signal generators that selectively generate a low signal and a high signal, and a signal generated by the signal generator, so that the input data
  • a gate circuit that switches between a low signal and a high signal instead of a signal and inputs the signal to a data input terminal is provided.
  • the plurality of registers are divided into a plurality of blocks each including a plurality of registers, a buffer is inserted between the blocks, and the input signal setting circuit uses the buffer as an input terminal. It is provided.
  • the present invention is a boundary scan circuit provided for performing diagnostic analysis of the internal circuit with respect to the internal circuit, and includes a plurality of registers provided in tandem in a chain shape; An input signal that is connected to the data input terminal of at least some of these registers and that switches between a low signal and a high signal instead of the input data signal that is input at the previous stage of the register. And a setting circuit.
  • the present invention provides a scan test method for shifting information set in the first register to the second register, and is provided between the first register and the second register.
  • the present invention provides a circuit that sequentially scans information in a plurality of registers connected in a column. A step of outputting circuit force information connected between the upstream side register and the downstream side register, and a step of sequentially shifting the outputted information to the downstream side. And determining whether or not the output information is a normal output of the circuit force.
  • the present invention is a method for detecting an abnormal part of a scan circuit for detecting an abnormal part of a scan circuit that scans data by cascading a plurality of registers in a chain, and among the plurality of registers A forcible signal input step for causing a data input terminal of at least one of the registers to switch between a low signal and a high signal instead of an input data signal to which the register power of the previous stage of the register is also input, and the register And an abnormal point determination step for determining an abnormal point in the scan circuit in correspondence with the input low signal and high signal.
  • FIG. 1 is a block diagram of a scan circuit showing a first embodiment of the present invention.
  • FIG. 2 is a block diagram showing an outline of the present invention.
  • FIG. 3 is a block diagram showing an input signal setting circuit in the embodiment of the present invention. [4] This is a diagram showing the relationship between the output values of the first and second signal generation circuits and the output value of the input signal setting circuit.
  • FIG. 5 is a diagram showing an example of a faulty part of the scan circuit in order to show the operation of the first embodiment.
  • FIG. 6 is a flowchart showing the operation of the first embodiment.
  • FIG. 7 is a block diagram showing a boundary scan circuit according to a second embodiment of the present invention.
  • FIG. 8 is a block diagram showing a conventional scan circuit.
  • FIG. 1 is a block diagram showing an overall configuration in Embodiment 1 of the present invention
  • FIG. 2 is a block diagram showing an outline of the present invention
  • FIG. 3 is a block diagram showing an input signal setting circuit in the embodiment of the present invention. is there.
  • a set value shift-in circuit 10 that is connected to the input terminal of the first stage register block 1-1 of the scan circuit 100 and shifts the set value of the scan circuit 100 is provided outside the LSI, for example. It is done.
  • an observation (determination) circuit or device 20 for observing and judging the output value shifted out is provided.
  • FIG. 2 showing the outline of the present invention
  • a buffer constituting the input signal setting circuit is inserted between two registers (a front-stage register and a rear-stage register), and a buffer output is generated by a control signal of this buffer. Show that “1”, “0”, “input value (output of previous register)” is output to the subsequent register! /
  • Each of the input signal setting circuits P1 to P8 is, as shown in FIG. 3, a first signal generating circuit that can generate a binary signal of either low (0) or high (1) ( (First signal generator) 5 and second signal generator circuit (second signal generator) 6, and generated signal instruction circuit 7 for indicating and setting the generated signals by the first signal generator circuit 5 and the second signal generator circuit 6 With.
  • the generation signal indicating circuit 7 can be configured in cooperation with the set value shift-in circuit or can be configured separately.
  • Each of the input signal setting circuits P1 to P8 is an AND circuit 8 having two input terminals as a gate circuit, and one input terminal of the input signal setting circuits P1 to P8 is an output terminal of the previous stage register block (of the previous stage scan FF). Output) 12 is connected, the AND circuit 8 is input to the other input terminal with the signal from the first signal generation circuit 5 being negated (via the knot circuit), and the OR circuit 9 having two input terminals 9 And one of the input terminals is connected to the output terminal of the AND circuit 8. And an OR circuit 9 to which the signal from the second signal generating circuit 6 is input to the other input terminal.
  • the configuration of the gate circuit is merely an example in the embodiment, and of course.
  • the output terminal of the OR circuit 9 is connected to the input terminal (input of the next-stage scan FF) 13 of the next-stage register block.
  • the generation signal instruction circuit should be configured outside the force that is configured inside the LSI.
  • the output of the input signal setting circuit based on the combination of the signals generated by the first signal generating circuit 5 and the second signal generating circuit 6 in the input signal setting circuit is as shown in the table of FIG.
  • the generation signals of the generation circuit 5 and the second signal generation circuit 6 are both low, the output signal of the previous register block is directly used as the input signal to the next register block.
  • the low signal is forcibly sent to the register block of the next stage (the register block of the previous stage). Input) regardless of the output signal.
  • the input signal setting circuit P8 closest to the output side generates a 0 (low) fixed value as an output to the next stage and shifts it.
  • the number of bits in the register from the input signal setting circuit P8 to the final output terminal of the scan circuit The output value when shifted by the minute is judged by the judgment circuit 20 and observed.
  • Step S3 If the output value is 0, go to (Step S3), and if the output value is 1 (High), It can be seen that a fault exists between the signal setting circuit P8 and the final output terminal.
  • This output value can be automatically determined by the determination circuit 20 in accordance with the input signal. The result can then be displayed as shown in step S10 in FIG.
  • the set value shift-in circuit 10 the generated signal instruction circuit 7 and the determination circuit 20 cooperate with each other, and in this embodiment, as can be understood from the description of the operation, the set value shift-in circuit
  • the generated signal instruction circuit 7 of each input signal setting circuit is set to the set value shift-in circuit 10 so that the input signal setting circuit P8 on the most downstream side is operated sequentially from the input signal setting circuit P8 on the most downstream side to P1 on the first stage side.
  • the first signal generation circuit 5 and the second signal generation circuit 6 of each input signal setting circuit are instructed so that the description of the operation is established based on the measured value.
  • the judgment circuit 20 measures the signal pulse from the set value shift-in circuit 10 in conjunction with the operation of the set value shift-in circuit 10, and selects which input signal setting among the plurality of input signal setting circuits P1 to P8. It is configured to recognize whether the circuit outputs a fixed value of 0 and to recognize the determination value to be determined corresponding to the number of shifts.
  • the decision value 20 determines the output value when the input signal setting circuit P8 closest to the final output terminal generates and shifts the fixed value 1 and shifts by the number of register bits from the input signal setting circuit P8 to the final output terminal. And observe it.
  • Step S5 If the output value is ⁇ , go to (Step S5). If the output value is 0, it can be seen that a fault exists between the input signal setting circuit P8 and the final output terminal of the scan circuit. This determination can be automatically determined and displayed by the determination circuit 20 as described above (step S10).
  • the second input signal setting circuit P7 from the final output end generates a fixed value of 0 and shifts, and the output when shifting by the number of register bits from the input signal setting circuit P7 to the final output end
  • the force value is judged by the judgment circuit 20 and observed.
  • Step S7 If the output value is ⁇ , go to (Step S7). If the output value is 1, there is a failure between the input signal setting circuit P7 and the input signal setting circuit P8. This can also be automatically determined and displayed as described above (step S11).
  • the second input signal setting circuit P7 from the final output end generates a fixed value 1 and shifts, and the output value when the input signal setting circuit P7 shifts by the number of register bits from the final output end is judged 20 Judgment and observe it.
  • Step S9 If the output value is ⁇ , go to (Step S9). If the output value is 0, it can be seen that there is a fault between the input signal setting circuit P7 and the input signal setting circuit P8. This result is displayed in (Step S11).
  • the position of the failure can be detected by sequentially moving the position of the input signal setting circuit that generates the fixed value 0 or 1 toward P1.
  • the test decision to shift by generating a fixed value of 0 in the input signal setting circuit P6 is affirmative, but the test to shift by generating 1 is fixed at 0 at the location of X, so 1 is The test judgment is denied because it cannot be observed. This indicates that the fault is between the input signal setting circuit P6 and the input signal setting circuit P7.
  • FIG. 7 is a block diagram showing an application example to the boundary scan circuit as the second embodiment of the present invention.
  • the present invention can also be applied to boundary scans that are not limited to internal scans.
  • a register (boundary) is provided around the internal circuit 30 of the LSI.
  • a boundary scan circuit that can easily detect an abnormal location by providing input signal setting circuits P1 to P7 that generate low, noise, or noise at appropriate locations in the middle of the BS. can do.
  • This input signal setting circuit can have the same configuration as that described in the first embodiment.
  • the present invention it is possible to easily identify the failure of the scan circuit and the location of the failure, and to easily diagnose the circuit test of the LSI etc. by distinguishing the failure power of the scan circuit! /, Has an effect.

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  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

In order to easily identify a fault and its location in a scan circuit and to easily distinguish a circuit test such as on an LSI from a fault in the scan circuit for diagnosis, a method for detecting a fault location in a scan circuit comprises a forced signal input step of forcing a low signal and a high signal to be inputted to data input terminals of at least part of a plurality of registers in place of an input data signal inputted from the preceding-stage register by switching therebetween and a fault location determining step of determining the fault location in the scan circuit by relating an output signal from the succeeding-stage register to the inputted low signal and high signal.

Description

明 細 書  Specification
回路素子、スキャン回路、バウンダリスキャン回路、スキャン試験方法、ス キャン回路の異常箇所検出方法  Circuit element, scan circuit, boundary scan circuit, scan test method, scan circuit abnormal point detection method
技術分野  Technical field
[0001] 本発明は、例えば LSI内に設けられたスキャン回路に関し、特に、そのスキャン回 路の故障箇所の解析を容易に行うことができる回路素子、スキャン回路、ノ ゥンダリス キャン回路、スキャン試験方法及びスキャン回路の異常箇所検出方法に関するもの である。  TECHNICAL FIELD [0001] The present invention relates to a scan circuit provided in, for example, an LSI, and in particular, a circuit element, a scan circuit, a noise scan circuit, and a scan test method capable of easily analyzing a failure location of the scan circuit. The present invention also relates to a method for detecting an abnormal part of a scan circuit.
背景技術  Background art
[0002] 今日の LSIの単体試験では、 LSI内部レジスタへの値の設定および値の読み出し にシリアルスキャン方式によるスキャン回路が用いられている。これは、図 8に示すよう に、 LSI内部のレジスタ（一つ又は複数のレジスタからなるレジスタブロック） 1—1〜1 —nを数珠繋ぎに接続し、 1つのシフトレジスタを構成し、設定値をシフトインしてその 出力をシフトアウトさせて、その出力を観測することで LSIの単体試験を行うようにした ものである。なお、レジスタは一つ又は複数のフリップフロップで構成されている。  [0002] In today's LSI unit tests, a scan circuit based on a serial scan method is used to set a value in an LSI internal register and read the value. As shown in Fig. 8, the LSI's internal registers (register block consisting of one or more registers) 1-1 to 1-n are connected in a daisy chain to form one shift register, and the set value is By shifting in and shifting out the output, and observing the output, a single unit test of the LSI is performed. The register is composed of one or a plurality of flip-flops.
[0003] また、テスト回路増加による集積度低下を抑えながら、テスト対象のユーザ回路のよ り多くのノードに対して、テストに伴った論理状態設定や観測を行えるようにして、故 障検出率や設計不良率の向上やテストパターンの短縮によるテスト能率向上を図る 技術の一例として下記バウンダリスキャンレジスタが知られる（例えば下記特許文献 1 参照)。  [0003] Furthermore, the failure detection rate can be set so that the logic state setting and the observation can be performed for more nodes of the user circuit to be tested while suppressing the decrease in the degree of integration due to the increase in the number of test circuits. The following boundary scan register is known as an example of a technique for improving the test efficiency by improving the design defect rate and shortening the test pattern (see, for example, Patent Document 1 below).
[0004] これは、入力側のマルチプレクサにもう一つのマルチプレクサを加え、 3入力択一 選択のマルチプレクサとし、被テスト回路のスキャンデータを入力し、その出力でユー ザ回路の観測を行えるようにしたものである。  [0004] This is because the multiplexer on the input side is added with another multiplexer to make it a 3-input selection multiplexer, and the scan data of the circuit under test can be input and the user circuit can be observed at the output. Is.
特許文献 1 :特開平 11 281710号公報  Patent Document 1: JP-A-11 281710
発明の開示  Disclosure of the invention
発明が解決しょうとする課題  Problems to be solved by the invention
[0005] し力しながら、図 8に示されたシリアルスキャン方式によるスキャン回路は上述したよ うに数珠繋ぎの構成をとるため、途中の回路に故障が発生すると、そこでデータのシ フトが止まってしまう等、動作が正常に行われなくなり、内部レジスタの読み書きが全 くできなくなる。 [0005] However, the serial scan scan circuit shown in FIG. Since the structure is connected in a daisy chain, if the circuit in the middle fails, the data shift stops and the operation is not performed normally, and the internal registers cannot be read or written at all.
[0006] 例えば、図 8に X印で示されるように、途中で障害があると全体がアクセスできなく なる。このような状態になった場合、故障箇所の特定は極めて困難となる。  [0006] For example, as indicated by an X in FIG. 8, if there is a failure along the way, the entire device cannot be accessed. In such a state, it becomes extremely difficult to identify the fault location.
[0007] このような場合、従来は次のようにして故障箇所を特定して 、る。 [0007] In such a case, conventionally, the failure location is specified as follows.
1)レジスタにリセットが備えられていれば、リセット後の値力^であることを利用して、シ フトアウトした値が 0から 1に変わる個数を数えて場所を特定することができる。ただし 1) If the register is equipped with a reset, it is possible to identify the location by counting the number of shift-out values from 0 to 1 using the value after reset. However,
、故障個所が 0とショートして 、る場合は特定が不可能であることは 、うまでもな!/、。If the fault location is shorted to 0, it is impossible to specify it.
2)また、従来は LSIを動作させた後停止し、その状態でシフトアウトした値から、故障 個所を推定する。ただし、停止した状態のレジスタの値を予測できなければ場所特定 は不可能である。 2) Conventionally, the LSI is operated and then stopped, and the fault location is estimated from the value shifted out in that state. However, if the value of the register in the stopped state cannot be predicted, the location cannot be specified.
[0008] しかし、近年の LSI規模の増大化に伴 、、レジスタ数が増加し、また、高密度化の 要求からレジスタの小型化のため、リセット回路の削除などが行われてきているため、 故障箇所の解析がより困難となってきている。  However, as the LSI scale has increased in recent years, the number of registers has increased, and the reset circuit has been removed to reduce the size of registers due to the demand for higher density. Failure point analysis is becoming more difficult.
[0009] この問題は、上記特許文献 1に示した構成においても、同様に発生する。 This problem also occurs in the configuration shown in Patent Document 1 above.
[0010] 本発明は、上述した問題点を解決するためになされたものであり、スキャン回路の 故障及びその故障箇所を容易に特定することができ、もって、 LSIなどの回路テスト をスキャン回路の故障力も容易に区別して診断することができる回路素子、スキャン 回路、バウンダリスキャン回路、スキャン試験方法及びスキャン回路の異常箇所検出 方法を提供することを目的として!ヽる。 The present invention has been made to solve the above-described problems, and can easily identify a failure of a scan circuit and a failure portion thereof, so that a circuit test of an LSI or the like can be performed on the scan circuit. The purpose is to provide a circuit element, a scan circuit, a boundary scan circuit, a scan test method, and a method for detecting an abnormal part of the scan circuit, which can easily distinguish and diagnose faulty power.
課題を解決するための手段  Means for solving the problem
[0011] 上述した課題を解決するため、本発明の回路素子は、第一のレジスタと、第二のレ ジスタと、前記第一のレジスタ出力が入力される第一の入力端と、制御信号が入力さ れる第二の入力端を備え、前記制御信号に対応した信号を前記第二のレジスタに出 力するバッファ回路とを備えたことを特徴とする。 In order to solve the above-described problem, a circuit element of the present invention includes a first register, a second register, a first input terminal to which the first register output is input, a control signal And a buffer circuit for outputting a signal corresponding to the control signal to the second register.
[0012] また、本発明の回路素子は、縦列に接続される複数のレジスタと、隣り合って接続さ れるレジスタの間に設けられるバッファ回路と、前記バッファ回路に指示信号を供給 する指示信号発生部とを備え、前記バッファ回路は、前記指示信号に応じて上流に 接続されたレジスタ出力を下流に接続されたレジスタに出力するカゝ、あるいはバッフ ァ回路で発生した信号を前記下流に接続されたレジスタに出力することを特徴とする [0012] Further, the circuit element of the present invention provides a plurality of registers connected in a column, a buffer circuit provided between the registers connected adjacent to each other, and an instruction signal to the buffer circuit An instruction signal generation unit that outputs a register output connected upstream to a register connected downstream according to the instruction signal, or a signal generated by a buffer circuit. Output to a downstream connected register
[0013] また、本発明は、データをスキャンするスキャン回路であって、チェーン状に縦列し て設けられる複数のレジスタ（またはレジスタブロック）と、前記複数のレジスタのうち の少なくともいずれか一部のレジスタのデータ入力端子に接続され、当該レジスタの 前段のレジスタ力も入力される入力データ信号に代えてロー信号とハイ信号とを切り 替えて入力させる入力信号設定回路とを備えてなるものである。 [0013] Further, the present invention is a scan circuit that scans data, and includes a plurality of registers (or register blocks) provided in cascade in a chain shape, and at least a part of the plurality of registers. An input signal setting circuit is connected to the data input terminal of the register, and is switched to input a low signal and a high signal in place of the input data signal to which the previous register power of the register is input.
[0014] このスキャン回路において、前記入力信号設定回路は、ロー信号とハイ信号を選択 的に生成する二組の信号発生器と、前記信号発生器の発生信号の組み合わせによ り、前記入力データ信号に代えてロー信号とハイ信号とを切り替えてデータ入力端子 に入力するゲート回路とを備えていることを特徴とする。  [0014] In this scan circuit, the input signal setting circuit includes a combination of two signal generators that selectively generate a low signal and a high signal, and a signal generated by the signal generator, so that the input data A gate circuit that switches between a low signal and a high signal instead of a signal and inputs the signal to a data input terminal is provided.
[0015] また、このスキャン回路において、前記複数のレジスタを複数のレジスタからなる複 数のブロックに分けると共に、該ブロック間にバッファを挿入し、前記入力信号設定回 路は該バッファを入力端子として設けられることを特徴とする。  In the scan circuit, the plurality of registers are divided into a plurality of blocks each including a plurality of registers, a buffer is inserted between the blocks, and the input signal setting circuit uses the buffer as an input terminal. It is provided.
[0016] また、本発明は、内部回路に対して、該内部回路の診断解析を行うために設けられ るバウンダリスキャン回路であって、チェーン状に縦列して設けられる複数のレジスタ と、前記複数のレジスタのうちの少なくともいずれか一部のレジスタのデータ入力端 子に接続され、当該レジスタの前段のレジスタ力 入力される入力データ信号に代え てロー信号とハイ信号とを切り替えて入力させる入力信号設定回路とを備えてなるも のである。  [0016] Further, the present invention is a boundary scan circuit provided for performing diagnostic analysis of the internal circuit with respect to the internal circuit, and includes a plurality of registers provided in tandem in a chain shape; An input signal that is connected to the data input terminal of at least some of these registers and that switches between a low signal and a high signal instead of the input data signal that is input at the previous stage of the register. And a setting circuit.
[0017] また、本発明は、第一のレジスタに設定された情報を第二のレジスタにシフトするス キャン試験方法において、前記第一のレジスタと前記第二のレジスタとの間に設けら れた回路に制御信号を加えるステップと、前記制御信号に応じて、前記第一のレジス タに設定された情報あるいは前記回路で生成された情報を前記第二のレジスタに出 力するステップとを備えたことを特徴とする。  [0017] Further, the present invention provides a scan test method for shifting information set in the first register to the second register, and is provided between the first register and the second register. A step of adding a control signal to the circuit, and a step of outputting the information set in the first register or the information generated by the circuit to the second register according to the control signal. It is characterized by that.
[0018] また、本発明は、縦列に接続された複数のレジスタに順次情報をスキャンして回路 を試験するスキャン試験方法にぉ 、て、上流側レジスタと下流側レジスタとの間に接 続された回路力 情報を出力するステップと、前記出力された情報を順次下流にシフ トするステップと、前記出力された情報が前記回路力 正常に出力された力否かを判 別するステップとを備えたことを特徴とする。 [0018] Further, the present invention provides a circuit that sequentially scans information in a plurality of registers connected in a column. A step of outputting circuit force information connected between the upstream side register and the downstream side register, and a step of sequentially shifting the outputted information to the downstream side. And determining whether or not the output information is a normal output of the circuit force.
[0019] また、本発明は、複数のレジスタをチェーン状に縦列してデータをスキャンするスキ ヤン回路の異常箇所を検出するスキャン回路の異常箇所検出方法であって、前記複 数のレジスタのうちの少なくともいずれか一部のレジスタのデータ入力端子に、当該 レジスタの前段のレジスタ力も入力される入力データ信号に代えてロー信号とハイ信 号とを切り替えて入力させる強制信号入力ステップと、当該レジスタよりも後段のレジ スタカもの出力信号を前記入力させたロー信号とハイ信号とに対応させてスキャン回 路の異常箇所を判断する異常箇所判断ステップとを備えるものである。  [0019] Further, the present invention is a method for detecting an abnormal part of a scan circuit for detecting an abnormal part of a scan circuit that scans data by cascading a plurality of registers in a chain, and among the plurality of registers A forcible signal input step for causing a data input terminal of at least one of the registers to switch between a low signal and a high signal instead of an input data signal to which the register power of the previous stage of the register is also input, and the register And an abnormal point determination step for determining an abnormal point in the scan circuit in correspondence with the input low signal and high signal.
図面の簡単な説明  Brief Description of Drawings
[0020] [図 1]本発明の実施の形態 1を示すスキャン回路のブロック図である。  FIG. 1 is a block diagram of a scan circuit showing a first embodiment of the present invention.
[図 2]本発明の概要を示すブロック図である。  FIG. 2 is a block diagram showing an outline of the present invention.
[図 3]本発明の実施の形態における入力信号設定回路を示すブロック図である。 圆 4]第 1及び第 2信号発生回路の出力値と入力信号設定回路の出力値の関係を示 す図である。  FIG. 3 is a block diagram showing an input signal setting circuit in the embodiment of the present invention. [4] This is a diagram showing the relationship between the output values of the first and second signal generation circuits and the output value of the input signal setting circuit.
[図 5]実施の形態 1の動作を示すために、スキャン回路の故障箇所の一例を示す図 である。  FIG. 5 is a diagram showing an example of a faulty part of the scan circuit in order to show the operation of the first embodiment.
[図 6]実施の形態 1の動作を示すフローチャートである。  FIG. 6 is a flowchart showing the operation of the first embodiment.
[図 7]本発明の実施の形態 2のバウンダリスキャン回路を示すブロック図である。  FIG. 7 is a block diagram showing a boundary scan circuit according to a second embodiment of the present invention.
[図 8]従来のスキャン回路を示すブロック図である。  FIG. 8 is a block diagram showing a conventional scan circuit.
発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
[0021] 以下、本発明の実施の形態を図を用いて説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0022] 実施の形態 1. [0022] Embodiment 1.
図 1は本発明の実施の形態 1における全体構成を示すブロック図、図 2は本発明の 概要を示すブロック図、図 3は本発明の実施の形態における入力信号設定回路を示 すブロック図である。 [0023] 図 1に示すスキャン回路 100は、 LSI内にチェーン状に縦列して設けられる一つ又 は複数のレジスタからなるレジスタブロック l— l〜l—n (図示では n= 12)と、複数の レジスタブロックの各ブロック間に設けられ、その出力が後段側のレジスタブロック初 段のレジスタのデータ入力端子に接続される入力信号設定回路 P1〜P8とを備える FIG. 1 is a block diagram showing an overall configuration in Embodiment 1 of the present invention, FIG. 2 is a block diagram showing an outline of the present invention, and FIG. 3 is a block diagram showing an input signal setting circuit in the embodiment of the present invention. is there. A scan circuit 100 shown in FIG. 1 includes a register block l—l to l-n (n = 12 in the figure) composed of one or a plurality of registers provided in a chain in the LSI. Provided between each block of a plurality of register blocks, and provided with input signal setting circuits P1 to P8 whose outputs are connected to the data input terminals of the first register of the subsequent register block
[0024] そして、故障箇所診断時には、スキャン回路 100の初段のレジスタブロック 1—1の 入力端子に接続され、スキャン回路 100の設定値をシフトさせる設定値シフトイン回 路 10が例えば LSI外に備えられる。また、シフトアウトされた出力値を観測、判定する ための観測 (判定）回路又は装置 20が設けられる。 [0024] At the time of failure location diagnosis, a set value shift-in circuit 10 that is connected to the input terminal of the first stage register block 1-1 of the scan circuit 100 and shifts the set value of the scan circuit 100 is provided outside the LSI, for example. It is done. In addition, an observation (determination) circuit or device 20 for observing and judging the output value shifted out is provided.
[0025] なお、実施の形態では、図 1に示すように、各ブロック間に入力信号設定回路を設 ける必要はなぐ複数のブロック間の任意の位置に必要に応じて適宜設けることがで きる。例えば、スキャン回路の設計上の故障頻度等を考慮し、その頻度が高くなるよう な位置に設けるようにすることもできる。  In the embodiment, as shown in FIG. 1, it is not necessary to provide an input signal setting circuit between each block, and it can be provided as needed at an arbitrary position between a plurality of blocks. . For example, considering the failure frequency in the design of the scan circuit, it can be provided at a position where the frequency is high.
[0026] 本発明の概要を示す図 2においては、入力信号設定回路を構成するバッファを二 つのレジスタ (前段レジスタと後段レジスタ）間に挿入し、このバッファの制御信号によ りバッファの出力として「1」、 「0」、「入力値 (前段レジスタの出力）」を後段のレジスタ に出力するようにしたことを示して！/、る。  In FIG. 2 showing the outline of the present invention, a buffer constituting the input signal setting circuit is inserted between two registers (a front-stage register and a rear-stage register), and a buffer output is generated by a control signal of this buffer. Show that “1”, “0”, “input value (output of previous register)” is output to the subsequent register! /
[0027] 入力信号設定回路 P1〜P8のそれぞれは、図 3に示されるように、ロー（0)とハイ（1 )のいずれかの二値信号を発生することができる第 1信号発生回路 (第 1信号発生器 ) 5及び第 2信号発生回路 (第 2信号発生器) 6と、第 1信号発生回路 5及び第 2信号 発生回路 6による発生信号を指示設定するための発生信号指示回路 7とを備える。 発生信号指示回路 7は設定値シフトイン回路と協働して構成することもできるし、別個 独立に構成することもできる。  Each of the input signal setting circuits P1 to P8 is, as shown in FIG. 3, a first signal generating circuit that can generate a binary signal of either low (0) or high (1) ( (First signal generator) 5 and second signal generator circuit (second signal generator) 6, and generated signal instruction circuit 7 for indicating and setting the generated signals by the first signal generator circuit 5 and the second signal generator circuit 6 With. The generation signal indicating circuit 7 can be configured in cooperation with the set value shift-in circuit or can be configured separately.
[0028] また、入力信号設定回路 P1〜P8のそれぞれは、ゲート回路として、二入力端子を 有するアンド回路 8であって、その一方の入力端子に前段のレジスタブロックの出力 端子 (前段スキャン FFの出力） 12が接続され、その他方の入力端子に第 1信号発生 回路 5からの信号が否定されて (ノット回路を介して)入力されるアンド回路 8と、二入 力端子を有するオア回路 9であって、その一方の入力端子にアンド回路 8の出力端 子が接続され、その他方の入力端子に第 2信号発生回路 6からの信号が入力される オア回路 9とを備える。なお、このゲート回路の構成は、実施の形態における一例に 過ぎな 、ことは 、うまでもな 、。 [0028] Each of the input signal setting circuits P1 to P8 is an AND circuit 8 having two input terminals as a gate circuit, and one input terminal of the input signal setting circuits P1 to P8 is an output terminal of the previous stage register block (of the previous stage scan FF). Output) 12 is connected, the AND circuit 8 is input to the other input terminal with the signal from the first signal generation circuit 5 being negated (via the knot circuit), and the OR circuit 9 having two input terminals 9 And one of the input terminals is connected to the output terminal of the AND circuit 8. And an OR circuit 9 to which the signal from the second signal generating circuit 6 is input to the other input terminal. Note that the configuration of the gate circuit is merely an example in the embodiment, and of course.
[0029] そして、オア回路 9の出力端子が次段のレジスタブロックの入力端子 (次段のスキヤ ン FFの入力） 13に接続される構成を有している。 The output terminal of the OR circuit 9 is connected to the input terminal (input of the next-stage scan FF) 13 of the next-stage register block.
[0030] なお、発生信号指示回路は、 LSIの内部に構成するようにしている力 外部に構成 するようにしてちょい。 [0030] It should be noted that the generation signal instruction circuit should be configured outside the force that is configured inside the LSI.
[0031] 入力信号設定回路における第 1信号発生回路 5及び第 2信号発生回路 6による発 生信号の組み合わせによる入力信号設定回路の出力は、図 4に示される表のように なり、第 1信号発生回路 5及び第 2信号発生回路 6の発生信号が共にローの場合は、 前段のレジスタブロックの出力信号がそのまま次段のレジスタブロックへの入力信号 となる。  [0031] The output of the input signal setting circuit based on the combination of the signals generated by the first signal generating circuit 5 and the second signal generating circuit 6 in the input signal setting circuit is as shown in the table of FIG. When the generation signals of the generation circuit 5 and the second signal generation circuit 6 are both low, the output signal of the previous register block is directly used as the input signal to the next register block.
[0032] また、第 1信号発生回路 5及び第 2信号発生回路 6それぞれの発生信号がハイ及 びローの場合はロー信号が次段のレジスタブロックへ強制的に（前段のレジスタブ口 ックの出力信号にかかわらず)入力される。  [0032] When the generated signals of the first signal generating circuit 5 and the second signal generating circuit 6 are high and low, the low signal is forcibly sent to the register block of the next stage (the register block of the previous stage). Input) regardless of the output signal.
[0033] さらに、第 1信号発生回路 5及び第 2信号発生回路 6それぞれの発生信号が不定（ Don't care)及びノヽィの場合はノ、ィ信号が次段のレジスタブロックへ強制的に入力さ れる。 [0033] Further, when the generated signals of the first signal generating circuit 5 and the second signal generating circuit 6 are indefinite (don't care) and no, the no and i signals are forcibly sent to the next register block. Entered.
[0034] 以下、実施の形態における異常箇所検出動作について、図 5に X印で示す箇所に 異常 (故障)が生じた場合にっ 、て説明する。図 6は対応フローチャートを示して 、る  [0034] The abnormal location detection operation in the embodiment will be described below in the case where an abnormality (failure) occurs in the location indicated by X in FIG. Figure 6 shows the corresponding flowchart.
[0035] (ステップ S1) [0035] (Step S1)
まず、出力側に一番近い入力信号設定回路 P8で次段への出力として 0 (ロー）固 定値を発生させシフトし、入力信号設定回路 P8からスキャン回路の最終出力端まで のレジスタのビット数分シフトしたときの出力値を判定回路 20により判定し、それを観 測する。  First, the input signal setting circuit P8 closest to the output side generates a 0 (low) fixed value as an output to the next stage and shifts it. The number of bits in the register from the input signal setting circuit P8 to the final output terminal of the scan circuit The output value when shifted by the minute is judged by the judgment circuit 20 and observed.
[0036] (ステップ S 2) [0036] (Step S 2)
そして、その出力値が 0の場合は (ステップ S3)へ、出力値が 1 (ハイ）の場合は入力 信号設定回路 P8から最終出力端までの間に故障が存在することがわかる。この出力 値は入力させた信号に対応させて判定回路 20により自動的に判断するようにするこ とができる。そしてその結果は図 6にステップ S10で示されるように表示することができ る。 If the output value is 0, go to (Step S3), and if the output value is 1 (High), It can be seen that a fault exists between the signal setting circuit P8 and the final output terminal. This output value can be automatically determined by the determination circuit 20 in accordance with the input signal. The result can then be displayed as shown in step S10 in FIG.
[0037] すなわち、設定値シフトイン回路 10と発生信号指示回路 7と判定回路 20は相互に 協働しており、本実施の形態では、本動作説明で理解できるように、設定値シフトイン 回路 10の動作に連動して、最も後段側の入力信号設定回路 P8から初段側の P1に かけて順次動作させるように、各入力信号設定回路の発生信号指示回路 7が設定値 シフトイン回路 10からの信号パルスを計測し、その計測値に基づいて本動作説明が 成立するように、各入力信号設定回路の第 1信号発生回路 5と第 2信号発生回路 6の 発生信号の指示を行う。また、判定回路 20も設定値シフトイン回路 10の動作に連動 して、設定値シフトイン回路 10からの信号パルスを計測し、複数の入力信号設定回 路 P1〜P8のうち、どの入力信号設定回路が 0固定値を出力しているかを認識してお り、判定対象とする判定値をシフト数に対応させて認識できるように構成されている。  That is, the set value shift-in circuit 10, the generated signal instruction circuit 7 and the determination circuit 20 cooperate with each other, and in this embodiment, as can be understood from the description of the operation, the set value shift-in circuit The generated signal instruction circuit 7 of each input signal setting circuit is set to the set value shift-in circuit 10 so that the input signal setting circuit P8 on the most downstream side is operated sequentially from the input signal setting circuit P8 on the most downstream side to P1 on the first stage side. The first signal generation circuit 5 and the second signal generation circuit 6 of each input signal setting circuit are instructed so that the description of the operation is established based on the measured value. In addition, the judgment circuit 20 measures the signal pulse from the set value shift-in circuit 10 in conjunction with the operation of the set value shift-in circuit 10, and selects which input signal setting among the plurality of input signal setting circuits P1 to P8. It is configured to recognize whether the circuit outputs a fixed value of 0 and to recognize the determination value to be determined corresponding to the number of shifts.
[0038] なお、力かる構成における具体的な論理回路の構成については設計事項に過ぎ ず、ここでの説明は省略する。  It should be noted that the specific logic circuit configuration in the powerful configuration is only a design item and will not be described here.
[0039] (ステップ S3)  [0039] (Step S3)
最終出力端に一番近い入力信号設定回路 P8で固定値 1を発生させシフトし、入力 信号設定回路 P8から最終出力端までのレジスタのビット数分シフトしたときの出力値 を判定回路 20により判定し、それを観測する。  The decision value 20 determines the output value when the input signal setting circuit P8 closest to the final output terminal generates and shifts the fixed value 1 and shifts by the number of register bits from the input signal setting circuit P8 to the final output terminal. And observe it.
[0040] (ステップ S4)  [0040] (Step S4)
出力値力^の場合は (ステップ S5)へ、出力値が 0の場合は入力信号設定回路 P8 からスキャン回路の最終出力端までの間に故障が存在することがわかる。この判定は 上述したように判定回路 20により自動的に判定し表示することができる (ステップ S10 If the output value is ^, go to (Step S5). If the output value is 0, it can be seen that a fault exists between the input signal setting circuit P8 and the final output terminal of the scan circuit. This determination can be automatically determined and displayed by the determination circuit 20 as described above (step S10).
) o ) o
[0041] (ステップ S5)  [0041] (Step S5)
最終出力端側から二番目の入力信号設定回路 P7で固定値 0を発生させシフトし、 入力信号設定回路 P7から最終出力端までのレジスタのビット数分シフトしたときの出 力値を判定回路 20で判定し、それを観測する。 The second input signal setting circuit P7 from the final output end generates a fixed value of 0 and shifts, and the output when shifting by the number of register bits from the input signal setting circuit P7 to the final output end The force value is judged by the judgment circuit 20 and observed.
[0042] (ステップ S6) [0042] (Step S6)
出力値力^の場合は (ステップ S 7)へ、出力値が 1の場合は入力信号設定回路 P7 力も入力信号設定回路 P8までの間に故障が存在することがわかる。これも上述した ように自動的に判定され表示されることができる (ステップ S11)。  If the output value is ^, go to (Step S7). If the output value is 1, there is a failure between the input signal setting circuit P7 and the input signal setting circuit P8. This can also be automatically determined and displayed as described above (step S11).
[0043] (ステップ S 7) [0043] (Step S 7)
最終出力端側から二番目の入力信号設定回路 P7で固定値 1を発生させシフトし、 入力信号設定回路 P7から最終出力端までのレジスタのビット数分シフトしたときの出 力値を判定回路 20で判定し、それを観測する。  The second input signal setting circuit P7 from the final output end generates a fixed value 1 and shifts, and the output value when the input signal setting circuit P7 shifts by the number of register bits from the final output end is judged 20 Judgment and observe it.
[0044] (ステップ S8) [0044] (Step S8)
出力値力^の場合は (ステップ S9)へ、出力値が 0の場合は入力信号設定回路 P7 力も入力信号設定回路 P8までの間に故障が存在することがわかる。この結果は (ス テツプ S 11)で表示される。  If the output value is ^, go to (Step S9). If the output value is 0, it can be seen that there is a fault between the input signal setting circuit P7 and the input signal setting circuit P8. This result is displayed in (Step S11).
[0045] (ステップ S 9) [0045] (Step S 9)
以下、同様に故障が検出されるまで、固定値 0または 1を発生させる入力信号設定 回路の位置を P1の方へ順次移動させていくことにより、故障箇所を検出することがで きる。図 5の場合、入力信号設定回路 P6で固定値 0を発生させてシフトする試験判 定は肯定であるが、 1を発生させてシフトする試験は Xの場所で 0固定となるため、 1 が観測できず試験判定は否定される。これにより故障個所は入力信号設定回路 P6と 入力信号設定回路 P7の間であることがわ力る。  Similarly, until the failure is detected, the position of the failure can be detected by sequentially moving the position of the input signal setting circuit that generates the fixed value 0 or 1 toward P1. In the case of Fig. 5, the test decision to shift by generating a fixed value of 0 in the input signal setting circuit P6 is affirmative, but the test to shift by generating 1 is fixed at 0 at the location of X, so 1 is The test judgment is denied because it cannot be observed. This indicates that the fault is between the input signal setting circuit P6 and the input signal setting circuit P7.
[0046] 実施の形態 2. [0046] Embodiment 2.
図 7は、本発明の実施の形態 2として、バウンダリスキャン回路への適用例を示すブ ロック図である。  FIG. 7 is a block diagram showing an application example to the boundary scan circuit as the second embodiment of the present invention.
[0047] ノゥンダリスキャン (BS)回路により端子および内部回路の解析を行うことはよく知ら れて 、るが、この手法もバウンダリスキャン回路自身が正常に動作して 、ることが前提 である。  [0047] Although it is well known that the terminal and internal circuit are analyzed by the nounscan (BS) circuit, this method is also premised on the normal operation of the boundary scan circuit itself.
[0048] 本発明は内部スキャンのみではなぐバウンダリスキャンに適用することも可能であ り、図 7に示すように LSIの内部回路 30周辺に周回状に設けられたレジスタ（バウン ダリスキャンレジスタ) BSの途中の適所にロー又はノ、ィを発生する入力信号設定回 路 P1〜P7を設けることにより、自己の異常箇所を容易に検出することが可能なバウ ンダリスキャン回路を提供することができる。この入力信号設定回路は実施の形態 1 で説明したものと全く同じ構成をとることができる。 The present invention can also be applied to boundary scans that are not limited to internal scans. As shown in FIG. 7, a register (boundary) is provided around the internal circuit 30 of the LSI. Provide a boundary scan circuit that can easily detect an abnormal location by providing input signal setting circuits P1 to P7 that generate low, noise, or noise at appropriate locations in the middle of the BS. can do. This input signal setting circuit can have the same configuration as that described in the first embodiment.
産業上の利用可能性 Industrial applicability
本発明によれば、スキャン回路の故障及びその故障箇所を容易に特定することが でき、もって、 LSIなどの回路テストをスキャン回路の故障力も容易に区別して診断す ることができると!/、う効果を奏する。  According to the present invention, it is possible to easily identify the failure of the scan circuit and the location of the failure, and to easily diagnose the circuit test of the LSI etc. by distinguishing the failure power of the scan circuit! /, Has an effect.

Claims

請求の範囲 The scope of the claims
[1] 第一のレジスタと、  [1] First register,
第二のレジスタと、  A second register;
前記第一のレジスタ出力が入力される第一の入力端と、制御信号が入力される第 二の入力端を備え、前記制御信号に対応した信号を前記第二のレジスタに出力する ノ ッファ回路と、  A first circuit for inputting the first register output and a second input terminal for inputting a control signal, and outputs a signal corresponding to the control signal to the second register When,
を備えたことを特徴とする回路素子。  A circuit element comprising:
[2] 縦列に接続される複数のレジスタと、  [2] Multiple registers connected in columns,
隣り合って接続されるレジスタの間に設けられるノ ッファ回路と、  A notch circuit provided between adjacently connected registers;
前記バッファ回路に指示信号を供給する指示信号発生部とを備え、  An instruction signal generator for supplying an instruction signal to the buffer circuit;
前記バッファ回路は、前記指示信号に応じて上流に接続されたレジスタ出力を下 流に接続されたレジスタに出力する力、あるいはバッファ回路で発生した信号を前記 下流に接続されたレジスタに出力することを特徴とする回路素子。  The buffer circuit outputs a force that outputs a register output connected upstream to a register connected downstream in response to the instruction signal, or outputs a signal generated in the buffer circuit to the register connected downstream. A circuit element characterized by the above.
[3] データをスキャンするスキャン回路であって、 [3] A scan circuit for scanning data,
チェーン状に縦列して設けられる複数のレジスタと、  A plurality of registers arranged in a chain in a column;
前記複数のレジスタのうちの少なくともいずれか一部のレジスタのデータ入力端子 に接続され、当該レジスタの前段のレジスタ力 入力される入力データ信号に代えて ロー信号とハイ信号とを切り替えて入力させる入力信号設定回路と  An input connected to a data input terminal of at least some of the plurality of registers and switching between a low signal and a high signal instead of an input data signal input to the register power of the previous stage of the register. Signal setting circuit and
を備えてなるスキャン回路。  A scan circuit comprising:
[4] 請求項 3に記載のスキャン回路において、 [4] In the scan circuit according to claim 3,
前記入力信号設定回路は、ロー信号とハイ信号を選択的に生成する二組の信号 発生器と、前記信号発生器の発生信号の組み合わせにより、前記入力データ信号 に代えてロー信号とハイ信号とを切り替えてデータ入力端子に入力するゲート回路と を備えて 、ることを特徴とするスキャン回路。  The input signal setting circuit includes two sets of signal generators that selectively generate a low signal and a high signal, and a combination of the generation signals of the signal generator, and a low signal and a high signal instead of the input data signal. And a gate circuit for switching to input to the data input terminal.
[5] 請求項 3に記載のスキャン回路において、 [5] The scan circuit according to claim 3,
前記複数のレジスタを複数のレジスタ力 なる複数のブロックに分けると共に、該ブ ロック間にバッファを挿入し、前記入力信号設定回路は該バッファを入力端子として 設けられることを特徴とするスキャン回路。 A scan circuit, wherein the plurality of registers are divided into a plurality of blocks each having a plurality of register powers, a buffer is inserted between the blocks, and the input signal setting circuit is provided with the buffer as an input terminal.
[6] 内部回路に対して、該内部回路の診断解析を行うために設けられるバウンダリスキヤ ン回路であって、 [6] A boundary scan circuit provided for the internal circuit to perform diagnostic analysis of the internal circuit,
チェーン状に縦列して設けられる複数のレジスタと、  A plurality of registers arranged in a chain in a column;
前記複数のレジスタのうちの少なくともいずれか一部のレジスタのデータ入力端子 に接続され、当該レジスタの前段のレジスタ力 入力される入力データ信号に代えて ロー信号とハイ信号とを切り替えて入力させる入力信号設定回路と  An input connected to a data input terminal of at least one of the plurality of registers and switching between a low signal and a high signal instead of an input data signal input to the register power of the previous stage of the register. Signal setting circuit and
を備えてなるバウンダリスキャン回路。  A boundary scan circuit comprising:
[7] 第一のレジスタに設定された情報を第二のレジスタにシフトするスキャン試験方法に おいて、 [7] In the scan test method that shifts the information set in the first register to the second register,
前記第一のレジスタと前記第二のレジスタとの間に設けられた回路に制御信号を加 免るステップと、  Exchanging a control signal to a circuit provided between the first register and the second register;
前記制御信号に応じて、前記第一のレジスタに設定された情報あるいは前記回路 で生成された情報を前記第二のレジスタに出力するステップと、  Outputting the information set in the first register or the information generated by the circuit to the second register in response to the control signal;
を備えたことを特徴とするスキャン試験方法。  A scan test method characterized by comprising:
[8] 縦列に接続された複数のレジスタに順次情報をスキャンして回路を試験するスキャン 試験方法において、 [8] In a scan test method for testing a circuit by sequentially scanning information into a plurality of registers connected in a column,
上流側レジスタと下流側レジスタとの間に接続された回路力 情報を出力するステ ップと、  A step of outputting circuit force information connected between the upstream register and the downstream register;
前記出力された情報を順次下流にシフトするステップと、  Sequentially shifting the output information downstream;
前記出力された情報が前記回路力 正常に出力された力否かを判別するステップ と、  Determining whether or not the output information is the normal output of the circuit force; and
を備えたことを特徴とするスキャン試験方法。  A scan test method characterized by comprising:
[9] 複数のレジスタをチェーン状に縦列してデータをスキャンするスキャン回路の異常箇 所を検出するスキャン回路の異常箇所検出方法であって、 [9] A method for detecting an abnormal portion of a scan circuit for detecting an abnormal portion of a scan circuit that scans data by cascading a plurality of registers in a chain,
前記複数のレジスタのうちの少なくともいずれか一部のレジスタのデータ入力端子 に、当該レジスタの前段のレジスタ力 入力される入力データ信号に代えてロー信号 とハイ信号とを切り替えて入力させる強制信号入力ステップと、  Forced signal input that switches between a low signal and a high signal instead of an input data signal input to the register input of the previous stage of the register at the data input terminal of at least some of the plurality of registers Steps,
当該レジスタよりも後段のレジスタからの出力信号を前記入力させたロー信号とハイ 信号とに対応させてスキャン回路の異常箇所を判断する異常箇所判断ステップと を備えるスキャン回路の異常箇所検方法。 The input low signal and the high signal output from the register following the register An abnormal part detection method for a scan circuit, comprising: an abnormal part determination step for determining an abnormal part of the scan circuit corresponding to a signal.
PCT/JP2006/300812 2006-01-20 2006-01-20 Circuit element, scan circuit, boundary scan circuit, scan test method and method for detecting fault location in scan circuit WO2007083381A1 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000009800A (en) * 1998-06-19 2000-01-14 Sharp Corp Scan test circuit and semiconductor device equipped with the same and scan testing method therefor
JP2004361351A (en) * 2003-06-06 2004-12-24 Sharp Corp Scan path circuit, and method of testing logic circuit and integrated circuit equipped with the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000009800A (en) * 1998-06-19 2000-01-14 Sharp Corp Scan test circuit and semiconductor device equipped with the same and scan testing method therefor
JP2004361351A (en) * 2003-06-06 2004-12-24 Sharp Corp Scan path circuit, and method of testing logic circuit and integrated circuit equipped with the same

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