WO2007017399A1 - Vorrichtung und verfahren zur konfiguration einer halbleiterschaltung - Google Patents
Vorrichtung und verfahren zur konfiguration einer halbleiterschaltung Download PDFInfo
- Publication number
- WO2007017399A1 WO2007017399A1 PCT/EP2006/064751 EP2006064751W WO2007017399A1 WO 2007017399 A1 WO2007017399 A1 WO 2007017399A1 EP 2006064751 W EP2006064751 W EP 2006064751W WO 2007017399 A1 WO2007017399 A1 WO 2007017399A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- semiconductor circuit
- functional units
- unit
- comparison
- faulty
- Prior art date
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1629—Error detection by comparing the output of redundant processing systems
- G06F11/165—Error detection by comparing the output of redundant processing systems with continued operation after detection of the error
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
Definitions
- ECC error correcting code
- check bits are also stored with this. The check bits are such that, if only one bit (or a known maximum number of bits) is corrupted, the error is caused by a
- Error in execution units is not a realistic, cost-effective concept for tolerating permanent errors known.
- a first object of the invention to improve the yield in the production process of .mu.Co of the semiconductor components, in particular by allowing use for components with defective functional units.
- a second object of the invention is to increase the availability of components in operation. For this purpose, means are to be made available which make it possible to identify faulty execution units (eg cores, ALUs, processors) in a component, and a "graceful degradation" or run-flat operation of a system that does this Component used, allow.
- faulty execution units eg cores, ALUs, processors
- a semiconductor circuit for example a ⁇ C, which contains at least two identical or similar functional units.
- a test program for example in a switching and comparison unit, which compares the output signals of a functional unit with the output signals of at least one further functional unit and / or with further reference values. It is stored in a memory element, which functional units are faulty.
- These functional units are, for. B. deactivated by the switching and comparison unit or via an interruption device. The device, while containing faulty functional units, is still usable and functional.
- a method for configuring a semiconductor circuit having at least two identical or similar functional units, characterized net, that in case of an error in at least one of the same or similar functional units, the faulty unit is identified and deactivated.
- a method is described, characterized in that the configuration of the semiconductor circuit as a process step of a manufacturing, test, diagnostic or
- a method is described, characterized in that in each case at least two of the same or similar functional units of the semiconductor circuit can be switched to an operating mode in which these functional units perform the same functions, commands, program segments or programs and a comparison of the output signals of these functional units is possible.
- a method is described, characterized in that the initiation of the switching and / or the mutual comparison of the output signals of at least two functional units and / or the comparison of output signals with reference values can be carried out with external production, test or diagnostic devices, which are not part of the semiconductor circuit.
- a method is described, characterized in that a configuration status and / or error status is formed for at least the functional units of the semiconductor circuit identified as faulty.
- a method is described, characterized in that a deactivation of a functional unit takes place in that information about the configuration status or the error status of this functional unit are stored in a memory device such that they are read during the initialization and / or operation of the semiconductor system and the stored information is processed in such a way that it is not possible to use the unit identified as defective during operation.
- a method is described, characterized in that the determination of the configuration status or the error status of at least one functional unit of the semiconductor circuit and / or the storage of this information in a memory device can be performed by external manufacturing, test or diagnostic facilities that are not part of the semiconductor circuit.
- a method is described, characterized in that a unit identified as defective is irreversibly deactivated.
- a method is described, characterized in that electrical connections to or between functional units of the semiconductor circuits are interrupted.
- a method is described, characterized in that an interruption of electrical connections on the semiconductor circuit is achieved by mechanical action on the semiconductor circuit.
- a method is described, characterized in that an interruption of electrical connections on the semiconductor circuit is achieved by chemical action on the semiconductor circuit.
- a method is described, characterized in that an interruption of electrical connections on the semiconductor circuit is achieved by optical action on the semiconductor circuit.
- a method is described, characterized in that an interruption of electrical connections on the semiconductor circuit by electrical action on the semiconductor circuit is achieved.
- a method is described, characterized in that the deactivation of a functional unit of external manufacturing, test or diagnostic facilities is performed
- an apparatus for configuring a semiconductor circuit is described with at least two identical or similar functional units, characterized in that there are means to identify an error in at least one of the same or similar functional units and to deactivate the defective unit.
- a device is included, characterized in that switching means are provided with which at least two of the same or similar functional units of the semiconductor circuit can be switched to an operating mode in which these functional units have the same functions, commands, program segments or
- a device is advantageously included, characterized in that comparison means are provided with which a comparison of the output signals of at least two furc tion units is possible.
- a device is included, characterized in that comparison means are provided with which a comparison of the output signals of at least one functional unit with reference values is possible.
- a device is included, characterized in that storage means are present in which reference values for the identification of faulty functional units are stored.
- a device is included, characterized in that the comparison means and / or storage means are at least partially present on the semiconductor circuit.
- a device is included, characterized in that there are receiving means on the semiconductor circuit with which signals from manufacturing, testing,
- a device is included, characterized in that there are means for storing data in which at least one piece of information about the configuration is available. figurationsstatus or the error status of functional units can be stored so that they can be read during initialization and / or operation of the semiconductor system.
- a device is included, characterized in that means are provided which can read out and process memory information and permit or prevent the use of the unit identified as defective in operation depending on the memory information.
- a device is included, characterized in that the means for
- Storage of data is non-volatile storage means.
- a device is included, characterized in that the storage means are designed so that a write access to the storage means of manufacturing, testing, diagnostic and maintenance facilities, which is not mounted on the semiconductor circuit, can take place.
- a device is included, characterized in that switching means are provided for the reversible deactivation of a functional unit, and these means are part of the semiconductor circuit or part of the component on which the semiconductor circuit is implemented.
- a device is included, characterized in that means are provided for irreversibly deactivating a functional unit.
- FIG. 1 describes a general switching component with a switching logic and processing logic
- FIG. 2 describes the connection of the switching component with a memory element
- FIG. 3 describes a basic process for increasing the yield using a storage element
- FIG. 4 describes a principle method for increasing availability, graceful degradation and emergency operation.
- FIG. 5 describes the connection of the switching component with an influencing component
- FIG. 6 describes a basic process for increasing the yield under
- FIG. 7 describes the structure of a possible memory element
- An execution unit can in the following both a processor / core / CPU, as well as a
- FPU Floating Point Unit
- DSP Digital Signal Processor
- ALU Arimetic logical Unit
- n signals N 140,..., N14n go to the switching and comparison component N100. This can generate up to n output signals N160, ..., N16n from these input signals.
- the "pure perfomance mode” all the signals N14i are directed to the corresponding output signals N16i.
- the "pure comparison mode” all of them are passed
- N100 contains the logical component of a switching logic N10. It The first task of the switching logic is to determine which inputs are switched to no output, ie which inputs are ignored, remain without consequences or are inactive. This function of the switching logic is often referred to below as the first function of the switching logic. Furthermore, switching logic Nl 10 determines how many output signals there are and which of the input signals contribute to which of the output signals. An input signal can contribute at most to exactly one output signal. This function of the switching logic is often referred to below as the second function of the switching logic.
- Switching logic defines a function that assigns to each element of the set ⁇ N140, ..., N14n ⁇ an element of the set ⁇ N160, ..., N16n ⁇ . With the blocking of individual input channels, more generally, the switching logic defines a function which assigns to each element of a fixed subset of ⁇ N140, ..., N14n ⁇ (the unlocked signals) an amount of the quantity ⁇ N 160, .. ., N 16n ⁇ .
- the processing logic N 120 determines to each of the outputs N16i how the inputs contribute to that output signal.
- the output N160 is generated by the signals N141, ..., N14m.
- a first possibility is to compare all signals and to detect an error in the presence of at least two different values, which can be optionally signaled.
- a second possibility is to make a k out of m selection (k> m / 2). This can be realized by using comparators.
- an error signal can be generated if one of the signals is detected as deviating.
- a possibly different error signal can be generated if all three signals are different.
- a third possibility is to supply these values to an algorithm.
- This may be, for example, the formation of an average, a median, or the use of a Fault Tolerant Algorithm (FTA).
- FTA Fault Tolerant Algorithm
- Such an FTA is based on eliminating extreme values of the input values and performing a kind of averaging over the remaining values. This averaging can be done over the entire set of residual values, or preferably over a subset that is easy to form in HW. In this case, it is not always necessary to actually compare the values. For example, averaging only adds and divides, FTM, FTA, or median require partial sorting. If necessary, an error signal can optionally also be output at sufficiently large extreme values.
- the task of the processing logic is thus to determine the exact shape of the comparison operation for each output signal - and thus also for the associated input signals. This is referred to below as the second function of the processing logic.
- the possible identification of faulty execution units which is usually possible in the following is referred to below as the first function of the processing logic.
- the combination of the information of the switching logic Nl 10 (i.e., the above mentioned function) and the processing logic (i.e., the determination of the comparison operation per output signal, i.e., per function value) is the mode information and sets the mode.
- This information is, of course, in the general case polyvalent, i. not just about a logical one
- Switching from a performance mode to a comparison mode is characterized in the general case by the fact that execution units that are displayed in the performance mode on different outputs are mapped in the compare mode to the same output. This is preferably realized in that there is a subsystem of execution units in which in the performance mode, all input signals N14i to be considered in the subsystem are switched directly to corresponding output signals N16i, while in comparison mode they are all switched to on
- the processing logic N 120 makes it possible to compare signals of different execution units. By a suitable comparison one can identify faulty execution units. This is possible if you use a sufficiently bug-covering test program. If necessary, external means of identification can also be used.
- fault tolerance can increase the yield, as well as faulty components can be used as long as the number of still correctly working execution units is large enough. This depends on the application.
- switching and comparison unit One possible logical form of the switching and comparison unit is described above. While it is advantageous for the application of the invention described herein, it is not necessary that the component exist as such and that the named sub-components switching and processing logic exist.
- a fiducial component can be identified.
- a preferred option is to have all execution units execute the same program in parallel. Preferably, but not necessarily, this can be realized by operating the execution units in a lockstep mode or else with a fixed clock or phase offset. Through a suitable comparison, a majority decision can be used to identify a potentially present defective component.
- the results of this program can additionally be compared with the previously known results by means of an external unit (Watdendag, other ⁇ C, test device, ASIC).
- the test program must be designed in such a way that an error is most likely to have an effect.
- an error model eg stuck-at model
- a portion of the application code may be run, or a complete command test.
- this may correspond to a test program today, which is limited to the execution units. But you can also link this with a common today band test and test only those components with this program, which have already failed by the first band end test.
- This last procedure has the particular advantage that only components subjected to an additional process step who otherwise belong to the committee. Every component that was obtained through this "rescue step" directly increases the yield of the manufacturing process.
- a non-volatile storage element is preferably used. This then stores which execution units are inactive.
- FIG. 2 shows the function of this memory element.
- the elements N510, N520, N54i, N56i of the switching and comparing unit N500 in Fig. 2 have the same functions as the elements NI10, N120, N14i, N16i of the switching and comparing unit N100 in Fig. 1.
- a memory element N530 is shown .
- the processing logic N520 sends the information about the identified as faulty
- Execution units to the memory element N530 This can be accessed by the N510 switching logic and the first function of the switching logic so that the elements marked as inactive by N530 actually become inactive.
- the memory element may be within the switching and comparison unit, but it may also be outside, even outside the device.
- the switching and comparison unit may also be outside, even outside the device.
- an external element is conceivable because then a more extensive test using the periphery may possibly be used.
- a first step N600 identification step
- the identification uses the first function of the processing logic N520 and thus the test program.
- the second step N610 storage step
- the error information is stored. The corresponding
- the switching logic N510 uses the information from N530 and uses the first function of the switching logic to configure the outputs of the execution units according to the required activity and passivity. Center. It should be emphasized that although this can optionally be done by SW, in a preferred application the configuration is not exercised by SW control here.
- test expires not only at the end of the tape but during operation (for example, in an initialization phase or even during normal operation), it is possible that faults which do not arise during operation but during operation are detected.
- the second function of the switching logic to link the active execution units together in operation
- the second function of the processing logic to make a comparison for the signals connected to an output
- error-free execution units are marked as inactive, it is possible to exchange a unit identified as faulty for a faultless but inactive unit when an error occurs during operation.
- information is preferably stored in the memory element N530 as to whether the execution unit is only inactive or whether it is also faulty.
- FIG. 7 describes a possible structure of a memory element 0100 (corresponds to N530). It contains a first memory area Ol 10, in which there are, preferably according to the number of execution units, memory locations 0120, ..., O12n. Each memory location is preferably realized via at least one bit. The number or address of the memory location O12i is uniquely linked to the number or identification of an execution unit. For example, a bit in 0120 that is set to 0 indicates that the associated execution unit is active. If set to 1, the associated execution unit should be inactive. This information may be fault tolerant or associated with other information in the storage locations 0120, ..., O12n However, the basic information content related to this application remains the same.
- a second memory area 0140 in which there are memory locations 0130,..., O13n, preferably corresponding to the number of execution units.
- Each memory location is preferably realized via at least one bit.
- the number or address of the memory location O13i is uniquely linked to the number or identification of an execution unit. For example, a bit in 0130 that is set to 0 indicates that the associated execution unit is healthy. If it is set to 1, it means that the associated execution unit is faulty.
- This information can be fault-tolerant or linked to further information in the memory locations 0130,..., O13n, but the basic information content related to this application always remains the same.
- this memory area can not be described or only under special circumstances or in a special way, so that it is ensured that an execution unit once marked as defective is not erroneously marked as error-free.
- Another way to use the invention is to enable graceful degradation and limp home modes.
- step N700 error coverage
- step N700 error coverage
- This can be z. B. done by using a test program. But if the system is in a compare mode, like ore. B. can be set via the second functions of the processing logic and the switching logic, such error detection is possible even in normal operation, ie the application software acts as a test program. This is particularly advantageous for two reasons: on the one hand, you do not need a dedicated test program, on the other hand, all errors of the execution units that have any effect are discovered in this way.
- step N705 a check is made as to whether a faulty execution unit can already be identified by the existing configuration of switching and processing logic. If so, steps N710 (Fault Detection Configuration) and N720 (Identification Step) are already completed, and it goes directly to Step N730. This is the case, for example, when the error occurs in a subsystem in which the signals from 3 execution units are compared. If this is not the case (in step N705) (for example, if an error is detected in a subsystem of two execution units running in a compare mode), a configuration that allows error identification should first be selected in step N710.
- the SW part which has disclosed the error is reused as the test program, but a dedicated test program can also be used.
- the first function of the processing logic then makes it possible to execute step N720 and to identify the faulty execution unit Alternatively, however, another method of identification may be chosen: for example, one of the suspected candidates is taken and coupled to another error-free execution unit. If no error is identified, another execution unit is faulty be closed this execution unit.
- a fundamentally different way of using the idea of this invention is to dispense with the memory element and use other means to disable potentially defective execution units to be reliably and irreversibly disabled. This can be done by influencing (for example separation or connection) of lines in the component.
- FIG. 5 shows the function of this influencing component.
- N810, N820, N84i, N86i of the switching and comparing unit N800 in Fig. 5 have the same functions as the elements NI10, N120, N14i, N16i of the switching and comparing unit N100 in Fig. 1.
- an influencing component N830 is shown.
- the processing logic N820 sends the information about the execution units identified as faulty to the influencing component N830. This has means, as enumerated above, to influence lines or functional groups in the component so that execution units are deactivated.
- N830 may be a component within the device, controller, or system, but N830 may also be a machine in the manufacturing process or a human operator of such a machine. It is also possible that this component in the
- the corresponding information can still be given to the switching logic so that it performs the first function in such a way that the elements marked as inactive by N830 actually become inactive.
- a first step N900 identification step
- the identification uses the first function of the processing logic N820 and thus the test program.
- the error information is given by the processing logic N820 to the influencing component N830.
- the influence component N830 uses this information in order to use the means at its disposal to influence the lines or functional groups in the component in such a way that the faulty components are inactive.
- the switching logic N810 uses the information and uses the first logic circuitry to configure the outputs of the execution units according to the required activity and passivity.
- the advantageous methods and devices can also be applied to further components of a semiconductor circuit, such as, for example, semiconductor devices.
- a semiconductor circuit such as, for example, semiconductor devices.
- analog / digital converters, timer modules, interrupt controllers, communication controllers or control units are applied.
- the totality of these components of a semiconductor circuit is summarized under the term functional units.
- the invention described herein is used with ECC protection for other memory elements.
- ECC protection for other memory elements.
- a highly available device is created in which both memory and execution units are designed to be fault-tolerant, thus making it possible to maximize both the yield and to ensure optimum availability during operation.
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- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Hardware Redundancy (AREA)
- Semiconductor Integrated Circuits (AREA)
- Logic Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/990,095 US20100295571A1 (en) | 2005-08-08 | 2006-07-27 | Device and Method for Configuring a Semiconductor Circuit |
EP06778034A EP1917591A1 (de) | 2005-08-08 | 2006-07-27 | Vorrichtung und verfahren zur konfiguration einer halbleiterschaltung |
JP2008525531A JP2009514064A (ja) | 2005-08-08 | 2006-07-27 | 半導体回路のコンフィギュレーション装置およびコンフィギュレーション方法 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102005037236A DE102005037236A1 (de) | 2005-08-08 | 2005-08-08 | Vorrichtung und Verfahren zur Konfiguration einer Halbleiterschaltung |
DE102005037236.8 | 2005-08-08 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2007017399A1 true WO2007017399A1 (de) | 2007-02-15 |
Family
ID=37547047
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2006/064751 WO2007017399A1 (de) | 2005-08-08 | 2006-07-27 | Vorrichtung und verfahren zur konfiguration einer halbleiterschaltung |
Country Status (9)
Country | Link |
---|---|
US (1) | US20100295571A1 (de) |
EP (1) | EP1917591A1 (de) |
JP (1) | JP2009514064A (de) |
KR (1) | KR20080032166A (de) |
CN (1) | CN101238445A (de) |
DE (1) | DE102005037236A1 (de) |
RU (1) | RU2008108473A (de) |
TW (1) | TW200725254A (de) |
WO (1) | WO2007017399A1 (de) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2207097A1 (de) * | 2009-01-07 | 2010-07-14 | Robert Bosch GmbH | Verfahren und Vorrichtung zum Betreiben eines Steuergerätes |
US9552241B2 (en) | 2011-11-10 | 2017-01-24 | Fujitsu Limited | Information processing apparatus, method of information processing, and recording medium having stored therein program for information processing |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11424621B2 (en) | 2020-01-28 | 2022-08-23 | Qualcomm Incorporated | Configurable redundant systems for safety critical applications |
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WO1998044416A1 (en) * | 1997-04-02 | 1998-10-08 | General Dynamics Information Systems, Inc. | Fault tolerant computer system |
WO2001046806A1 (en) * | 1999-12-21 | 2001-06-28 | Intel Corporation | Firmware mechanism for correcting soft errors |
US20040078715A1 (en) * | 2000-05-18 | 2004-04-22 | Vaeth Joachim | Peripheral component with high error protection for stored programmable controls |
US20050023656A1 (en) * | 2002-08-08 | 2005-02-03 | Leedy Glenn J. | Vertical system integration |
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JPS58127242A (ja) * | 1982-01-25 | 1983-07-29 | Nec Corp | 論理回路 |
JPH08148573A (ja) * | 1994-11-21 | 1996-06-07 | Hitachi Ltd | 半導体装置 |
US5732209A (en) * | 1995-11-29 | 1998-03-24 | Exponential Technology, Inc. | Self-testing multi-processor die with internal compare points |
JPH09325946A (ja) * | 1996-06-05 | 1997-12-16 | Toshiba Corp | マルチプロセッサのテスト回路 |
JP3142801B2 (ja) * | 1997-09-04 | 2001-03-07 | 松下電器産業株式会社 | 半導体集積回路の検査方法、プローブカード及びバーンイン用ボード |
US6452411B1 (en) * | 1999-03-01 | 2002-09-17 | Formfactor, Inc. | Efficient parallel testing of integrated circuit devices using a known good device to generate expected responses |
US6550020B1 (en) * | 2000-01-10 | 2003-04-15 | International Business Machines Corporation | Method and system for dynamically configuring a central processing unit with multiple processing cores |
US6798225B2 (en) * | 2002-05-08 | 2004-09-28 | Formfactor, Inc. | Tester channel to multiple IC terminals |
US6812691B2 (en) * | 2002-07-12 | 2004-11-02 | Formfactor, Inc. | Compensation for test signal degradation due to DUT fault |
KR100688517B1 (ko) * | 2005-01-11 | 2007-03-02 | 삼성전자주식회사 | 전압공급유닛 분할을 통한 반도체 소자의 병렬검사 방법 |
US7557592B2 (en) * | 2006-06-06 | 2009-07-07 | Formfactor, Inc. | Method of expanding tester drive and measurement capability |
US7888955B2 (en) * | 2007-09-25 | 2011-02-15 | Formfactor, Inc. | Method and apparatus for testing devices using serially controlled resources |
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2005
- 2005-08-08 DE DE102005037236A patent/DE102005037236A1/de not_active Withdrawn
-
2006
- 2006-07-27 WO PCT/EP2006/064751 patent/WO2007017399A1/de active Application Filing
- 2006-07-27 US US11/990,095 patent/US20100295571A1/en not_active Abandoned
- 2006-07-27 EP EP06778034A patent/EP1917591A1/de not_active Ceased
- 2006-07-27 KR KR1020087003202A patent/KR20080032166A/ko not_active Application Discontinuation
- 2006-07-27 RU RU2008108473/09A patent/RU2008108473A/ru not_active Application Discontinuation
- 2006-07-27 CN CNA2006800291941A patent/CN101238445A/zh active Pending
- 2006-07-27 JP JP2008525531A patent/JP2009514064A/ja active Pending
- 2006-08-07 TW TW095128807A patent/TW200725254A/zh unknown
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WO1998044416A1 (en) * | 1997-04-02 | 1998-10-08 | General Dynamics Information Systems, Inc. | Fault tolerant computer system |
WO2001046806A1 (en) * | 1999-12-21 | 2001-06-28 | Intel Corporation | Firmware mechanism for correcting soft errors |
US20040078715A1 (en) * | 2000-05-18 | 2004-04-22 | Vaeth Joachim | Peripheral component with high error protection for stored programmable controls |
US20050023656A1 (en) * | 2002-08-08 | 2005-02-03 | Leedy Glenn J. | Vertical system integration |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2207097A1 (de) * | 2009-01-07 | 2010-07-14 | Robert Bosch GmbH | Verfahren und Vorrichtung zum Betreiben eines Steuergerätes |
US9552241B2 (en) | 2011-11-10 | 2017-01-24 | Fujitsu Limited | Information processing apparatus, method of information processing, and recording medium having stored therein program for information processing |
Also Published As
Publication number | Publication date |
---|---|
EP1917591A1 (de) | 2008-05-07 |
US20100295571A1 (en) | 2010-11-25 |
TW200725254A (en) | 2007-07-01 |
JP2009514064A (ja) | 2009-04-02 |
KR20080032166A (ko) | 2008-04-14 |
CN101238445A (zh) | 2008-08-06 |
DE102005037236A1 (de) | 2007-02-15 |
RU2008108473A (ru) | 2009-09-20 |
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