WO2007017398A1 - Procede et dispositif pour determiner un etat de demarrage dans un systeme informatique comprenant au moins deux unites d'execution par commutation d'ensembles de registres - Google Patents

Procede et dispositif pour determiner un etat de demarrage dans un systeme informatique comprenant au moins deux unites d'execution par commutation d'ensembles de registres Download PDF

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Publication number
WO2007017398A1
WO2007017398A1 PCT/EP2006/064749 EP2006064749W WO2007017398A1 WO 2007017398 A1 WO2007017398 A1 WO 2007017398A1 EP 2006064749 W EP2006064749 W EP 2006064749W WO 2007017398 A1 WO2007017398 A1 WO 2007017398A1
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WO
WIPO (PCT)
Prior art keywords
register
mode
execution units
execution unit
registers
Prior art date
Application number
PCT/EP2006/064749
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German (de)
English (en)
Inventor
Reinhard Weiberle
Bernd Mueller
Eberhard Boehl
Yorck Collani
Rainer Gmehlich
Original Assignee
Robert Bosch Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch Gmbh filed Critical Robert Bosch Gmbh
Priority to EP06778032A priority Critical patent/EP1917590A1/fr
Priority to JP2008525530A priority patent/JP2009505187A/ja
Publication of WO2007017398A1 publication Critical patent/WO2007017398A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1658—Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G06F11/1641—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/845—Systems in which the redundancy can be transformed in increased performance

Definitions

  • the invention relates to a method and a device for switching between at least two operating modes of a microprocessor having at least two execution units for processing program segments according to the preambles of the independent claims.
  • Transient errors triggered by alpha particles or cosmic rays, are increasingly becoming a problem for integrated circuits. Decreasing feature widths, decreasing voltages, and higher clock frequencies increase the likelihood that a voltage spike, caused by an alpha particle or cosmic radiation, will degrade a logic value in an integrated circuit. A wrong calculation result can be the result. In safety-relevant systems, therefore, such errors must be reliably detected.
  • Dual-core or multi-core architectures are also used in other applications to increase performance, ie to increase performance. Both cores run different program segments, which can achieve a performance improvement compared to the comparison mode or a single core system. This configuration is called
  • This system is also referred to as a symmetrical multiprocessor system (SMP) in a special form with the same cores.
  • SMP symmetrical multiprocessor system
  • Modes of accessing a specific address and specialized hardware devices In comparison mode, the output signals of the cores are compared with each other. In performance mode, the two cores work as a symmetric multiprocessor (SMP) system and execute different programs, program segments, or commands.
  • SMP symmetric multiprocessor
  • the internal states (registers, pipeline, etc.) of the execution units must be adjusted before switching from the performance mode to the comparison mode. In the case of an execution unit with many registers, this can take up a relatively large amount of computing time and prolong a mode changeover from the performance mode to the comparison mode.
  • the usual method for aligning the states of the execution units is to set all registers in the execution units to zero or to mark their contents invalid.
  • the object of this invention is to shorten this transition from the performance mode to the comparison mode.
  • the embodiments described herein have the advantage over the prior art that they allow a faster switching from the performance mode to the comparison mode, since the registers of the execution units, depending on the mode in which they involved can be initialized quickly by using the method according to the invention
  • a method for determining a start state in a computer system having at least two execution units, wherein a switch between a performance mode and a comparison mode and the performance mode, a first register set is provided, consisting of at least a first register for a first execution unit and at least a second register for a second execution unit, characterized in that when switching from the performance mode in the comparison mode, a start state for the comparison mode in a second register set is present, consisting of at least a third register for the first execution unit and at least a fourth register for the second execution unit, wherein the start state for the comparison mode is obtained by switching between the first and second register sets.
  • the start state for the performance mode is obtained by switching between the second and the first register set.
  • a device for determining a start state in a computer system having at least two execution units is advantageously included, wherein means are provided which are configured such that they switch between a performance mode and a comparison mode and a first register set is provided for the performance mode at least one first register for a first execution unit and at least one second register for a second execution unit, characterized in that when switching from the performance mode to the compare mode, a start state for the compare mode is generated in a second register set consisting of at least one third register for the first execution unit and at least one fourth register for the second execution unit, wherein the start state for the comparison mode is obtained by switching between the first and second register sets.
  • Figure 1 shows the general structure of a processor with two execution units and a comparison unit. - A -
  • FIG. 2 shows a possible structure of an execution unit with two different register groups and the processing logic.
  • FIG. 3 shows a possible structure of an execution unit with two different register sets and the processing logic.
  • the register sets are in turn divided into two different groups.
  • FIG. 4 shows two execution units with their internal registers, a buffer and a connection between the execution units for transmitting the internal states.
  • FIG. 5 shows two execution units with their internal registers and a buffer for reading out the internal states for the start state of the comparison mode.
  • Figure 6 shows the structure of a register with user and control data.
  • FIG. 7 shows a multiprocessor with two execution units as well as the internal registers of the execution units.
  • FIG. 8 shows a multiprocessor system with two execution units, their internal registers and a special register
  • FIG. 1 shows a processor system CLOOO which can switch between a comparison mode and a performance mode, consisting of two execution units ClOOa and ClOOb.
  • the execution units are identical. Both execution units ClOOa and ClOOb each have an interface
  • the output signals of the execution units ClOOa, ClOOb are compared with each other via the unit C 120.
  • this comparison is performed with exact clock or with a fixed clock offset, this means that in each clock, the output signals of the at least two execution units ClOOa, ClOOb are compared by the unit C120. If there is a difference between the compared signals, then an error signal is generated by the unit C 120.
  • the input signals of the execution units ClOOa and ClOOb can additionally be compared.
  • the comparison unit C 120 is not active and no error signal is generated if there are differences in the output signals of the execution units.
  • the deactivation of the comparison unit can be realized in various ways: A comparison by the unit C 120 is not performed. No signals are applied to the unit C 120 for comparison. A comparison is made by the unit C 120, but the result is ignored.
  • Output signals would detect the comparator as an error, although the same input signals are present and no error to be detected in the processing has occurred.
  • One way to achieve the same state in both execution units at the beginning of the compare mode is to mark all internal registers in the execution units as invalid. However, this possibility of marking does not exist for all internal registers. These must then be set to a defined value, which is identical in both execution units.
  • FIG. 2 describes a possible implementation of the embodiment unit C100. It contains at least two different groups of registers ClOl and C 102 and an internal logic C 103.
  • the group of registers ClOl can be marked as invalid. This means that the internal logic C 103 of the execution unit recognizes when accessing an invalid marked register of this group that the content for this register must be redetermined; for example by reloading from RAM, ROM, Flash or by recalculation. Registers from the other group C 102 always have valid content.
  • the working registers of an execution unit belong, for example, to this group.
  • This condition for the register group ClO1, CI 02 does not necessarily have to be valid from the moment of switching from the performance mode to the comparison mode, but not later than the first read access to two identical registers in the execution units ClOO after switching to the compare mode.
  • a common procedure is to assign a fixed value to all registers of group C 102 in good time before switching to comparison mode. Irrespective of this, when switching to the comparison mode, registers of the group ClOl are marked as invalid.
  • Register used In comparison mode, the registers of group ClOIa and C 102a are used, while in performance mode the registers of group ClOIb and C102b are used. Switching between these register sets in the comparison mode or in the performance mode at the time of switching. Is for the registers 101a and 102a once it has been ensured that the content is identical, for example by means of a corresponding initialization when the processor is switched on, these registers remain the same even during operation on both execution units. Thus, no adjustment of the register contents is necessary when switching from the performance mode to the comparison mode, since in the comparison mode only registers are accessed which are identical between the two execution units C100a and C150b and can only be described in the comparison mode.
  • FIG. It consists of copying the internal status C104d resp. C104e from an execution unit ClOOd, ClOOe to the other execution unit ClOOd or ClOOe.
  • C104d at ClOOd and C104e at ClOOe which is ready sooner, are initialized before the changeover to the values which are required in the compare mode, then the internal state of a second execution unit succeeding in time can be adjusted when the state is taken over by the first execution unit.
  • Execution unit ClOOd formerly ready for a changeover as the execution unit ClOOe, so the status C104d to C104e is copied during the changeover.
  • This copying of the internal state can be performed by directly using a connection C300 between the two execution units, via which the internal state is copied.
  • the state may be copied from a first, earlier execution unit to a (fast) cache C200, from which a second, successive execution unit takes over the state into the internal registers.
  • partial states are marked which do not have to be adjusted between the execution units when switching to the comparison mode. It is not always necessary to align all registers of the execution units when switching from the performance mode to the comparison mode. In order not to erroneously detect an error in comparison mode, only the registers of one execution unit need to be aligned with the registers of a second execution unit that are actually used in the compare mode. Especially in architectures that provide a large number of registers in the execution units, this is the case or can be considered in the software development as a constraint. The number of registers used in a comparison mode can be determined in any case. If not all are used, it is not necessary to adjust all registers but only the ones used. Therefore, it is proposed to provide additional bits in each register.
  • this register It may be lodged in these bits whether or not the contents of this register should be matched with the corresponding registers of the other execution units when switching from a performance mode to a comparison mode.
  • a special register may exist whose content defines which register of one execution unit must be aligned with the corresponding registers of the other execution units. The approximation itself can be done independently of the markings via the known or presented here method.
  • FIG. 7 shows a processor system C300 with a plurality of execution units C310, C320 with free registers C311, C321.
  • Each register of C311, C321 consists of n bits (n> 1) with payload data (shown in Figure 6 C2010).
  • n bits n bits
  • m bits m bits
  • control data shown in Figure 6 C2000.
  • m-bits is coded whether an adjustment takes place when changing to the comparison mode. For example, if the control bits consist of only one bit in the simplest case, a value of zero means that an approximation does not have to take place and a value of one implies that an alignment must take place. The evaluation of these bits then takes place when switching from the performance to the comparison mode.
  • FIG. 8 shows a further embodiment of the invention with a processor system C400 which includes execution units C410, C420 with their registers C411, C422.
  • the C400 processor system has a register C430.
  • the content of this register C430 d ⁇ - defines which registers of C411, C421 of the execution units C410, C420 must be adjusted when changing to the compare mode.
  • register C430 may be implemented such that one bit is provided in C430 for each potential register of C411, C421 to be matched. If the corresponding bit is set, the corresponding register must be adjusted; if the bit is not set, the corresponding register does not have to be adjusted. The evaluation of this register then happens when switching from performance to comparison mode.
  • a central register C430 is not provided as shown in Fig. 8, but a register is provided in each execution unit to perform the task of the register C430. This means that in this register is coded which of the registers of the execution unit must be adapted when switching from the performance mode in a comparison mode to the registers of at least one second execution unit. When switching from a performance mode to a comparison mode, however, it must then be ensured that the contents of these special registers are identical in all execution units to be synchronized.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)

Abstract

La présente invention concerne un procédé pour déterminer un état de démarrage dans un système informatique comprenant au moins deux unités d'exécution. Selon cette invention, il est possible d'effectuer une commutation entre un mode performance et un mode comparaison. Pour le mode performance, un premier ensemble de registres est prévu. Ce premier ensemble de registres est constitué d'au moins un premier registre pour une première unité d'exécution et d'au moins un deuxième registre pour une seconde unité d'exécution. Cette invention est caractérisée en ce que, lors d'une commutation du mode performance au mode comparaison, un état de démarrage pour le mode comparaison est présent dans un second ensemble de registres constitué d'au moins un troisième registre pour la première unité d'exécution et d'au moins un quatrième registre pour la seconde unité d'exécution. L'état de démarrage pour le mode comparaison est obtenu en effectuant une commutation entre le premier ensemble de registres et le second ensemble de registres.
PCT/EP2006/064749 2005-08-08 2006-07-27 Procede et dispositif pour determiner un etat de demarrage dans un systeme informatique comprenant au moins deux unites d'execution par commutation d'ensembles de registres WO2007017398A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP06778032A EP1917590A1 (fr) 2005-08-08 2006-07-27 Procede et dispositif pour determiner un etat de demarrage dans un systeme informatique comprenant au moins deux unites d'execution par commutation d'ensembles de registres
JP2008525530A JP2009505187A (ja) 2005-08-08 2006-07-27 少なくとも２つの命令実行部を備えたコンピュータシステムにおいてレジスタセットの切り替えにより初期状態を設定する方法および装置

Applications Claiming Priority (2)

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DE102005037259.7 2005-08-08
DE200510037259 DE102005037259A1 (de) 2005-08-08 2005-08-08 Verfahren und Vorrichtung zur Festlegung eines Startzustandes bei einem Rechnersystem mit wenigstens zwei Ausführungseinheiten durch Umschalten von Registersätzen

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WO2007017398A1 true WO2007017398A1 (fr) 2007-02-15

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EP (1) EP1917590A1 (fr)
JP (1) JP2009505187A (fr)
CN (1) CN101243409A (fr)
DE (1) DE102005037259A1 (fr)
WO (1) WO2007017398A1 (fr)

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JP2015114952A (ja) * 2013-12-13 2015-06-22 株式会社日立製作所 ネットワークシステム、監視制御装置およびソフトウェア検証方法

Citations (2)

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US6615366B1 (en) * 1999-12-21 2003-09-02 Intel Corporation Microprocessor with dual execution core operable in high reliability mode
US20040019771A1 (en) * 1999-12-21 2004-01-29 Nhon Quach Firmwave mechanism for correcting soft errors

Family Cites Families (3)

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Publication number Priority date Publication date Assignee Title
JPH0256029A (ja) * 1988-08-20 1990-02-26 Fujitsu Ltd 汎用レジスタ切換方式
JP2004178427A (ja) * 2002-11-28 2004-06-24 Toshiba Microelectronics Corp 中央処理装置
DE10349580A1 (de) * 2003-10-24 2005-05-25 Robert Bosch Gmbh Verfahren und Vorrichtung zur Operandenverarbeitung in einer Prozessoreinheit

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Publication number Priority date Publication date Assignee Title
US6615366B1 (en) * 1999-12-21 2003-09-02 Intel Corporation Microprocessor with dual execution core operable in high reliability mode
US20040019771A1 (en) * 1999-12-21 2004-01-29 Nhon Quach Firmwave mechanism for correcting soft errors

Non-Patent Citations (1)

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Title
MAEJIMA H ET AL INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS: "A 16-bit microprocessor with multi-register bank architecture", PROCEEDINGS OF THE FALL JOINT COMPUTER CONFERENCE. DALLAS, NOV. 2 - 6, 1986, WASHINGTON, IEEE COMP. SOC. PRESS, US, 2 November 1986 (1986-11-02), pages 1014 - 1019, XP002192173 *

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CN101243409A (zh) 2008-08-13
JP2009505187A (ja) 2009-02-05
DE102005037259A1 (de) 2007-02-15
EP1917590A1 (fr) 2008-05-07

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