WO2006070807A1 - Tableau de connexions et son procede de fabrication - Google Patents

Tableau de connexions et son procede de fabrication Download PDF

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Publication number
WO2006070807A1
WO2006070807A1 PCT/JP2005/023909 JP2005023909W WO2006070807A1 WO 2006070807 A1 WO2006070807 A1 WO 2006070807A1 JP 2005023909 W JP2005023909 W JP 2005023909W WO 2006070807 A1 WO2006070807 A1 WO 2006070807A1
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WO
WIPO (PCT)
Prior art keywords
ceramic
dielectric layer
layer
conductor
laminate
Prior art date
Application number
PCT/JP2005/023909
Other languages
English (en)
Japanese (ja)
Inventor
Shinji Yuri
Makoto Origuchi
Yasuhiko Inui
Jun Otsuka
Original Assignee
Ngk Spark Plug Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ngk Spark Plug Co., Ltd. filed Critical Ngk Spark Plug Co., Ltd.
Priority to EP05822355A priority Critical patent/EP1833286A1/fr
Priority to US11/793,817 priority patent/US20080289866A1/en
Publication of WO2006070807A1 publication Critical patent/WO2006070807A1/fr

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0187—Dielectric layers with regions of different dielectrics in the same layer, e.g. in a printed capacitor for locally changing the dielectric properties
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0147—Carriers and holders
    • H05K2203/016—Temporary inorganic, non-metallic carrier, e.g. for processing or transferring
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0502—Patterning and lithography
    • H05K2203/0537—Transfer of pre-fabricated insulating pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases

Definitions

  • the present invention relates to a wiring board and a method of manufacturing the wiring board.
  • Patent Document 1 Japanese Unexamined Patent Application Publication No. 2003-142624
  • Patent Document 1 discloses a decoupling capacitor in which a ferroelectric film and a metal film are laminated, and a large number of capacitor terminals are individually connected to dense integrated circuit side terminals. It is done. In high frequency areas (especially 100 MHz or more) where noise problems due to power supply voltage fluctuations during high speed switching are particularly likely to occur, the specific gravity of the inductive reactance term that occupies the power supply impedance becomes large. It is effective to reduce the power supply impedance by making the distance between the terminal and the ground terminal closer. In addition, when the inductance at the terminal portion increases, there is a problem that a resonance point is generated by combining with the capacitive component of the decoupling capacitor, and the bandwidth for obtaining a sufficient impedance reduction effect is reduced. Therefore, as mentioned above, the distance between terminals is small The fabrication of the capacitor has the advantage of contributing to the reduction of the power supply impedance, which is the original purpose, and the wide bandwidth, which is the sole purpose of the miniaturization of the device.
  • the capacitor is incorporated in the intermediate substrate provided between the electronic component and the wiring substrate, and the wiring substrate of the electronic component is provided to the extent that the intermediate substrate is interposed.
  • the buildup layer made of a polymer material as the dielectric layer, and built a capacitor using a high dielectric ceramic layer on a so-called organic wiring board. We considered incorporating part of the layer in the form of replacement. If this is compared to the configuration using an intermediate substrate, the assembly can be made lower in height, but the following problems have emerged.
  • the capacitance that can be formed is larger when the capacitor is formed in the wide area of the extreme compared to the external size of the unit (package) of the wiring substrate, the unit (package) of the wiring substrate If the same size as the capacitor is used, the following problems occur because the capacitor portion is cut off when dicing the wiring board into a unit (package).
  • the interface with the electrode or ceramic dielectric layer as compared with polymer materials may become delamination due to shear stress at the time of dicing where adhesion is weak, and a moisture absorption penetration path thereafter.
  • a capacitor using a high dielectric ceramic layer is used as a dielectric layer, for example, on an organic wiring board using a buildup resin insulating layer made of a polymer material.
  • a buildup resin insulating layer made of a polymer material.
  • Capacitors may be formed on both the first side (front side) and the second side (back side) of the substrate core, but if only one of them is sufficient in capacity, cost increase is suppressed. In order to do so, the capacitor should be formed only on the first side to mount the electronic components. When adopting such a structure, the following problems emerge.
  • One problem is that the processing solution used to form the first side capacitor affects the second side element.
  • the desmear liquid used to remove the residue of the via hole is a problem because it corrodes the polymer material.
  • the buildup process is performed simultaneously on both sides of the substrate core, and therefore, there is no problem of corrosion on one side or more.
  • the reasoning applies when creating a capacitor that includes a ceramic dielectric layer only on one side of the substrate core while applying force.
  • a via is formed to connect the conductor layer to a conductor layer of the same polarity on the substrate core portion side.
  • the via hole to be the via is formed, and the via conductor is formed on the inner surface of the via hole.
  • the via hole is always cleaned before the conductor formation.
  • the polymer dielectric layer exposed on the second side is subjected to unnecessary corrosion by the cleaning liquid.
  • non-uniformity of the surface state occurs between the polymeric material dielectric layer newly formed on the first side after formation of the capacitor and the polymeric material dielectric layer on the second side. This fact means that it is difficult to form a uniform thickness, uniform property layer on the first side and the second side.
  • Another problem is that the mechanical characteristics of the first side and the second side are not good based on the presence or absence of the capacitor.
  • An object of the present invention is to provide a method of manufacturing a wiring board capable of easily manufacturing a wiring board having a structure in which a ceramic dielectric layer and a polymeric material dielectric layer are composite-laminated.
  • An object of the present invention is to provide a wiring board which is capable of enhancing the adhesion strength between layers and which is less likely to cause problems such as peeling during reflow processing.
  • Another object of the present invention is that, in the structure of a wiring board incorporating a capacitor, the outer end face of the ceramic dielectric layer forming the capacitor is pulled down more than the package end face, and the outer end face of the capacitor electrode layer is a ceramic dielectric. It is an object of the present invention to provide a wiring board having a highly reliable structure in which interlayer short circuit is difficult to occur by avoiding exposure of a capacitor to the end face of the package by further pulling down from the outer end face of the body layer and a manufacturing method thereof.
  • a wiring laminate portion in which a dielectric layer and a conductor layer are laminated is formed on at least one main surface of a substrate core portion; A method of manufacturing a wiring substrate having a composite lamination portion laminated in contact with each other in this order from the substrate core portion side to the polymer material dielectric layer, the conductor layer, the ceramic dielectric layer, and the force S in this order.
  • a process of producing a first laminate by forming a ceramic dielectric layer and a conductor layer in this order on one main surface of a transfer source substrate, and a polymer on the main surface of the substrate core portion A second laminate manufacturing step of forming a second dielectric layer by forming a material dielectric layer, and a bonding step of bonding the conductor layer of the first laminate and the polymeric material dielectric layer of the second laminate. And a transfer source substrate removing step of removing the transfer source substrate from the ceramic dielectric layer
  • a method of manufacturing a wiring board is provided, which is characterized in that the steps (a) and (b) are performed in this order.
  • a wiring laminate portion in which a dielectric layer and a conductor layer are laminated is formed on at least one of the main surfaces of a substrate core portion.
  • a ceramic dielectric layer and a conductor layer are formed in this order on one main surface of the original substrate to produce a first laminate, and this is used as a polymer material dielectric layer on the main surface of the substrate core portion.
  • the transfer source substrate After being superimposed and bonded on the second laminated body on which is formed, the transfer source substrate is removed. That is, the thin and fragile ceramic dielectric layer is reinforced by the transfer source substrate. Since it is not necessary to use the lamination process alone if it is subjected to the laminating process, as described above, there is a composite layer portion in which the polymeric material dielectric layer, the conductor layer and the ceramic dielectric layer are laminated. It is possible to dramatically improve the manufacturing efficiency and yield of the wiring substrate.
  • a wiring stack portion in which a dielectric layer and a conductor layer are stacked is formed on at least one of the main surfaces of the substrate core portion, and the wiring core portion has the substrate core portion side.
  • a composite laminate portion in which a polymer dielectric layer, a conductor layer and a ceramic dielectric layer are laminated in this order in contact with each other, and in the composite laminate portion, the conductor layer is in-plane
  • a conductor-layer-side notch in which a portion of the layer is notched in the direction
  • the ceramic dielectric layer has a ceramic-side notch in which a portion of the layer is notched in the in-plane direction
  • a communication notch portion in which the side notch portion and the conductor side notch portion are in communication with each other is formed, and the polymer material constituting the polymeric material dielectric layer passes through the conductor side notch portion in the communication notch portion and the ceramic side notch portion
  • a wiring board is provided which is characterized in that it is filled in the following manner
  • the composite laminated portion in which the polymeric material dielectric layer, the conductor layer, and the ceramic dielectric layer are in contact with each other in this order from the substrate core portion side is laminated. Since the polymer material constituting the polymer material dielectric layer is filled on the side of the communication notch formed on the side of the conductor layer and the ceramic dielectric layer, the anchor effect improves the adhesion strength between the layers. As a result, problems such as peeling at the time of reflow processing can be made less likely to occur.
  • the wiring board can be manufactured as follows by using the manufacturing method of the present invention. That is, in the first laminated body manufacturing step, the ceramic side notched portion patterning step of forming the ceramic side notched portion in the ceramic dielectric layer formed on one of the main surfaces of the transfer source substrate; A conductor layer forming step of forming a conductor layer on the ceramic dielectric layer after forming the conductor layer, and a conductor side notch portion forming a pattern so that the conductor side cutout portion communicates with the ceramic side cutout portion with respect to the conductor layer Implement as including the patterning process.
  • the first laminated body in which the communication notch portion including the ceramic side notch portion and the conductor side notch portion communicating with the first laminate is formed on the main surface on the opening side of the communication notch portion;
  • a second laminated body in which the polymeric material dielectric layer is in an uncured or semi-cured state is superposed on the main surface of the polymeric material dielectric layer, and in such a state, The laminate and the second laminate are pressed in the laminating direction, and the polymer material in the uncured or semi-cured state constituting the polymeric material dielectric layer is force-filled into the communication notch, and then the polymer material Cure.
  • the uncured or semi-cured polymer material constituting the polymer dielectric layer can be reliably filled in the communication notch by pressure bonding, and the structure of the wiring substrate is simplified. Can be obtained.
  • the conductor layer included in the composite laminate portion is used as the first conductor layer, and the second one is laminated from the side opposite to the first conductor layer with respect to the ceramic dielectric layer.
  • a conductor layer is provided, and the first conductor layer, the ceramic dielectric layer and the second conductor layer can form a capacitor.
  • a wiring board having a composite laminate portion in which a polymeric material dielectric layer, a conductor layer, and a ceramic dielectric layer made of high dielectric constant ceramic are stacked in contact with each other in this order.
  • the conductor layer has a conductor layer side cutout portion in which a portion of the layer is cut away in the in-plane direction, and the ceramic dielectric layer is formed of the layer in the in-plane direction.
  • a communication notch is formed having a partially cut ceramic side notch, and the ceramic side notch and the conductor layer side notch communicate with each other, to form the high dielectric material dielectric layer.
  • a molecular material is filled in the communication notch through the conductor layer side notch to reach the ceramic side notch, and the conductor layer included in the composite laminate is the first conductor layer;
  • the above for the ceramic dielectric layer With the conductor layer stacked from the opposite side to the one conductor layer as the second conductor layer, the outer end face of the ceramic dielectric layer is pulled down by at least the first pull-down width from the end face of the unit of the wiring substrate, The outer conductor end face of the first conductor layer and the second conductor layer is pulled down by at least a second pull-down width which is larger than the first pull-down width, so that the first conductor layer, the ceramic dielectric layer, and the second conductor
  • the layer is characterized in that a capacitor is formed
  • a wiring board is provided.
  • a wiring board having a composite laminate portion in which a polymer material dielectric layer, a conductor layer, and a ceramic dielectric layer made of high dielectric constant ceramic are stacked in contact in this order.
  • the outer conductor end face of the first conductor layer and the second conductor layer is pulled down by at least a second pulling width larger than the first pulling width, and a capacitor is formed by the first conductor layer, the ceramic dielectric layer and the second conductor layer.
  • a method of manufacturing a wiring substrate comprising: performing a transfer source substrate removing step of removing from the ceramic dielectric layer in this order.
  • the outer end face of the ceramic dielectric layer is at least the first drawn width from the end face of the unit of the wiring board. And the outer end surface of the first conductor layer and the second conductor layer is reduced at least by a second pulling width greater than the first pulling width, and the first conductor layer, the ceramic dielectric layer and the second conductor layer Since the capacitor is formed, the following effects can be obtained.
  • a wiring laminated portion in which a dielectric layer and a conductor layer are laminated is formed on at least one of the main surfaces of the substrate portion. It can be configured to have a composite laminate portion in which a polymer material dielectric layer (so-called buildup resin insulating layer), a conductor layer and a ceramic dielectric layer are stacked in contact with each other in this order from the core portion side. It is of course possible to apply the present invention to so-called coreless substrates etc. that do not have a force core.
  • a composite laminate portion in which a polymeric dielectric layer, a conductor layer, and a ceramic dielectric layer made of a high dielectric constant ceramic are laminated in contact with each other in this order.
  • a transfer source substrate removing step of removing the transfer source substrate from the ceramic dielectric layer in this order A method of manufacture is provided.
  • a composite laminate portion in which a polymeric material dielectric layer, a conductor layer and a ceramic dielectric layer are in contact with each other in this order.
  • a ceramic dielectric layer and a conductor layer are formed in this order on one main surface of the transfer source substrate to manufacture a first laminated body, which is then bonded Then, the transfer source substrate is removed after being superposed and bonded on the second laminate having the polymer material dielectric layer.
  • the thin and fragile ceramic dielectric layer does not need to be singled out when it is subjected to the bonding step in the form of being reinforced with the transfer source substrate, and as described above, it is possible to It is possible to dramatically improve the production efficiency and yield of a laminate having a composite laminate portion in which a conductor layer and a ceramic dielectric layer are laminated.
  • the high dielectric constant ceramic refers to a ceramic having a relative dielectric constant of 10 or more, and in particular, when a high dielectric constant is required, a ferroelectric ceramic is preferably employed.
  • a high dielectric constant ceramic a ferroelectric composite oxide ceramic having a velovskite crystal structure, for example, one or two of barium titanate, strontium titanate and lead titanate Ceramics composed of species or more are particularly high in dielectric constant and relatively easy to manufacture, so that they can be suitably employed in the present invention.
  • the bonding step when a method of pressing and bonding the first laminate and the second laminate in the laminating direction is adopted, polymer materials of the conductor layers of the first laminate and the second laminate are induced.
  • the adhesion strength after bonding to the current collector layer can be increased.
  • the conductor layer has a conductor layer side notch portion in which a portion of the layer is cut away in the in-plane direction, and ceramic
  • the dielectric layer has a ceramic side cutout in which a part of the layer is cut in the in-plane direction, and a communication cutout in which the ceramic side cutout and the conductor side cutout communicate with each other is formed.
  • the polymer material constituting the dielectric layer can be filled at the communication notch through the conductor-side notch and to the ceramic-side notch.
  • the polymer material constituting the polymer material dielectric layer is filled in the communication notch portion side formed on the conductor layer and the ceramic dielectric layer side, so that the adhesion strength between the layers is obtained by the anchor effect.
  • problems such as peeling at the time of reflow processing can be less likely to occur.
  • the wiring laminate portion of the structure can be manufactured as follows by using the manufacturing method of the present invention. That is, in the first laminate manufacturing step, a ceramic side notch patterning step of forming a ceramic side notch in the ceramic dielectric layer formed on one of the main surfaces of the transfer source substrate; A conductor layer forming step of forming a conductor layer on the ceramic dielectric layer after patterning, and patterning of the conductor side notch portion in which the conductor side cutout portion is communicated with the ceramic side cutout portion with respect to the conductor layer Conduct as including the process.
  • the first laminated body having the communication notch portion formed of the ceramic side notch portion and the conductor side notch portion communicating therewith is formed on the main surface on the opening side of the communication notch portion.
  • the second laminated body in a state in which the polymeric material dielectric layer is uncured or semi-cured is superposed on the main surface of the polymeric material dielectric layer, and the first laminated body and the second laminated body in that state are laminated.
  • the polymer material in the uncured or semi-cured state constituting the polymeric material dielectric layer is force-filled into the communication notch and thereafter the polymeric material is cured.
  • the polymeric material dielectric layer is constructed.
  • the polymer material in an uncured or semi-cured state can be reliably filled in the communication notch by pressure bonding, and the structure of the wiring board can be easily obtained.
  • the ceramic dielectric layer can also be used as a dielectric layer constituting a distributed constant circuit laminate such as a microstrip line, a strip line, or a coplanar waveguide other than a capacitor.
  • a distributed constant circuit laminate such as a microstrip line, a strip line, or a coplanar waveguide other than a capacitor.
  • the microstrip line Alternatively, a stripline structure can be obtained.
  • the line conductor is used as a first conductor layer, and a polymeric material dielectric layer is disposed in contact with the main surface of the ceramic dielectric layer forming the background region of the line conductor in a form covering the same. it can.
  • a support base in which a conductor extending in the upper and lower direction in the thickness direction is formed, and on each of the first side and the second side of the support base
  • a wiring board with a built-in capacitor in which a wiring stack portion in which a dielectric layer and a conductor layer are stacked is formed, and a capacitor including a ceramic dielectric layer is formed only in the first side wiring stack portion located on the first side.
  • the structure in which conductive connections between layers are taken by via conductors does not change even in a wiring board with a built-in capacitor. That is, the conduction between the second conductor layer forming the electrode of the capacitor and the conductor layer on the support base is taken by the via conductor.
  • the via hole for the via conductor can be formed by laser irradiation technology or photolithographic technology. Regardless of the cleaning process for cleaning the via hole, it is essential to prevent the occurrence of the conduction failure. In the cleaning process, it is ideal to target only the first side. However, in the notching process that places importance on productivity, the method of immersing the entire work in the cleaning tank containing the chemical solution is adopted.
  • the polymeric dielectric layer on the second side is covered with another polymeric dielectric layer.
  • tape masking may be applied when cleaning the first-side via hole. Therefore, it does not lead to the correction of the imbalance in mechanical characteristics between the first side wiring stack and the second side wiring stack.
  • the thick polymer material dielectric layer compensates for the absence of the capacitor, the strength of the second side wiring laminated portion can be improved, and thus the second side wiring laminated portion and the first side wiring It is possible to obtain a structure excellent in strength balance with the laminated portion and resistant to warpage and peeling.
  • the step of coating the polymer material dielectric layer with another polymer material dielectric layer is a step of laminating a film of polymer material or a liquid polymer material. Can be applied. In particular, build up a build-up resin film (for example, available from Ajinomoto Co., Ltd.) having the same thickness and the same characteristics. The method is preferred. According to this method, the apparatus used in the normal build-up method can be used as it is, which contributes to the reduction of the manufacturing cost. For the same reason, the step of coating the second-layer polymer material dielectric layer with another polymer material dielectric layer, and the step of forming a new polymer material dielectric layer on the first side are the same. It is possible to proceed with the formation of the first side wiring stack portion and the second side wiring stack portion by the buildup method in which other conductor layers are formed by the via formation step and the pattern plating step.
  • a build-up resin film for example, available from Ajinomoto Co., Ltd.
  • a capacitor using a thin layer of high dielectric ceramic has a problem of poor manufacturing efficiency, which makes handling difficult when bonding to a buildup resin insulating layer for wiring.
  • the step of forming the composite laminate portion is a first laminate producing step of producing the first laminate by forming the ceramic dielectric layer and the conductor layer in this order on one main surface of the transfer source substrate.
  • a second laminate manufacturing step of producing a second laminate by forming a polymer material dielectric layer on the main surface of the supporting substrate, and a polymer material of the conductor layer of the first laminate and the second laminate A bonding step of bonding the dielectric source layer and a transfer source substrate removing step of removing the transfer source substrate from the ceramic dielectric layer may be performed in this order.
  • the thin and fragile ceramic dielectric layer may be subjected to the bonding step in the form of being reinforced with the transfer source substrate, and since it is not necessary to stand it alone, the polymer as described above It is possible to dramatically improve the production efficiency and yield of a wiring substrate having a composite laminate portion in which a material dielectric layer, a conductor layer and a ceramic dielectric layer are stacked.
  • a wiring board for mounting an electronic component comprising: a support base having therein through-hole conductors extending vertically in the thickness direction, the support base The polymer material dielectric layer and the conductor layer are laminated on the first side and the second side of the A wiring stack portion is formed, and a capacitor including a ceramic dielectric layer is formed only on the first side wiring stack portion located on the first side, and the first side wiring stack portion is high from the supporting substrate side.
  • the dielectric layer of the molecular material, the conductor layer forming one of the electrodes of the capacitor, and the ceramic dielectric layer are in this order and have a composite laminate portion laminated in contact with each other in this order, and the conductor layer forming the other electrode of the capacitor is the ceramic dielectric.
  • the second side wiring stack which is formed to cover the body layer, and which is located on the second side, corresponds to the first side composite lamination on the supporting substrate by counting the force of the support base.
  • a wiring substrate is provided, characterized in that it comprises a polymeric dielectric layer having a thickness greater than that of the polymeric dielectric layer contained therein.
  • the second side wiring stack portion does not have a capacitor but has a thick high molecular weight dielectric layer. That is, the mechanical characteristics of the first side wiring stack portion and the mechanical characteristics of the second side wiring stack portion can be made close to each other, and the strength balance between the both can be made uniform. Therefore, even if only the first side wiring stack portion has a capacitor, problems such as warpage and peeling can occur.
  • the number of conductor layers of the second side wiring stack portion positioned on the second side is smaller than the number of conductor layers of the first side wiring stack portion. Good. In this way, the structure of the second side wiring stack portion can be simplified.
  • a wiring laminate portion in which a dielectric layer and a conductor layer are laminated is formed on at least one of the main surfaces of a support base, and the wiring laminate portion is supported
  • a composite laminate portion in which a polymer material dielectric layer, a conductor layer and a ceramic dielectric layer are stacked in contact with each other in this order from the substrate side is included, and in the composite laminate portion, the conductor layer extends in the in-plane direction.
  • the ceramic dielectric layer has a ceramic side cutout in which a portion of the layer is cut in the in-plane direction, and the ceramic side cut A communication notch is formed in which the notch and the conductor-side notch communicate with each other, and the polymer material constituting the high-polymer dielectric layer passes through the conductor-side notch in the communication notch and is cut into the ceramic-side notch. It is characterized in that it is filled in a form.
  • the polymer material dielectric layer, the conductor layer, and the ceramic dielectric layer are stacked in contact with each other in this order from the supporting substrate side.
  • the polymer material constituting the polymer material dielectric layer in the cured composite laminate portion is the conductor layer and the ceramic layer. Since it is filled in the communication notch formed on the side of the dielectric dielectric layer, the anchor effect can enhance the adhesion strength between the layers, and thus it is difficult to cause problems such as peeling during reflow processing etc. it can.
  • the first laminated body manufacturing step described above is a ceramic side notch portion patterning step of forming a ceramic side notch portion in the ceramic dielectric layer formed on one main surface of the transfer source substrate;
  • the first laminated body in which the communication notch portion including the ceramic side notch portion and the conductor side notch portion in communication with the ceramic side notch portion is formed on the main surface on the opening side of the communication notch portion.
  • the second laminate with the polymeric material dielectric layer in an uncured or semi-cured state is superposed on the main surface of the polymeric material dielectric layer, and the first laminate and the second laminate are in that state.
  • the polymer material is pressed in the laminating direction, and the polymer material in the uncured or semi-cured state constituting the polymer material dielectric layer is force-filled into the communication notch and then the polymer material is cured.
  • the uncured or semi-cured polymer material constituting the polymer material dielectric layer can be reliably filled in the communication notch by pressure bonding, and the structure of the wiring substrate can be simplified. You can get it.
  • FIG. 1 is a cross-sectional view of a wiring board according to an embodiment of the present invention.
  • FIG. 2 is a view showing a manufacturing process of the wiring board of FIG.
  • FIG. 3 A diagram showing a manufacturing process of the wiring board of FIG.
  • FIG. 4 A diagram showing a manufacturing process of the wiring board of FIG.
  • FIG. 5 A diagram showing a manufacturing process of the wiring board of FIG.
  • FIG. 6 A diagram showing a manufacturing process of the wiring board of FIG. 1.
  • FIG. 7 A diagram showing a manufacturing process of the wiring board of FIG. 1.
  • FIG. 8 A diagram showing a manufacturing process of the wiring board of FIG.
  • FIG. 9 A diagram showing a manufacturing process of the wiring board of FIG.
  • FIG. 10 is a view showing a manufacturing process of the wiring board of FIG. 1;
  • FIG. 11 A diagram showing a manufacturing process of the wiring board of FIG.
  • FIG. 12 A diagram showing a manufacturing process of the wiring board of FIG.
  • FIG. 13 is a view showing a manufacturing process of the wiring board of FIG. 1.
  • FIG. 14A A view schematically showing a diced package.
  • FIG. 14B is a view schematically showing a diced package.
  • FIG. 15A An enlarged cross-sectional view of a wiring stack portion.
  • FIG. 15B An enlarged cross-sectional view of a wiring stack portion.
  • FIG. 1 schematically shows the cross-sectional structure of a wiring board 1 according to an embodiment of the present invention.
  • the wiring board 1 is formed of a heat resistant resin board (for example, bismaleimide-triazine resin board), a fiber reinforced resin board (for example, glass fiber reinforced epoxy resin), etc.
  • core conductor layers 4Y and 4y forming wiring metal layers in a predetermined pattern are respectively formed.
  • the core conductor layers 4Y and 4y are formed as a plane conductor pattern that covers most of the surface of the plate-like core 2c, and are used as a power supply layer (reference numeral 41 in the drawing) or a ground layer (reference numeral 40 in the drawing) .
  • a through hole 112 drilled by a drill or the like is formed on the plate-like core 2c, and a through hole conductor 30 is provided on the inner wall surface thereof to make the core conductor layers 4Y and 4y conduct each other.
  • the through holes 112 are filled with a resin filling material 31 such as epoxy resin.
  • a polymer material such as epoxy resin (and an inorganic filler that becomes a dielectric such as dielectric constant or silica powder for adjusting the withstand voltage, etc .: other polymer material dielectric layer
  • third conductor layers 4A, 4a are formed on the surface by Cu plating.
  • the core conductor layers 4Y and 4y and the third conductor layers 4A and 4a are connected to each other by vias 34, respectively.
  • second via layers 3A, 3a are respectively formed on the third conductor layers 4A, 4a.
  • the substrate core portion 2 is composed of a plate-like core 2c, core conductor layers 4Y and 4y, and first via layers 3Y and 3y.
  • the first polymer material dielectric layer 3A On the first main surface side (the main surface appearing on the upper side in the figure) of the substrate core portion 2, the first polymer material dielectric layer 3A, Cu plating layer is formed on the third conductor layer 4A.
  • a fourth conductor layer 4B consisting of a ceramic dielectric layer 5, a second conductor layer 4C consisting of a Cu plating layer, a second polymer material dielectric layer 3B, and a plurality of terminal pads 10 for connecting electronic components
  • the conductor layer 4D is stacked in this order to form the first side wiring stack portion 6.
  • the first conductor layer 4B, the second conductor layer 4C, and the fourth conductor layer 4D are conductively connected in the stacking direction via the vias 34 formed as a Cu filled film portion via the intermediate pads 12, respectively.
  • the back surface third conductor layer 4a the polymeric material dielectric layer is formed on the first via layer 3y.
  • a back side first conductor layer 4 b including the back side metal terminal pad 10 ′ is laminated in this order to form a second side wiring laminated portion 7.
  • the back surface side metal terminal pad 10 ' is used as a back surface pad for connecting the wiring substrate 1 itself to a mother board or the like by a pin grid array (PGA) or a ball grid array (BGA).
  • the conduction path consisting of via 34, intermediate pad 12 and through hole conductor 30 connecting terminal pad 10 and rear surface side terminal pad 10 'is a signal conduction path SL, a power supply conduction path PL and a ground conduction path.
  • the through hole conductor 30 included in the signal conduction path SL is insulated from the power supply layer 41 or the ground layer 40 by the insulating air gaps 40i and 41i.
  • the through-hole conductor 30 included in the power supply conduction path PL is connected to the ground layer 40 by the insulating gap 40i, and the through-hole conductor 30 included in the ground conduction path GL is connected to the power supply layer 41 by the insulating gap 41i. And are each isolated.
  • the wiring laminate portion 6 in which the dielectric layer and the conductor layer are laminated is formed on at least one of the main surfaces of the substrate core portion 2.
  • Core part 2 side Ka-like polymer material dielectric layer 3A, conductor layer 4B, and ceramic dielectric layer 5 (including notches 16): except for notches 16, ceramic layers are denoted by reference numeral 15 , And so on have a composite laminated portion 8 laminated in contact with each other in this order.
  • the summary of the method for manufacturing a wiring board of the present invention for manufacturing such a wiring board 1 is as follows.
  • the ceramic dielectric layer 5 and the conductor layer 4B are arranged in this order on one main surface of the transfer source substrate 50
  • the first laminated body 60 is manufactured by first forming the first laminated body 60 (first laminated body manufacturing process: FIGS. 4 to 5, steps 1 to 9).
  • a polymeric material dielectric layer 3A is formed on the main surface of the substrate core portion 2 to manufacture a second laminate 70 (a second laminate manufacturing step: FIG. 6, steps 10 to 11).
  • the laminate of the first laminate 60 and the second laminate 70 (panel) is diced into a unit (package) 70 u of the wiring board 1 (FIGS. 14A and 14B).
  • the first stacked body 60 is formed by forming the ceramic dielectric layer 5 and the conductor layer 4 B in this order on one main surface of the transfer source substrate 50.
  • the transfer base substrate 50 is removed after being manufactured and laminated on a second laminate 70 in which the polymer material dielectric layer 3A is formed on the main surface of the substrate core portion 2, and then the transfer source substrate 50 is removed. Dicing to unit 70u. That is, the thin and fragile ceramic dielectric layer 5 can be removed by providing it to the bonding step in the form of being reinforced with the transfer source substrate 50, so that it is not necessary to separate and insert it. It is possible to dramatically improve the manufacturing efficiency and yield of the wiring board 1 having the composite laminate portion 8 in which the material dielectric layer 3A, the conductor layer 4B and the ceramic dielectric layer 5 are stacked.
  • positioning pins 90 are passed through the guide through holes 50h and 70h respectively formed in the first laminate 60 and the second laminate 70 shown in FIGS. 7 to 9.
  • the first stacked body 60 and the second stacked body 70 can be bonded to each other while being positioned relative to each other.
  • pattern deviation or the like between the ceramic dielectric layer 5 on the first laminated body 60 side and the conductor layer 4B laminated in contact with this, and the polymeric material dielectric layer 3A on the second laminated body 70 side are effectively achieved. Can be prevented.
  • the transfer source substrate 50 the one in which the guide through holes 50h shown in FIG. 2 are formed by drilling or the like is used as the transfer source substrate 50.
  • a metal substrate 50 having a melting point higher than the firing temperature of the ceramic forming the ceramic dielectric layer 5 can be used as the transfer source substrate 50.
  • the above-mentioned first laminate manufacturing process More specifically, the unfired ceramic material layer forming step of forming an unfired ceramic material layer 15 g which is a material force before firing of the ceramic dielectric layer 5 on the main surface of the transfer source substrate 50 (FIG. 4: Step 1 to Step 3) And a firing step (FIG. 5: step 4) of firing 15 g of the unfired ceramic material layer together with the metal substrate 50.
  • the transfer source substrate 50 is used for the solder ring also when firing the unfired ceramic material layer 15g. The handling is extremely simple because no problem occurs even if the transfer source substrate 50 together with the ceramic dielectric layer 5 is exposed to the thermal history of firing.
  • the ceramic dielectric layer 5 can also be formed by a vapor phase film forming method such as a sputtering method or a chemical solution film forming method such as a sol-gel method.
  • a vapor phase film forming method such as a sputtering method
  • a chemical solution film forming method such as a sol-gel method.
  • ceramic dielectric layer 5 used for a capacitor is a composite oxide having a perovskite-type crystal structure, for example, barium titanate, strontium titanate, and lead titanate 1 in order to improve capacitance. It is particularly preferable to use the present invention because it is particularly high in dielectric constant and composed of two or more species and it is relatively easy to manufacture.
  • the metal substrate 50 may be an Fe-based or Ni-based metal plate, or a metal plate such as Mo-based, W-based, or Ta-based metal having a high melting point.
  • the unfired ceramic material layer 15 g can be made into a ceramic green sheet 15 g formed into a sheet shape by kneading the ceramic material powder with a bonding polymer material (V, a binder).
  • a thin layer of ceramic green sheet 15 g can be easily manufactured by a doctor blade method or the like, and since it is flexible, it can be easily soldered.
  • the thickness of the ceramic dielectric layer 5 obtained by the firing is, for example, 1 ⁇ m to 100 m.
  • the ceramic dielectric layer 5 also provides a high dielectric constant ceramic force having a relative dielectric constant of 10 or more.
  • Ceramic dielectric layer 5 is suitable for formation of vias described later, capacity adjustment of a capacitor, etc. It is necessary to putter in a shape. However, since the ceramic dielectric is chemically stable, patterning by chemical etching is not easy, and since it has a high melting point, patterning by a laser or the like is also difficult in a densified state by firing. However, if the following method is adopted, the above patterning can be carried out very easily. That is
  • step 2 After bonding 15 g of the ceramic green sheet on the metal substrate 50 (FIG. 4: step 1) and then patterning in the form of the ceramic dielectric layer 15 to obtain the ceramic green sheet 15 g (step 2), the firing step (step 2) Figure 5: Perform step 4).
  • step 2 Figure 5: Perform step 4.
  • the ceramic dielectric layer 5 By forming the ceramic dielectric layer 5 by firing the unbaked ceramic dry coating layer obtained by the sol-gel method.
  • the ceramic green sheet 15g shown in FIG. 3 can be formed on a carrier sheet 51 (for example, a polyethylene terephthalate resin sheet) which also has a high polymer material strength.
  • a carrier sheet 51 for example, a polyethylene terephthalate resin sheet
  • 15 g of ceramic green sheets can be produced with high efficiency by the well-known doctor blade method or the like.
  • a ceramic raw material powder is coated with a binding polymer material, a dispersing agent, a plasticizer, a solvent, and the like to form a slurry, which is coated on a carrier sheet 51 and dried to form a ceramic durin sheet 15 g.
  • the green sheet 15 g is formed into a long form as a ceramic green sheet 52 with a carrier sheet by applying a slurry while pulling out the carrier sheet 51 wound in a roll shape.
  • the carrier sheet 51 is preferably made of polyethylene terephthalate resin from the viewpoint of securing strength at the time of green sheet production such as slurry application / drying, and releasability of the 15 g of daren sheet.
  • the thickness of the ceramic dielectric layer obtained by firing is preferably adjusted so as to be 1 ⁇ m or more and 100 m or less when it is desired to use it for forming a high capacity capacitor or the like. Therefore, the thickness of the ceramic green sheet 15g used for firing and forming the ceramic dielectric layer is also appropriately adjusted so as to obtain the thickness after firing (for example, 200 m or less).
  • the ceramic green sheet 52 with a carrier sheet needs to be cut into an appropriate size and used with a cutting blade when it is used for manufacturing a substrate (multilayer body). There is.
  • the thickness of the ceramic green sheet 15g is adjusted to be thin as described above, if the carrier sheet 51 is excessively thin, the ceramic green sheet 15g tends to tear in the vicinity of the cutting blade, etc.
  • the thickness of the carrier sheet 51 made of polyethylene terephthalate resin it is desirable to set the thickness of the carrier sheet 51 made of polyethylene terephthalate resin to 20 m or more.
  • the upper limit of the thickness of the carrier sheet 51 is not particularly limited, but if it is set to 100 m or less, appropriate flexibility for achieving convenience such as winding is exhibited.
  • a guide through hole 52 h is formed by punching or the like. Further, as shown in FIG. 2, guide through holes 50h are formed in the metal substrate 50 at corresponding positions.
  • This guide through hole 50h can be easily formed by chemical etching (in particular, in the case where the thickness of the metal substrate is 100 m or less (20 m or more in consideration of the ring)). Specifically, the main surface of the metal substrate 50 is covered with an etching resist, an etching window corresponding to the shape of the through hole in the guide is formed, and the substrate is formed by immersion in an etching solution.
  • the etchant may be the same as that used when removing the metal substrate 50 (described later).
  • the ceramic green sheet 15 g in a state where the carrier sheet 51 is bonded to the opposite side of the step 1 of FIG. In this state, the carrier sheet 51 is laser-patterned with the carrier green sheet 51, and then the carrier sheet 51 can be removed and the baking process can be performed, as shown in step 3.
  • the carrier sheet 51 is laser-patterned with 15 g of the ceramic green sheet, the periphery of the area to be patterned is protected by the carrier sheet 51. Therefore, the burned ceramic green sheet 15 g is also dispersed with the carrier sheet 51. There is an advantage that it can be removed and it is difficult to cause contamination by the droplets on 15 g of the ceramic green sheet after patterning.
  • the second laminate 70 including the substrate core portion 2 shown in FIG. 6 is a wiring substrate to be manufactured.
  • a plurality of units 70u (specifically, a portion which becomes a part of one wiring board unit in the second stacked body 70) are integrated in a plurality of planes.
  • the dielectric layers 3A, 3a of the polymeric material are formed on both main surfaces of the substrate core portion 2 prepared in advance, and the through holes 70h of the guide are formed by drilling all the way in step 11.
  • the guide through holes 70h are formed at the four corners of each unit 70u.
  • the first stacked body 60 is a unit 70 u included (specifically, a part of the unit of one wiring board in the first stacked body 60).
  • a plurality of portions having a smaller number than the second stacked body 70 (specifically, the number of portions which become a part of one wiring board unit in the second stacked body 70) It is effective to adopt a step of combining and disposing on the second laminated body 70.
  • the unfired ceramic material layer 15g is shrunk by sintering, and if the large-area metal substrate 50 is used, the warpage of the first laminate 60 obtained by the contraction may increase.
  • the effect of warpage at the time of firing is greater than in the case where the entire first laminate 60 is integrally formed. Can be kept low.
  • the metal substrate 50 can be removed by chemical etching. According to this method, the metal substrate 50 can be removed while minimizing mechanical damage to the thin layer ceramic dielectric layer 5.
  • the etchant used in the case of using the Fe-based or Ni-based metal substrate 50 may be, for example, a sodium chloride (III) aqueous solution, a copper (II) aqueous solution, or an acid etchant such as hydrochloric acid.
  • the entire metal substrate 50 may be chemically etched. For example, when using an Fe-based or Ni-based metal substrate 50, the metal substrate 50 has a main layer and an Fe content higher than that of the main layer. The entire substrate etching amount can be reduced by etching the separation layer to peel off the substrate main body.
  • the wiring substrate 1 has a conductor-side cutout 18 in which a part of the layer is cut away in the in-plane direction in the composite laminated portion 8, and the ceramic dielectric Layer 5 in the in-plane direction
  • a communication notch 21 is formed which has a ceramic side notch 16 in which a part of the layer is cut and the ceramic side notch 16 and the conductor side notch 18 communicate with each other, and a polymer material dielectric is formed.
  • the polymer material constituting the layer 3A is filled in the communication notch 21 through the conductor-side notch 18 and the ceramic-side notch 16.
  • the polymeric material dielectric layer 3A, the conductor layer 4B and the ceramic dielectric layer 5 are in contact with each other in this order from the substrate core portion 2 side
  • the polymer material constituting the polymer material dielectric layer 3A is filled on the side of the communication notch portion 21 formed on the conductor layer 4B and the ceramic dielectric layer 5 side.
  • the adhesion strength can be increased, and problems such as peeling at the time of reflow processing can also occur.
  • the above structure can be obtained by performing the first laminate manufacturing step as follows.
  • the ceramic side notch portion 16 is pattern formed on the ceramic dielectric layer 15g formed on one of the main surfaces of the transfer source substrate 50 (ceramic side notch portion patterning step: FIG. 4, step) 3).
  • a conductor layer 54 (which will be 4B later) is formed on the ceramic dielectric layer 15 after the patterning (conductor layer formation step: FIG. 5, step 5).
  • the conductor-side notches 18 are formed so as to communicate with the ceramic-side notches 16 with respect to the conductor layer 4 B (conductor-side notches patterning step: steps 6 to 9).
  • the conductor layer 54 is formed as a Cu plating layer that entirely wraps the transfer source substrate 50 and the ceramic dielectric layer 15 subjected to patterning and firing.
  • a photosensitive etching resist layer 55 is formed, and in step 7, the etching window 55p is patterned by exposing and developing it.
  • the conductor layer 54 is etched using the etching resist layer 55 in step 8, the etching resist layer 55 is removed as shown in step 9.
  • the dicing surface force should also be at least a second pulling width W (> W) pull it down (inside)
  • Etch window 55p to form As the second pull-down width W, a range of 0.8 mm or more and 2.5 mm or less is desirable, for example: 1. O mm
  • the area of the pole 20 is reduced, which is not preferable.
  • the value of the second pull-down width W is set for the second electrode 11.
  • the outer end faces of the ceramic dielectric layer 15 forming the capacitor is lowered (formed inside) than the package end face, the outer end faces of the first electrode 20 and the second electrode 11 By further pulling down (forming inward) the outer end face of the body layer 15, exposure of the capacitor to the end face of the package can be avoided, and the occurrence of interlayer short circuit can be surely prevented.
  • the first laminated layer is formed with the communication notch 21 including the ceramic side notch 16 and the conductor side notch 18 communicating with the ceramic side notch 16.
  • the second laminated body 70 in the polymeric material dielectric layer 3A in an uncured or semi-cured state is applied to the main surface on the opening side of the communication notch 21 with respect to the body 60, Overlay on the main surface.
  • the upper force upper base 80 (having a guide wedging hole 80h), the auxiliary plate 81 (having a guiding weir through hole 8 lh) which is also stainless steel and the like, and the release film 82 (having a guide wedging hole 82h ),
  • Auxiliary plate 85 (with guide hole 85h), lower surface 86 (with pin holding hole 86h for holding the base end of positioning pin 90), cushion sheet 87 and carrier plate 88 It is laminated in this order.
  • the above-mentioned laminated body is pressurized using a known hydraulic press device or the like (not shown).
  • a known hydraulic press device or the like not shown.
  • the uncured or semi-cured polymer material constituting the polymer dielectric layer 3A is notched in communication.
  • the part 21 is press-fit filled.
  • the polymer material is cured by heating or the like.
  • the polymer material in the non-cured or semi-cured state constituting the polymer material dielectric layer 3A can be reliably filled in the communication notch 21 by pressure bonding, and the structure of the wiring substrate 1 can be easily obtained. It is
  • a spacer 83 made of a metal plate having the same thickness as the first laminate 60 is disposed also in the space serving as a margin. By doing so, pressure can be applied without any level difference, and unnecessary polymer material flow can be suppressed.
  • the thickness of the first laminate 60 at the time of transfer pressing is not less than 0.1mmt and not more than 1lmt (preferably, not less than 0.235 mmt and not more than 0.360 mmt).
  • a metal plate for example, a stainless steel plate having a thickness of 1 to lmmt and 1 to 10 lmmt (preferably, 0.235 mmt or more and 0.30 mmt or less).
  • wiring board 1 uses conductor layer 4B included in composite laminated portion 8 as first conductor layer 4B, and from the opposite side to ceramic dielectric layer 5 from first conductor layer 4B. It has a second conductor layer 4C to be stacked, and the first conductor layer 4B, the ceramic dielectric layer 5 and the second conductor layer 4C can form a capacitor.
  • the first electrode 20 of the capacitor is formed on the first conductor layer 4B, and the second electrode 11 is formed on the second conductor layer 4C.
  • One of the first electrode 20 and the second electrode 11 is connected to the power supply conduction path PL, and the other is connected to the ground conduction path PL.
  • the in-plane projected overlapping area appears less, but in practice other than the notches In the part of the figure, a continuous thin film is formed in the in-plane direction, and the projected overlapping area is also much larger than that in the cross section. The same applies to the ceramic dielectric layer 5.
  • the wiring laminated portion 6 including the molecular material dielectric layer (build-up layer), and the wiring substrate and the electronic components mounted thereon (not shown) It is no longer necessary to externally attach an intermediate board incorporating a capacitor between them), which contributes to the low profile of the assembly.
  • at least one of the communication cutouts 21 communicates with the conductor-side cutout 18 with respect to the ceramic-side polymer material-filled portion 17 for filling the ceramic-side cutout 16 on the opposite side to the one on the other side.
  • a conductor pattern (second electrode) 11 forming a part of the second conductor layer 4C is disposed in contact with the second conductor layer 4C.
  • the interface between the conductor pattern 11 and the ceramic-side polymer material-filled portion 17 is formed flush with the main surface of the ceramic dielectric layer 5 on the side of the second conductor layer 4C.
  • the flatness of the second conductor layer 4C side main surface of the ceramic dielectric layer 5 is improved, and the flatness of the surface of the wiring laminated portion 6 is taken over, for example, the outermost layer of the wiring laminated portion 6
  • the coplanarity of the node 12 for connecting electronic components formed in the part becomes good.
  • Such a structure can be obtained by pressing the polymer material into the communication notch 21 and curing the same in the bonding step as described above, so that the ceramic side polymer material filling portion 17 can be formed on the transfer source substrate 50. It can be easily formed by carrying out the transfer source substrate removing step after the main surface is formed to be flush with the ceramic dielectric layer 5 (FIG. 10: step 14).
  • the wiring board 1 is provided with a third conductor layer 4A in contact with the polymer material dielectric layer 3A from the side opposite to the first conductor layer 4B, and the second conductor layer 4C
  • the conductor pattern 11 and the third conductor layer 4A are conductively connected by the via 34 penetrating the ceramic dielectric layer 5, the first conductor layer 4B, and the polymeric material dielectric layer 3A in this order, and the first conductor
  • the through hole 34h for forming a via in the ceramic side notch 16 is insulated while being mutually insulated by the polymer material filling the conductor side notch 18.
  • the ceramic-side polymeric material filling portion 17 filling the portion 16 is formed.
  • the through holes for the vias are directly drilled in the ceramic dielectric layer 5 having an insulating function inherently, the through holes are formed in the ceramic side polymer material filled portion 17 on the inside thereof. Because of this, there is an advantage that the formation of the through holes 34h is easy. Specifically, as shown in steps 15 and 16 of FIG. 10, through holes for forming vias from the main surface side exposed by removing the transfer source substrate 50 to the ceramic side polymer material filled portion 17. Via hole 34h) can be easily formed by laser LB (laser processing).
  • the laser LB is a CO 2 laser, a YAG laser or an excimer laser.
  • the second conductor-side notch 18 in which a portion of the layer is cut away in the in-plane direction is formed in the second conductor layer 4 C It is formed in the form of communication.
  • the second conductor layer 4C is formed after the transfer source substrate removing step is completed, and the second conductor side cutout portion 18 is communicated with a part of the communication cutout portion 21.
  • FIG. 11 Step 17 to FIG. 12: Step 21
  • another polymeric material dielectric layer 3B is formed on the second conductor side notch 18 as a main portion of the second conductor layer 4C.
  • Method of laminating and forming on the surface step 22), filling the polymer material constituting the polymer material dielectric layer 3B in the second conductor side notch 18 and bonding it with the ceramic side polymer material filled portion 17 Can easily be obtained.
  • step 17 the exposed surface portion of the ceramic-side polymer material-filled portion 17 and the inner surface of the via hole 34 h are covered with the electroless Cu plating layer 91 for metal conduction, and in step 18, the metal resist layer 92 further. Form Then, in step 19, the photo resist layer 92 is exposed and developed to form a photo window 92p corresponding to the portion to be plated.
  • the following plating step is performed.
  • Fig. 12 Step 20
  • the external end face of the second electrode 11 formed by the unit of the wiring board 1 to be obtained (package) 70u, as well as the external size of the second electrode 11 to be obtained is also reduced by at least the second pull width w (> w)
  • step 20 of FIG. 12 the inside of the via hole 34 h is filled and plated by electrolytic Cu plating to form the via 34 and the intermediate pad 12.
  • the second conductor side notch 18 is formed by removing the plating resist layer 92 in step 21 and removing the exposed electroless Cu plating layer by quick etching without forming electrolytic copper plating and forming an electroless Cu plating.
  • the second conductor layer 4C is formed.
  • a polymeric material dielectric layer 3B is formed.
  • the via holes 34h are formed in the polymer dielectric layer 3B in step 23 of FIG. 13, and the vias 34 filling the via holes 34h and the terminal pads 10 and 10 'are formed in step 24. doing.
  • the panel obtained in step 24 is diced by a known die-indicator machine not shown, and as schematically shown in FIG. 14A and FIG. Do.
  • the outer end face of the ceramic dielectric layer 15 is formed by reducing the dicing surface force by at least the first pull-down width W (FIG. 4:
  • Steps 2 and 3 and the outer end face of the first electrode 20 and the second electrode 11 are also formed by lowering by at least the second pulling width W (FIG. 5: Step 8, FIG. 12)
  • Step 20 the ceramic dielectric layer 15 and the first electrode 20 and the second electrode 11 are prevented from being exposed at the package end face after dicing, and the occurrence of oxidative corrosion can be prevented in advance. Further, since the adhesion between the first electrode 20 and the second electrode 11 and the interface with the ceramic dielectric layer 15 becomes strong, delamination due to shear stress at the time of dicing and a moisture absorption intrusion path thereafter are prevented beforehand. Furthermore, there is no possibility of an interlayer short circuit that would cause no sag in the first electrode 20 and the second electrode 11 during dicing.
  • a conductor e.g., Cu
  • a ferroelectric e.g., barium titanate
  • the wiring board 1 forms a capacitor only in the first side wiring laminated portion 6 and forms a capacitor in the second side wiring laminated portion 7 as shown in FIG. ...
  • the necessary capacitance for example, 1 ⁇ F or more
  • the material of the ceramic dielectric layer 5 and the like can be secured only by the first side wiring laminate portion 6. If this is the case, no capacitor is necessary for the second side wiring stack portion 7.
  • the number of conductor layers of the second side wiring stack portion 7 is smaller than the number of conductor layers of the first side wiring stack portion 6 because the capacitor is not provided.
  • the layer thickness of the second side wiring stacked portion 7 becomes smaller than the layer thickness of the first side wiring stacked portion 6.
  • the layers are included in the composite laminated portion 8 at the layer level corresponding to the composite laminated portion 8 on the first side, counting from the substrate core portion 2 shown in comparison with FIGS. 15A and 15B.
  • the second side wiring laminate portion 7 has a polymeric material dielectric layer 33 whose thickness is increased more than that of the high molecular weight material dielectric layer 3.
  • the thickness of the high-polymer dielectric layer 3 included in the composite lamination portion 8 of the first-side wiring lamination portion 6 is D1
  • the thickness of the high-polymer dielectric layer 33 of the second-side wiring lamination portion 7 is D2.
  • the thickness of the polymer material dielectric layer is basically defined by the thickness of the portion sandwiched between the upper and lower conductor layers.
  • the polymeric material dielectric layer 33 having the thickness D2 as described above is obtained by two film laminations.
  • the polymeric dielectric layer is made of a resin film for buildup having the same thickness and the same material strength regardless of whether it is the first side or the second side, so it becomes D2 2D1. There is a reason to form the polymeric material dielectric layer 33 in multiple times.
  • the process will be described in detail after completion of the transfer source substrate process.
  • step 1 of FIG. 4 to step 15 of FIG. 10 transfer source substrate removing step
  • step 15 of FIG. 10 When the transfer source substrate removing step shown in step 15 of FIG. 10 is completed, the step of forming a second conductor layer 4C which is an upper electrode of the capacitor is started. At this time, the second side is advanced to the stage of providing the base conductor layer 4 a and the polymeric material dielectric layer 3 a on the substrate core portion 2. That is, the formation of the second side wiring stacked portion 7 is stopped at the stage of the second laminated body forming step (step 11 of FIG. 6) described above.
  • step 16 of FIG. 10 in order to form a second conductor layer 4C that forms an electrode of the capacitor.
  • a step of forming via holes 34 h for forming via conductors 34 for interlayer connection in the composite laminate portion 8 to be performed is performed.
  • a main surface side force via hole 34h exposed by removing the transfer source substrate 50 is formed on the ceramic side polymer material filled portion 16 by the laser etching or the photolithography technique as described above; Be done.
  • the polymer dielectric layer 3a remains exposed on the second side during the process of forming the via hole. Therefore, in the case of employing the photolithographic technique, it is preferable to perform masking with a protective material such as a tape so that the second-layer polymer material dielectric layer 3a is not etched. With the laser LB method, the number of processes can be reduced since such labor is unnecessary.
  • the diameter of the via hole 34h shown in step 16 is the size (diameter) of the polymer material filling the conductor side notch 18 in the in-plane direction with the conductor pattern forming the first conductor layer 4B. And the ceramic dielectric layer 5, the first conductor layer 4B, and the polymer material dielectric layer 3A, which form the composite laminate portion 8, and the base material layer 4A at the bottom through the surface-side force in this order. Form a form of exposure.
  • the second conductor layer 4C (connected to the base conductor layer 4A by the via conductor 34) so as to be galvanically separated from the first conductor layer 4A. It is possible to form easily.
  • the diameter of the via hole 34h corresponds to the spot diameter of the laser LB appropriately adjusted.
  • a chemical solution having a corrosive force to the polymer material in the via hole 34 h. Wash with At the bottom of the via hole 34h, a smear (resin residue) derived from laser processing is attached.
  • the desmear liquid for example, alkaline potassium permanganate solution can be used.
  • a wet process using a desmear solution can be employed in the step of removing the smear at the bottom of the via hole 34h. Also, in consideration of productivity, it is preferable to immerse the entire work (wiring substrate under production) in the desmear liquid.
  • each cleaning process such as washing with water or neutralization is not performed, and after the surface of the work (wiring substrate during production) is activated, Move on to the electroless Cu plating process of step 17.
  • an electroless plating layer 91 is formed on the entire surface of the work.
  • the workpiece is immersed as it is in the active solution processing solution and the electroless Cu plating solution, so the second side
  • the electroless Cu plating layer 91 is also formed on the surface of the high-polymer material dielectric layer 3a. This can be easily removed by the quick etching described later.
  • the electroless Cu plating layer 91 is a base conductor for current conduction for performing the electrolytic Cu plating step of step 20.
  • the electrolytic Cu plating step is a step of forming the via conductor 34 on the inner surface of the via hole 34 h and forming the second conductor layer 4 C integrally with the via conductor 34.
  • the electrolytic Cu plating process is performed in a state where the plating resist 92 is formed so that only a portion to form a conductor pattern is exposed.
  • the tack resist 92 is formed by applying a dry film resist 92 molded into a film shape shown in step 18 and then patterning the dry film resist 92 shown in step 19 by photolithography. Be done.
  • the plating resist 92 is formed to cover the entire surface of the polymeric material dielectric layer 3a on the second side. This is to prevent the polymeric material dielectric layer 3a from coming into contact with the electrolytic Cu plating liquid.
  • the electrolytic Cu plating process of FIG. 12 is performed to laminate the second conductor layer 4C from the side opposite to the first conductor layer 4B with respect to the ceramic dielectric layer 5.
  • a capacitor structure is completed by the first conductor layer 4B, the ceramic dielectric layer 5 and the second conductor layer 4C.
  • the via conductor 34 is a filled via in which the entire inside of the via hole 34 h is filled with a plating conductor.
  • a conformal via may be adopted in which the plating conductor is formed only on the inner wall surface of the via hole 34 h.
  • the second additive layer is formed by the semi-additive process in which the electrolytic Cu plating process is performed. It is also possible to form conductor layer 4C.
  • the first and second plating resists 92 shown in step 21 are removed, and the electroless plating layer 92 is removed by quick etching. .
  • the first external connection terminal (terminal pad 10) and the second external connection terminal (terminal pad 10 ') are formed by a via formation and build-up method using a plating technique.
  • the polymer material dielectric layer 3B is formed on the first side second conductor layer 4C, and the polymer material dielectric layer 3a of the second side is the polymer material dielectric layer 3a. It is covered with another polymeric material dielectric layer 3b.
  • the polymer material dielectric layer 3a on the second side is roughened in the desmear process at the time of forming the via hole 34h in FIG.
  • a polymeric material dielectric layer 33 is formed.
  • the high-molecular-weight dielectric layer 3a and the high-molecular-weight dielectric layer 3b can be combined to obtain a thick high-molecular-weight dielectric layer 33 having a surface that is not roughened.
  • via holes 34 h are formed as shown in step 23 and the terminal pads 10 ′ are formed as shown in step 24 in the second-side polymer material dielectric layer 3 a which has been roughened.
  • the polymer material dielectric layer 3a is subjected to the desmear treatment twice, and the surface is excessively roughened.
  • the plating conditions are different between the first side and the second side, which causes a problem that it becomes difficult to form a resin layer of uniform thickness and uniform characteristics.
  • the polymer material dielectric layer 3b is newly formed on the second side, so there is no such problem.
  • the thicknesses of the polymer dielectric layer 3B on the first side and the dielectric layer 33 on the second side are different, the conditions of the laser to be irradiated at the time of forming the via holes should be appropriately adjusted. is necessary.
  • the thick polymer material dielectric layer 33 on the second side an effect of improving the strength of the second side wiring laminate portion 7 can also be expected.
  • the polymer material dielectric layer 3a on the second side is protected to prevent surface roughening, and a desmear process is performed, or a desmear solution is sprayed only on the first side. It is sufficient if the desmear process is carried out by the method or the desmear process is carried out dry. However, this alone can not be expected to improve the strength of the second side wiring stack portion 7. Therefore, it is preferable to adopt the procedure of the present embodiment.
  • the polymer material dielectric layer 3a on the second side is protected to carry out the desmear process, or the desmear process is carried out by spraying the desmear solution only on the first side, or the desmear process is carried out dry.
  • the method is inferior to the present embodiment in terms of productivity.
  • the thicknesses of the first side wiring stacked portion 6 and the second side wiring stacked portion 7 can be made equal to each other. Warpage of the wiring board can be prevented.
  • the polymeric material dielectric layer 3b can be formed by film laminating a plurality of times.
  • the vias 34 of the second side wiring stacked portion 7 there is a problem if the polymer material dielectric layer 33 is too thick. Therefore, a polymer material dielectric layer 33 consisting only of the polymer material dielectric layer 3a and the polymer material dielectric layer 3b is divided into two layers via the conductor layer. (Or a plurality of layers) may be formed.
  • a polymer material dielectric layer (having a thickness equal to that of the polymer material dielectric layer 33) is further formed. Form as in step 22). Thereafter, the via holes 34 are formed in the polymeric material dielectric layer in the same manner as in step 23, and thereafter, the vias 34 filling the via holes 34 and the terminal pads 10 'are formed in the same manner as in step 24. It is.
  • the polymer material dielectric layers 3B and 3b of the first side and the second side can be formed by applying and drying a liquid polymer material, in addition to a method of laminating the polymer material previously formed into a film.
  • the former method is preferred.
  • the guide through holes 70 h used when forming the composite laminated portion 8 on the substrate core portion 2 remain, Because the layer 3B, 3b is blocked! /, So the guide through hole 70h does not appear in the appearance! /.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

L’invention concerne un tableau de connexions (1) qui comporte une partie de câblage stratifiée (6) où sont mises en place une couche diélectrique et une couche conductrice au moins sur une surface majeure d'une partie centrale du tableau (2). La partie de câblage stratifiée (6) inclut une partie stratifiée composite (8) où une couche diélectrique de matériau polymère (3A), une couche conductrice (4B) et une couche diélectrique en céramique (5) sont mises en place dans l’ordre cité depuis le côté de la partie centrale du tableau (2) et sont en contact l’une avec l’autre. La couche conductrice (4B) de la partie stratifiée composite (8) présente une entaille du côté conducteur (18) formée en découpant une partie de la couche conductrice (4B) dans la direction parallèle à la couche conductrice (4B), et la couche diélectrique en céramique (5) présente une entaille du côté céramique (16) formée en découpant une partie de la couche diélectrique en céramique (5) dans la direction parallèle à la couche diélectrique en céramique (5), formant ainsi une entaille de communication (21) où l’entaille du côté céramique (16) et l’entaille du côté conducteur (18) communiquent l’une avec l’autre. Le matériau polymère formant la couche diélectrique de matériau polymère (3A) est placé dans l’entaille de communication (21) de telle manière qu’il se prolonge depuis l’entaille du côté conducteur (18) vers l’entaille du côté céramique (16).
PCT/JP2005/023909 2004-12-28 2005-12-27 Tableau de connexions et son procede de fabrication WO2006070807A1 (fr)

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US11/793,817 US20080289866A1 (en) 2004-12-28 2005-12-27 Wiring Board and Wiring Board Manufacturing Method

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JP2004381462 2004-12-28
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2178116A1 (fr) * 2007-08-08 2010-04-21 Ibiden Co., Ltd. Substrat de montage de circuit intégré et procédé pour sa fabrication

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7956293B2 (en) * 2006-04-03 2011-06-07 Panasonic Corporation Multilayer printed wiring board and manufacturing method thereof
US7572709B2 (en) * 2006-06-29 2009-08-11 Intel Corporation Method, apparatus, and system for low temperature deposition and irradiation annealing of thin film capacitor
US8018568B2 (en) * 2006-10-12 2011-09-13 Cambrios Technologies Corporation Nanowire-based transparent conductors and applications thereof
JP5409369B2 (ja) 2006-10-12 2014-02-05 カンブリオス テクノロジーズ コーポレイション ナノワイヤベースの透明導電体およびその適用
US8877565B2 (en) * 2007-06-28 2014-11-04 Intel Corporation Method of forming a multilayer substrate core structure using sequential microvia laser drilling and substrate core structure formed according to the method
US8440916B2 (en) * 2007-06-28 2013-05-14 Intel Corporation Method of forming a substrate core structure using microvia laser drilling and conductive layer pre-patterning and substrate core structure formed according to the method
JP5436963B2 (ja) * 2009-07-21 2014-03-05 新光電気工業株式会社 配線基板及び半導体装置
US20110024898A1 (en) * 2009-07-31 2011-02-03 Ati Technologies Ulc Method of manufacturing substrates having asymmetric buildup layers
CN102822112B (zh) 2010-03-30 2014-06-18 株式会社村田制作所 金属基基板及其制造方法
WO2012137548A1 (fr) * 2011-04-04 2012-10-11 株式会社村田製作所 Substrat multicouche à composant de puce intégré et son procédé de fabrication
SG187278A1 (en) * 2011-07-20 2013-02-28 Sony Corp A waveguide
US9935166B2 (en) 2013-03-15 2018-04-03 Qualcomm Incorporated Capacitor with a dielectric between a via and a plate of the capacitor
US9634640B2 (en) 2013-05-06 2017-04-25 Qualcomm Incorporated Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) and related components and methods
KR20140134479A (ko) * 2013-05-14 2014-11-24 삼성전기주식회사 인쇄회로기판
CN103413766B (zh) * 2013-08-06 2016-08-10 江阴芯智联电子科技有限公司 先蚀后封芯片正装三维***级金属线路板结构及工艺方法
CN103456645B (zh) * 2013-08-06 2016-06-01 江阴芯智联电子科技有限公司 先蚀后封三维***级芯片正装堆叠封装结构及工艺方法
CN103400771B (zh) * 2013-08-06 2016-06-29 江阴芯智联电子科技有限公司 先蚀后封芯片倒装三维***级金属线路板结构及工艺方法
CN104752318B (zh) * 2013-12-27 2019-01-22 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法
US9844136B2 (en) * 2014-12-01 2017-12-12 General Electric Company Printed circuit boards having profiled conductive layer and methods of manufacturing same
US10952320B2 (en) * 2016-03-24 2021-03-16 Kyocera Corporation Printed wiring board and method for manufacturing same
US10249561B2 (en) * 2016-04-28 2019-04-02 Ibiden Co., Ltd. Printed wiring board having embedded pads and method for manufacturing the same
KR20190012485A (ko) * 2017-07-27 2019-02-11 삼성전기주식회사 인쇄회로기판 및 그 제조 방법
JP2018021914A (ja) * 2017-08-04 2018-02-08 スリーエム イノベイティブ プロパティズ カンパニー Ｉｃデバイス用ソケット
CN107889350B (zh) * 2017-12-22 2024-06-25 珠海市中祺电子有限公司 多层线路板
US11715688B2 (en) * 2020-05-26 2023-08-01 Qualcomm Incorporated Variable dielectric constant materials in same layer of a package
US11974031B1 (en) 2021-04-16 2024-04-30 Apple Inc. Hybrid sensor shift platform with multi-core substrate for camera
TWI781049B (zh) * 2022-01-24 2022-10-11 欣興電子股份有限公司 電路板結構及其製作方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000208945A (ja) * 1999-01-18 2000-07-28 Ngk Spark Plug Co Ltd コンデンサ内蔵配線基板及びその製造方法
JP2002009416A (ja) * 2000-06-20 2002-01-11 Matsushita Electric Works Ltd プリント配線板製造用シート材、このプリント配線板製造用シート材を用いたプリント配線板の製造方法及びプリント配線板
JP2002217540A (ja) * 2001-01-17 2002-08-02 Matsushita Electric Ind Co Ltd 多層配線基板の製造方法及びその装置
JP2003142624A (ja) 2001-10-31 2003-05-16 Fujitsu Ltd 受動素子を内臓した半導体装置の製造方法、中継基板及びその製造方法
JP2004179288A (ja) * 2002-11-26 2004-06-24 Shinko Electric Ind Co Ltd 電子部品実装構造及びその製造方法
WO2004056160A1 (fr) * 2002-12-13 2004-07-01 E.I. Du Pont De Nemours And Company Cartes imprimees equipees de condensateurs encastres a faible inductance et procedes de fabrication correspondants

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5073840A (en) * 1988-10-06 1991-12-17 Microlithics Corporation Circuit board with coated metal support structure and method for making same
US5413807A (en) * 1994-10-17 1995-05-09 Xerox Corporation Method of manufacturing a donor roll
WO1996022008A1 (fr) * 1995-01-10 1996-07-18 Hitachi, Ltd. Appareil electronique a faible interference electromagnetique, carte de circuit a faible interference electromagnetique et procede de fabrication de la carte de circuit a faible interference
US6207522B1 (en) * 1998-11-23 2001-03-27 Microcoating Technologies Formation of thin film capacitors
US6270835B1 (en) * 1999-10-07 2001-08-07 Microcoating Technologies, Inc. Formation of this film capacitors
US6433993B1 (en) * 1998-11-23 2002-08-13 Microcoating Technologies, Inc. Formation of thin film capacitors
US6214445B1 (en) * 1998-12-25 2001-04-10 Ngk Spark Plug Co., Ltd. Printed wiring board, core substrate, and method for fabricating the core substrate
US6349456B1 (en) * 1998-12-31 2002-02-26 Motorola, Inc. Method of manufacturing photodefined integral capacitor with self-aligned dielectric and electrodes
US6317023B1 (en) * 1999-10-15 2001-11-13 E. I. Du Pont De Nemours And Company Method to embed passive components
TW533758B (en) * 2000-07-31 2003-05-21 Ngk Spark Plug Co Printed wiring substrate and method for manufacturing the same
US6532143B2 (en) * 2000-12-29 2003-03-11 Intel Corporation Multiple tier array capacitor
EP1265466A3 (fr) * 2001-06-05 2004-07-21 Dai Nippon Printing Co., Ltd. Procédé de fabrication d'un panneau à circuit muni d'éléments passifs et panneau à circuit muni d'éléments passifs
US6826830B2 (en) * 2002-02-05 2004-12-07 International Business Machines Corporation Multi-layered interconnect structure using liquid crystalline polymer dielectric
US20050063135A1 (en) * 2003-09-18 2005-03-24 Borland William J. High tolerance embedded capacitors
GB2420912B (en) * 2002-12-11 2006-07-26 Dainippon Printing Co Ltd Multilayer wiring board and manufacture method thereof
TW556452B (en) * 2003-01-30 2003-10-01 Phoenix Prec Technology Corp Integrated storage plate with embedded passive components and method for fabricating electronic device with the plate
US20040231885A1 (en) * 2003-03-07 2004-11-25 Borland William J. Printed wiring boards having capacitors and methods of making thereof
US6764748B1 (en) * 2003-03-18 2004-07-20 International Business Machines Corporation Z-interconnections with liquid crystal polymer dielectric films
US20050081376A1 (en) * 2003-10-21 2005-04-21 Sir Jiun H. Robust interlocking via
US7100277B2 (en) * 2004-07-01 2006-09-05 E. I. Du Pont De Nemours And Company Methods of forming printed circuit boards having embedded thick film capacitors
US7339260B2 (en) * 2004-08-27 2008-03-04 Ngk Spark Plug Co., Ltd. Wiring board providing impedance matching

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000208945A (ja) * 1999-01-18 2000-07-28 Ngk Spark Plug Co Ltd コンデンサ内蔵配線基板及びその製造方法
JP2002009416A (ja) * 2000-06-20 2002-01-11 Matsushita Electric Works Ltd プリント配線板製造用シート材、このプリント配線板製造用シート材を用いたプリント配線板の製造方法及びプリント配線板
JP2002217540A (ja) * 2001-01-17 2002-08-02 Matsushita Electric Ind Co Ltd 多層配線基板の製造方法及びその装置
JP2003142624A (ja) 2001-10-31 2003-05-16 Fujitsu Ltd 受動素子を内臓した半導体装置の製造方法、中継基板及びその製造方法
JP2004179288A (ja) * 2002-11-26 2004-06-24 Shinko Electric Ind Co Ltd 電子部品実装構造及びその製造方法
WO2004056160A1 (fr) * 2002-12-13 2004-07-01 E.I. Du Pont De Nemours And Company Cartes imprimees equipees de condensateurs encastres a faible inductance et procedes de fabrication correspondants

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2178116A1 (fr) * 2007-08-08 2010-04-21 Ibiden Co., Ltd. Substrat de montage de circuit intégré et procédé pour sa fabrication
EP2178116B1 (fr) * 2007-08-08 2012-10-17 Ibiden Co., Ltd. Substrat de montage de circuit intégré et procédé pour sa fabrication
US8455766B2 (en) 2007-08-08 2013-06-04 Ibiden Co., Ltd. Substrate with low-elasticity layer and low-thermal-expansion layer

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TW200629491A (en) 2006-08-16
US20080289866A1 (en) 2008-11-27
KR20070086706A (ko) 2007-08-27
EP1833286A1 (fr) 2007-09-12

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