WO2006006387A1 - ホスト機器、記憶装置、及び記憶装置へのアクセス方法 - Google Patents
ホスト機器、記憶装置、及び記憶装置へのアクセス方法 Download PDFInfo
- Publication number
- WO2006006387A1 WO2006006387A1 PCT/JP2005/011799 JP2005011799W WO2006006387A1 WO 2006006387 A1 WO2006006387 A1 WO 2006006387A1 JP 2005011799 W JP2005011799 W JP 2005011799W WO 2006006387 A1 WO2006006387 A1 WO 2006006387A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- command
- storage device
- access
- host device
- response
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
- G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
Definitions
- the present invention relates to a host device, a storage device, and an access method to the storage device, in which a storage device and a host device are connected by a bus, and the storage device is initialized and data is transmitted / received using a command.
- a memory card equipped with a non-volatile memory is used as a storage device that holds digital information. is there.
- a mechanism for accessing the host device memory card is standardized.
- the standard version will be upgraded as the capacity of the memory card increases.
- a method for making it possible to access the host device memory force of different versions there has been proposed a method in which different storage capacities are shown to each host by using a plurality of capacity representation methods (for example, (See Patent Document 1).
- Patent Document 1 Japanese Patent Laid-Open No. 2004-86505
- an object of the present invention is to provide a host device, a storage device, and a method for accessing the storage device that can perform access control with a simple structure and control.
- the host device of the present invention is a host device that is connected to a storage device via a bus and writes and reads data in the storage device, and the storage contents of the storage device
- a command transmission unit that sequentially transmits commands in a command sequence including a series of commands that do not change the response, and a response that receives a response from the storage device and determines whether there is an error each time each command is transmitted from the command transmission unit
- a reception unit and an access permission determination unit that allows access when normal reception is determined by the response reception unit after sending each command from the command transmission unit, and does not accept access at other times.
- a storage device of the present invention is a storage device that is connected to a host device via a bus and stores and reads data based on a command from the host device.
- a memory that holds data given from the memory, a memory control unit that controls writing and reading of data to and from the memory, and a command receiving unit that receives commands issued from the host device and performs processing according to each command
- a response transmission unit that returns a response when the command reception unit receives a predetermined command every time it receives each command;
- An access determination unit that determines whether the command received by the command reception unit is a predetermined command sequence and accepts an access when the command is a predetermined command sequence.
- a method for accessing a storage device is a method for accessing a storage device of a host device that is connected to the storage device via a bus and writes and reads data in the storage device.
- commands are sequentially transmitted in a command sequence having a series of command powers without changing the storage contents of the storage device, and each time each command is transmitted, a response from the storage device is accepted and whether there is an error. If normal reception is determined after each command is sent, access is possible, and access is not accepted at any other time! /.
- the storage device determines the sequence of transmission commands of the host device, and Therefore, it is possible to provide a host device, a storage device, and a method for accessing the storage device that can perform access control with a simple structure 'control. it can.
- FIG. 1 is a block diagram showing a configuration of a storage system according to an embodiment of the present invention.
- FIG. 2 is a flowchart showing a first command sequence process of the host device.
- FIG. 3 is a flowchart showing a second command sequence process of the host device.
- FIG. 4 is a flowchart showing a first command sequence reception process of the storage device.
- FIG. 5 is a flowchart showing reception of the first and second command sequence processes of the storage device.
- FIG. 6 is a flowchart showing third command sequence processing of the host device.
- FIG. 7 is a flowchart showing reception processing of a third command sequence in the storage device.
- FIG. 8 is a flowchart showing a fourth command sequence process of the host device.
- FIG. 9 is a flowchart showing a reception process of a fourth command sequence in the storage device.
- FIG. 10 is a flowchart showing processing after it is determined that the host device cannot accept access.
- FIG. 1 is a block diagram showing a configuration of a storage system according to an embodiment of the present invention.
- the storage system according to the embodiment of the present invention has a host device 1 and a storage device 2, and the host device 1 and the storage device 2 are connected by a bus 3.
- the host device 1 has a CPU 101, a ROM 102 for storing a program of the CPU 101, a RAM 103 serving as a work area of the CPU, and an interface 104.
- the interface 104 transmits commands, data, and addresses to the storage device 2 and receives responses.
- the ROM 102 stores an access program for realizing an access method executed by the CPU 101 and a sequence of commands used by the host device 1.
- the CPU 101 achieves the functions of a command transmission unit 101a, a response reception unit 101b, and an access determination unit 101c.
- the command transmission unit 101 a is a command sequence including a series of commands held in the ROM 102, and sequentially transmits commands via the interface 104.
- the response receiving unit 101b receives a response every time a command is transmitted from the command transmitting unit, and determines whether or not there is an error.
- the access determination unit 101c determines whether or not access is possible when a normal response is determined by the response reception unit after each command is transmitted, and access is disabled at other times.
- the storage device 2 includes an interface 201, a control unit 202, a memory control unit 203, and a memory 204.
- the interface 201 receives commands and data from the host device 1.
- a response is sent.
- the control unit 202 includes a command reception unit 202a, a response transmission unit 202b, and an access determination unit 202c.
- the command receiving unit 202a receives a command issued by the host device, and performs processing according to each command.
- the response transmitting unit 202b determines whether the command is in accordance with a predetermined command sequence, and if it is that command, it responds normally.
- the access determination unit 202c determines whether the command received by the command receiving unit is a predetermined command sequence, and performs a process of accepting access when the command is a predetermined command sequence.
- the memory control unit 203 controls writing and reading of data to and from the memory 204, and the memory 204 holds data given from the host device.
- the storage device 2 checks whether the command sequence transmitted from the host device 1 is a predetermined sequence. If the command sequence is a predetermined command sequence, the storage device 2 determines that access from the host device 1 can be accepted.
- FIG. 2 is a flowchart showing a first example of a command sequence transmitted by the host device 1.
- the host device 1 first transmits a command CMD-A (S201). Then, it waits for a response from the storage device 2 (S202), and checks for an error if there is a response (S203). If there is no response and no error, command CMD-B is transmitted in step S204. Then, a response is waited (S205), and if there is a response, an error is checked (S206). If there is no response and no error, the command CMD —C is transmitted in step S207. In S208, a response is awaited, and if there is a response, an error is checked (S209).
- FIG. 3 is a flowchart showing a second example of a command sequence used by the host device.
- the host device 1 first transmits the command CMD-C (S301). Then, a response from the storage device 2 is waited (S302), and if there is a response, an error is checked (S303).
- command CMD_B is transmitted in step S304. Then, a response is waited (S305), and if there is a response, an error is checked (S306). If there is no response and no error, command CMD-A is transmitted in step S307. A response is awaited in S308, and if there is a response, an error is checked in S309. If there is no error in S309, a response is returned correctly, and the storage device 2 determines that access can be accepted (S310). If any command returns a response or returns an error response, the storage device 2 determines that access cannot be accepted (S311). If it is determined that access is impossible, it may not accept any subsequent commands from the host device, or it may wait for the correct sequence again.
- the host device 1 may use only a specific command sequence.
- a host device that supports an older version of the standard uses one of the command sequences shown in Figs.
- the corresponding host device may use the other command sequence. It is also possible for a host device that supports a new version of the standard to use the two command sequences shown in Figs.
- FIG. 4 is an example of a flowchart of command reception processing of the storage device 2 corresponding to the first command sequence.
- the storage device 2 checks whether this command is CMD-A. If it is this command, this command is executed in step S403 and a response is made. Further, in step S404, the reception of the command is checked, and when the command is received, it is checked whether the command is CMD-B (S405). If it is CMD-B, this command is executed and responded in step S406, and the next command is awaited. When a further command is received in step S407, it is checked in S408 whether the command is CMD-C.
- an error response is made (S411).
- the storage device 2 accepts only the access of the host device that transmits the command in the sequence of the commands CMD-A, CMD-B, and CMD-C shown in FIG.
- the command sequence order accepted by the storage device may be sent to the host device 1.
- no response may be made.
- FIG. 5 is a flowchart showing command reception processing of the storage device 2 corresponding to the first and second command sequences.
- S501 when a command is received in S501, it is checked whether this command is CMD-A (S502). If it is this command, it performs necessary processing and returns a response (S503), and then receives the command.
- S504 to S511 The subsequent processing of S504 to S511 is the same as S404 to S411 of FIG.
- the command is not command CMD-A in S502, it is checked in S512 whether the command is CMD-C. If it is this command, it responds after executing the command in S513, and waits for the command in step S514. If there is a command, it is checked whether it is command CMD-B (S515). If it is this command, necessary processing is performed and a response is made (S516). If there is more command (S517), it is checked whether CMD-A or not (S518). If it is this command, it performs necessary processing and responds (S519), and accepts access to the host device (S512). The command sequence accepted by S519!
- the storage device 2 can determine a plurality of command sequences. That is, the storage device 2 accepts the access of the host device that transmits the command in the first and second sequences shown in FIG. 2 or FIG.
- the number of sequences for which the storage device 2 performs the determination is not limited to two, and it is also possible to perform determination for more sequences.
- Figure 6 shows the command transmission process by the third command sequence from host device 1. It is a flowchart which shows.
- a command CMD-A is transmitted in S601, and it is determined whether there is a response (S602). If there is a response to CMD-A, an error is checked in S603, and if there is no error, CMD-A is transmitted a predetermined number of times (S601, S602, S612). Then issue the command CMD—B.
- the following processes S604 to S611 are the same as S204 to S211 in FIG.
- a flowchart on the storage device 2 side corresponding to the third command sequence will be described with reference to FIG.
- the storage device 2 receives a certain command as shown in the flowchart of FIG. 7 (S701), it determines whether or not it is a command CMD-A (S702).
- the storage device 2 returns a response to the host device 1 and repeats the same processing until the predetermined number of times is exceeded (S703, S704). If this command is not CMD_A, go to S712 to return an error response or do not respond!
- FIG. 8 is a flowchart showing an example of a fourth command sequence of the host device 1. This is specific, for example, repeating the first command sequence multiple times.
- the processing of S801 to S809 is the same as that of S201 to S209 in Fig. 2, and the host device sends 1 command ⁇ CMD 1 A (S80 1), CMD-B (S804), CMD-C (S807) in sequence .
- S810 If there is no error in S8 09, it is determined in S810 whether the predetermined sequence has been executed. If the predetermined number of times has not been reached, the process returns to S801 and the same processing is repeated. If the predetermined number of times has been executed, it is determined in S811 that access can be accepted. If there is no normal response during the sequence, it is determined in S812 that access cannot be accepted.
- FIG. 9 is a flowchart on the storage device side for the fourth command sequence.
- S901 to S909 are the same processes as S401 to S409 of FIG.
- S910 it is determined whether this process has been executed a predetermined number of times. If it has not been executed a predetermined number of times, it returns to S901 and repeats the same process. Proceed to 11 to accept host device access. If it is not normal in the middle of the command sequence, it does not respond in S912, or an error response is sent and access acceptance is prohibited. If it is determined that access is not possible, it is possible to accept no commands from the host device thereafter, or to correct and wait for the sequence again.
- the access program for the storage device 2 in the host device of FIGS. 2, 3, 6, and 8 in the embodiment shown here is held in the ROM 102 in the host device 1 as an access program. ing.
- the command CMD-A, CMD-B, and CMD-C are combined into a different sequence, and a sequence that can be used with another command is formed.
- the command is different.
- the command sequence for transmitting the command a predetermined number of times is not limited to the third and fourth methods.
- the host device 1 may combine the determination of the sequences of FIGS.
- a specific command may be transmitted a predetermined number of times, and a command having a force of 2 or more may be transmitted a plurality of times.
- a force that repeats a specific command sequence a predetermined number of times may be repeated a plurality of command sequences a predetermined number of times.
- the command transmission interval may be set to a predetermined time or less.
- the storage device 2 may use the host device if the command transmission interval exceeds the predetermined time. It is determined that access 1 cannot be accepted. If it is determined that access is impossible, it is possible to accept no commands from the host device thereafter, or to wait for the correct sequence again.
- the function permitted to be used can be switched according to the command sequence.
- the type of file system that is, the type of file system such as FAT16, FAT32, UDF, etc.
- the ability to use additional functions such as an interrupt function and additional functions such as a high-speed interface can be switched by a command sequence at the start of access.
- FIG. 10 is a flowchart showing processing after determining that access is impossible in S211. After determining that access is not possible, it is determined in S213 whether or not this response includes a command sequence. If the command sequence is not included in S213, another command sequence is stored in the host device, and if it is determined in S215, the command sequence is switched to another command sequence and is retried. If a command sequence is included, the process proceeds to S214 to determine whether the specified command sequence is supported. If this command sequence is not supported, the process is terminated. If this command is supported, the process proceeds to S215 to send a command with the specified command sequence and retry. In other words, it starts sending commands again with the specified command sequence. In this way, access can be made if it matches the command sequence of the storage device.
- the storage device determines the sequence of commands transmitted by the host device, and determines that the host device can accept access only when it matches the predetermined command sequence. Therefore, access control can be performed with a simple structure control, which is useful for various storage devices such as memory cards and various host devices using the storage devices.
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- Human Computer Interaction (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Security & Cryptography (AREA)
- Debugging And Monitoring (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Small-Scale Networks (AREA)
- Information Transfer Between Computers (AREA)
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006528687A JPWO2006006387A1 (ja) | 2004-07-08 | 2005-06-28 | ホスト機器、記憶装置、及び記憶装置へのアクセス方法 |
EP05755303A EP1798641A4 (en) | 2004-07-08 | 2005-06-28 | HOST SETUP, STORAGE DEVICE, AND METHOD OF ACCESSING A STORAGE DEVICE |
US11/571,592 US7900007B2 (en) | 2004-07-08 | 2005-06-28 | Host device, storage device, and method for accessing storage device |
US13/014,875 US20110125928A1 (en) | 2004-07-08 | 2011-01-27 | Host device, storage device, and method for accessing storage device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004-201511 | 2004-07-08 | ||
JP2004201511 | 2004-07-08 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/014,875 Division US20110125928A1 (en) | 2004-07-08 | 2011-01-27 | Host device, storage device, and method for accessing storage device |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2006006387A1 true WO2006006387A1 (ja) | 2006-01-19 |
Family
ID=35783732
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2005/011799 WO2006006387A1 (ja) | 2004-07-08 | 2005-06-28 | ホスト機器、記憶装置、及び記憶装置へのアクセス方法 |
Country Status (6)
Country | Link |
---|---|
US (2) | US7900007B2 (ja) |
EP (1) | EP1798641A4 (ja) |
JP (1) | JPWO2006006387A1 (ja) |
CN (1) | CN1981271A (ja) |
TW (1) | TWI410794B (ja) |
WO (1) | WO2006006387A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015138294A (ja) * | 2014-01-20 | 2015-07-30 | 株式会社東芝 | 携帯可能電子装置、電子回路および端末 |
Citations (4)
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JPH0228741A (ja) * | 1988-07-18 | 1990-01-30 | Nippon Telegr & Teleph Corp <Ntt> | 入出力デバイスの状態制御方式 |
JPH05242002A (ja) * | 1992-02-28 | 1993-09-21 | Kawasaki Steel Corp | 補助記憶装置 |
JPH0660235A (ja) * | 1992-08-13 | 1994-03-04 | Matsushita Electric Ind Co Ltd | Icカード |
JP2003223623A (ja) * | 2001-11-05 | 2003-08-08 | Matsushita Electric Ind Co Ltd | 半導体メモリカード、その制御方法及び半導体メモリカード用インターフェース装置 |
Family Cites Families (9)
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JP2972805B2 (ja) * | 1988-08-12 | 1999-11-08 | セイコーエプソン株式会社 | メモリーの書き込み保護回路 |
EP0583006B2 (en) | 1992-08-13 | 2006-11-29 | Matsushita Electric Industrial Co., Ltd. | IC card with hierarchical file structure |
KR0182939B1 (ko) * | 1995-06-28 | 1999-04-15 | 김광호 | 특정 기록포멧을 갖는 아이씨 카드 메모리 및 그로부터의 디지탈음성 기록 및 재생방법 |
US6820203B1 (en) * | 1999-04-07 | 2004-11-16 | Sony Corporation | Security unit for use in memory card |
US20070168614A1 (en) * | 2000-01-06 | 2007-07-19 | Super Talent Electronics Inc. | Secure-Digital (SD) Flash Card with Auto-Adaptive Protocol and Capacity |
JP2003015958A (ja) | 2001-06-29 | 2003-01-17 | Nec Microsystems Ltd | ライトプロテクト方法 |
US6842395B2 (en) * | 2001-11-05 | 2005-01-11 | Matsushira Electric Industrial Co., Ltd. | Semiconductor memory card, method of controlling the same and interface apparatus for semiconductor memory card |
JP3806077B2 (ja) | 2002-08-26 | 2006-08-09 | 株式会社東芝 | メモリカード認識システム、容量切り替え型メモリカード・ホスト機器、容量切り替え型メモリカード、記憶容量設定方法及び記憶容量設定プログラム |
CN100454226C (zh) * | 2004-07-08 | 2009-01-21 | 松下电器产业株式会社 | 主机、存储装置以及对存储装置的访问方法 |
-
2005
- 2005-06-28 EP EP05755303A patent/EP1798641A4/en not_active Withdrawn
- 2005-06-28 JP JP2006528687A patent/JPWO2006006387A1/ja active Pending
- 2005-06-28 US US11/571,592 patent/US7900007B2/en active Active
- 2005-06-28 CN CNA2005800230286A patent/CN1981271A/zh active Pending
- 2005-06-28 WO PCT/JP2005/011799 patent/WO2006006387A1/ja active Application Filing
- 2005-07-01 TW TW094122461A patent/TWI410794B/zh active
-
2011
- 2011-01-27 US US13/014,875 patent/US20110125928A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0228741A (ja) * | 1988-07-18 | 1990-01-30 | Nippon Telegr & Teleph Corp <Ntt> | 入出力デバイスの状態制御方式 |
JPH05242002A (ja) * | 1992-02-28 | 1993-09-21 | Kawasaki Steel Corp | 補助記憶装置 |
JPH0660235A (ja) * | 1992-08-13 | 1994-03-04 | Matsushita Electric Ind Co Ltd | Icカード |
JP2003223623A (ja) * | 2001-11-05 | 2003-08-08 | Matsushita Electric Ind Co Ltd | 半導体メモリカード、その制御方法及び半導体メモリカード用インターフェース装置 |
Cited By (1)
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JP2015138294A (ja) * | 2014-01-20 | 2015-07-30 | 株式会社東芝 | 携帯可能電子装置、電子回路および端末 |
Also Published As
Publication number | Publication date |
---|---|
EP1798641A4 (en) | 2010-04-07 |
TWI410794B (zh) | 2013-10-01 |
JPWO2006006387A1 (ja) | 2008-04-24 |
US7900007B2 (en) | 2011-03-01 |
CN1981271A (zh) | 2007-06-13 |
US20110125928A1 (en) | 2011-05-26 |
TW200604803A (en) | 2006-02-01 |
EP1798641A1 (en) | 2007-06-20 |
US20070255917A1 (en) | 2007-11-01 |
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