WO2005076280A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- WO2005076280A1 WO2005076280A1 PCT/JP2005/000742 JP2005000742W WO2005076280A1 WO 2005076280 A1 WO2005076280 A1 WO 2005076280A1 JP 2005000742 W JP2005000742 W JP 2005000742W WO 2005076280 A1 WO2005076280 A1 WO 2005076280A1
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- phase change
- sense amplifier
- memory cell
- semiconductor device
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5678—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using amorphous/crystalline phase transition storage elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
- G11C2013/0047—Read destroying or disturbing the data
Definitions
- the present invention relates to a semiconductor device, and in particular, to a high-density integrated memory circuit formed using a phase change material, a logic mixed memory in which a memory circuit and a logic circuit are provided on the same semiconductor substrate, or an analog memory.
- the present invention relates to a technology effective when applied to a semiconductor integrated circuit device having a circuit.
- a memory using a resistance element that also has a phase change material force is a memory that uses an electric pulse to cause a phase change of a phase change material between an amorphous state and a crystalline state reversibly.
- This is a non-volatile memory that records the difference between the (reset) and crystalline (set) resistance values as information.
- the high resistance value of the amorphous state and the low resistance value of the crystalline state of the phase-change material are not necessarily the complete amorphous state and the perfect crystalline state, respectively. It can take any value between the high resistance state, which is a state, and the low resistance state, which is a perfect crystalline state.
- FIG. 14 is an example of a current-voltage characteristic of a phase change material for realizing a recording operation of a phase change memory.
- Vset The voltage at which a phase change from an amorphous state to a crystalline state occurs.
- Vset The voltage at which a phase change from an amorphous state to a crystalline state occurs.
- phase change material in a crystalline state changes to an amorphous state.
- the voltage at which a phase change from a crystalline state to an amorphous state occurs is defined as a reset voltage (Vreset).
- Vreset The voltage at which a phase change from a crystalline state to an amorphous state occurs.
- the resistance of the phase change material changed from the crystalline state to the amorphous state changes from the low resistance state to the high resistance state.
- a low resistance value in a crystalline state is set to a "0" state, and a high resistance in an amorphous state is Record information with value "1". Reading of information is performed by impressing a reading voltage (Vread) on both ends of the phase change material. As shown in FIG. 14, the current generated in the crystalline state having a low resistance value becomes larger than the current generated in the amorphous state having a high resistance value due to the impressed read voltage Vread.
- Vread reading voltage
- FIG. 15 schematically shows a voltage drop of a bit line electrically connected to a phase change material.
- the bit line is set to the precharge level Vp in the initial state at the time of reading.
- the precharge level Vp of the bit line is set to 0.3V.
- the bit line electrically connected to the amorphous phase change material having a high resistance value was electrically connected to the crystalline phase change material having a low resistance value.
- the voltage drops at a lower speed than the bit line. The reason for this is that the charge stored in the bit line flows into the phase change material at a higher rate in a phase change material having a high resistance value than in a phase change material having a low resistance value.
- the "0" state and the "1" state of the phase change memory are read by sensing the speed of the voltage drop of the bit line using the read voltage.
- the low resistance value in the crystalline state is set to the “0” state
- the high resistance value in the amorphous state is set to the “1” state
- the high resistance value in the amorphous state is set to the “0” state.
- the low resistance value in the crystalline state may be set to the “1” state.
- Patent Document 1 Japanese Patent Application No. 2003-145305
- Patent Document 2 Japanese Patent Application No. 2003-081724
- the phase change memory has a problem of so-called erroneous setting in which an amorphous state is erroneously changed into a crystalline state.
- Erroneous setting is likely to occur when excessive electrical energy is input during low-voltage operation or during high-speed operation.
- Factors that cause erroneous setting are, for example, variations in physical property values, variations in electrical characteristics, or variations in dimensions.
- variations in characteristics of a phase change material, a selection transistor, LSI wiring, and the like, variations in operating voltages, and variations in power supply voltages are also factors that cause erroneous setting.
- the read voltage is set to be equal to or lower than the set voltage.
- phase change memory when low-voltage operation is required for the phase change memory, a problem occurs in that the margin between the set voltage and the read voltage is reduced. For example, when used in low power consumption products such as mobile phones, mobile information terminals, or IC cards, low power operation is required for phase change memories. Also, when used as a microcomputer embedded memory operating at a low voltage, the phase change memory is required to operate at a low voltage.
- the read current in the crystalline state obtained by the read voltage Vreadl is Ireadl.
- the read voltage Vread is a read current in a crystalline state obtained by a read voltage as small as Iread2, and Iread becomes smaller. If the read current is small, the discharge speed of the bit line is reduced, and the speed of sensing the amorphous state and the crystalline state of the phase change material by the sense amplifier is reduced. As a result, the operation speed of the phase change memory is reduced.
- the record retention reliability of the phase change memory deteriorates.
- the set voltage varies and becomes small, and may be lower than the read voltage.
- the read operation causes the phase change material to change the amorphous state force to the crystalline state incorrectly.
- the erroneous setting occurs when the reset voltage is higher than the set voltage as shown in FIG. 14 and in FIG. 17.
- the reset voltage is smaller than the set voltage as shown below, it can occur both when the phase change memory operates at low voltage and the margin between the read voltage and the set voltage is small. Therefore, erroneous setting occurs due to slight phase change material or characteristic variation of the selection transistor.
- phase change memory has a large capacity
- an erroneous setting of a drop-out bit occurs due to a slight yield defect such as a wiring process.
- the phase change memory has a problem of a so-called erroneous reset in which a crystalline state is erroneously changed into an amorphous state.
- the margin between the reset voltage and the read voltage is reduced. Therefore, when the characteristic variation of the phase change memory is large, the reset voltage varies and becomes small, and may be lower than the read voltage. As a result, a phenomenon occurs in which the phase change material is erroneously reset from the crystalline state to the amorphous state by the read operation.
- An erroneous reset may occur both when the reset voltage as shown in FIG. 14 is higher than the set voltage and when the reset voltage as shown in FIG. 17 is lower than the set voltage.
- phase-change memory When the phase-change memory operates at a low voltage, the margin between the read voltage and the reset voltage becomes small, so that a slight reset may occur due to a slight phase-change material or variation in characteristics of the selection transistor.
- phase change memory when the phase change memory operates at a low voltage, the margin between the set voltage and the reset voltage is reduced, so that an erroneous reset may occur during the set operation due to slight phase change material or characteristic variation of the selection transistor. appear.
- the erroneous setting of the phase change memory also occurs when the phase change material is operated or left at a high environmental temperature or a high junction temperature because the amorphous state of the phase change material is a quasi-stationary state. Erroneous setting caused by leaving at high temperature for a long time is observed as a so-called "drop-out bit phenomenon" seen in large-capacity memories such as DRAMs. As a result, phase change used in highly integrated memory circuits and logic embedded memories There is a problem that the long-term record retention reliability of the memory is degraded.
- An example of a product that requires high-temperature operation of the phase change memory is an embedded microcomputer for controlling an automobile engine. Operating and 20 year shelf temperature requirements are, for example, 125 ° C. or higher at the junction temperature, or 145 ° C. or higher.
- An object of the present invention is to provide, for example, a high-density integrated memory circuit using a phase-change material, a logic-mixed memory in which a memory circuit and a logic circuit are provided on the same semiconductor substrate, and an analog circuit.
- Another object of the present invention is to provide a technology capable of improving the reliability of a memory cell element using a phase change material that requires long-term record retention reliability.
- Another object of the present invention is to achieve low-voltage operation of a semiconductor integrated circuit device. Another object of the present invention is to achieve high-temperature operation of a semiconductor integrated circuit device. Another object of the present invention is to extend the time of leaving the semiconductor integrated circuit device at a high temperature. Another object of the present invention is to achieve high integration of a semiconductor integrated circuit device. Another object of the present invention is to increase the capacity of a semiconductor integrated circuit device. Another object of the present invention is to achieve high-speed operation of a semiconductor integrated circuit device.
- a high voltage is applied by a bit line to perform reading, and a rewriting operation is performed for each of the high-resistance cell and the low-resistance cell.
- the present invention uses an OR cell for relieved bit loss, that is, holds one-bit information by using two or more memory cells.
- an OR cell for relieved bit loss that is, holds one-bit information by using two or more memory cells.
- FIG. 3 shows a circuit diagram of the phase change memory cell of the present invention.
- the memory cell portion in FIG. 3 includes a lower electrode dwc, a phase change material PCR, an upper electrode upc, a source line SL, a bit line BL, and a selection transistor MT, for example, a MISFET, and a word line WL. Be composed.
- FIG. 18 shows an example of a cross-sectional view of a phase change memory cell.
- the phase change material PCR also includes the upper electrode upc, the lower electrode plug dwc, and the interlayer IL force.
- the phase change material PCR is electrically connected to the upper electrode upc and the lower electrode plug dwc.
- the upper electrode upc is electrically connected to the bit line BL or the source line SL.
- the lower electrode plug dwc is electrically connected to one end of the source / drain of the selection transistor MT composed of, for example, an MISFET.
- the other end of the source / drain of the select transistor is a saw. It is electrically connected to the wiring that is not connected to the upper electrode of the source line SL or bit line BL. That is, the circuit diagram of the memory cell is as shown in FIG. 3 (a) or FIG. 3 (b).
- the processing of the memory cell structure is performed by using a known method. It should be noted that Patent Document 1 discloses one related to this
- the phase change material PCR used in the phase change memory operating at a low voltage includes, for example, a Ge—Sb—Te based phase change material, a Zn—Te based phase change material, or a Zn—Te based phase change material.
- a Zn-X-Te phase change material in which additive elements are added. Examples of the additional element X include Sb.
- a material related to a Zn—X—Te phase change material is disclosed in, for example, Patent Document 2.
- the material used for the lower electrode plug dwc includes, for example, tungsten.
- Tungsten is a material suitable for low-voltage and high-speed operation, which is one of the objects of the present invention, because of its good interfacial properties with the phase change material.
- Figure 19 shows Ge Sb Te
- Figure 20 shows Ge Sb when tungsten and titanium nitride are used for the lower electrode.
- Te phase change material has a crystalline state force.
- the reset current force when using tungsten for the lower electrode is smaller than the reset current when using titanium nitride.
- the use of tungsten as the lower electrode material reduces the current required for the phase change, thereby enabling the phase change memory to operate at a low voltage at the same time.
- a margin which is a difference between the read voltage, the set voltage, and the reset voltage is reduced.
- phase change memory operates at a low voltage
- the phase change material is a thin film.
- the reason for realizing a phase change memory by using a phase change material of a thin film will be described below.
- an electric power P per unit volume required for a phase change material to undergo a phase change to a crystalline state is obtained using ohmic approximation, it can be expressed as the following equation 1.
- Iset is the set current required when the amorphous phase change material changes phase to the crystalline state
- R is the resistance value of the phase change material
- r is the resistivity of the phase change material
- A is the area of the lower electrode
- T Is the thickness of the phase change material.
- Equation 2 shows that the set voltage Vset is proportional to the thickness of the phase change material.
- Equations 1 and 2 represent a set operation in which the phase change material changes from an amorphous state to a crystalline state. Equations 1 and 2 can also be used approximately when the reset operation in which the phase change material changes from a crystalline state to an amorphous state is performed. However, Equations 1 and 2 were obtained using only the ohmic approximation.In consideration of the generation and diffusion of Joule heat, the power required for the phase change material to undergo a phase change is expressed by Equations 1 and 2. Is larger than the value obtained by
- the maximum value of the absolute value of the potential difference between the source line and the bit line is 1.8 V or less.
- the voltage applied to the phase change material is assumed to be 1.2 V or less.
- FIG. 21 shows experimental data of the reset voltage and the film thickness of the phase change material when the phase change material also changes its crystalline state into an amorphous state.
- the film thickness must be, for example, 20 nm or less. Also, Zn Sb T
- the film thickness must be, for example, 60 nm or less.
- the film thickness depends on the composition of the phase change material is that the resistivity of the phase change material is different. Also, at the above-mentioned lower limit of zero film thickness, the reset voltage does not become OV because the power required when the phase change material changes phase includes the contribution of generation and diffusion of Joule heat. It is.
- phase change memory examples include high melting point phase change material, Zn-Te phase change material, or Zn-Te phase change material.
- Zn-X-Te phase change material that is made from silicon.
- Patent Document 2 discloses, for example, a material related to a Zn—X—Te phase change material.
- the present invention provides a GeSbTe-based phase change material, a Zn-Te-based phase change material, or a Zn-X-Te-based phase-change material obtained by adding an additive element to a Zn-Te-based phase change material.
- a phase change material is provided, it can be applied to other phase change materials. In that case, the data retention reliability of the phase change element can be improved, and a decrease in operating speed at low voltage can be prevented.
- it can be applied to operation at a force of 1.8 V, which assumes an operating voltage of about 1.2 V. Even in this case, the operation margin can be improved and the operation speed can be improved.
- the present invention is desirably used for a semiconductor using a processing technique having a processing dimension of 0.13 m or less.
- the operating margin becomes a problem.
- the present invention can be improved.
- the present invention can be applied to a single memory and a mixed logic memory. By applying to these, data reliability and memory cell failure can be relieved, and the yield can be improved.
- data reliability in high-temperature operation can be improved, so that a semiconductor device capable of operating in a wide temperature range can be realized.
- circuit elements constituting each functional block of the embodiment are not particularly limited, they are formed on a semiconductor substrate such as single crystal silicon by a known integrated circuit technology such as CMOS (complementary MOS transistor).
- CMOS complementary MOS transistor
- the PMOS transistor is distinguished from the NMOS transistor by adding an arrow symbol to the body.
- the connection of the substrate potential of the MOS transistor is not particularly specified in the drawings, the connection method is not particularly limited as long as the MOS transistor can operate normally. Unless otherwise specified, the low level of a signal is “0”, the no level is T, and the low level is T.
- the present embodiment solves the problem that when the array operation voltage is lowered, the read voltage range is narrowed and the operation margin is reduced.
- the applied voltage is kept low so that a phase change element in a high resistance state or a low resistance state does not undergo a phase change due to a current at the time of reading.
- the read current is reduced, so that the read signal amount is reduced, and there is a concern that the operation speed and the operation margin may be reduced.
- the applied voltage is increased so that a sufficient amount of signal is generated in the sense amplifier, and a rewrite operation is performed on a cell in which a phase change may occur due to the read operation. To improve data reliability.
- examples of the present invention will be described.
- FIG. 1 is a diagram showing a memory cell array MCA, a sense amplifier block SAB, and a row decoder / word driver RDEC for realizing this operation.
- FIG. 2 shows a configuration example of the memory cell array MCA.
- Memory cells MC are provided at intersections of word lines WLO, WL1, WL2, WL3,... And bit lines BL0, BL1, BL2, BL3,.
- source lines SL01, SL23,... are provided.
- the source line is connected to, for example, the ground voltage VSS.
- Each memory cell MC includes a phase change resistance PCR and a memory cell transistor MT.
- Figure 3 shows two types of memory cell configurations. In (a), one end of the phase change resistor PCR is connected to the bit line BL, and the other end is connected to one of the source and the drain of the memory cell transistor MT.
- the other of the source 'and the drain of the memory cell transistor is connected to a source line, and the gate is connected to a word line.
- This configuration is advantageous in that when driving the bit line BL to a higher potential, for example, 1.2 V, than the source line SL at the time of writing, the driving force of the memory cell transistor MT can be increased.
- the connection relationship between the phase change resistor PCR and the memory cell transistor MT in (a) is reversed. In this configuration, the bit line is driven to a lower potential than the source line SL.For example, when the bit line BL is driven to 0 V by the potential power S1.2 V of the source line SL, the driving force of the memory cell transistor MT is reduced. It is superior because it can be taken large.
- NMOS transistor is shown here as a memory cell transistor, a PMOS transistor or a bipolar transistor can also be used.
- the NMOS transistor is preferable because the channel resistance in the ON state is smaller than that of the PMOS transistor, which is desired by the MOS transistor, from the viewpoint of high integration. The operation and the like will be described below in relation to the voltage when an NMOS transistor is used as a memory cell transistor.
- the bit line is also called a data line.
- the memory cell array MCA is provided with a dummy cell for generating a reference signal at the time of reading, if necessary.
- the sense amplifier block SAB includes a bit line selector BLSEL, a sense amplifier SA, and a write driver WD.
- Figure 4 shows a configuration example of the bit line selector BLSEL.
- the bit line selector BLSEL is provided with a selection switch for connecting the bit lines BL0, BL1, '1,' of the memory array to the sense amplifier. These switches are controlled by the column selection signals C0t / b, Clt / b,. Further, a precharge transistor for precharging the bit line on the memory array side and the bit line BLSA on the sense amplifier side to a desired level for a desired period is arranged.
- a sense amplifier block is arranged adjacent to the bit line selector.
- FIG. 5B shows a configuration example of the sense amplifier.
- the level of the sense amplifier bit line BLSA is compared with the reference level VREF, and a cross-coupled amplifier is used to amplify the power supply voltage VWE.
- FIG. 5A shows a configuration example of the write driver WD.
- the write driver WD drives the sense amplifier bit line BLSA according to external write data or data read to the sense amplifier SA.
- the write driver WD includes only a driver for bringing the phase change element of the memory cell into a high resistance state.
- the number of power bit lines in which one sense amplifier bit line BLSA, sense amplifier SA, and write driver WD are connected to four bit lines BL0, BL1, BL2, and BL3 is not limited. By increasing the number, the number of operating sense amplifiers can be reduced, so that an unnecessary increase in power consumption can be suppressed. On the other hand, when the number is small, the number of output bits increases, so that it is suitable for inputting / outputting a large amount of data at high speed.
- FIG. 6 is a timing chart of the read operation.
- the column selection line C0t / b corresponding to the input address is activated.
- the bit line connected to the sense amplifier SA in the figure, the bit line BL0 is set to the bit line precharge level VR together with the bit line BLSA in the sense amplifier.
- the precharge level VR and the memo The potential difference between the source lines SL of the recell MC is set so that the current necessary for the phase change element to change to the high resistance state and the low resistance state flows.
- the source line SL is set to 0V
- the bit line precharge level VR is set to about 0.6V.
- the precharge signal PRE is deselected and the word line WL is selected. Accordingly, the bit line BL and the bit line BLSA in the sense amplifier are discharged via the transistor MT of the memory cell and the phase change element PCR. At this time, when the phase change element PCR of the memory cell is in a low resistance state, it is rapidly discharged. On the other hand, when the resistance is in the high resistance state, it is discharged slowly.
- the sense amplifier amplifies a small signal appearing on a bit line to a power supply voltage. By this read operation, the phase change element in the high resistance state changes its phase from the high resistance state to the low resistance state due to the heat generated by the read current, and all the cells read out to the sense amplifier are reduced in resistance. .
- the sense amplifier amplifies the signal read to the bit line and outputs it to the I / O for external output.
- the write driver is activated in the sense amplifier from which the phase change element of the memory cell has read the data in the high resistance state.
- a high voltage is applied to the bit line by the write enable signal WRE for a time required for the reset operation, and a current required for the reset operation is supplied to the phase change element via the bit line and the memory cell transistor.
- the phase change element is rapidly cooled and changes phase to a high resistance state.
- the word line WL and the column selection line C0t / b transition to the non-selection level, and the read cycle ends.
- FIG. 7 is a timing chart of the write operation.
- a write address is sent according to the write command.
- the column selection line C0t / b corresponding to the address is activated, and at the same time, the precharge operation of the bit line is performed.
- the word line WL corresponding to the address is selected, and the bit line is discharged via the transistor and the phase change element of the memory cell.
- the phase change element generates heat due to the read current, and causes a phase change from a high resistance state to a low resistance state.
- the phase change elements of all the memory cells connected to the sense amplifier change phase to a low resistance state.
- write data is transferred to the sense amplifier.
- the write driver corresponding to only the sense amplifier holding the data corresponding to the high resistance state of the phase change element of the memory cell in the sense amplifier row is used. Activate the ba. After that, the activated write driver applies a high voltage to the bit line by a write enable signal for a time required for the reset operation, and applies a current required for the reset operation via the bit line and the memory cell transistor. Flow through the change element. Thereafter, by interrupting the current, the phase change element is rapidly cooled and changes into a high resistance state. Thereafter, the read line WL and the column select line C0t / b transition to the non-select level, and the read cycle ends.
- the bit line precharge level can be set high at the time of reading, and the amount of signals read to the sense amplifier can be increased, so that a high-speed and stable reading operation can be realized.
- a write driver which conventionally required a set-reset driver, can be configured with only a reset driver, so that the circuit configuration can be simplified and the layout area and chip area can be reduced.
- Rewriting is performed every time the high resistance state is read, so that a reduction in data reliability due to data destruction during the reading operation can be reduced.
- the recording retention characteristics of the phase change element are degraded. For example, high-speed operation at 125 ° C. or higher and long-term storage are possible.
- This configuration uses a voltage higher than Vset or Vrese at which the phase change element does not cause a phase change at the bit line precharge level at the time of reading.
- the phase state of the phase change element may be destroyed by the force read operation that sets the bit line precharge level high to increase the amount of read signals. Is performed.
- FIG. 8 shows a configuration of the sense amplifier block SAB of the present embodiment.
- the memory cell array MCA and the word driver RDEC are the same as in the above-described embodiment.
- the sense amplifier block SAB also has a write driver WD for setting and resetting the bit line selector BLSEL and the phase change element, and amplifying the sense amplifier bit line BLSA.
- Figure 9 shows the light drive.
- 2 shows the circuit configuration of the driver WD.
- the write driver WD supplies current required for set and reset to the phase change element via the sense amplifier bit line BLSA and the memory cell transistor according to the set enable signal WSE and the reset enable signal WRE and the data of the sense amplifier SA. .
- the configuration of the write driver differs from that of the above-described embodiment, and a write driver for increasing the resistance of the phase change element and lowering the resistance thereof is arranged.
- FIG. 10 is a timing chart of the read operation.
- the column selection line C0t / b corresponding to the input address is activated according to the read command.
- the bit line connected to the sense amplifier SA in the figure, the bit line BL0 is set to the bit line precharge level VR together with the bit line BLSA in the sense amplifier.
- the potential difference between the precharge level VR and the source line SL of the memory cell MC is a voltage at which the current necessary for the phase change element to change its phase into the high resistance state and the low resistance state flows. The voltage at which the low-resistance state changes to the high-resistance state does not matter.
- the phase change element does not necessarily need to cause a phase change from a high resistance state force to a low resistance state.
- the source line SL is set to 0V
- the bit line precharge level VR is set to about 0.8V.
- the precharge signal PRE enters a non-selected state, and the word line WL is selected. Accordingly, the bit line BL and the bit line BLSA in the sense amplifier are discharged via the transistor MT of the memory cell and the phase change element PCR.
- the sense amplifier amplifies the small signal appearing on the bit line to the power supply voltage.
- the resistance value of the phase change element of the memory cell connected to the sense amplifier does not always hold the resistance state before reading. That is, the stored data is destroyed by the read operation.
- the sense amplifier amplifies the signal read to the bit line and outputs it to the outside.
- the write driver is activated in the sense amplifier in which the phase change element of the memory cell has read the data in the high resistance state.
- the activated write driver In the activated write driver, a high voltage is applied to the bit line by the write enable signal for the time required for the reset operation. Then, the current necessary for the reset operation is passed to the phase change element via the bit line and the memory cell transistor. Thereafter, by interrupting the current, the phase change element is rapidly cooled and changes into a high resistance state. After that, the column selection line C0t / b and the word line WL shift to the non-selection level, and the reading operation is completed.
- FIG. 11 is a timing chart of the write operation.
- a write address is sent according to the write command.
- the column selection line C0t / b corresponding to the address is activated, and at the same time, the precharge operation of the bit line is performed.
- the word line WL corresponding to the address is selected, and the bit line is discharged via the transistor and the phase change element of the memory cell.
- the phase change element generates heat by the read current, causing a phase change from a high resistance state to a low resistance state or from a low resistance state to a high resistance state, and the state before reading is destroyed.
- write data is transferred to the sense amplifier.
- the reset driver in the write driver is selected.
- the set driver in the write driver is selected for a sense amplifier that holds data corresponding to the low resistance state of the phase change element of the memory cell in the sense amplifier array.
- the phase change element is rapidly cooled and changes its phase to a high resistance state or a low resistance state.
- the column selection line C0t / b word line WL transitions to the non-selection level, and the write cycle ends.
- the bit line precharge level can be set high at the time of reading, and the amount of signals read to the sense amplifier can be increased, so that a high-speed and stable reading operation can be realized.
- the record-holding characteristics of the phase-change element are degraded. For example, high-speed operation at 125 ° C. or higher and long-term storage are possible.
- the read voltage is equal to or higher than Vset at which the phase state of the phase change element changes, or is equal to or higher than Vreset.
- Performing the rewrite operation as in 1 and 2 does not work. In this case, since it is not necessary to perform rewriting every time a reading operation is performed, the rewriting operation is performed a predetermined number of times, for example, about 1Z10 times of the readable number, or every elapse of a predetermined operation time. May be.
- phase change element in the reset state may undergo a thermal disturbance due to a read operation or an operation at a high room temperature, causing a phase change to the set state.
- the possibility that the phase change element in the set state causes a phase change to the reset state is considered to be sufficiently small that the phase change element in the reset state will cause a phase change in the set state. Therefore, by storing 1-bit data in a plurality of memory cells with redundancy, the reliability of the stored data in the phase change element is improved.
- FIG. 12 shows an embodiment of the present invention. Bit lines 8 and 00, 8 and 01, 8 and 02, 8 and 03
- bit line BL10, BL11, BL12, BL13 are connected to memory cell arrays MCA0, MCA1 having the same configuration as the memory cell array MCA of FIG. 2 described above.
- Bit line BL10, BL11, BL12, BL13 are connected to memory cell arrays MCA0, MCA1 having the same configuration as the memory cell array MCA of FIG. 2 described above.
- the sense amplifier block SAB1 to which the bit lines BL10, BL11, BL12.BL13 are connected may have the circuit configuration of the sense amplifier block SAB of any of the above-described embodiments.
- the data input / output line I / O0 is output from the sense amplifier block SAB0 and the data input / output line 1/11 is output as a complementary signal (t / b).
- the output signal line is input to the OR block ORB.
- the OR block ORB outputs the external output data DOt / b using these input signals.
- the OR block ORB is used to store externally written data. DIt / b is transmitted to sense amplifier blocks SABO and SAB1.
- the memory cell arrays MCA0 and MCA1 are activated as soon as one address is input.
- the signal read from the memory cell MC at the designated address is read from the memory cell MC in the memory cell array MCA0, and the signal read from the memory cell MC in the memory cell array MCA0 is sensed and amplified by the sense amplifier block SAB0.
- the read signal is sensed and amplified by the sense amplifier block SAB1.
- the sense amplifier block outputs data according to the relationship between the phase state of the memory cell MC and the output voltages of the complementary signals I / O * t and I / O * b as shown in Fig. 13. I do.
- the external output data is in the H ′ state. This is because if the state of the phase change element of the memory cell is replaced, the V of the read memory cell array MCA0 or the memory cell of the MCA1 is shifted, or if both are in the high resistance state (Reset), the external output Data DOt becomes H '.
- write data is input to the OR block ORB via the external input data signal DIt / b.
- the external input data signal DIt / b is transferred to the entrance force signals I / O0t and I / O0b and the input / output signals I / 01t and I / Olb via the switch.
- These input / output signals are sent to the sense amplifier blocks SAB0 and SAB1, respectively.
- the sense amplifier blocks SAB0 and SAB1 perform an operation of writing data to the memory cells MC in the memory cell arrays MCA0 and MCA1, similarly to the sense amplifier block SAB of the above-described embodiment.
- phase change memory it is possible to prevent data destruction due to a phase change due to a high-temperature standby or a continuous read operation, and a decrease in data reliability due to a defective bit or a dropout bit.
- the recording retention characteristics of the phase change element deteriorate, For example, high-speed operation at 125 degrees Celsius or higher and long-term storage are possible.
- the reliability is greatly improved, but the read voltage is higher than Vset or Vreset where the phase state of the phase change element changes.
- a rewrite operation is always required during a read operation, which increases power consumption.
- the read voltage is equal to or lower than Vset and Vreset at which the phase state of the phase change element changes in order to reduce power consumption in the same circuit configuration. In this case, even if a read operation is performed, a rewrite operation only needs to be performed in a specific operation cycle, so that low power consumption can be realized.
- the circuit configuration can be any of the first, second, and third embodiments. That is, in order to perform the rewrite operation only in a specific cycle, the reset enable signal WRE and the set enable signal WSE in each embodiment are activated only in a specific cycle. For example, by using a logic circuit as shown in FIG. 22 to generate a reset write signal WRE and a set write signal WSE for performing a rewrite operation, the rewrite operation is realized in a specific operation.
- a rewrite enable signal RW is a signal indicating that a rewrite operation is performed on a column selected memory cell on a selected word line.
- the mat select signal MSB decodes an input address and indicates a specific address range. Regardless of the read operation or write operation, any one of the memory arrays corresponding to the input address is read. Mat select signal MSB is selected.
- Reset time regulation pulse TReset is a pulse that regulates the write time of the reset write operation.
- the set time defining pulse TSet is a pulse that defines the write time of the set write operation.
- Figure 23 shows an operation example of this circuit configuration.
- the mat select signal MSB is activated, for example, After the transition to the reset state, when the rewrite enable signal is activated, the reset enable signal WRE is activated by these signals and the reset time regulation pulse TReset. Similarly, the set enable signal WSE is activated by the set time regulation pulse TSet. Conversely, when the rewrite enable signal RW is in the inactive state, the reset enable signal WRE and the set enable signal WSE are both active even if the mat select signal MSB is in the active state. I won't be mad. That is, the rewrite operation can be controlled by the rewrite enable signal RW.
- FIG. 24 shows a simple block diagram of a memory chip having an input pin or a command for performing a rewrite operation REF in addition to a normal read and write command.
- the real array MA includes a plurality of memory cell arrays MCA, and a sense amplifier block SAB is arranged adjacent to each memory cell array MCA.
- a predecoder RPDEC for driving an address line for controlling the row decoder RDEC and a column decoder CDEC for outputting a column selection signal are arranged.
- a data control unit I / 0-CTL for external output of data and transfer of externally input data to the array is provided.
- the memory chip has an address buffer INPUT Buffer for temporarily storing addresses ⁇ , ⁇ , 'and commands input from the outside, a DQ Buffer for inputting and outputting data to and from the outside, and an external voltage VCC.
- an internal power supply generation circuit VG that generates a sense amplifier power supply VDL, a reset write voltage VWR, a set write voltage VWS, a peripheral circuit power supply voltage VCL, a ground level VSS, and a source line potential VS is provided.
- This configuration is characterized in that the input command includes a rewrite command REF for performing a rewrite operation! /, Which includes a rewrite pin REF! /.
- the sense amplifier block and the memory cell array MCA in FIG. 24 are the same as those in FIGS. 1 and 2 described above.
- FIG. 25 shows an operation example of the configuration in which FIG. 1 is applied to the sense amplifier block SAB in FIG.
- the column selection signal is activated according to the input address at the same time.
- the precharge signal PRE of the sense amplifier block corresponding to the address is activated.
- the bit line is precharged to the read level VR.
- the bit line isolation signal connecting the sense amplifier SA and the read bit line BLSA is set to the high potential state.
- the bit line precharge signal PRE is deactivated, and the word line WL transitions to the selected VWH from the non-selected VWL according to the input address.
- the state of the phase change element of the memory cell MC when the resistance state of the phase change element of the memory cell MC is in the low resistance state, the state changes rapidly to the source line SL potential VS as shown by the broken line in the figure.
- the bit line read level VR is maintained at around VR.
- the bit line separation signal BLI transitions to the low voltage V SS to separate the sense amplifier from the read bit line BLSA.
- the sense amplifier SA amplifies the small signal, which has also read the memory cell MC power, to the sense amplifier power supply VDL by activating the sense amplifier activation signal SEZSEB. After that, it is transferred to the I / O control unit and DQ buffer.
- the activated word line WL transitions to the unselected level VWL.
- the sense amplifier deactivates the sense amplifier activation signal, thereby transitioning to the standby state.
- the column selection signal transits to the non-selection state, and the read cycle ends.
- the reset enable signal When the reset enable signal is activated, if the data held in the sense amplifier corresponds to the high potential state, that is, I / Ot is set to the high resistance state and I / Ob is set to the low potential state. Then, in the write driver WD, a reset voltage is applied to the memory cell MC via the sense amplifier bit line BLSA and the bit line BL0, and a current required for writing flows. After the reset enable signal is activated for a time determined by the reset time regulation pulse TReset, the reset enable signal transits to a low potential state and the reset operation ends. The operation after the end of the write operation is the same as the above-described read operation. In this operation, the rewrite operation is limited to the reset operation with a short write time.
- FIG. 25 shows an operation example of this configuration.
- This configuration is characterized in that both a reset operation and a set operation are performed as a rewrite operation of memory cell data at a specific address in accordance with a command input from the outside.
- the read cycle when a read command is input is the same as in FIG. 25 described above.
- the operation when the restart command REF is input will be described. Keys entered at the same time as the command
- the operation until the address generated by the address or the address counter ADD-C in the memory chip CHIP is activated and read out to the sense amplifier is the same as in FIG. 25 described above.
- the rewrite enable signal RW is activated to a high potential state according to the rewrite command REF.
- the reset enable is performed by the mat select signal MSB corresponding to the selected address and the reset time regulation pulse TReset.
- the signal WRE is activated.
- the reset enable signal is activated, the data held in the sense amplifier corresponds to a high resistance state, that is, I / Ot is set to a high potential state and I / Ob is set to a low potential state.
- a reset voltage is applied to the memory cell MC via the sense amplifier bit line BLSA and the bit line BL0, and a current required for writing flows.
- the reset enable signal is activated for a time determined by the reset time regulation pulse TReset, and then transitions to a low potential state, ending the reset operation.
- the set enable signal WSE is changed by the mat select signal MSB corresponding to the selected address and the set time regulation pulse TSet. Be activated.
- the set enable signal WSE is activated, if the data held in the sense amplifier corresponds to the low resistance state, that is, I / Ot is set to the low potential state and I / Ob is set to the high potential state.
- the set voltage is applied to the memory cell MC via the sense amplifier bit line BLSA and bit line BL0, and a current required for writing flows.
- the set enable signal WSE is activated for a time determined by the set time prescribed pulse TSet, the set enable signal WSE transitions to the low potential state, and the set operation ends.
- the operation after the end of the write operation is the same as the above-described read operation. In this operation, compared to the read cycle tRC, the cycle tRC 'for rewriting is not only reset but also set, and thus is relatively long, requiring a time, for example, about 100 ns to lus.
- FIG. 27 is an example of a block diagram of a memory chip having an error detection function added to the memory chip. The feature is that the address counter is omitted as compared with Fig. 24 described above. Other configurations are the same as in FIG. 24 described above.
- FIG. 28 shows a block diagram of the memory cell array MCA and its peripheral circuits. As in Figure 1 above, the memory is connected via a row decoder RDEC that drives word lines WLO, WL1, WL2, and bit lines BLO, BL1, BL2, and BL2 adjacent to the memory cell array MCA.
- RDEC row decoder
- Sense amplifier block SAB for reading data stored in cell MC is arranged. Further, in this configuration, a replica bit line BL-REP arranged adjacent to the bit lines BLO, BL1, BL2,... Is arranged in the memory cell array MCA. Further, a replica bit line sense amplifier block circuit SAB-REP is arranged corresponding to the replica bit line. The replica bit line sense amplifier block SAB-REP outputs RWO which is the original signal of the rewrite enable signal RW. The rewrite enable signal RW is output from the rewrite enable source signal RWO after adjusting the pulse width by the pulse width conversion circuit RW_GEN as shown in FIG. FIG. 30 shows a configuration example of the memory cell array MCA in FIG.
- the replica memory cells MC-REP are arranged for all the word lines.
- the replica memory cell MC-REP has a configuration similar to that of a normal memory cell MC as shown in FIG. 3, for example.
- the phase change elements in all the memory cells on the bit line are set to a high resistance state.
- FIG. 31 shows an example of a block diagram of the above-described sense amplifier block for repli- cation force SAB-REP! /.
- the bit line precharge circuit BLPC is a circuit for precharging a bit line to a desired level VR in a read operation.For example, as shown in Fig. 32, a MOS transistor for precharging to a VR and a source line potential during standby are used.
- the MOS transistor power set to VS also becomes.
- the write driver WD has the same configuration as that of FIG. 5 (a).
- the sense amplifier circuit SA_REP is a circuit for amplifying a small signal read to the bit line BLSA to the amplitude of the sense amplifier power supply VDL and outputting a rewrite enable signal RW0 and write data to the write driver WD.
- FIG. 33 shows a circuit configuration example of the sense amplifier SA_REP. In this sense amplifier, the reference The replica reference VREF_REP is used as the level. VREF_REP is set to a higher level than VREF used in the sense amplifier block SAB.
- FIG. 34 shows the memory cell array MCA and the sense amplifier block SAB of FIG. 12 and the OR logic block ORB2.
- the OR logic block ORB2 can reduce errors caused by the transition from the high-resistance state to the low-resistance state by performing an OR logic on the read data as in the third embodiment.
- the output circuit of the rewrite enable source signal RW0 for writing the high resistance state to the two memory cells is further provided. Is added.
- Other configurations are the same as those of the third embodiment. The advantages of this configuration will be described.
- the error state of the resistance state of the phase change element is basically an error in which a reset state (high resistance state) transitions to a set state (low resistance state). If it is detected, it is clear that the memory cell in the set state has caused a data error.
- the operation when the circuit configuration of FIG. 28 is used will be described with reference to FIG.
- the operation when a read command is input and an error is detected and no error is detected is the same as that in FIG. 25 described above.
- the operation in the second cycle in FIG. 35 shows a case where an error is detected together with the read operation.
- the operation is the same as a normal read operation until a command is input, data is read out to the bit line, and data is held in the sense amplifier.
- the output node I / 0_REPt / b of the replica sense amplifier that has read the replica bit line detects the low resistance state. .
- the rewrite enable signal RW0 When a low resistance state is detected, the rewrite enable signal RW0 is activated and the rewrite enable signal RW is activated.
- the reset enable signal WRE and the sense amplifier output I / 0_REPb for the replica bit line are sensed and the reset write voltage VWR is applied to the write driver WD card bit line. Mark Caro.
- the reset write voltage is applied only while the reset enable signal WRE is activated, and immediately falls. Thereby, the replica memory cell is rewritten to the high resistance state.
- the reset write operation is performed on the memory cell MC storing data and the memory cell whose read resistance state is high as in the reset write operation on the replica memory cell. The operation is performed.
- the high-resistance storage phase change element of the memory cell storing the data is also subjected to the rewrite operation, and the data retention characteristics are improved.
- the advantages of this operation will be described. In this operation, since only the reset write operation with a short write time is performed, the restart operation can be performed within the cycle time of the normal read operation, and the access penalty due to the rewrite operation can be concealed. There is.
- FIG. 36 is characterized in that a busy pin WAIT is provided as an output pin in addition to the configuration of FIG. 27 described above.
- Other configurations are the same as those in FIG. 27 described above. This configuration is suitable for a case where the cycle time is longer in a read cycle involving a rewrite operation than in a normal read cycle, unlike the above-described embodiment.
- FIG. 37 is a block diagram showing a busy pin WAIT output method.
- the busy pin WAIT serves to notify the external memory controller that the memory cannot be used by changing the high potential state to the low potential state in response to the rewrite enable signal.
- the busy pin WAIT serves to notify the external memory controller that the memory cannot be used by changing the high potential state to the low potential state in response to the rewrite enable signal.
- a rewrite operation is performed along with a read operation. Also in this operation, the operation is the same as that of the above-described embodiment until the signal read from the memory cell is held in the sense amplifier.
- FIG. 35 which is an example of the operation waveform diagram of FIG. Outputs a signal in a low resistance state.
- the rewrite enable signal RW is activated.
- the reset enable signal WRE is activated, and a reset write operation is performed on the cell from which the reset state has been read.
- the set enable signal WSE is also activated, and a set write operation is performed on the cell from which the set state has been read.
- the reset enable signal WRE becomes inactive after a reset write time.
- a write time of 100 ns to 1 ⁇ s or more is required, during which the set enable signal maintains an activated state.
- the set enable signal WSE is deactivated and enters a standby state.
- the memory chip does not have access to external force, so the busy pin WAIT transitions to the low potential state to transmit this to the controller. This allows the operation command of the external controller Issuance is avoided.
- the advantages of this configuration will be described. In the rewrite operation, the reliability of both data can be improved by performing the set write by using only the reset write. Further, by providing a busy pin, it is possible to suppress the issuance of commands by the controller during a period when the memory chip cannot be accessed, thereby preventing data collision and loss.
- This configuration is characterized in that only a reset operation is performed as a write operation.
- only the reset enable signal WRE is activated, and the reset write operation is performed on the memory cell from which the reset state has been read.
- no write operation is performed on the memory cell from which the set state has been read.
- the busy pin WAIT transitions to the low potential state so that no command is issued by the external controller. As a result, the external controller does not access the memory chip.
- FIG. 40 shows the distribution of resistance values when performing multi-value storage using a phase change element. From the high resistance state, resistance state R3 '11', resistance state R2 10 ', resistance state R1 00', and resistance state R0 01 'are allocated. Other allocation methods will not work, but especially in this way, even if the state transitions to the adjacent state, there is an advantage that the possibility that both bits become errors S can be reduced.
- the resistance state of the phase change element is basically an error in which a reset state (high resistance state) transitions to a set state (low resistance state).
- FIG. 41 shows the relationship between the resistance states of the phase change elements of the memory cells at the same address in the two memory cell arrays MCA0 and MCA1 and the stored data MLBt / MSBt.
- the configuration is such that the data of the memory cell in the high resistance state of the two memory cells is output as a true value. For example, when the state of the memory cell of the memory cell array MCA0 is R3, the state of the memory cell of the memory cell array MCA1 is! / However, the output data MLBt / MSBt becomes TI 1 '.
- FIG. 42 shows a block diagram of the peripheral circuit of the memory cell array.
- the memory cell arrays MCA1 and MCA0, the sense amplifier blocks SAB_M, SAB_M, and the OR logic unit ORB_M are arranged.
- FIG. 43 is a block diagram example of the sense amplifier block SAB_M.
- a bit line selection circuit BLSEL, a write driver WD_M, and a sense amplifier circuit SA are arranged, and a 10-gate IOG for converting and outputting read data is arranged in the input / output unit.
- the sense amplifier circuit is provided with three sense amplifier circuits using three reference levels VREF0, VREF1, and VREF2 in order to simultaneously read multiple values.
- FIG. 44 shows the circuit configuration of the write driver WD_M arranged in the sense amplifier block SAB_M.
- the write voltage is determined by 1/00, 1/1/1/02, 1/03 corresponding to the resistance state of the memory cell, and the write period is determined by the write enable signals W0, W1, W2, W3.
- these three sense amplifiers SA mainly refer to SAO0t / b, SA01t / b, and SA2t / b, and output nodes 1 / 00,1 / 01,1 correspond to the resistance state of the memory cell.
- FIG. 46 shows a block diagram of the OR logic unit.
- the read block RE_M is a circuit block that detects errors and outputs likely data to the data read from the two memory cell arrays MCA0 and MCA1.
- the write block WE_M outputs a signal corresponding to the resistance state from the input data to the memory cell array MCA0 when external data is input or when correct data is written back by error detection.
- FIG. 47 shows a specific example of the circuit configuration of the read block RE_M.
- the most significant bit MLBt is a combination of NOR logic of I / O00 and I / O10 and NOR logic of I / O01 and 1/1/011.
- FIG. 48 shows a circuit configuration example of the write block WE_M. Here, the reverse conversion of the read block RE_M is performed.
- FIG. 49 shows a circuit configuration example of the error detection circuit unit DET. Output signals corresponding to the output signals I / O00 and I / O10, I / O10 and 1/101, and I / O02 and 1/102 of the memory cell array MCA0 and MCA1 with OR logic It is.
- the rewrite enable signal RW0 is activated.
- the reliability of stored data is improved by combining with an OR cell array that stores the same data in multiple memory cells, I can take power. Further, since an error detection circuit is added, by performing rewriting at the time of error detection, an error in memory cell data can be corrected, and data reliability can be improved.
- the voltage condition will be described.
- the word line selection level may be 1.8 V or 1.5 V, which is equal to the external voltage VCC, or 2.5 V or 3.0 V, which is internally boosted. Therefore, the rewrite current can be secured even if the size of the memory cell transistor is reduced, so that there is an advantage that a small memory cell area can be realized.
- the sense amplifier power supply VDL and the peripheral circuit power supply VCL do not operate at 1.8V, 1.5V, or 1.2V. By reducing the voltage, low power consumption can be achieved. It is preferable to set the reset write voltage VWR to a potential equal to 1 external voltage VCC in order to reduce power consumption.
- the present invention may be applied to a memory-mixed microcomputer and a memory-dedicated chip used for a mobile phone, a PDA, a system home appliance, or a ubiquitous information terminal. Further, the present invention may be used for a microcomputer with a built-in memory mounted on an automobile, such as for controlling an engine that requires high-temperature operation.
- FIG. 1 is a configuration diagram of an array and peripheral circuits according to Embodiment 1 of the present invention.
- FIG. 2 is a configuration diagram of a memory cell array.
- FIG. 3 is a configuration diagram of a memory cell.
- FIG. 4 is a circuit configuration example of a bit line selector.
- FIG. 5 is a circuit configuration example of a write driver and a sense amplifier.
- FIG. 6 is a waveform diagram of a read operation of Embodiment 1 of the present invention.
- FIG. 7 is a write operation waveform diagram according to the first embodiment of the present invention.
- FIG. 8 is a circuit configuration of a sense amplifier block according to Embodiment 2 of the present invention.
- FIG. 10 is a waveform diagram of a read operation of Embodiment 2 of the present invention.
- FIG. 11 is a waveform diagram of a write operation in Example 2 of the present invention.
- FIG. 12 is a configuration diagram of an array and peripheral circuits according to Embodiment 3 of the present invention.
- FIG. 13 is a table showing a relationship between memory cell data and output data in Embodiment 3 of the present invention.
- FIG. 14 is a current-voltage diagram of a phase change memory.
- FIG. 15 is an operation waveform diagram of a precharge level and a voltage drop of a bit line.
- FIG. 16 is a current-voltage diagram of a phase change memory.
- FIG. 17 is a current-voltage diagram of a phase change memory.
- FIG. 18 is a cross-sectional view of a memory cell of the phase change memory according to Embodiment 1 of the present invention.
- FIG. 22 is a diagram showing a control method of a reset enable signal and a set enable signal.
- FIG. 23 is a diagram showing an example of an operation waveform diagram of FIG. 22.
- FIG. 24 is an example of a block diagram of a memory having a rewrite command.
- FIG. 25 is an example of an operation waveform diagram of the memory in FIG. 24.
- FIG. 26 is another example of an operation waveform diagram of the memory of FIG. 24.
- FIG. 27 is an example of a block diagram of a memory having a self-rewrite determination operation function.
- FIG. 28 is a block diagram of a main part of a memory array of the memory in FIG. 27.
- FIG. 30 is a configuration example of a memory cell array in FIG. 27.
- FIG. 31 is a configuration example of a sense amplifier block for a replica bit line.
- FIG. 32 is a configuration example of a precharge circuit.
- FIG. 33 is a configuration example of a sense amplifier circuit for a replica bit line.
- FIG. 34 is a configuration example of a write enable signal generation method using an OR cell array.
- FIG. 35 is an example of an operation waveform diagram of a memory having a self-rewrite determination function.
- FIG. 36 is an example of a block diagram of a memory having a self-rewrite determination function and a status output pin.
- FIG. 37 is an example of a wait pin output circuit block diagram.
- FIG. 38 is an example of an operation waveform diagram of the memory in FIG. 36.
- FIG. 39 is another example of an operation waveform diagram of the memory in FIG. 36, showing a waveform diagram (with / without replica cell / non-retention determination cycle Set / Reset) with and without rewriting.
- FIG. 40 is a diagram showing a resistance distribution and a direction of data transition when performing multi-value storage in a phase change element.
- FIG. 41 is a diagram showing an example of data mapping when an OR cell array using two multi-value storage elements is configured.
- FIG. 42 is a diagram showing a memory cell array, a sense amplifier block, and an OR logic unit when a multi-value storage element and an OR cell array are combined.
- FIG. 43 is a diagram illustrating a configuration example of a sense amplifier block circuit in FIG. 42.
- FIG. 44 is a circuit configuration example of the write driver in FIG. 43.
- FIG. 45 shows an example of an input / output circuit configuration in FIG. 43.
- FIG. 46 is a block diagram of an OR logic unit in FIG. 42.
- FIG. 47 is a diagram showing a read data configuration block in FIG. 46.
- FIG. 48 is a diagram showing a write data configuration block in FIG. 46.
- FIG. 49 is a diagram showing a configuration example of the error detection circuit in FIG. 46.
- DIt / b External input data line
- Vp, VR bit line precharge level
- TSet Set period prescribed pulse
- RPDEC Row predecoder
- DQ Buffer Input / output data buffer
- SA_REP Sense amplifier block for replica bit line
- RW0 Rewrite enable signal
- VREF_REP Sense amplifier reference level for replica
- I / 0_REPt Sense amplifier output for replica
- MSBt / b Least significant bit
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Abstract
Description
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Cited By (21)
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JP2017512354A (ja) * | 2014-03-11 | 2017-05-18 | インテル・コーポレーション | クロスポイントメモリにおける読み出しディスターブの軽減 |
JP2021022417A (ja) * | 2016-08-08 | 2021-02-18 | マイクロン テクノロジー,インク. | マルチレベルメモリセルを含む装置およびその動作方法 |
US11615844B2 (en) | 2015-11-04 | 2023-03-28 | Micron Technology, Inc. | Apparatuses and methods including memory and operation of same |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4668668B2 (ja) * | 2005-04-14 | 2011-04-13 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2012027977A (ja) | 2010-07-23 | 2012-02-09 | Elpida Memory Inc | 半導体装置 |
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JP2014026568A (ja) * | 2012-07-30 | 2014-02-06 | Hitachi Automotive Systems Ltd | 組込制御装置 |
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002244932A (ja) * | 2001-02-15 | 2002-08-30 | Ricoh Co Ltd | 制御装置 |
WO2003044802A2 (en) * | 2001-11-20 | 2003-05-30 | Micron Technology Inc. | Complementary bit pcram (programmable conductor ram) and method of operation |
JP2003229537A (ja) * | 2002-02-01 | 2003-08-15 | Hitachi Ltd | 半導体記憶装置及びその製造方法 |
JP2004021520A (ja) * | 2002-06-14 | 2004-01-22 | Denso Corp | 車両用電子制御装置 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4002A (en) * | 1845-04-16 | Method of checking- the motion of dkop cut-off valves of steam-engines | ||
JPH1196776A (ja) * | 1997-09-18 | 1999-04-09 | Sanyo Electric Co Ltd | 不揮発性半導体メモリ装置 |
JP2001043691A (ja) * | 1999-07-28 | 2001-02-16 | Hitachi Ltd | 不揮発性記憶回路およびマイクロコンピュータ |
JP3866511B2 (ja) * | 2000-12-22 | 2007-01-10 | 東芝マイクロエレクトロニクス株式会社 | 不揮発性メモリ |
US7116593B2 (en) * | 2002-02-01 | 2006-10-03 | Hitachi, Ltd. | Storage device |
US6768665B2 (en) * | 2002-08-05 | 2004-07-27 | Intel Corporation | Refreshing memory cells of a phase change material memory device |
DE102004016408B4 (de) * | 2003-03-27 | 2008-08-07 | Samsung Electronics Co., Ltd., Suwon | Phasenwechselspeicherbaustein und zugehöriges Programmierverfahren |
CN1717748A (zh) * | 2003-06-25 | 2006-01-04 | 松下电器产业株式会社 | 驱动非易失性存储器的方法 |
JP4540352B2 (ja) * | 2003-09-12 | 2010-09-08 | ルネサスエレクトロニクス株式会社 | 記憶装置 |
-
2004
- 2004-12-06 TW TW93137644A patent/TW200527656A/zh unknown
-
2005
- 2005-01-21 JP JP2005517643A patent/JP4500268B2/ja not_active Expired - Fee Related
- 2005-01-21 WO PCT/JP2005/000742 patent/WO2005076280A1/ja active Application Filing
-
2009
- 2009-11-30 JP JP2009271762A patent/JP5049334B2/ja not_active Expired - Fee Related
-
2012
- 2012-04-13 JP JP2012091968A patent/JP5492245B2/ja not_active Expired - Fee Related
-
2013
- 2013-08-28 JP JP2013176414A patent/JP2013235648A/ja active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002244932A (ja) * | 2001-02-15 | 2002-08-30 | Ricoh Co Ltd | 制御装置 |
WO2003044802A2 (en) * | 2001-11-20 | 2003-05-30 | Micron Technology Inc. | Complementary bit pcram (programmable conductor ram) and method of operation |
JP2003229537A (ja) * | 2002-02-01 | 2003-08-15 | Hitachi Ltd | 半導体記憶装置及びその製造方法 |
JP2004021520A (ja) * | 2002-06-14 | 2004-01-22 | Denso Corp | 車両用電子制御装置 |
Cited By (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005244235A (ja) * | 2004-02-25 | 2005-09-08 | Samsung Electronics Co Ltd | 相変化メモリ装置及びそれの製造方法 |
JP2007134032A (ja) * | 2005-11-07 | 2007-05-31 | Samsung Electronics Co Ltd | 相変化メモリ装置及びそれの読み出し方法 |
JP5145217B2 (ja) * | 2006-05-31 | 2013-02-13 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US8618523B2 (en) | 2006-05-31 | 2013-12-31 | Renesas Electronics Corporation | Semiconductor device |
JP2007335068A (ja) * | 2006-06-09 | 2007-12-27 | Qimonda North America Corp | アクセス部からの電流を用いて書き込まれるメモリセル |
JP2008059736A (ja) * | 2006-06-19 | 2008-03-13 | Qimonda North America Corp | 温度制御されるセットパルスを用いてプログラムされるメモリセル |
JP2008071473A (ja) * | 2006-07-27 | 2008-03-27 | Qimonda North America Corp | 相変化メモリの読み出し障害検知センサ |
JP2008135150A (ja) * | 2006-10-06 | 2008-06-12 | Qimonda North America Corp | マルチビットメモリセルおよび温度バジェットセンサを備えた半導体デバイス |
JP2008152904A (ja) * | 2006-11-22 | 2008-07-03 | Qimonda North America Corp | リフレッシュ動作を含む抵抗メモリ |
JP2015043251A (ja) * | 2007-03-06 | 2015-03-05 | クゥアルコム・インコーポレイテッドQualcomm Incorporated | スピン転移トルク磁気抵抗ランダムアクセスメモリにおける読出し及び書込みのためのワードライン・トランジスタ強度制御 |
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JP2014154201A (ja) * | 2013-02-06 | 2014-08-25 | Toshiba Corp | 不揮発性半導体記憶装置 |
US10304532B2 (en) | 2013-04-02 | 2019-05-28 | Micron Technology, Inc. | Methods of storing and retrieving information for RRAM with multi-cell memory bits |
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JP2016522527A (ja) * | 2013-04-02 | 2016-07-28 | マイクロン テクノロジー, インク. | Rramおよびrramに対して情報を格納し検索する方法 |
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Also Published As
Publication number | Publication date |
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JP4500268B2 (ja) | 2010-07-14 |
JP2010049792A (ja) | 2010-03-04 |
TW200527656A (en) | 2005-08-16 |
JPWO2005076280A1 (ja) | 2007-10-18 |
JP5492245B2 (ja) | 2014-05-14 |
JP2013235648A (ja) | 2013-11-21 |
JP5049334B2 (ja) | 2012-10-17 |
JP2012178216A (ja) | 2012-09-13 |
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