WO2005020275A2 - 縦型半導体装置 - Google Patents
縦型半導体装置Info
- Publication number
- WO2005020275A2 WO2005020275A2 PCT/JP2004/011969 JP2004011969W WO2005020275A2 WO 2005020275 A2 WO2005020275 A2 WO 2005020275A2 JP 2004011969 W JP2004011969 W JP 2004011969W WO 2005020275 A2 WO2005020275 A2 WO 2005020275A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- region
- semiconductor
- column
- conductivity type
- substrate
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 199
- 239000000758 substrate Substances 0.000 claims description 93
- 210000000746 body region Anatomy 0.000 claims description 49
- 239000007772 electrode material Substances 0.000 claims description 7
- 230000015556 catabolic process Effects 0.000 abstract description 16
- 230000005684 electric field Effects 0.000 abstract description 8
- 239000010410 layer Substances 0.000 description 28
- 239000013078 crystal Substances 0.000 description 18
- 238000010586 diagram Methods 0.000 description 8
- 230000002093 peripheral effect Effects 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 230000014509 gene expression Effects 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
Definitions
- the present invention relates to a vertical semiconductor device having a high breakdown voltage, and is suitable for, for example, MS.
- FIG. 11 shows the structure of a conventional vertical MOS field-effect transistor and the like (hereinafter, referred to as a vertical MOSFET) (see Japanese Patent Application Laid-Open No. 2002-184985).
- the N-type semiconductor region 2 and the P-type semiconductor region 3 exist in a trench shape having a certain depth in the substrate depth direction, and these are alternately arranged on the semiconductor substrate 1.
- This is a column structure known as a "super junction structure”.
- a column region 4 having this column structure is formed on a semiconductor substrate 1, and an active region 13 including a source region 7, a gate region 11, and a body region 6 is formed on the column region 4, thereby providing a high withstand voltage and a low withstand voltage.
- the device structure has an on-resistance.
- the junction breakdown voltage between the N-type semiconductor region (hereinafter, referred to as N-type column region 2) and the P-type semiconductor region (hereinafter, referred to as P-type column region 3) is determined. It is important to raise it. Therefore, in the conventional vertical MOSFET, in the cross-sectional structure in which the N-type column regions 2 and the P-type column regions 3 are alternately arranged on the semiconductor substrate 1, the outermost peripheral portion of the active region 13 and the terminal 16 Is set to be equal to or greater than the depth of the column structure 4.
- FIG. 2 is a layout diagram of a column region 4 in which N-type column regions 2 and P-type column regions 3 are alternately arranged on a semiconductor substrate.
- the P-type column region 3 is configured by arranging a plurality of strips in a strip shape, each of which is a polygon.
- the strip-shaped polygon has a pair of long sides facing each other and has a short side located at both ends of the long side. Therefore, for example, in the case of a quadrangle, one of two opposite sides is elongated, and the elongated side is a long side and the other side is a short side.
- One if the polygon is hexagonal
- the paired sides are elongated, with one elongated side being the long side and the other two opposite sides being the short side.
- the active regions 13 are indicated by alternate long and short dash lines in FIG.
- the present invention provides a high-voltage semiconductor device in which ⁇ -type column regions and ⁇ -type column regions are alternately arranged on a semiconductor substrate, and is small in size and capable of achieving sufficient withstand voltage and on-resistance characteristics.
- the purpose is to provide.
- the present inventor has determined a distance between a terminal end 17 of the active region 13 determined by a terminal end of the body contact region and a terminal end 16 on the short side of the ⁇ -shaped column region 3 in the column region 4. Was considered as the termination region length L, and it was found that this termination region length L must be separated at the same distance as the depth of the depletion layer spreading in the substrate depth direction of the column region at the time of complete depletion. Obtained.
- FIG. 3 shows a part of a cross section of a column region 4, that is, a structure in which ⁇ -shaped column regions 2 and ⁇ -shaped column regions 3 are alternately arranged.
- the region composed of the ⁇ -type column region 2 and the ⁇ -type column region 3 has a width (W
- the depth (d) is designed to be depleted.
- the width of the depletion layer extending in the direction parallel to the substrate surface must also be It is necessary to make it equal to the width of the depletion layer that extends. Therefore, the distance from the end 17 of the active region 13 defined by the end of the body contact region 8 to the end 16 of the column region 4 must be set as follows.
- FIG. 4 shows a perspective sectional view of a semiconductor element having a column structure.
- the outermost periphery of the depletion layer which extends from the end of the active region 13 in the direction parallel to the substrate, that is, the end of the depletion layer is, as described above, the N-type column region width (W ) Is located outside by the length of 1Z2. Therefore, from the active area termination 17
- the width of the N-type column area (W) is larger than the distance corresponding to the depth (d) of the ram area.
- the depletion layer spreading in the region facing the short side of the P-type column region 3 extends in a direction perpendicular to the substrate surface The electric field does not concentrate at a specific portion inside the depletion layer because it spreads out equally to the depletion layer.
- the distance from the end 17 of the active region facing the short side of the active region to the P / N junction located at the end 16 of the column region facing the short side of the column region is defined as the end region length L.
- the distance between the end of the body contact region (8), which is the end (17) of the active region, and the end of the column region (16) Is defined as the termination region length L, the width of the first semiconductor region as W, and the depth of the column region as d.
- the width of the depletion layer extending from the inside of the column region (4) toward the end of the column region (16) can be increased. It is possible to increase the breakdown voltage of the vertical semiconductor device (vertical MOSFET) because it is possible to increase the width of the vertical semiconductor device to the same width as it and to avoid electric field concentration at a specific portion in the region facing the short side of the column structure. It becomes possible.
- At least one surface formed on the first conductivity type Si (110) substrate and constituting the outer shape (frame) of the second conductivity type semiconductor region (3) is provided.
- a vertical semiconductor device including a pair of Si (111) planes the end of the body contact region (8), which is the end of the active region (17), and the short side of the second semiconductor region (3) in the column region (4)
- the distance to the termination region (16) is defined as the termination region length L
- the width of the first semiconductor region is defined as W
- the column structure depth is defined as d.
- At least a surface formed on the first conductivity type Si (110) substrate and constituting the outer shape (frame) of the second conductivity type semiconductor region (3) is provided.
- a vertical semiconductor device including a pair of Si (111) planes the end of the body contact region (8), which is the end of the active region (17), and the short side of the second semiconductor region (3) in the column region (4)
- the distance to the side termination (16) is the termination region length L, the first semiconductor region width W, the column structure depth is d, and the body region depth is
- a depletion layer extending from the inside of the column region (4) toward the end of the column region (16) is formed at a substrate depth from the inside of the column region (4). It is possible to expand the depletion layer in the same direction as the depletion layer spreading in the direction, and to avoid electric field concentration at a specific portion in the area facing the short side of the column structure.
- FIG. 1 is a view showing a cross section of a vertical MOSFET according to a first embodiment of the present invention.
- FIG. 2_a is a diagram showing a layout of a vertical MOSFET according to the first embodiment of the present invention.
- FIG. 2-b is a diagram showing a layout of a vertical MOSFET in another example of the first embodiment.
- FIG. 2-c is a diagram showing a layout of a vertical MOSFET in another example of the first embodiment.
- FIG. 2-d is a diagram showing a layout of a vertical MOSFET in another example of the first embodiment.
- FIG. 3 is a view for explaining how a depletion layer spreads in a column region according to the present invention.
- FIG. 4 is a view for explaining the arrangement of column region ends according to the present invention.
- FIG. 5 is a graph showing the dependency of the breakdown voltage of the vertical MOSFET on the termination region length L in the first embodiment of the present invention.
- FIG. 6 is a view showing a cross section of a vertical MOSFET according to a second embodiment of the present invention.
- FIG. 7 is a view showing a cross section of a vertical MOSFET according to a third embodiment of the present invention.
- FIG. 8 is a diagram showing a layout of a vertical MOSFET according to a third embodiment of the present invention.
- FIG. 9 is a view showing a cross section of a vertical MOSFET according to a fourth embodiment of the present invention.
- FIG. 10 is a view showing a cross section of a vertical MOSFET according to another embodiment of the present invention.
- FIG. 11 is a diagram showing a conventional structure.
- FIG. 1A is a cross-sectional view of the vertical MOSFET according to the first embodiment of the present invention, and has a structure corresponding to the BB ′ cross-sectional structure of a region facing the short side of the p-type column region 3 shown in FIG. Is shown.
- FIG. 1 (b) shown to facilitate understanding of the present embodiment shows a structure corresponding to the AA ′ cross-sectional structure of the region facing the long side of the P-type column region 3 shown in FIG. This structure is known from the prior art.
- the vertical MOSFET structure shown in these figures will be described.
- the vertical MOSFET is formed on an N + type semiconductor substrate, and has N + type drain region 1, column region 4, N + type source region 7, P type body region 6, P + type body contact region 8, trench gate Eleven.
- the N + type drain region 1 is formed of an N + type semiconductor substrate, and an electrode portion made of, for example, aluminum is attached to the back surface of the semiconductor substrate.
- the column region 4 is located on the N + type drain region 1.
- the column structure constituting the column region 4 has a P-type column region 3 made of a P-type semiconductor single crystal and an N-type column region 2 made of an N-type semiconductor single crystal alternately. Are arranged side by side.
- FIG. 1 (a) shows a cross section of only the P-type column region 3 of the column region 4.
- the column region 4 is formed of N-type silicon single crystal adjacent to the depth direction of the drawing.
- N-type column region 2 exists.
- the N-type column region 2 can be regarded as a drift region of the vertical MOSFET, and the drain current flows through the N-type column region 2.
- N-type semiconductor region 21 is located outside column region.
- the P- type semiconductor single crystal region 5 is located on the column region 4, or on the N-type semiconductor single crystal region 21 outside the column region 4 and the column region 4, the P- type semiconductor single crystal region 5
- a P-type body region 6 is formed in the surface layer portion of the substrate of the P- type semiconductor single crystal region 5, and an N + source is formed in the P-type body region 6.
- Region 7, P + body contact region 8, and trench are formed.
- a gate insulating film 9 such as a silicon oxide film is formed on the side and bottom surfaces of the trench, and an electrode material 10 such as polysilicon is buried to form a trench gate 11.
- N + type source region 7 is located around trench gate 11 and on the surface of P type body region 6.
- the P + type body contact region 8 is also located on the surface of the P type body region 6. Basically, the P + type body contact region 8 may be formed only in the P type body region 6 disposed between the trench gates 11, but is located at the outermost periphery of the active region 13. The surface of the P-type body region 6 is also formed. By doing so, the potential of the P-type body region 6 located at the outermost periphery of the active region 13 can be fixed, and the parasitic operation can be prevented.
- the N buffer region 12 is provided so as to be in contact with the N-type column region 2 serving as a drift region, the trench gate 11 and the P-type body region 6, and the trench gate 11 reaches the N buffer region 12. It is formed in It is possible to form such a buffer layer 12 over the entire active region 13 only under the trench gate 11, but the P-type body region 6 disposed between the trench gates 11 is a P-type column region. Since it is electrically separated from 3 and becomes a floating state, it is preferable to form it only below the trench gate 11.
- an N-type single-crystal region 22 is formed above the N-type silicon single-crystal region 21 and outside the P-type semiconductor single-crystal region 5 so as to be in contact with the single-crystal region 21 from the surface.
- the single crystal region 22 is arranged from the same position as the terminal position of the P-type column region 3 or from the outside thereof toward the outer peripheral side of the active region 13. Then, the single crystal regions 21 and 22 form a structure in which the outermost periphery of the element is surrounded.
- the depletion layer extending from the inside of the column region 4 toward the column region end 16 is expanded as well as the depletion layer extending from the inside of the column region 4 in the substrate depth direction. Therefore, electric field concentration in a region facing the short side of the column structure can be avoided, and the withstand voltage of the vertical MOS FET can be improved.
- FIG. 5 is a graph showing the dependence of the breakdown voltage on the termination region length L of the vertical MOSFET having a breakdown voltage design value of about 220 V in the present embodiment.
- the vertical axis of the graph indicates the breakdown voltage
- the horizontal axis indicates the termination region length L.
- the breakdown voltage cannot satisfy the design value, and in the region of L> d-W / 2, the breakdown voltage
- the termination region length L is determined by focusing only on the repeating structure of the PN junction in the column region 4. No consideration is given to the repeated structure of the PN junction formed by the buffer layer 12 formed at the depth at which the sofa layer 12 is formed and the P- type semiconductor single crystal region 5. This is because the withstand voltage of the vertical MOSFET shown in the present embodiment is determined by the depth of the column region 4, and even if the buffer layer 12 is provided, the withstand voltage is not determined by it. Therefore, as described above, it is sufficient to determine the termination region L by focusing only on the repeating structure of the PN junction in the column region 4.
- the column structure in addition to the force stripe structure exemplified in the stripe structure shown in Fig. 2 ⁇ , a square dot structure shown in Fig. 2-b and a hexagonal structure shown in Fig. 2-c It is also possible to use a shaped dot structure and a circular dot structure as shown in Figure 2-d.
- the distance between the active region 13 shown by the dashed line in FIG. 2_b and FIG. 2_d and the end of the column region 4 shown by the dashed line, that is, the minimum dimension of the end region length L is the dot.
- Each interval is defined as WN to satisfy the above relationship.
- the gate structure can also have a stripe structure or a periodic structure of dots similarly to the column structure. Even in the case of a stripe structure, the gate structure is parallel to the column structure when viewed from the surface. It is not limited to the structure, and an arrangement having a perpendicular or diagonal positional relationship is also possible.
- FIG. 6A is a cross-sectional view of a vertical MOSFET according to the second embodiment of the present invention.
- This embodiment is different from the first embodiment in that the P ⁇ type semiconductor single crystal region 5 and the N buffer region 12 on the substrate surface in the cross-sectional views shown in FIGS. The difference is that the column structure does not exist in the P body region 6 and reaches the substrate surface.
- the layout on the substrate surface is a structure corresponding to the BB ′ cross-sectional structure of the region facing the short side of the P-type column region 3 shown in FIG.
- FIG. 6 (b) shown to facilitate understanding of the present embodiment is a structure corresponding to the AA ′ cross-sectional structure of the region facing the long side of the P-type column region 3 shown in FIG. This is a conventionally known structure.
- the active region 13 and the N-type semiconductor region 21 made of N-type silicon single crystal are formed so as to satisfy the same numerical formula 2 as in the first embodiment.
- the depletion layer extending from the inside of the column region 4 toward the end 16 of the column region is reduced by the substrate depth of the column region 4. It is possible to expand the depletion layer in the same direction as the depletion layer spreading in the direction, avoiding electric field concentration in the area facing the short side of the column structure, and improving the breakdown voltage of the vertical MOSFET.
- FIG. 7A is a cross-sectional view of the vertical MOSFET according to the third embodiment of the present invention, and has a structure corresponding to the D-D ′ cross-sectional structure of a region facing the short side of the P-type column region 3 shown in FIG.
- FIG. 7B shown for easy understanding of the present embodiment is a structure corresponding to the C-C ′ cross-sectional structure of the region facing the long side of the P-type column region 3 shown in FIG. Yes, it is a known structure.
- the third embodiment is the same as the first embodiment, except that when forming a column structure, a Si (110) substrate is used, and the column structure is formed by wet etching utilizing the plane orientation dependence of the etching rate. Is formed, the column shape is different from that of the above-described embodiment. Others The basic configuration is almost the same as the first embodiment.
- the P / N junction surface at the column region end portion 16 is located perpendicular to the direction parallel to the substrate surface. As shown in FIG. 7 (a), the PZN bonding surface at the column region end portion 16 is 35.27 with respect to the direction parallel to the substrate surface. With an angle of The distance at which the depletion layer spreads is the same as in the above-described embodiment.
- the distance from the end 17 of the active region to the end 16 on the short side of the P-type column region 3 in the column region 4 is N-type. Empty by the length of the column area width W plus half the length
- the termination region length L on the substrate surface is expressed using a trigonometric function, and is specifically expressed as follows.
- a perpendicular line is drawn from the end 17 of the active region in the column region to the substrate surface in the substrate depth direction, and the intersection of the perpendicular line and the boundary line between the P ⁇ type semiconductor region 5 and the P type column region 3
- the starting point is 18, and the distance is calculated by subtracting half the width of the N-type column area W from the column depth.
- the termination region length L is set to be the distance shown in Expression 3.
- the active region determined by the outermost peripheral portion of P + type body contact region 8 The distance from the terminal 17 to the P / N junction at the column region terminal 16 on the substrate surface is defined as the terminal region length.
- the active region 13 and the N-type silicon An N-type semiconductor region 21 made of a crystal is formed.
- the depletion layer extending from the inside of column region 4 toward column region end 16 is expanded to the same extent as the depletion layer extending from column region 4 in the substrate depth direction. Therefore, it is possible to avoid the electric field concentration in the region facing the short side of the column structure, and it is possible to improve the breakdown voltage of the vertical MOSFET.
- FIG. 9A is a sectional view of a vertical MOSFET according to the fourth embodiment of the present invention.
- the difference from the third embodiment is that the P-type semiconductor region 5 and the N buffer region 12 on the surface of the substrate in the sectional views of FIGS. 7A and 7B of the third embodiment are present. That is, the P body region 6 exists inside the column region 4.
- the layout on the substrate surface is a structure corresponding to the D-D ′ cross-sectional structure of a region facing the short side of the second semiconductor region 3 of the second conductivity type shown in FIG. It is.
- FIG. 9 (b) shown to facilitate understanding of the present embodiment is a cross-sectional structure taken along the line CC ′ of a region facing the long side of the second semiconductor region 3 of the second conductivity type shown in FIG. This is a structure that has been conventionally known.
- Equation 4 is satisfied by adding a term (d / tan35.27) with the depth (d) of the P-type body region as a variable shown in FIG.
- the active region 13 and the N-type silicon single crystal region 21 are formed.
- the column region 4 As in the third embodiment, the column region 4 The depletion layer extending from the inside of the column toward the end 16 of the column region can be expanded to the same extent as the depletion layer extending in the depth direction of the substrate.
- the breakdown voltage of the MOSFET can be improved.
- the electric field concentration in the region facing the short side of the column structure is avoided at the corners of the column region in the above-described embodiment, and the withstand voltage of the vertical MOSFET is improved. That is, as shown in FIG. 10, in the portion where the range of the termination region length L from the active region termination 17 is shown with a curvature when viewed from the top surface of the substrate, the column is shorter than the range of the termination region length L. Make sure the side is on the outside.
- the width of the P-type or N-type column region (W, W) in the entire substrate surface and the concentration of the P-type or N-type column region are constant.
- the present invention is applied to the vertical MOSFET, the present invention can be applied to other vertical semiconductor devices.
- the vertical MOSFET is an N-type, but may be a P-type.
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Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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CN2004800200356A CN1823421B (zh) | 2003-08-20 | 2004-08-20 | 垂直型半导体装置 |
DE112004001163.9T DE112004001163B4 (de) | 2003-08-20 | 2004-08-20 | Halbleiteranordnung eines vertikalen Typs |
US10/549,151 US7170119B2 (en) | 2003-08-20 | 2004-08-20 | Vertical type semiconductor device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP2003295946 | 2003-08-20 | ||
JP2003-295946 | 2003-08-20 |
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WO2005020275A2 true WO2005020275A2 (ja) | 2005-03-03 |
WO2005020275A3 WO2005020275A3 (ja) | 2005-04-14 |
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PCT/JP2004/011969 WO2005020275A2 (ja) | 2003-08-20 | 2004-08-20 | 縦型半導体装置 |
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US (1) | US7170119B2 (ja) |
KR (1) | KR100726383B1 (ja) |
CN (1) | CN1823421B (ja) |
DE (1) | DE112004001163B4 (ja) |
WO (1) | WO2005020275A2 (ja) |
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US7285469B2 (en) * | 2005-09-02 | 2007-10-23 | Intersil Americas | Bipolar method and structure having improved BVCEO/RCS trade-off made with depletable collector columns |
US7601603B2 (en) | 2004-03-31 | 2009-10-13 | Denso Corporation | Method for manufacturing semiconductor device |
CN107424928A (zh) * | 2016-05-23 | 2017-12-01 | 英飞凌科技股份有限公司 | 具有充电平衡设计的功率半导体器件 |
CN110121784A (zh) * | 2016-12-14 | 2019-08-13 | 通用电气公司 | 用于超结(sj)器件的边缘终端的***和方法 |
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Also Published As
Publication number | Publication date |
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KR20060014044A (ko) | 2006-02-14 |
CN1823421A (zh) | 2006-08-23 |
US7170119B2 (en) | 2007-01-30 |
WO2005020275A3 (ja) | 2005-04-14 |
US20060170037A1 (en) | 2006-08-03 |
DE112004001163T5 (de) | 2006-07-06 |
CN1823421B (zh) | 2010-04-28 |
DE112004001163B4 (de) | 2017-12-28 |
KR100726383B1 (ko) | 2007-06-08 |
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