WO2005002051A1 - Filtre numérique - Google Patents

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Publication number
WO2005002051A1
WO2005002051A1 PCT/JP2004/003690 JP2004003690W WO2005002051A1 WO 2005002051 A1 WO2005002051 A1 WO 2005002051A1 JP 2004003690 W JP2004003690 W JP 2004003690W WO 2005002051 A1 WO2005002051 A1 WO 2005002051A1
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WO
WIPO (PCT)
Prior art keywords
moving average
output
processing unit
average calculation
filter
Prior art date
Application number
PCT/JP2004/003690
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English (en)
Japanese (ja)
Inventor
Yukio Koyanagi
Original Assignee
Neuro Solution Corp.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Neuro Solution Corp. filed Critical Neuro Solution Corp.
Publication of WO2005002051A1 publication Critical patent/WO2005002051A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/06—Non-recursive filters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/0223—Computation saving measures; Accelerating measures

Definitions

  • the present invention relates to a digital filter, and more particularly to an improved technique of a FIR filter.
  • FIR Finite Impulse Response
  • This FIR filter is a type of filter that has a delay line with taps consisting of multiple delay devices, multiplies the output signal of each tap by a filter coefficient, adds the result of multiplication, and outputs the result. It has the following advantages. First, the pole of the transfer function of the FIR filter is only at the origin of the z-plane, so the circuit is always stable. Second, if the filter coefficients are symmetric, completely accurate linear phase characteristics can be realized.
  • designing a FIR filter means determining the filter coefficients so as to obtain the desired frequency characteristics.
  • an infinite impulse response is obtained based on a target frequency characteristic, and a so-called “windowing” is performed on the response to determine a finite number of filter coefficients.
  • Figure 1 is a diagram showing the configuration of a conventional FIR filter.
  • N— 1 cascaded (N— 1) D-type flip-flops 10 1 to 10
  • N— 1 D-type flip-flops
  • N- 1 D-type flip-flops
  • Adder of 1 0 —, ⁇ :! 0 3- (N-1 ) is added.
  • N multipliers and (N_1) adders are required to configure an FIR filter with N taps by hardware. Even if the circuit configuration is rationalized using the symmetry of the filter coefficients, ⁇ (N-1) / 2 + 1 ⁇ multipliers and (N-1) adders are required.
  • Windowing in the design of the FIR filter is because if the filter coefficients based on the infinite impulse response are used as they are, the number of taps becomes enormous, and an extremely large number of multipliers and adders must be provided. It is. However, in order to obtain a characteristic as close as possible to the target frequency characteristic, the filter coefficient could not be reduced unnecessarily by windowing, and the number of taps N had to be increased.
  • the conventional FIR filter has a problem that the hardware scale becomes very large. Therefore, IIR (Infinite Impulse Response), which can make the circuit size relatively small, was often used, but the phase characteristics of IIR filters are worse than those of FIR filters. There was a problem. Disclosure of the invention
  • the present invention has been made to solve such a problem, and an object of the present invention is to make it possible to configure a FIR filter that realizes favorable frequency characteristics on an extremely small hardware scale.
  • a digital filter adds or subtracts input data and previous data that is a predetermined delay before the input data.
  • the moving average calculation circuit includes: an output processing unit that switches between outputting the result of the amplitude adjustment to the next stage or feeding back the input result as its own input data; And an input processing unit for switching between inputting the data fed back from the output processing unit and inputting the data, and the moving average calculation of the m times is performed by time division multiplexing processing. .
  • a waveform which has a contact at a position where the frequency amplitude characteristic of the n-stage moving average arithmetic circuit has a local maximum value, and realizes a correction frequency amplitude characteristic having a local minimum value at the contact point.
  • An adjustment circuit is further provided, wherein the waveform adjustment circuit is cascaded to the n-stage moving average calculation circuit.
  • the waveform adjustment circuit includes: a plurality of cascade-connected delay circuits; a plurality of coefficient units connected to input / output taps of the plurality of delay circuits; And a plurality of adders connected to the output stage.
  • three coefficient units are connected to input / output taps of two sets of the delay circuits, and output data of the input / output taps are multiplied by coefficients a, b, and a.
  • the two adders connected to the output stages of the three coefficient units are configured to add and subtract the result of the multiplication and to output the result.
  • the coefficients a, b, and a are
  • the FIR filter is configured by repeatedly performing a simple moving average operation on input data.
  • the multiplier can be eliminated from the FIR filter.
  • special time division multiplexing processing is applied to the moving average calculation, the number of adders used can be significantly reduced.
  • an FIR filter having good frequency characteristics can be configured on a very small hardware scale without using a window function.
  • FIG. 1 is a diagram showing a configuration of a conventional FIR filter.
  • FIG. 2 is a diagram illustrating an example of the overall configuration of the FIR filter according to the present embodiment.
  • FIG. 3 is a diagram showing in detail the configuration of the delay processing unit in the first-stage multiplex processing unit.
  • FIG. 4 is a diagram illustrating a detailed configuration example of the input processing unit.
  • FIG. 5 is a timing chart showing each clock used in the present embodiment.
  • FIG. 6 is a diagram illustrating an operation when an impulse signal having an amplitude of “1” is input to the first-stage multiplex processing unit.
  • FIG. 7 is a diagram illustrating a detailed configuration example of the waveform adjustment unit.
  • FIG. 8 is a frequency characteristic diagram for explaining the operation of the waveform adjustment unit.
  • FIG. 9 is a diagram illustrating the frequency amplitude characteristics of the moving average operation processing unit and the frequency amplitude characteristics obtained when one to three waveform adjustment units are cascaded to the moving average operation processing unit.
  • FIG. 10 is a diagram for explaining a principle of a change in frequency characteristics obtained when a plurality of waveform adjustment units are connected in cascade.
  • FIG. 11 is a diagram illustrating filter coefficients of 107 taps that constitute the FIR filter of the present embodiment.
  • FIG. 12 is a diagram illustrating frequency characteristics of the FIR filter according to the present embodiment.
  • the inventor of the present invention focused on the fact that the convolution of the impulse response is the integration of the frequency response in the relationship between the impulse response on the time axis and the frequency characteristics on the frequency axis.
  • the filter design method described in No. 65 has already been proposed. In this method, a basic filter having a finite impulse response is synthesized on the frequency axis, and the slope of the stopband, the bandwidth of the passband, and the flatness of the passband are adjusted by coefficient calculation.
  • the method described in Japanese Patent Application No. 2003-56265 is further generalized, and the simplest moving average is repeated. It is possible to eliminate the multiplier from.
  • the bandwidth of the passband can be adjusted without using a multiplier.
  • special time-division multiplexing processing to the moving average calculation unit, it was possible to reduce the number of adders occupying a large area in the circuit configuration.
  • FIG. 2 shows the F according to the present embodiment.
  • FIG. 3 is a diagram illustrating an example of the overall configuration of an IR filter 10.
  • the FIR filter 10 of the present embodiment includes a moving average calculation processing unit 1 and a waveform adjustment unit 2.
  • the moving average calculation processing unit 1 includes n stages (n ⁇ 1) of multiplex processing units 1-2 ,..., 1- n .
  • Individual multiple processing unit 1 have 1 _ 2, ..., the interior of l _ n is the input processing unit 1 1 having a Sui tool switch function of the data, a plurality of D-type flip-flop is cascade connected It comprises a delay processing unit 12, an adder 13, a shift operation unit 14, and an output processing unit 15 having a data switch function.
  • Each multiplexing processor 1 1; 1 - 2, ⁇ , the delay amount of the delay processing unit 1 2 provided in the 1- n M l, M 2, ⁇ ⁇ ⁇ M n are all may be the same, wherein Let's assume that they are different.
  • the waveform adjustment unit 2 operates according to the clock ck of the reference frequency.
  • FIG. 2 the configurations of the input processing unit 11 and the delay processing unit 12 are shown in a simplified manner. These detailed configuration examples will be described with reference to FIGS. 3 and 4 below.
  • FIG. 3 is a diagram showing in detail the configuration of the delay processing unit 12 for the first-stage multiplex processing unit 1-i.
  • the delay processing unit 12 is configured by cascade-connecting a plurality (nine in this example) of D-type flip-flops. These D-type flip-flops operate in accordance with a quadruple clock 4 ck having a frequency four times that of the reference clock ck, and propagate input data sequentially with a delay corresponding to the quadruple clock 4 ck. .
  • First stage D-type flip-flop Dl 1 output tap and final stage D-type Off 1] and flop D 3 1 output taps are connected to respective adders 1 third input terminal.
  • the adder 13 subtracts the output data of the last stage D-type flip-flop D 31 from the output data of the first stage D-type flip-flop D 11, and outputs the result to the shift operation unit 14. To supply.
  • the shift calculator 14 adjusts the amplitude by multiplying the output data from the adder 13 by 1Z2. Here, multiplication of 1 Z 2 times is performed, but this can be handled by bit shift.
  • the data output from the shift operation unit 14 is switched by the output processing unit 15 and is supplied to the multiplex processing unit 1-2 at a certain timing and fed to the input processing unit 11 at a certain timing. Be packed.
  • the input processing unit 11 and the output processing unit 15 perform switching operation in synchronization with a switching clock ck 1 described below.
  • FIG. 4 is a diagram illustrating a detailed configuration example of the input processing unit 11.
  • FIG. 5 is a timing chart showing the reference clock ck, the quadruple clock 4 ck, and the switching clock ckl.
  • the input processing unit 11 of the present embodiment includes a D-type flip-flop 21, an inverter 22, AND gates 23 and 24, and an OR gate 25. It is configured.
  • the D-type flip-flop 21 holds and outputs the input data for the time of the switching clock ck1.
  • the switching clock c kl is a clock that becomes ⁇ N during one cycle period at a rate of once every four clocks of the quadrupled clock 4 c k.
  • the switching clock c kl is supplied to the input terminal of one AND gate 23 and supplied to the input terminal of the other AND gate 24 via the inverter 22.
  • the AND gate 23 inputs the output data of the D-type flip-flop 21 in addition to the switching clock ck1, and outputs the output data of the D-type flip-flop 21 while the switching clock ck1 is ON. Let it pass. AN of the other The D gate 24 feeds in the output data of the output processing unit 15 in addition to the switching clock ck1 passed through the inverter 22 and feeds back the input data during the period when the switching clock ck1 is FFFF. Pass the data through. The OR gate 25 passes one of the data output from the two AND gates 23 and 24 and supplies the data to the first stage D-type flip-flop D 11. The switching operation in the output processing unit 15 in FIG. 3 is performed in synchronization with the switching operation in the input processing unit 11.
  • the output processing section 1 5, during switching clock ckl is ON, you sweep rate Tsuchingu operative to provide the output data of the shift operation unit 1 4 to the next multiple processing unit 1 _ 2.
  • the switching clock ckl is OFF, the switching operation is performed so that the output data of the shift operation unit 14 is fed back to the input processing unit 11. .
  • the external input data is transmitted to the first stage. Is supplied to the D-type flip-flop D 11 of FIG. 1, and the output data of the shift operation unit 14 is supplied to the multiplex processing unit 1-2 in the next stage. During the remaining three cycles during which the switching clock ck 1 becomes FFFF, the output data of the shift operation unit 14 is fed to the first stage D-type flip-flop D 11 by feed knocking. You.
  • FIG. 6 is a diagram illustrating an operation when an impulse signal having an amplitude of “1” is input to the multiplex processing unit 1_ illustrated in FIG. In FIG.
  • the vertical axis indicates the cycle of 4 times clock 4 ck
  • the horizontal axis indicates the data holding state of each D-type flip-flop constituting the delay processing unit 12.
  • the multiplex processing unit 1 inputs one data every four clocks and outputs one moving average calculation data, during which four moving average calculations are performed. I have done it repeatedly.
  • the numerical value sequence of the output data shown in the rightmost column ⁇ 0.0625,0, -0.25,0,0.375,0, -0.25,0 , 0.06 2 5 ⁇ indicates the filter coefficient obtained as a result of repeating the moving average calculation four times.
  • This filter coefficient is equivalent to a four-stage cascade connection of a basic filter having a filter coefficient of ⁇ 0.5, 0, 0.5 ⁇ , and realizes a high-pass filter frequency characteristic. The details of this are described in Japanese Patent Application No. 2003-56265.
  • multiplexing having the delay amount d between the first stage and the last stage of the delay processing unit 12 is performed.
  • the high-pass filter configured by the processing unit is represented by “H 0 d”. If the moving average operation is repeated four times with the delay amount d, the number of D-type flip-flops used will be ⁇ 4 (d + 1) + 1 ⁇ .
  • the pass band of the filter can be adjusted by changing the delay amount d.
  • the multiplex processing unit 1 i becomes ⁇ —0.5, 0, 10.
  • the multiplex processing unit 1 i becomes ⁇ —0.5, 0, 10.
  • L 0 the low-pass filter
  • L 0 1 1 By cascade-connecting a high-pass filter and a single-pass filter appropriately in this way, the respective frequency characteristics are multiplied, and a band-pass filter having good attenuation characteristics is generated.
  • FIG. 7 is a diagram illustrating a detailed configuration example of the waveform adjustment unit 2.
  • FIG. 8 is a frequency characteristic diagram for explaining the operation of the waveform adjustment unit 2.
  • the waveform indicated by the symbol A in FIG. 8 is realized by the moving average calculation processing unit 1.
  • the original filter a digital filter that has a numerical sequence output from the multiplexing unit 1- n at the final stage as a filter coefficient when an impulse signal with amplitude "1" is input to the multiplexing unit 1-i at the first stage
  • the frequency amplitude characteristics are shown.
  • the gain is normalized (normalized) by "1" in the frequency amplitude characteristics of the original filter.
  • the stopband (the part that changes from the passband to the cutoff) is obtained.
  • Slope and pass bandwidth can be adjusted. That is, as shown by a waveform indicated by reference character C in FIG. 8, the slope can be made steep and the pass band width can be widened.
  • the frequency amplitude characteristic of the correction waveform indicated by reference sign B in FIG. 8 has a contact at a position where the maximum value is obtained in the frequency amplitude characteristic of the original waveform, and has a minimum value at the contact. is there.
  • FIG. 7 shows a configuration example for realizing such a frequency amplitude characteristic of the correction waveform.
  • the waveform adjusting unit 2 includes two cascaded sets of D-type flip-flops 3 l—i S 1 — 2 (corresponding to the delay circuit of the present invention) and each D-type flip-flop.
  • flops 3 and 1 _ i ⁇ 3 1 _ 2 of the three coefficient units, which are connected to the input and output taps 3 S- i S 2 3, connected to these three output stages of the coefficient multiplier 3 2 i to 3 2 3 is configured to include a 2 and - 2 adders 3 3- i to 3 3, which is.
  • the first adder 33_i subtracts the multiplication result of the first coefficient unit 32_2_i from the multiplication result of the second coefficient unit 32_2.
  • the second adder 3 3 2 from the subtraction result of the first adder 3 third coefficient multiplier 3 2 3 multiplication result is subtracted output.
  • the resulting waveform C can be obtained by multiplying the original waveform A in FIG. 8 by the correction waveform B.
  • the coefficient values a and b changes the slope and amplitude of the correction waveform B.
  • the coefficient values a and b be powers of two. If a power of 2, because the coefficient units 3 2- 2- 3 can be constituted by a shift operation unit.
  • Fig. 9 shows the frequency amplitude characteristics of the moving average calculation processing unit 1 (original filter) and the frequency amplitude obtained when one to three waveform adjustment units 2 are cascaded to this moving average calculation processing unit 1. It is a figure showing a characteristic.
  • 4 1 is the frequency amplitude characteristic of the original filter
  • 4 2 is Frequency amplitude characteristics obtained when one waveform adjustment unit 2 is cascaded
  • 4 3 frequency amplitude characteristics obtained when two waveform adjustment units 2 are cascaded
  • 4 4 cascade 3 waveform adjustment units 2 The frequency amplitude characteristics obtained when connected are shown below.
  • FIG. 10 is a diagram for explaining the principle of a change in frequency characteristics obtained when a plurality of waveform adjustment units 2 are cascaded. It should be noted that FIG. 10 is for explaining the basic principle, and does not match the waveform of the frequency characteristic shown in FIG.
  • FIG. 10A shows a change in the frequency amplitude characteristic when the first waveform adjustment unit 2 is cascade-connected to the moving average calculation processing unit 1.
  • A is the frequency amplitude characteristic of the moving average calculation processing unit 1
  • B is the frequency amplitude characteristic of the first waveform adjustment unit 2
  • C is the moving average calculation processing unit 1 and the first waveform.
  • the figure shows the frequency amplitude characteristics obtained when cascaded with the adjustment unit 2.
  • the new frequency amplitude characteristic C is the frequency amplitude characteristic A of the moving average arithmetic processing unit 1 and the waveform adjusting unit 2
  • FIG. 10 (b) shows the change in the frequency amplitude characteristic when the second waveform adjustment unit 2 is further cascaded.
  • a ' is the frequency amplitude characteristic when the first waveform adjustment unit 2 is connected in cascade, and is the same as the frequency amplitude characteristic C obtained in Fig. 10 (a).
  • B is the frequency amplitude characteristic of the second waveform adjustment unit 2, which is the same as that in Fig. 10 (a). is there.
  • C ′ is a new frequency amplitude characteristic obtained when the second waveform adjustment unit 2 is further connected in cascade, and has a form in which the two frequency amplitude characteristics A ′ and B are multiplied.
  • multiplex processing units l_i, 1—2 ,..., 1— such as H01 * L03 * H05 * L07 * H09 * L011 6 are cascaded to form a moving average calculation processing section 1, and one waveform adjustment section 2 is connected to this to form an FIR filter 10.
  • the waveform adjustment unit 2 outputs filter coefficients for 107 taps as shown in FIG.
  • FIG. 12 is a diagram showing frequency characteristics obtained when the filter coefficients of the 107 taps are subjected to FFT (fast Fourier transform).
  • Fig. 12 (a) shows the frequency amplitude characteristics in which the gain is expressed in a linear scale
  • Fig. 12 (b) shows the frequency amplitude characteristics in which the gain is expressed in a logarithmic scale
  • Fig. 12 (c) shows the phase characteristics. Is shown.
  • FIG. 12 it is possible to obtain an extremely good bandpass filter having a linear phase characteristic with an attenuation of 70 dB or more in the cutoff region.
  • the number of multipliers and adders required as a hardware configuration for realizing such good frequency characteristics can be extremely small. That is, although the moving average calculation processing unit 1 and the waveform adjustment unit 2 perform multiplication, the coefficients are all expressed by powers of 2, so the shift operation is sufficient, and no multiplier is required. . Also, the adder multiplexing processing unit of the six stages 1- i, 1 _ 2, ⁇ ⁇ ⁇ , requires only a total of eight one at 6 and two for the waveform adjusting section 2.
  • the moving average calculation is repeated. Since the filter coefficients are obtained by return, the number of multipliers can be zero. Furthermore, since the moving average calculation is performed by time-division multiplexing, the number of adders can be reduced to only eight. As a result, the circuit scale can be significantly reduced as a whole. Moreover, the FIR filter 10 of the present embodiment is extremely easy to design and does not require windowing. As described in detail above, according to the present embodiment, a filter is provided for each tap output of the tapped delay line.
  • the FIR filter 10 is configured using a moving average calculation processing unit 1 that repeatedly performs a simple moving average calculation. All multipliers needed to multiply the filter coefficient can be eliminated. In other words, during the moving average calculation, it is necessary to perform multiplication for amplitude adjustment, but the multiplication can be realized by pit shift calculation. Therefore, the moving average calculation processing unit 1 can completely eliminate the need for a multiplier.
  • the moving average processing unit 1 multiplexing processing unit 1 - I 1 _ 2, ⁇ ⁇ ⁇ , 1. , And the moving average calculation is performed four times by time division multiplexing under a 4 ⁇ clock 4 ck. Therefore, the number of adders required for performing the moving average calculation can be reduced to 14 as compared with the case of performing the normal moving average calculation. Thereby, the circuit scale of the moving average calculation processing unit 1 can be significantly reduced.
  • the waveform adjustment unit 2 is provided for adjusting the waveform of the frequency characteristic, but all the multiplications can be realized by bit shift operation. Therefore, a multiplier can be dispensed with at all in the waveform adjusting section 2 as well. Therefore, even if the FIR filter 10 including the moving average calculation processing unit 1 and the waveform adjustment unit 2 is viewed as a whole, The number of uses is zero, the number of adders used is very small, and an FIR filter 10 having an excellent frequency characteristic with an extremely small hardware scale can be configured.
  • the waveform adjustment unit 2 is provided, but this is not an essential configuration in the present invention. That is, if the target characteristic can be achieved with the frequency characteristic realized by the moving average calculation processing unit 1 depending on the application of the electronic device using the digital filter of the present embodiment, the waveform adjustment unit 2 needs to be provided. Absent.
  • the waveform adjustment unit 2 may be connected in an arbitrary number of stages when the frequency characteristics realized by the moving average calculation processing unit 1 have a narrow passband width or when the slope of the stopband is insufficient.
  • the present invention provides an FIR digital filter of a type that includes a delay line with taps composed of a plurality of delay units, multiplies the output signal of each tap by a filter coefficient, adds the multiplication results thereof, and outputs the result. Useful.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Filters That Use Time-Delay Elements (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

L'invention concerne un filtre numérique qui comprend des sections de traitement en multiplex à n étages (1-1, 1-2, , 1-n) connectées longitudinalement de façon à répéter un calcul de moyenne mobile m fois par multiplexage temporel conformément à une horloge de m fréquences de multiplication m*horloge. Dans le calcul de moyenne mobile, une addition ou une soustraction est effectuée au moyen d'un sommateur (13) entre les données d'entrée et les données précédentes précédant d'un taux de retard prédéterminé et le résultat est réglé en amplitude par un calculateur de décalage (14) afin d'être émis. Le calcul de moyenne mobile simple est renouvelé sur les données d'entrée, constituant ainsi le filtre à réponse impulsionnelle finie (10). Il est ainsi possible d'éliminer le multiplicateur communément utilisé pour multiplier le coefficient du filtre pour chaque sortie de prise de la ligne de retard équipée de prises. De plus, la répétition d'un calcul de moyenne mobile m fois par multiplexage temporel permet également de réduire de façon significative le nombre d'utilisations du sommateur.
PCT/JP2004/003690 2003-06-27 2004-03-18 Filtre numérique WO2005002051A1 (fr)

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US7912884B2 (en) * 2006-12-04 2011-03-22 Aloka Co., Ltd. Method and apparatus for implementing finite impulse response filters without the use of multipliers
JP2009250807A (ja) * 2008-04-07 2009-10-29 Seiko Epson Corp 周波数測定装置及び測定方法
US8510589B2 (en) * 2008-08-29 2013-08-13 Intel Mobile Communications GmbH Apparatus and method using first and second clocks
JP5517033B2 (ja) * 2009-05-22 2014-06-11 セイコーエプソン株式会社 周波数測定装置
JP6474246B2 (ja) * 2014-12-09 2019-02-27 ローム株式会社 オーディオ信号処理回路、車載用オーディオ装置、オーディオコンポーネント装置、電子機器
CN113381730B (zh) * 2021-05-19 2022-10-28 浙江传媒学院 一种鲁棒性自适应滤波***

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0629785A (ja) * 1992-07-13 1994-02-04 Fujitsu Ltd 波形等化器
JPH0697773A (ja) * 1992-09-16 1994-04-08 Matsushita Electric Ind Co Ltd デジタルフィルタ装置
JP2002541706A (ja) * 1999-04-05 2002-12-03 ソニック イノヴェイションズ インコーポレイテッド 多段デシメーション・フィルタ
JP2002368584A (ja) * 2001-06-06 2002-12-20 Sony Corp ディジタルフィルタおよびそれを用いたディジタルビデオエンコーダ

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0629785A (ja) * 1992-07-13 1994-02-04 Fujitsu Ltd 波形等化器
JPH0697773A (ja) * 1992-09-16 1994-04-08 Matsushita Electric Ind Co Ltd デジタルフィルタ装置
JP2002541706A (ja) * 1999-04-05 2002-12-03 ソニック イノヴェイションズ インコーポレイテッド 多段デシメーション・フィルタ
JP2002368584A (ja) * 2001-06-06 2002-12-20 Sony Corp ディジタルフィルタおよびそれを用いたディジタルビデオエンコーダ

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