WO1999056321A1 - Lateraler hochvolt-seitenwandtransistor - Google Patents
Lateraler hochvolt-seitenwandtransistor Download PDFInfo
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- WO1999056321A1 WO1999056321A1 PCT/DE1999/000703 DE9900703W WO9956321A1 WO 1999056321 A1 WO1999056321 A1 WO 1999056321A1 DE 9900703 W DE9900703 W DE 9900703W WO 9956321 A1 WO9956321 A1 WO 9956321A1
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- Prior art keywords
- semiconductor
- lateral high
- type
- transistor according
- voltage
- Prior art date
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- 239000004065 semiconductor Substances 0.000 claims abstract description 66
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 239000004020 conductor Substances 0.000 claims abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 238000009792 diffusion process Methods 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 claims description 3
- 238000000407 epitaxy Methods 0.000 claims 1
- 238000009413 insulation Methods 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 239000002019 doping agent Substances 0.000 description 7
- 239000000463 material Substances 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 235000012239 silicon dioxide Nutrition 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 210000000746 body region Anatomy 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
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- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode
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- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
- H01L29/78624—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile the source and the drain regions being asymmetrical
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- H01L29/0843—Source or drain regions of field-effect devices
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
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- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7812—Vertical DMOS transistors, i.e. VDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-VDMOS transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
Definitions
- the invention relates to a lateral high-voltage sidewall transistor.
- the drain drift path consists of an n-type region in which one or more p-type regions are embedded (cf. for example DE 43 09 764 C2).
- a lateral high-voltage sidewall transistor in which mutually alternating semiconductor layers of one and the other conduction type are provided on a weakly doped semiconductor substrate of the other conduction type, in which a source region of one conduction type and a drain region of one conduction type are also located each extend through the semiconductor layers to the semiconductor substrate, in which a gate electrode made of a gate trench (or trench) filled with a gate insulating layer and conductive material also extends through the semiconductor layers to the semiconductor body and adjoins the source region in Direction is arranged on the drain region, and in which finally a semiconductor region of the other conductivity type is provided at least on one side of the source region and gate trench, which extends to the semiconductor substrate and under the source e area and partially extends under the gate electrode.
- the more pairs of semiconductor layers with alternating conductivity types are provided, the better the conductivity of this sidewall transistor.
- the one line type is preferably the n line type, so that the other line type is given by the p line type and the semiconductor substrate is therefore p ⁇ -doped.
- inventive semiconductor layers are first to an example, p "-doped semiconductor substrate over the entire surface with alternately opposite conductivity type. This may in a preferred manner by a plurality of epitaxially diagram deposits occur and subsequent ion implantations.
- SOI silicon on insulator
- it is also possible, with Using the SOI technology (SOI silicon on insulator) to use an oxidized silicon wafer as a semiconductor substrate, onto which the semiconductor layers alternating in the line type can then be applied using the direct wafer bonding technology Cut technology with subsequent epitaxial deposition are used, in which thin layers are transferred from a first semiconductor wafer by direct bonding to a second semiconductor wafer.
- the areal density of the n-doping, for example phosphorus, and the p-doping, for example boron, in the semiconductor layers should not exceed about 10 12 cm “2 when silicon is used as the semiconductor material, ie it should not be above the" breakdown concentration " If silicon carbide (SiC) is used as the semiconductor material, an areal density of the n-doping or the p-doping in the semiconductor layers of about 10 13 cm -2 should be aimed for, which should not be exceeded.
- SiC silicon carbide
- a structure is therefore first produced in which n-doped and p-doped semiconductor layers are applied in succession to a weakly p -- doped semiconductor body, which have a surface density of the dopings of the order of 10 12 cm -2 for silicon and 10 13 cm Do not exceed -2 for silicon carbide.
- Trenches (trenches) for the source and drain areas and for the "body” area are introduced into the structures produced in this way.
- An n-dopant for example phosphorus or arsenic, is then diffused into the surrounding semiconductor material from the walls of the trenches for the source region and drain region.
- p-dopant for example boron
- the respective trenches for source, drain and body can be filled with doped polycrystalline silicon in order to form leads to the individual levels of the semiconductor layers.
- These supply lines can be separated from one another by an insulating layer made of silicon dioxide, for example. If necessary, it is also possible to reinforce the polycrystalline silicon with a conductive material.
- the gate trenches are introduced and covered with an insulating layer made of, for example, silicon dioxide.
- the gate trenches are then filled with n + -conducting polycrystalline silicon.
- n-type semiconductor layers are thus in contact along the drift path through the source region and drain region. tated, ie connected via the respective trenches for the source electrode and the gate electrode.
- the p-type semiconductor layers of the drift path are connected through the p-type semiconductor region or the body trench.
- the position of the source region and the p-type semiconductor region indicated above means that the source regions are interrupted by the p-type semiconductor region and a channel zone is formed in which the current along the trench wall of the gate trench positive gate-source voltage can flow.
- the lateral high-voltage sidewall transistor according to the invention can optionally also be equipped with a field plate which has an increasing distance from the semiconductor layers continuously or stepwise in the direction from source to drain and is embedded in an insulating layer which consists, for example, of silicon dioxide or silicon nitride.
- the drain region is expediently enclosed at a distance from the drift path from the source region. This does not apply to a design of the lateral high-voltage sidewall transistor using the SOI technology already mentioned.
- the source area and drain area are preferably arranged parallel to one another.
- the trenches are then etched through the entire epitaxial area down to the insulating oxide.
- the n-doping should predominate in the drift path, so that preferably in addition to respective pairs of semiconductor layers with alternating conductivity types, another n-type layer with a surface doping in the range of 10 12 cm "2 without associated p-type Layer is present.
- the one line type is the n line type and the other line type is the p line type
- the reverse line types can also be provided if necessary.
- FIG. 1 shows a sectional illustration with the output material for producing the lateral high-voltage sidewall transistor according to the invention
- Fig. 2 is a sectional view of the finished lateral high-voltage side wall transistor
- FIG. 3 shows a section b-b through FIG. 2, which in turn represents a section a-a of FIG. 2, FIG. 3 having a different scale than FIG. 2.
- FIGS. 1 and 2 show sectional representations, not all cut surfaces are shown hatched for better clarity.
- FIG. 1 shows a p " -conducting semiconductor substrate 1 made of silicon, on which a low-doped epitaxial zone 2 is applied. P-doped layers 3 and n-doped layers 4 are introduced into this epitaxial zone 2, so that in the present exemplary embodiment as a whole there are three pairs of layers 5.
- an additional n-type layer 4 is also present on the surface of the p " -type semiconductor substrate 1.
- the individual layers 3, 4 are preferably produced by several epitaxial depositions and ion implantations.
- the dopant also diffuses from the implanted layers 3, 4 into the regions of the adjoining low-doped epizone 2, so that overall a layer sequence of alternating n-type layers and p-type layers is present on the p " -doped semiconductor substrate 1 , in which the n-doping predominates, since in addition to the layer pairs 5 there is still the additional n-conducting layer on the surface of the p " -containing semiconductor substrate 1.
- the surface density of the doping in the n-type layers 4 and in the p-type layers 3 is below the breakdown concentration, that is to say approximately 10 12 cm “2 for silicon (and 10 13 cm “ 2 for silicon carbide).
- a trench 6 for a drain region, trenches 7 for source regions and trenches 8 for body regions are then introduced into the starting material shown in FIG. 1 (cf. in particular FIG. 3).
- the drain region 9 and the source regions 10 with n-type dopant, for example phosphorus, are then diffused out of the trench walls.
- p-type dopant is diffused from the body trench 8, so that p-type semiconductor regions 11 are formed.
- the gate trench is produced, the wall of which is covered with insulating material 12 made of, for example, silicon dioxide and / or silicon nitride .
- the trenches 6, 7 and 8 for the drain region 9 or the source regions 10 or the semiconductor region 11 are as filled with doped polycrystalline silicon or with metallizations 13, which connect the drain region 9 to a drain electrode D and the source region 10 to a source electrode S.
- the gate trench is filled with n + -conducting polycrystalline silicon 14, which is likewise connected to a metallization 13 for a gate electrode G.
- the n-type layers 4 are thus contacted in the drift path through the source electrode S via the source regions 10, and the p-type layers 3 are not shown in the figures via the semiconductor regions 11 or their metallization introduced into the trench 8 ) contacted.
- the semiconductor regions 8 with the p-doping are designed between the source regions 10 in such a way that their n-doping is interrupted in the gate region and a channel zone is formed in which current runs along the trench wall of the gate trench with a positive gate-source Tension can flow.
- the lateral high-voltage side wall transistor according to the invention can also be equipped with a field plate 15, which is arranged such that its distance from the layers 3, 4 becomes larger as the drain electrode D is approached.
- This field plate 15 is embedded in an insulating layer 16 made of silicon dioxide.
- the field plate 15 can rise steadily in the direction of the drain (as shown in FIG. 2) or also gradually.
- the drain electrode D is expediently enclosed by source. If such a field plate 15 is provided, the n-doping should predominate in the drift path, which is why - as was explained at the beginning - an additional n-conducting layer 4 is provided on the surface of the semiconductor substrate 1 in addition to the pairs 5.
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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JP2000546398A JP2002513211A (ja) | 1998-04-23 | 1999-03-15 | 横形高電圧側壁トランジスタ |
EP99916792A EP1074052A1 (de) | 1998-04-23 | 1999-03-15 | Lateraler hochvolt-seitenwandtransistor |
US09/694,435 US6507071B1 (en) | 1998-04-23 | 2000-10-23 | Lateral high-voltage sidewall transistor |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19818300.3 | 1998-04-23 | ||
DE19818300A DE19818300C1 (de) | 1998-04-23 | 1998-04-23 | Lateraler Hochvolt-Seitenwandtransistor |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/694,435 Continuation US6507071B1 (en) | 1998-04-23 | 2000-10-23 | Lateral high-voltage sidewall transistor |
Publications (1)
Publication Number | Publication Date |
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WO1999056321A1 true WO1999056321A1 (de) | 1999-11-04 |
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ID=7865648
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE1999/000703 WO1999056321A1 (de) | 1998-04-23 | 1999-03-15 | Lateraler hochvolt-seitenwandtransistor |
Country Status (5)
Country | Link |
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US (1) | US6507071B1 (de) |
EP (1) | EP1074052A1 (de) |
JP (1) | JP2002513211A (de) |
DE (1) | DE19818300C1 (de) |
WO (1) | WO1999056321A1 (de) |
Cited By (3)
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JP2004312037A (ja) * | 2001-09-07 | 2004-11-04 | Power Integrations Inc | 多層拡張ドレイン構造を有する高電圧トランジスタを作製する方法 |
JP2006303543A (ja) * | 1999-05-21 | 2006-11-02 | Kansai Electric Power Co Inc:The | 半導体装置 |
JP2009135547A (ja) * | 2002-05-02 | 2009-06-18 | Power Integrations Inc | 高電圧トランジスタの製造方法 |
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WO2000035020A1 (de) * | 1998-12-07 | 2000-06-15 | Infineon Technologies Ag | Laterales hochvolt-halbleiterbaulement mit reduziertem spezifischem einschaltwiderstand |
DE60040798D1 (de) * | 1999-10-27 | 2008-12-24 | Kansai Electric Power Co | Halbleiteranordnung mit Driftbereichen mit entgegengesetzten Leitungstypen |
DE10012610C2 (de) * | 2000-03-15 | 2003-06-18 | Infineon Technologies Ag | Vertikales Hochvolt-Halbleiterbauelement |
US7221011B2 (en) * | 2001-09-07 | 2007-05-22 | Power Integrations, Inc. | High-voltage vertical transistor with a multi-gradient drain doping profile |
US7786533B2 (en) * | 2001-09-07 | 2010-08-31 | Power Integrations, Inc. | High-voltage vertical transistor with edge termination structure |
DE10231966A1 (de) * | 2002-07-15 | 2004-02-12 | Infineon Technologies Ag | Feldeffekttransistor, zugehörige Verwendung und zugehöriges Herstellungsverfahren |
DE10325748B4 (de) * | 2003-06-06 | 2008-10-02 | Infineon Technologies Ag | Sperrschicht-Feldeffekttransistor (JFET) mit Kompensationsstruktur und Feldstoppzone |
US7126166B2 (en) * | 2004-03-11 | 2006-10-24 | Semiconductor Components Industries, L.L.C. | High voltage lateral FET structure with improved on resistance performance |
DE102004063991B4 (de) * | 2004-10-29 | 2009-06-18 | Infineon Technologies Ag | Verfahren zur Herstellung von dotierten Halbleitergebieten in einem Halbleiterkörper eines lateralen Trenchtransistors |
DE102005003127B3 (de) * | 2005-01-21 | 2006-06-14 | Infineon Technologies Ag | Laterales Halbleiterbauelement mit hoher Spannungsfestigkeit und Verfahren zur Herstellung desselben |
US7804150B2 (en) * | 2006-06-29 | 2010-09-28 | Fairchild Semiconductor Corporation | Lateral trench gate FET with direct source-drain current path |
US8860136B2 (en) | 2012-12-03 | 2014-10-14 | Infineon Technologies Ag | Semiconductor device and method of manufacturing a semiconductor device |
US9799762B2 (en) | 2012-12-03 | 2017-10-24 | Infineon Technologies Ag | Semiconductor device and method of manufacturing a semiconductor device |
US10861938B2 (en) | 2013-07-19 | 2020-12-08 | Nissan Motor Co., Ltd. | Semiconductor device and method of manufacturing the same |
US9287404B2 (en) | 2013-10-02 | 2016-03-15 | Infineon Technologies Austria Ag | Semiconductor device and method of manufacturing a semiconductor device with lateral FET cells and field plates |
US9306058B2 (en) | 2013-10-02 | 2016-04-05 | Infineon Technologies Ag | Integrated circuit and method of manufacturing an integrated circuit |
US9401399B2 (en) | 2013-10-15 | 2016-07-26 | Infineon Technologies Ag | Semiconductor device |
DE102016104317B4 (de) | 2015-04-14 | 2024-07-04 | Infineon Technologies Ag | Halbleitervorrichtung mit transistor einschliesslich eines bodykontaktteiles und herstellungsverfahren für die halbleitervorrichtung |
JP2022048690A (ja) * | 2020-09-15 | 2022-03-28 | 住友電気工業株式会社 | 半導体装置 |
CN114639607B (zh) * | 2022-03-16 | 2023-05-26 | 江苏东海半导体股份有限公司 | Mos器件的形成方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0735589A2 (de) * | 1995-03-30 | 1996-10-02 | Kabushiki Kaisha Toshiba | Halbleiteranordnung mit Graben-Gateelektrode und Verfahren zur Herstellung |
GB2309336A (en) * | 1996-01-22 | 1997-07-23 | Fuji Electric Co Ltd | Drift regions in semiconductor devices |
DE19604043A1 (de) * | 1996-02-05 | 1997-08-07 | Siemens Ag | Durch Feldeffekt steuerbares Halbleiterbauelement |
JPH1079503A (ja) * | 1996-08-08 | 1998-03-24 | Samsung Electron Co Ltd | Mosトランジスタ及びその製造方法 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4622569A (en) * | 1984-06-08 | 1986-11-11 | Eaton Corporation | Lateral bidirectional power FET with notched multi-channel stacking and with dual gate reference terminal means |
DE4309764C2 (de) * | 1993-03-25 | 1997-01-30 | Siemens Ag | Leistungs-MOSFET |
-
1998
- 1998-04-23 DE DE19818300A patent/DE19818300C1/de not_active Expired - Fee Related
-
1999
- 1999-03-15 WO PCT/DE1999/000703 patent/WO1999056321A1/de not_active Application Discontinuation
- 1999-03-15 JP JP2000546398A patent/JP2002513211A/ja active Pending
- 1999-03-15 EP EP99916792A patent/EP1074052A1/de not_active Withdrawn
-
2000
- 2000-10-23 US US09/694,435 patent/US6507071B1/en not_active Expired - Lifetime
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0735589A2 (de) * | 1995-03-30 | 1996-10-02 | Kabushiki Kaisha Toshiba | Halbleiteranordnung mit Graben-Gateelektrode und Verfahren zur Herstellung |
GB2309336A (en) * | 1996-01-22 | 1997-07-23 | Fuji Electric Co Ltd | Drift regions in semiconductor devices |
DE19604043A1 (de) * | 1996-02-05 | 1997-08-07 | Siemens Ag | Durch Feldeffekt steuerbares Halbleiterbauelement |
JPH1079503A (ja) * | 1996-08-08 | 1998-03-24 | Samsung Electron Co Ltd | Mosトランジスタ及びその製造方法 |
US5804863A (en) * | 1996-08-08 | 1998-09-08 | Samsung Electronics Co., Ltd. | Field effect transistors including side branch grooves and fabrication methods therefor |
Non-Patent Citations (1)
Title |
---|
PATENT ABSTRACTS OF JAPAN vol. 098, no. 008 30 June 1998 (1998-06-30) * |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006303543A (ja) * | 1999-05-21 | 2006-11-02 | Kansai Electric Power Co Inc:The | 半導体装置 |
JP4653704B2 (ja) * | 1999-05-21 | 2011-03-16 | 関西電力株式会社 | 半導体装置 |
JP2004312037A (ja) * | 2001-09-07 | 2004-11-04 | Power Integrations Inc | 多層拡張ドレイン構造を有する高電圧トランジスタを作製する方法 |
JP2009135547A (ja) * | 2002-05-02 | 2009-06-18 | Power Integrations Inc | 高電圧トランジスタの製造方法 |
Also Published As
Publication number | Publication date |
---|---|
DE19818300C1 (de) | 1999-07-22 |
EP1074052A1 (de) | 2001-02-07 |
US6507071B1 (en) | 2003-01-14 |
JP2002513211A (ja) | 2002-05-08 |
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