WO1997003542A1 - Plaquette de circuits imprimes et son procede de fabrication - Google Patents

Plaquette de circuits imprimes et son procede de fabrication Download PDF

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Publication number
WO1997003542A1
WO1997003542A1 PCT/JP1996/001909 JP9601909W WO9703542A1 WO 1997003542 A1 WO1997003542 A1 WO 1997003542A1 JP 9601909 W JP9601909 W JP 9601909W WO 9703542 A1 WO9703542 A1 WO 9703542A1
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WO
WIPO (PCT)
Prior art keywords
pattern
conductor pattern
film
chemical formula
circuit board
Prior art date
Application number
PCT/JP1996/001909
Other languages
English (en)
Japanese (ja)
Inventor
Hideo Sotokawa
Akira Yabushita
Takashi Inoue
Yasunori Narizuka
Hidetaka Shigi
Mamoru Ogihara
Haruhiko Matsuyama
Minoru Tanaka
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to US08/981,835 priority Critical patent/US5958600A/en
Publication of WO1997003542A1 publication Critical patent/WO1997003542A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S428/00—Stock material or miscellaneous articles
    • Y10S428/901—Printed circuit
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/31504—Composite [nonstructural laminate]
    • Y10T428/31678—Of metal
    • Y10T428/31681—Next to polyester, polyamide or polyimide [e.g., alkyd, glue, or nylon, etc.]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/31504—Composite [nonstructural laminate]
    • Y10T428/31721—Of polyimide

Definitions

  • the present invention relates to a circuit board and a method for manufacturing the same, and more particularly, to a structure of a thin film circuit formed on a wiring board such as a ceramic and a method for manufacturing the same.
  • connection points are enormous for large substrates with high-density wiring, and for ceramic substrates, printing on wiring green sheets, lamination of green sheets, sintering of laminates, etc. It is difficult to connect all the connection points between the conductor on the ceramic substrate side and the thin film circuit without any problem because of the displacement of the connection points and the variation in the displacement caused by the respective steps.
  • the present inventors have conducted intensive studies with the aim of solving all of these problems (1) to (3) and realizing a high-density, high-reliability circuit board and a method of manufacturing the same. This has led to the present invention. Disclosure of the invention
  • the ceramic substrate is manufactured such that the first conductor on the surface of the ceramic substrate takes as large an area as possible so as not to come into contact with the surrounding conductor. At this time, the shape of the first conductor pattern is approximately square, which is advantageous in taking the largest area.
  • an insulating film material such as polyimide is formed in the form of a via hole.
  • the via hole is formed by photolithography.
  • the first conductor on the ceramic substrate is electrically connected to the thin film circuit through the via hole.
  • the first conductor pattern on the ceramic substrate side has a large area, while the size of this via hole can be reduced to the limit by photolithography, so that the displacement and the variation in displacement of the first conductor pattern on the ceramic substrate are almost the same. It is permissible up to the area of the first conductor pattern.
  • a conductive material is deposited on the entire surface by sputtering or vapor deposition, and patterned into a desired shape. I do.
  • a dummy pattern for wiring repair is provided in the first conductive pattern on the ceramic substrate. Conduct a continuity test before forming the thin film circuit to determine which pattern has a defect and which one of the dummy patterns for wiring repair is to be used instead.
  • a first insulating film is formed in the form of a via hole.
  • the via hole on the defective pattern in the first conductive pattern is used to prevent the hole from being opened. Or open holes need to be refilled.
  • the first method is a method of using a negative photosensitive material as a material for forming the first insulating film. In this case, after performing regular exposure for patterning, additional exposure is partially performed only on the defective pattern in the first conductive pattern, so that a via hole is formed in this portion. Prevent it from forming.
  • a non-photosensitive material is used as a material for forming the first insulating film, and a via hole is formed with a negative resist.
  • the exposure method in this case is the same as the first method.
  • the third method is a method of filling the via holes on the defective pattern in the formed via holes by locally applying a material for forming the first insulating film or a material similar thereto. In this case, any method can be used for forming the via hole first.
  • the first conductor pattern can be distinguished by making the shape of the power supply pattern slightly different from that of the signal transmission pattern. It is desirable that the correction of the via hole on the defective pattern in the first conductor pattern can be performed with less errors.
  • a second conductor is deposited and patterning is performed.
  • a negative type is used as a resist for patterning.
  • the second conductor pattern above the defective pattern in the first conductor pattern needs to be connected to a circuit repair wiring pattern formed in the vicinity of the second conductor pattern. Therefore, the portion to be connected is partially subjected to additional exposure.
  • the resist is imaged thereon, in addition to the second conductor pattern, which is a regular pattern, and the wiring pattern for repairing the circuit, on the pattern having the defect in the first conductor pattern, A pattern in which the second conductor pattern and the wiring pattern for circuit repair are connected is completed.
  • the second conductor is etched and the resist is stripped, completing the conductor pattern.
  • the shape of the second conductor pattern can be distinguished by making the shape slightly different between the pattern for supplying power and the pattern for transmitting signals in consideration of later inspection and correction. This makes it possible to reduce errors in later inspections and corrections.
  • a second insulating film is formed in a via hole, and a third conductor is formed in a pattern.
  • a module substrate is completed.
  • the second conductor pattern or the wiring pattern for circuit repair is made of a conductor having a structure sandwiching copper from above and below with at least one of titanium, chromium, molybdenum and tungsten, and the first insulating film is formed.
  • a polyamic acid obtained by polymerizing at least one selected from tetracarboxylic dianhydrides represented by Chemical Formula 1 and at least one selected from diamine compounds represented by Chemical Formula 2 It consists of the generated polyimide.
  • the first insulating film is formed by polymerizing at least one selected from tetracarboxylic dianhydrides represented by the above-mentioned chemical formula 1 with a diamine compound.
  • the content is at least one mole selected from diamine compounds represented by the following chemical formula 3.
  • the sum of the numbers is 0 to 95 moles, and the sum of at least one mole selected from the diamine compounds represented by the following chemical formula 4 is 5 to 100 moles.
  • the first insulating film is made of polyimide formed from a polyamic acid obtained by polymerizing tetracarboxylic dianhydride and a diamine compound,
  • the total amount of tetracarboxylic dianhydride is 100 moles
  • the total content of at least one mole selected from tetracarboxylic dianhydrides represented by the above-mentioned chemical formula 1 is 600 moles.
  • the total amount of the diamine compound is 100 to 100 moles
  • the total number of the at least one kind of the tetracarboxylic dianhydrides represented by the following chemical formula 5 is 0 to 40 moles, and the total amount of the diamine compound is 100 to 100 moles.
  • the total number of moles of at least one selected from the diamine compounds represented by the above-mentioned chemical formula 2 is 60 to 95 mol, and the content is selected from the diamine compounds represented by the following chemical formula 6. At least a kind of mo The total number of components is 5 to 40 moles. ]
  • the conductor pattern of (1) is composed of a conductor having at least one of nickel, chromium, molybdenum, and tungsten on a conductor having nickel on the conductor pattern.
  • the insulating film of the above, at least one selected from tetracarboxylic dianhydride represented by the above-mentioned chemical is composed of a polyimide formed from a polyamic acid obtained by polymerizing at least one selected from the diamine compounds represented by the aforementioned chemical formula 2.
  • the second insulating film is formed of a polyimide formed from a polyamic acid obtained by polymerizing at least one selected from tetracarboxylic dianhydrides represented by the above-mentioned chemical formula 1 and a diamine compound.
  • the total amount of the diamine compound is 100 moles
  • the total content of at least one mole selected from the diamine compounds represented by Chemical Formula 3 is 0 to 95 moles.
  • the total number of moles of at least one selected from the diamine compounds represented by Chemical Formula 4 is 5 to 100 moles.
  • the second insulating film is made of a polyimide generated from a polyamic acid obtained by polymerizing a tetracarboxylic dianhydride and a diamine compound, and the total amount of the tetracarboxylic dianhydride Is 100 moles, the sum of the total number of moles of at least one selected from tetracarboxylic dianhydrides represented by the above-mentioned chemical formula 1 is 60 to:
  • the total of at least one kind of moles selected from the tetracarboxylic dianhydrides represented by the following chemical formula 5 is constituted by 0 to 40 moles, and the total amount of the diamine compound is set to 100 moles.
  • the total is at least 60 to 95 moles of at least one mole selected from the diamine compounds represented by Chemical Formula 2 described above, and at least one selected from the diamine compounds represented by Chemical Formula 6 described above.
  • a kind of mole number The make up at 5-4 0 mol.
  • the reason for increasing the tolerance for connecting the conductor on the ceramic substrate and the thin-film circuit is that the pattern area of the conductor on the ceramic substrate is reduced. Take as wide as possible. On the other hand, the area where the thin film circuit is connected is made as small and accurate as possible.
  • FIG. 1 is a cross-sectional view illustrating an example of a structure and a manufacturing process of a circuit board according to the present invention.
  • FIG. 2 is a cross-sectional view illustrating an example of a multi-chip module manufactured according to the present invention.
  • FIG. 4 is a cross-sectional view showing an example of a structure and a manufacturing process of a circuit board according to the present invention.
  • FIG. 4 is a plan view showing a shape of a conductor pattern of the circuit board according to the present invention and a state of wiring correction.
  • FIG. 5 is a cross-sectional view showing an example of a multi-chip module manufactured according to the present invention.
  • FIG. 1 is a cross-sectional view illustrating an example of a structure and a manufacturing process of a circuit board according to the present invention.
  • FIG. 2 is a cross-sectional view illustrating an example of a multi-chip module manufactured according to the present invention.
  • FIG. 4 is a cross-sectional view showing an example of
  • FIG. 6 is a cross-sectional view showing an example of a structure and a manufacturing process of a circuit board according to the present invention.
  • FIG. 8 is a cross-sectional view showing an example of a structure and a manufacturing process of a circuit board according to the present invention.
  • FIG. 8 is a cross-sectional view showing an example of a structure and a manufacturing process of the circuit board according to the present invention.
  • the present invention FIG. 10 is a cross-sectional view showing an example of the structure of a circuit board and a manufacturing process according to the present invention.
  • FIG. 10 is a characteristic diagram showing the effect of the present invention.
  • a polyimide precursor varnish was synthesized in the same manner as in Synthesis Example 1 using the components shown in Table 1. The solid content concentration and viscosity at that time are also shown in Table 1 (shown as varnish No. 2 to 8 in Table 1). 2 Table 1 Polyimide front varnish
  • BPDA 3,4,3 ', 4, -biphenyltetracarboxylic dianhydride
  • 0DPA 3,4,3', 4, oxydiphthalic dianhydride
  • BAP B 4,4,1-bis (4-aminophenoxy) biphenyl
  • BAP P 2,2-bis [4- (4-aminophenoxy) phenyl] pu bread
  • DMB P 3,3,1-dimethyl-4,4'-diaminobiphenyl
  • DAT P 4,4 "-diamino-p-t-phenyl
  • MDAP dimethylaminopropyl methacrylate
  • MDAE dimethylaminoethyl methacrylate
  • BISAZ Bis (4-azidodenzal) 1-4-potassium lipoxycyclohexanone
  • D AZ B 3, 3 'dimethoxy 4, 4, 1-diazidobiphenyl, APS: 3-aminopropyl trimethoxysilane,
  • APE S 3-aminopropyltriethoxysilane.
  • a glass-based ceramic substrate 1 (15 Omm square, 4.5 mm) having thick film conductors 2 (to be a first conductor pattern) and 3 made of copper on the front and rear surfaces and having copper wiring 4 in the center. on mm thick), 0.5 volume 0/0 solution (solvent APMS is 2-propanol 9 5%, water 5% by volume of the mixture) was spin-coated, 1 1 0 ° C on a hot plate And dried for 15 minutes (Fig. 1 (a)
  • a varnish of Varnish No. 1 in Table 1 was spin-coated as an insulating film 5 (to be a first insulating film), and prebaked on a hot plate at 140 ° C. for 20 minutes.
  • a negative resist is applied as a resist 6, and after prebaking on a hot plate at 110 ° C for 7 minutes, exposure and development are performed, and further, an ashing treatment is performed for 3 minutes, and tetramethylammonium is applied. Exposure to an aqueous hydroxide solution (2.4% by weight) formed via holes 7 [Fig. 1 (b)
  • the resist 6 was peeled off, and kept in a nitrogen stream at 140 ° C for 30 minutes, heated at 4 ° C per minute, kept at 200 ° C for 60 minutes, and heated at 4 ° C per minute, 3 After holding at 50 ° C. for 60, the insulating film 5 was cured through a cooling step (FIG. 1 (c)).
  • a conductor is sputtered in the order of chromium, copper, and chromium, and the conductor pattern 8 (which becomes the second conductor pattern) and the circuit compensator are used using a negative resist. Patterning was performed to include the repair wiring 9, and the resist was stripped [Fig. 1 (d)].
  • the insulating film 10 (To be the second insulating film) [Fig. 1 (e)].
  • a module substrate was completed in the same manner as in Example 1, except that the varnishes N 0, 2 to 8 in Table 1 were used as the insulating layers 5 and 10 in Example 1. Also in these, no cracks, cracks, or peeling were observed in the lower layer and the periphery of the conductor pattern 8, the repair wiring pattern 9, and the conductor pattern 11, and good electrical continuity was obtained over all the wirings. Further, a multichip module shown in FIG. 2 was completed in the same manner as in Example 1. No defects such as cracks, cracks, and peeling were observed in the obtained multichip module, and good electrical continuity and operation characteristics were obtained over all wirings.
  • a glass-based ceramic substrate 1 150 mm square, 4.5 mm
  • thick film conductors 2 to be a first conductor pattern
  • 3 made of copper on the front and back surfaces and having copper wiring 4 inside.
  • a 0.5% by volume solution of APMS solvent is a mixture of 95% by volume of 2-propanol and 5% by volume of water
  • APMS solvent is a mixture of 95% by volume of 2-propanol and 5% by volume of water
  • a varnish of Varnish No. 1 in Table 1 was spin-coated as an insulating film 5 (to be a first insulating film), and prebaked on a hot plate at 140 ° C. for 20 minutes.
  • a negative resist was applied as resist 6, and after prebaking on a hot plate at 110 ° C. for 7 minutes, exposure was performed using a predetermined mask. It is known that the wiring under the conductor pattern 16 has been broken by a continuity test in advance, so it is necessary not to open the via hole in this portion. Therefore, additional exposure is only on conductor pattern 16 Performed locally.
  • the film was developed, and further subjected to an asking treatment for 3 minutes, and exposed to an aqueous solution of tetramethylammonium hydroxide (2.4% by weight) to form a via hole 7 on the conductor 2 [FIG. 3 (b)]. ].
  • the resist 6 is peeled off, kept at 140 ° C for 30 minutes, heated at 4 ° C per minute, heated at 200 ° C for 60 minutes, and heated at 4 ° C per minute in a nitrogen stream.
  • the insulating film 5 was cured through a step of cooling [FIG. 3 (c)] c.
  • a conductor was sputtered in the order of chromium, copper, and chromium to form a negative resist.
  • the conductor pattern 8 (which will be the second conductor pattern) and the circuit repair wiring 9 are exposed using a predetermined mask so that patterning can be performed. 9 was exposed locally to connect.
  • the resist was developed, and after performing asshing for 3 minutes, the conductors of chromium, copper, and chromium were etched, and the resist was peeled [FIG. 3 (d)].
  • FIG. 4 is a plan view showing this state viewed from the upper surface of the substrate.
  • the portion where the conductor pattern 8 and the circuit repair wiring 9 are connected (the fourth conductor pattern) is indicated by 17.
  • a repair conductor pattern is connected to the end of the repair wiring 9 connected by 17, and the defect of the ceramic substrate is saved by this operation.
  • the conductor pattern 8, the circuit repair wiring 9, and the connecting portion 17 serving as the fourth conductor pattern are formed on the surface of the insulating film 5, but the insulating film 5 has a light transmitting property. Therefore, in this figure, the underlying thick film conductor patterns 2, 16 and 16 'are also visible. 4 is connected to the conductor pattern 8 (to be the second conductor pattern) through the via hole 7 because there is no defect in the wiring thereunder.
  • I / O pins 13 are set up via the halves 12, and LSI 15 is connected to the front side via the halves 14.
  • the multichip module shown was completed. No defects such as cracks, cracks, and peeling were observed in the obtained multichip module, and good electrical continuity and operation characteristics were obtained over all wirings.
  • the varnish N 0.2 to 8 in Table 1 was used as the varnish of the polyimide precursor in Example 9, and the same as in Example 9 except that a ceramic substrate having defective wiring was used.
  • a module substrate was completed in the same manner as in 9. Also in these, conductor pattern 8, repair wiring pattern No cracks, cracks, or peeling were observed in the lower layer and the periphery of the conductor 9 and the conductor pattern 11, and good electrical continuity was obtained over all wirings.
  • the multi-chip module shown in FIG. 5 was completed in the same manner as in Example 9. No defects such as cracks, cracks and peeling were observed in the obtained multi-chip module, and good electrical continuity and operation characteristics were obtained over all wirings.
  • % Solution solvent is a mixed solution of 95 volume% of 2 propanol and 5 volume% of water, and dried on a hot plate at 110 ° C for 15 minutes [Fig. 6 (a)] ].
  • a varnish N 0.1 of Table 1 was spin-coated as an insulating film 5 and pre-baked on a hot plate for 14 (TC, 20 minutes. Then, a negative type resist was coated as a resist 20. After pre-baking at 110 ° C for 7 minutes on a hot plate, exposure using a predetermined mask, development, and ashing treatment for 3 minutes were performed, and tetramethylammonium hydroxide aqueous solution was used. (2.4 wt% concentration) to form via holes 7 [Fig. 6 (b)].
  • the resist 6 was peeled off.
  • the varnish of No. 1 in Table 1 was applied locally only to the upper part of the conductor pattern 16 and kept at 140 ° C for 30 minutes in a nitrogen stream, heated at 4 ° C per minute, At ° C After holding for 60 minutes, raising the temperature at 4 ° C. per minute, and holding for 60 at 350 ° C., the insulating film 5 was cured through a cooling step (FIG. 6 (c)).
  • Example 9 Thereafter, through the same steps as in Example 9 [FIGS. 3 (c!) To (f)], a module substrate was completed in the same manner as in Example 9.
  • the completed module board was inspected, no cracks or peeling were observed in the conductor pattern 8, the repair wiring 9, the conductor pattern 11 and its surroundings, or in the lower layer, and good electrical conductivity was observed over all wiring. Conduction was obtained.
  • the pins 13 for input / output are set up via the half 12 and the LSI 15 is connected via the half 14 to the front side.
  • the obtained multi-chip module did not show any defects such as cracks, cracks, and peeling, and good electrical continuity and operation characteristics were obtained over all wirings.
  • a varnish of N 0.1 in Table 1 was spin-coated as an insulating film 5 and prebaked on a hot plate at 140 ° C. for 20 minutes.
  • a positive resist was applied as the resist 20, pre-baked on a hot plate at 110 ° C. for 6 minutes, and then exposed using a predetermined mask. Then, it was exposed to an aqueous solution of tetramethylammonium hydroxide (2.4% by weight wasted).
  • the development of the substrate 20 and the processing of the via hole 7 of the insulating film 5 were collectively performed [FIG. 6 (b)].
  • the resist 20 was peeled off.
  • the varnish of N 0.1 in Table 1 was applied locally only to the upper part of the conductor pattern 16 and kept at 140 ° C for 30 minutes in a nitrogen stream, and at 4 ° C per minute.
  • the insulating film 5 was cured through a cooling process [Fig. c)]).
  • Example 9 Thereafter, through the same steps as in Example 9 [FIGS. 3 (d) to (f)], a module substrate was completed in the same manner as in Example 9.
  • the completed module board was inspected, no cracks or peeling were observed in the conductor pattern 8, the repair wiring 9, the conductor pattern 11 and its surroundings, or in the lower layer. Conduction was obtained.
  • the pins 13 for input / output are set up via the half 12, and the LSI 1 is connected to the front side via the half 14. 5 was connected, and a multi-chip module as shown in Fig. 5 was completed. No defects such as cracks, cracks, and peeling were observed in the obtained multi-chip module, and good electrical continuity and operation characteristics were obtained over all wirings.
  • Example 18 The varnishes Nos. 2 to 8 in Table 1 were used as varnishes of the polyimide precursor in Example 18 except that a ceramic substrate having defective wiring was used as in Example 18; A module substrate was completed in the same manner as in Example 18.
  • conductor pattern 8 repair wiring pattern 9, and conductor pattern No crack, crack, or peeling was observed in the lower layer and the periphery of the pattern 11, and good electrical continuity was obtained over all wirings.
  • the multichip module shown in FIG. 5 was completed in the same manner as in Example 18. No defects such as cracks, cracks, and peeling were observed in the obtained multichip module, and good electrical continuity and operation characteristics were obtained over all wirings.
  • the insulating film 5 is formed of two layers, and as the first insulating film 21, a varnish of No. 9 in Table 2 is spin-coated, and placed on a hot plate at 140 ° C. for 20 minutes. Prebaked. Then, in a nitrogen stream, hold at 14 CTC for 30 minutes, heat up at 4 ° C / min, hold at 200 ° C for 60 minutes, heat up at 4 ° C / min, hold at 350 ° C for 60 minutes Thereafter, the insulating film 21 was cured through a cooling step. The thickness of the insulating film 21 was 1.0 zm [Fig. 7 (b)].
  • a varnish of N0.1 in Table 1 was spin-coated, and pre-betaed at 140 ° C for 20 minutes on a hot plate.
  • a negative resist is applied as a resist 6, and after pre-baking on a hot plate at 110 ° C for 7 minutes, exposed, developed, and further subjected to an asking process for 3 minutes, to thereby prepare tetramethylammonium. Exposure to aqueous hydroxide solution (2.4% by weight) formed via holes [Fig. 7 (c):].
  • the resist 6 was peeled off, kept at 140 ° C for 30 minutes, heated at 4 ° C per minute, kept at 200 ° C for 60 minutes, and kept at 4 ° C per minute in a nitrogen stream. After raising the temperature and maintaining the temperature at 350 ° C. for 60, the insulating film 22 was cured through a cooling step. The thickness of the insulating film 22 was 7 ⁇ (FIG. 7 (d)).
  • Example 1 Thereafter, through the same steps as in Example 1 (FIGS. 1 (d) to 1 (f)), a Joule substrate was completed in the same manner as in Example 1.
  • the completed module board was inspected, no cracks or peeling were observed on the conductor pattern 8, the repair wiring 9, the conductor pattern 11 and its surroundings, or its lower layer. Conduction was obtained.
  • the pins 13 for input / output are set up via the half 12 and the LSI 1 is connected to the front side via the half 14. 5 was connected, and a multi-chip module as shown in Fig. 2 was completed.
  • the obtained multi-chip module did not show any defects such as cracks, cracks, and peeling, and good electrical continuity and operation characteristics were obtained over all wirings.
  • Example 26 In the same manner as in Example 26 except that varnishes of N 0.10 and 14 in Table 2 were used as the first-layer insulating film 21 of the insulating film 5 in Example 26.
  • the module substrate was completed. When the completed module board was inspected, there were no cracks or peeling in conductor pattern 8, repair wiring 9, conductor pattern 11 and its surroundings, or in the lower layer, and good electrical continuity across all wiring was gotten.
  • the input / output pins 13 are set up via the half 12 and the LSI 15 is connected to the front side via the half 14 to complete the multi-chip module as shown in Fig. 2. .
  • the obtained multi-chip module did not show any defects such as cracks, cracks, and peeling, and good electrical continuity and operation characteristics were obtained over all wirings.
  • the insulating film 5 is formed of two layers, and as the first insulating film 21, the varnish of No. 1 in Table 1 is 3 ⁇ after baking up to 350 ° C.
  • the solution was spin-coated as before, and prebaked on a hot plate at 140 ° C for 20 minutes.
  • a negative resist is applied as a resist 6, and prebaked on a hot plate at 110 ° C. for 7 minutes, exposed, developed, and further subjected to a flushing process for 3 minutes to obtain tetramethylammonium. (FIG. 8 (b)).
  • the resist 6 was peeled off and kept at 140 ° C. for 30 minutes in a nitrogen stream. The temperature was raised at 4 ° C for 60 minutes, kept at 200 ° C for 60 minutes, and then cooled (Fig. 8 (c)).
  • the resist 6 was peeled off, and kept in a nitrogen stream at 140 ° C for 30 minutes, heated at 4 ° C per minute, kept at 200 ° C for 60 minutes, heated at 4 ° C per minute, 350
  • the insulating film 21 and the insulating film 22 were hardened through a cooling step, and the insulating film 5 was combined with the insulating film 5 (FIG. 8 (e)).
  • Example 1 Thereafter, through the same steps as in Example 1 (FIGS. 1 (d) to (f)), a module substrate was completed in the same manner as in Example 1.
  • the completed module board was inspected, no cracks or peeling were observed in the conductor pattern 8, the repair wiring 9, the conductor pattern 11 and its surroundings, or in the lower layer. Conduction was obtained.
  • the pins 13 for input / output are set up via the half 12 and the LSI 1 is connected to the front side via the half 14. 5 was connected, and a multi-chip module as shown in Fig. 2 was completed.
  • the obtained multi-chip module did not show any defects such as cracks, cracks, and peeling, and good electrical continuity and operation characteristics were obtained over all wirings.
  • the insulating film 5 is formed of two layers, and as the first insulating film 21, a varnish of No. 14 in Table 2 is applied after baking up to 350 ° C.
  • the solution was spin-coated so that it became ⁇ , and it was overnight on a hot plate for 110 and 15 minutes.
  • exposure was performed using a predetermined mask, and development was performed with a mixed solution of 1-methyl-2-pyrrolidone and water at a volume ratio of 1: 1 to form via holes (FIG. 8 (b)).
  • the resist 6 was peeled off, kept at 140 ° C for 30 minutes in a nitrogen stream, heated at 4 ° C per minute, kept at 200 ° C for 60 minutes, and cooled [Fig. )] c then performs Atsushingu 3 minutes, as the insulating film 22 N 0. 1 varnish Table 1 3 50 ° after baking up C was spin coated so that the 6 Myupaiiota, in Ho Tsu preparative plates Prebaked at 1 40 ° C for 20 minutes.
  • a negative resist is applied as a resist 6 and prebaked on a hot plate at 110 ° C. for 7 minutes, exposed, developed, and further subjected to an ashering treatment for 3 minutes to obtain tetramethylammonium hydroxide. Exposure to an aqueous solution (2.4% by weight) formed via holes [Fig. 8 (d)].
  • the resist 6 was peeled off, and kept at 14 CTC for 30 minutes in a nitrogen stream, heated at 4 ° C per minute, kept at 200 ° C for 60 minutes, heated at 4 ° C per minute, 350
  • the insulating film 21 and the insulating film 22 were cured through a cooling step, and the insulating film 21 and the insulating film 5 were combined to form an insulating film 5 (FIG. 8 (e)).
  • Example 1 Thereafter, through the same steps as in Example 1 (FIGS. 1 (d) to 1 (f)), a module substrate was further completed in the same manner as in Example 1.
  • the completed module board was inspected, there were no cracks or peeling in the conductor pattern 8, the repair wiring 9, the conductor pattern 11 and its surroundings, or in the lower layer, and good electrical continuity over all wiring was gotten.
  • the pins 13 for input and output are set up via the half 1 and the LSI 15 is connected to the front side via the half 14 to complete the multi-chip module as shown in Fig. 2. did. No defects such as cracks, cracks, and peeling were observed in the obtained multi-chip module, and good electrical continuity and operation characteristics were obtained over all wirings.
  • the thin film layer of the present invention is formed on a glass-based ceramic substrate having no wiring defects.
  • FIG. 9 The manufacturing process of the wiring structure manufactured in the present embodiment is shown in FIG. 9 ⁇ Up to the step of FIG. 9 (a), it was performed in the same manner as in FIGS. 7 (a) to (e) of Example 26. .
  • the amino silane is coated on the glass-based ceramic substrate. This not only improves the adhesion between the ceramic and polyimide, but also improves the adhesion between the copper and polyimide exposed on the surface of the ceramic. It also has the effect of preventing the reaction and improving the reliability of the interface between copper and polyimide.
  • Chromium and copper were formed on the substrate by sputtering, respectively.
  • On one side directly apply the material of varnish N 0.1 (Table 1), and in a nitrogen stream at 140 ° C and 200 ° C 350 ° C for 60 minutes each Each baked (sample without AP ES).
  • a 0.5% 2-propanol solution was applied and dried for 15 minutes at 110. Then, the material of varnish N0.1 (Table 1) was applied, and the solution was applied in a nitrogen stream. The sample was baked at 60 ° C, 200 ° C and 350 ° C for 60 minutes each (samples with APES).
  • a module substrate was manufactured in the same manner as in Example 1, except that the varnish No. 11 to 13 in Table 3 was used as the varnish of the polyimide precursor to be the insulating film 5 in Example 1. Done.
  • the conductor 8 made of chromium, copper, and chromium was patterned, and the conductor pattern 8 and the resist were peeled off with a stripper (Fig. 1 (d)). However, it was confirmed that a crack was formed under the end of the conductor pattern 5. In addition, it was confirmed that the lower conductive pattern 2 was partially etched, and the insulating film 5 was floating from the conductive pattern 2 at the crack.
  • Example 1 The varnish of the polyimide precursor to be the insulating film 10 in Example 1 was used.
  • a module substrate was manufactured in the same manner as in Example 1 except that the varnishes No. 11 to 13 in Table 3 were used.
  • the conductor 11 composed mainly of chromium and nickel was etched from the upper layer, and the resist was peeled off with a stripper (Fig. 1 (f)). At 0, it was confirmed that a crack was present below the end of the conductor pattern 11. Also, it was found that a part of the lower conductor pattern 8 composed of chromium, copper, and chromium was etched below the crack.
  • the intended object has been achieved by the present invention. That is, as described in Examples and Comparative Examples, the polyimide formed from the polyimide precursor used in the present invention has a low stress generated by itself, at the same time has a high tensile strength, and further has a high tensile strength. Because of its excellent adhesion to the upper layer metal, even when a conductor layer with large stress such as nickel is formed on it in a pattern, cracks occur in the polyimide or the upper layer metal becomes There is no peeling off.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

L'invention concerne un substrat de circuit en céramique de haute fiabilité. Ce substrat permet d'éviter la fissuration d'une couche isolante placée sous un conducteur soumis à de fortes contraintes. En outre, cette couche isolante se compose d'un isolant organique spécifique. L'invention traite également d'un procédé pour corriger le câblage sur le substrat en céramique, ainsi que d'un procédé de fabrication du substrat du circuit, dans des conditions stables. Ce substrat de circuit se compose d'un substrat de câblage (1) sous forme de film épais, comprenant un premier motif de conducteur (2) et une couche de film mince formée sur ce motif (2). La couche de film mince comprend un premier film isolant (5) formé sur le motif (2), un deuxième film isolant (10) formé sur le film (5), un deuxième motif de conducteur (8) qui est formé sur le film (5), pénètre partiellement dans ce dernier, et est électriquement connecté au motif (2). Elle comprend également un motif de câblage (9) pour la réparation du circuit formé sur le film (5), et un troisième motif de conducteur (11) qui est électriquement connecté au motif (2) par le motif (8) et formé dans les films (5 et 10).
PCT/JP1996/001909 1995-07-10 1996-07-10 Plaquette de circuits imprimes et son procede de fabrication WO1997003542A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US08/981,835 US5958600A (en) 1995-07-10 1996-07-10 Circuit board and method of manufacturing the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP7/173100 1995-07-10
JP17310095 1995-07-10

Publications (1)

Publication Number Publication Date
WO1997003542A1 true WO1997003542A1 (fr) 1997-01-30

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Families Citing this family (7)

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Publication number Priority date Publication date Assignee Title
US5822856A (en) * 1996-06-28 1998-10-20 International Business Machines Corporation Manufacturing circuit board assemblies having filled vias
JP2000232269A (ja) * 1999-02-10 2000-08-22 Nec Toyama Ltd プリント配線板およびプリント配線板の製造方法
US6492600B1 (en) * 1999-06-28 2002-12-10 International Business Machines Corporation Laminate having plated microvia interconnects and method for forming the same
JP2001168125A (ja) * 1999-12-03 2001-06-22 Nec Corp 半導体装置
JP3596807B2 (ja) * 2000-08-09 2004-12-02 インターナショナル・ビジネス・マシーンズ・コーポレーション プリント配線板及びその製造方法
US6956098B2 (en) * 2002-09-20 2005-10-18 E. I. Du Pont De Nemours And Company High modulus polyimide compositions useful as dielectric substrates for electronics applications, and methods relating thereto
CN104037115B (zh) * 2014-06-12 2017-05-17 中国电子科技集团公司第四十一研究所 一种氮化铝基薄膜电路制作方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56118394A (en) * 1980-02-22 1981-09-17 Fujitsu Ltd Method of manufacturing multilayer circuit board
JPH02260695A (ja) * 1989-03-31 1990-10-23 Toppan Printing Co Ltd 多層配線板用銅張積層板および多層配線板
JPH04192405A (ja) * 1990-11-26 1992-07-10 Showa Denko Kk 固体電解コンデンサ
JPH04196390A (ja) * 1990-11-28 1992-07-16 Fujitsu Ltd 薄膜多層配線基板
JPH04248871A (ja) * 1991-01-25 1992-09-04 Hitachi Chem Co Ltd ポリイミド系樹脂ペーストおよびこれを用いたｉｃ
JPH05259651A (ja) * 1992-01-16 1993-10-08 Hitachi Ltd 回路修正機能を有する多層回路配線基板とその回路修正方法及び電子回路装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5536584A (en) * 1992-01-31 1996-07-16 Hitachi, Ltd. Polyimide precursor, polyimide and metalization structure using said polyimide
US5851681A (en) * 1993-03-15 1998-12-22 Hitachi, Ltd. Wiring structure with metal wiring layers and polyimide layers, and fabrication process of multilayer wiring board
JPH08134212A (ja) * 1994-11-14 1996-05-28 Hitachi Ltd 配線構造体とその製造法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56118394A (en) * 1980-02-22 1981-09-17 Fujitsu Ltd Method of manufacturing multilayer circuit board
JPH02260695A (ja) * 1989-03-31 1990-10-23 Toppan Printing Co Ltd 多層配線板用銅張積層板および多層配線板
JPH04192405A (ja) * 1990-11-26 1992-07-10 Showa Denko Kk 固体電解コンデンサ
JPH04196390A (ja) * 1990-11-28 1992-07-16 Fujitsu Ltd 薄膜多層配線基板
JPH04248871A (ja) * 1991-01-25 1992-09-04 Hitachi Chem Co Ltd ポリイミド系樹脂ペーストおよびこれを用いたｉｃ
JPH05259651A (ja) * 1992-01-16 1993-10-08 Hitachi Ltd 回路修正機能を有する多層回路配線基板とその回路修正方法及び電子回路装置

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