WO1993022861A1 - Receiver for digital communication system - Google Patents
Receiver for digital communication system Download PDFInfo
- Publication number
- WO1993022861A1 WO1993022861A1 PCT/JP1993/000510 JP9300510W WO9322861A1 WO 1993022861 A1 WO1993022861 A1 WO 1993022861A1 JP 9300510 W JP9300510 W JP 9300510W WO 9322861 A1 WO9322861 A1 WO 9322861A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- phase
- digital signal
- received digital
- signal
- receiver
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
- H04L27/22—Demodulator circuits; Receiver circuits
- H04L27/227—Demodulator circuits; Receiver circuits using coherent demodulation
- H04L27/2271—Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses only the demodulated signals
- H04L27/2273—Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses only the demodulated signals associated with quadrature demodulation, e.g. Costas loop
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/0014—Carrier regulation
- H04L2027/0024—Carrier regulation at the receiver end
- H04L2027/0026—Correction of carrier offset
- H04L2027/0028—Correction of carrier offset at passband only
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/0014—Carrier regulation
- H04L2027/0044—Control loops for carrier regulation
- H04L2027/0063—Elements of loops
- H04L2027/0067—Phase error detectors
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/0014—Carrier regulation
- H04L2027/0044—Control loops for carrier regulation
- H04L2027/0063—Elements of loops
- H04L2027/0069—Loop filters
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
- H04L7/042—Detectors therefor, e.g. correlators, state machines
Definitions
- the present invention relates to a receiver used in a digital communication system. More particularly, an apparatus and method for compensating for a carrier frequency offset in a receiver of a digital communication system that uses complex correlation to establish or monitor synchronization with a received digital signal;
- the present invention relates to a phase locked loop suitably used for the receiver. Background technology
- this synchronization process There are two types of this synchronization process: That is, at the start of communication, a synchronization establishment process that captures the time slot of a received data frame, and once synchronization is established and communication starts, the position of the reception time slot is monitored and the synchronization is monitored to correct the synchronization. Process.
- the receiver gives a reference signal in advance. (Hereinafter, this reference signal is called “synchronous sequence”).
- this reference signal is called “synchronous sequence”.
- frequency offset In a system that is actually operated, there is a slight difference (hereinafter referred to as “frequency offset”) between the carrier frequency of the transmitting station and the carrier frequency of the receiving station. Because of this frequency offset, the phase of the received signal at the receiving station changes so as to monotonically increase or decrease. For this reason, the calculated correlation value may decrease in the receiving station, and synchronization may not be detected correctly.
- the receiving station controls the carrier frequency of the receiver to match the transmitted carrier frequency using an automatic frequency control circuit (AFC).
- AFC automatic frequency control circuit
- a signal is interfered by an obstacle existing between a base station and a mobile station, and a multi-wave propagation path, a so-called multipath ⁇ Fusing occurs.
- the phase of each vector term of the complex function greatly varies depending on the magnitude and phase of the interference wave, the delay, and the like.
- mobile stations are required to correctly detect and compensate for frequency offsets even under these conditions. This is necessary not only to correctly detect synchronization, but also to maintain the accuracy Z stability of the frequency of the transmission carrier of the mobile station. Disclosure of the invention
- an object of the present invention is to appropriately detect and establish synchronization with a TDMA frame in a receiver applied to a digital communication system. To provide a receiver capable of
- a further object of the present invention is to provide a receiver capable of appropriately compensating for phase fluctuation caused by a frequency offset.
- Another object of the present invention is to provide a receiver capable of correctly detecting the correlation between a received signal and a carrier and controlling the frequency of the carrier oscillator in a short time even when the initial frequency offset of the carrier is large. That is.
- Still another object of the present invention is to provide a digital phase-locked loop capable of sufficiently attenuating noise even when applied to a transmission line with large noise.
- the present invention is a receiver of a communication system for transmitting and receiving a digital signal between a transmitting station and a receiving station, wherein the receiver comprises: a storage unit for storing a reference signal; Means for receiving a signal, calculating a complex correlation between the received digital signal and the reference signal, means for receiving the received digital signal and the reference signal, and estimating a transmission path between the transmitting station and Receiving the received digital signal and an estimation result output from the transmission path estimating means, estimating a phase of the received digital signal, and obtaining a phase change amount; and inputting the phase change amount. And a phase rotation means for compensating for the phase of the digital signal received.
- Another aspect of the present invention is a receiver of a communication system for transmitting and receiving a digital signal between a transmitting station and a receiving station, the receiver comprising: a storage unit for storing a reference signal; and a received digital signal. And a means for calculating a complex correlation between the received digital signal and the reference signal; a transmission path between the received digital signal and the reference signal; Means for estimating: the received digital signal; Phase estimation means for receiving the estimation result output from the determination means, estimating the phase of the received digital signal, and calculating the phase change amount, and inputting the phase change amount, and compensating for the phase of the reception digital signal.
- a receiver for digital communication characterized in that a second loop is formed with the carrier generation means, and the phase of the received digital signal is compensated.
- Still another invention is a phase error detecting means for detecting a phase error between an input signal and an output signal, a means for receiving an output of the phase error detecting means and outputting a correction amount of the phase error, A digital phase-locked loop, characterized in that the output of the correction amount output means is input and the phase of the input signal is corrected.
- FIG. 1 is a functional block diagram of a digital receiver to which the present invention is applied.
- FIG. 2 is a flowchart for explaining the correlation processing applied to the present invention.
- FIG. 3 is a flowchart for explaining another correlation processing of the present invention.
- FIG. 4 is a block diagram of a digital synchronization loop applied to the present invention.
- FIG. 5 is a diagram showing an example of a frequency characteristic of the digital phase locked loop shown in FIG.
- FIG. 6 is a diagram showing a coefficient control method of the digital phase locked loop shown in FIG. BEST MODE FOR CARRYING OUT THE INVENTION
- FIG. 1 is a block diagram showing a digital receiver according to the present invention.
- This digital receiver receives, for example, an 800 MHz band high frequency signal transmitted from a base station (not shown) by an antenna 1.
- This received signal is input to the signal converter 2.
- the signal converter 2 receives the received carrier wave supplied from the carrier oscillator 3.
- the received signal is The carrier signal is converted into a baseband digital signal
- the carrier oscillator 3 generates a reception carrier and a transmission carrier The control of the carrier oscillator 3 will be described later in detail.
- the phase rotator 5 compensates for the phase of the input digital signal.
- the output of the phase rotator 5 is the correlator 4, the PLL 6, And a transmission path estimator 7.
- the correlator 4 is a circuit for calculating a correlation between the signal compensated by the phase rotator 5 and a synchronization sequence held in advance by the digital receiver.
- the output of the phase rotator 5 and the synchronization sequence are supplied to the transmission path estimator 6.
- the transmission path is estimated by an adaptive algorithm.
- the output of P L L 7 is input to phase rotator 5 and L P F 8.
- PLL 7 estimates the phase of the received signal. The estimation of the transmission path in the transmission path estimator 6 and the estimation of the phase in the PLL 7 will be described later in detail.
- step S11 the registers or variables of the transmission path estimator 6 and the PLL 7 are reset.
- step S12 PLL 7
- the phase of the received signal is estimated based on the signal input from the rotator 5. Based on this estimation, the phase rotator 5 compensates for the phase of the received signal.
- the channel estimation is performed by the channel estimator 6 using an adaptive algorithm.
- a general algorithm such as RLS (Recursive Least Squares) or LMS (Least Mean Square) can be used.
- LMS Least Mean Square
- another appropriate algorithm may be used.
- the estimation of the transmission path in the estimator 6 is performed in order to estimate the amount of phase change of the received signal due to the frequency offset in the PLL 7.
- the transmission path estimator 6 transmits And supplies a signal for detecting the phase error of the received signal.
- the transmission path estimation by the transmission path estimator 6 is performed by the following equations (1) to (3).
- C r cr n exp [-j E n ).
- K n represents the Kalman gain vector for RLS, or k tt for LMS with ⁇ 5 as a constant. (* Is complex conjugate).
- the estimated value of E r n is the received signal, e "is the estimation error signal of the transmission line, as shown in later-described equation (4), the phase error detection of PL L 7 Used for exit.
- a second-order PLL is used for the PLL 7 in order to estimate a constant phase change amount due to the frequency offset. This is performed by equations (4) to (7).
- I m [] indicates that an imaginary part is taken. Also, na and ⁇ are
- step S13 the correlation processing proceeds to step S13.
- the complex correlation between the received signal whose phase has been compensated in step S12 and the synchronization sequence is calculated.
- the calculated correlation value between the received signal and the synchronization sequence obtained by correlator 4 is compared with a predetermined threshold value. As a result of the comparison in step S14, if the correlation value is a dog value smaller than the threshold value, the synchronization process ends, assuming that synchronization between the received signal and the carrier wave has been detected.
- the process returns to step S11.
- the same process is performed for each of the N symbols whose symbols of the received signal are shifted backward by one symbol.
- the calculations from (1) to (7) above, the estimation of the transmission path, the estimation of the phase, and the compensation of the phase are performed for the second to (N + 1) th symbols of the received signal, and the correlation value Perform calculations. In this way, thereafter, the same processing is repeated until the correlation value exceeds the threshold.
- the amount of phase change given to the phase rotator 5 by this process is the amount of phase change per symbol due to the frequency offset.
- the phase of the received signal is changed at a fixed rate, and the compensation is performed for each symbol of the received signal.
- Completion of the above-described processing shown in FIG. 2 indicates that synchronization between the received signal and the synchronization sequence has been detected.
- the synchronization between the transmitter and the receiver is established when the synchronization between the received signal and the synchronization sequence is detected several times, not once. ing. Therefore, it is necessary to repeat the synchronization detection process further.o
- FIG. 3 is a Jr r-chart showing another embodiment of the correlation processing of the present invention.
- the correlation processing according to this embodiment is performed by the synchronization establishment process as described above. If the synchronization detection process is performed several times in succession, it can be applied to the second and subsequent processes.
- step S21 the phase error integrator of PLL 7 is initialized, and other registers or variables are reset.
- the phase error integrator is given the value of a ⁇ at the end of the previous correlation processing or the average value of aN obtained in the synchronization detection processing up to the previous time. In other words, in this process, the calculation is not repeated for each symbol of the received signal, but the value already obtained is used.
- step S22 the transmission path estimator 6 estimates the transmission path
- the PLL 7 estimates the phase of the received signal
- the correlator 4 calculates the correlation at the same time.
- step S23 the correlation value is compared with a threshold to determine whether the received signal is synchronized with the synchronization sequence.
- the judgment made in step S23 is the same as that described in FIG. 2. c By performing such processing, it is not necessary to repeat the calculation for each symbol of the received signal. Therefore, the number of repetitive overhead processes and the number of processes of the phase rotator are reduced, and the total amount of calculation can be reduced.
- the estimated value of the frequency offset ⁇ output from the PLL 7 is filtered by the LPF 8 and input to the carrier oscillator 3 to control the carrier oscillator 3.
- a loop including PLL 7, LPF 8, carrier oscillator 3, and signal input unit 2 is formed, and controls the frequency offset of the received signal.
- FIG. 4 shows a detailed circuit diagram of the phase rotator 5 and PLL 7 shown in FIG.
- the phase of the received signal is compensated by the phase rotator 5 and is input to the phase error detection circuit 70.
- the phase error detection circuit 70 includes a complex conjugate unit 71, a multiplier 72, and an imaginary part extraction unit 73.
- the received signal input to the phase error detection circuit 70 is input to the multiplier 72 via the complex conjugate unit 71.
- the multiplier 72 also receives ett from the transmission channel estimator 6.
- the output obtained by multiplying the two is supplied to the imaginary part extraction unit 73.
- the output of the imaginary part extraction portion, and Kurai ⁇ 0 eta of the received signal, the error ⁇ 0 eta with phase E 0 eta of the recovered carrier. This phase error ⁇ 0 ⁇ is supplied to the loop filter 80.
- the received signal is directly input to the multiplier 72 without passing through the complex conjugate unit 71.
- the signal input to the multiplier 7 2 from the transmission path estimator 6, E r n next instead of e n, and a configuration in which the complex conjugate of the E r "is inputted to the multiplier As is clear from equation (4), in any of the above configurations, only the signal that takes the complex conjugate changes, and the output of the phase error detection circuit 70 is the phase error ⁇ 3 ⁇ 46 ⁇ .
- the loop filter 80 includes a first multiplier 81 that multiplies the phase error ⁇ 0 ⁇ by a first coefficient ⁇ , an integrator 82 that integrates an output of the first multiplier 81, and a phase error.
- second multiplier 8 3 multiplying the second coefficient .DELTA.0 eta, is further, an adder 8 4 for summing the integrator 82 output and the output of the multiplier 8 3.
- integrator 8 2 Calculates the DC component of the phase error ⁇ 0 ⁇ by accumulating the output of the multiplier 81 by the adder 82 a and the register 82 b.
- the phase change amount ⁇ ⁇ ⁇ to be given to the phase rotator 5 is stored in the register 82b.
- the instantaneous value of the phase error is calculated by 83.
- the adder 84 adds the output of the integrator 82 and the output of the multiplier 83 and outputs the sum as the phase correction amount ⁇ + 1 of the reproduced carrier.
- the phase correction amount ⁇ 0 ⁇ + 1 is input to the adder 91 included in the VC 090.
- the adder 91 stores the input phase correction amount in the register 92. Add to the phase of the recovered carrier ⁇ 0 ⁇
- the content of this register 92 is output as the phase of the recovered carrier at the next time ⁇ 0 ⁇ +1 and fed back to the phase rotator 5.
- FIG. 5 shows an example of the frequency characteristic of equation (8), where the peak frequency ⁇ . Is, from the pole of equation (8),
- phase locked loop In a digital phase-locked loop, there is a trade-off between the noise component of the output phase and the convergence speed of the phase error. Therefore, when the characteristic of the loop filter 80 is set to a narrow band, the effect of attenuating the noise increases, but it takes a longer time until the synchronous loop is converged. In particular, when the initial phase error between the input received signal and the recovered carrier extracted from the received signal is large, it takes a long time until the phase locked loop becomes convergent, during which time the signal is The problem of not being demodulated may occur. However, the synchronization sequence of a digital cellular system is usually only about a dozen symbols, and the receiver must converge the phase locked loop in a short time during this period.
- the noise can be attenuated during the convergence operation and the convergence can be achieved in a short time from a state having a large initial phase error to a steady operation state.
- the loop filter 80 includes a coefficient control circuit 85.
- the value of the coefficient ⁇ is set to the initial value, and the operation of the digital phase-locked loop is started. Next, every time a predetermined time elapses, the value of the coefficient ⁇ is sequentially reduced toward the convergence value. Finally, the value of the coefficient ⁇ is fixed to the convergence value.
- the initial value of the coefficient ⁇ is sufficient for the loop filter 80 so that the phase of the reproduced carrier can be pulled in a short time even when the initial phase error between the input received signal and the reproduced carrier is large.
- the convergence value is set to a sufficiently small value so that the loop filter 80 has a sufficiently narrow band in order to sufficiently attenuate the phase error noise during the steady operation even in a transmission line with large noise.
- FIG. 6 shows a specific method of controlling the coefficient ⁇ of the coefficient control circuit 85.
- T i represents the time to operate with the coefficient. ⁇ . If the coefficient ⁇ is reduced, the bandwidth of the filter becomes narrower, but the convergence time becomes longer. Therefore, as shown in Fig. 6, as the coefficient ⁇ is reduced, the phase error due to the noise component of the transmission line at the previous coefficient value is sufficiently attenuated. Control to make it longer than the operation time with the value.
- This phase locked loop is realized by an individual circuit using an integrated circuit or the like or program control by a processor.
- the frequency offset is controlled by a loop composed of the PLL 7, the LPF 8, the carrier oscillator 3, and the signal input unit 2 for each frame of the received signal.
- a loop composed of the PLL 7 and the phase rotator 5 controls the frequency offset for each symbol of the received signal.
- the correlation process used in this process is performed in the same manner as described in FIG. However, in this case, the initial value of the phase error integrator of PLL7 is set to zero. Further, it is desirable that the coefficient ⁇ of PLL 7 is fixed at a small convergence value in order to reduce the influence of noise. In this process, the frequency offset is reduced due to the control of the carrier oscillator at the time of establishing the cycle, and therefore, the time required until the convergence of the synchronization is shorter than the control in the synchronization establishment process. Therefore, the control in this process is mainly intended to suppress noise.
- the receiver used in the digital cellular system has been described as an example, but the present invention is also applicable to a system using a reference signal for synchronization detection in general.
- AGC, AZD converters, DZA converters, etc. that maintain the level of the received Description of functions provided in digital receivers is omitted.
- the configuration of the digital phase-locked loop shown here and the coefficient control by this phase-locked loop are not limited to the configuration described here, but are widely applied to other devices using the digital phase-locked loop. It is possible to do so.
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/167,967 US5602881A (en) | 1992-04-24 | 1993-04-20 | Receiver for a digital communication system |
EP93908119A EP0592686B1 (en) | 1992-04-24 | 1993-04-20 | Receiver for digital communication system |
JP5519120A JP2892502B2 (ja) | 1992-04-24 | 1993-04-20 | ディジタル通信システムのための受信機 |
DE69332139T DE69332139T2 (de) | 1992-04-24 | 1993-04-20 | Empfänger für digitale Nachrichtensysteme |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10650192 | 1992-04-24 | ||
JP4/106501 | 1992-04-24 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1993022861A1 true WO1993022861A1 (en) | 1993-11-11 |
Family
ID=14435189
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP1993/000510 WO1993022861A1 (en) | 1992-04-24 | 1993-04-20 | Receiver for digital communication system |
Country Status (5)
Country | Link |
---|---|
US (2) | US5602881A (ja) |
EP (1) | EP0592686B1 (ja) |
CA (1) | CA2112221A1 (ja) |
DE (1) | DE69332139T2 (ja) |
WO (1) | WO1993022861A1 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8532233B2 (en) | 2008-08-21 | 2013-09-10 | Fujitsu Limited | Apparatus and method for frequency offset estimation |
JP2022053144A (ja) * | 2020-09-24 | 2022-04-05 | 株式会社東芝 | 位相補正装置及び測距装置 |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0698970B1 (fr) * | 1994-08-25 | 1998-04-29 | Laboratoires D'electronique Philips S.A.S. | Système de transmission numérique à double boucle de synchronisation |
JP3482722B2 (ja) * | 1995-01-13 | 2004-01-06 | ソニー株式会社 | Tdma方式の受信機 |
JP3414558B2 (ja) * | 1995-08-25 | 2003-06-09 | 沖電気工業株式会社 | 最大相関値タイミング推定回路及び受信装置 |
GB2309866A (en) * | 1996-01-30 | 1997-08-06 | Sony Corp | Frequency error detection in mobile radio communications |
US6097770A (en) * | 1996-10-31 | 2000-08-01 | Lucent Technologies Inc. | Frequency offset estimation for wireless systems based on channel impulse response |
US6208617B1 (en) * | 1998-02-27 | 2001-03-27 | Lucent Technologies, Inc. | Channel tracking in a mobile receiver |
KR100606673B1 (ko) * | 1999-06-24 | 2006-08-01 | 엘지전자 주식회사 | 파일럿 패턴을 이용한 프레임 동기 방법 |
US7496132B2 (en) * | 1999-03-15 | 2009-02-24 | Kg Electronics Inc. | Pilot signals for synchronization and/or channel estimation |
US7643540B2 (en) * | 1999-03-15 | 2010-01-05 | Lg Electronics Inc. | Pilot signals for synchronization and/or channel estimation |
US6891815B1 (en) * | 1999-03-15 | 2005-05-10 | Young-Joon Song | Pilot signals for synchronization and/or channel estimation |
KR100294711B1 (ko) * | 1999-03-15 | 2001-07-12 | 서평원 | 최적의 파일럿 심볼을 이용한 프레임 동기 방법 |
US6721299B1 (en) * | 1999-03-15 | 2004-04-13 | Lg Information & Communications, Ltd. | Pilot signals for synchronization and/or channel estimation |
US6363102B1 (en) * | 1999-04-23 | 2002-03-26 | Qualcomm Incorporated | Method and apparatus for frequency offset correction |
KR100710344B1 (ko) | 1999-06-24 | 2007-04-23 | 엘지전자 주식회사 | 이동통신 시스템에서의 무선 프레임 구조 및 파일롯 패턴전송 방법 |
US8363757B1 (en) * | 1999-10-12 | 2013-01-29 | Qualcomm Incorporated | Method and apparatus for eliminating the effects of frequency offsets in a digital communication system |
US6928120B1 (en) * | 2000-09-25 | 2005-08-09 | Cingular Wireless Ii, Llc | Methods and apparatus for use in reducing residual phase error in OFDM communication signals |
GB2379840A (en) * | 2001-09-13 | 2003-03-19 | Ipwireless Inc | Automatic frequency correction |
US7020222B2 (en) * | 2001-10-24 | 2006-03-28 | Texas Instruments Incorporated | Efficient method and system for offset phasor determination |
JP3973543B2 (ja) * | 2002-11-20 | 2007-09-12 | 三洋電機株式会社 | 受信方法と装置 |
EP3672070A1 (en) * | 2018-12-19 | 2020-06-24 | Nxp B.V. | Communications device and method for operating a communications device |
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JPS5963849A (ja) * | 1982-10-04 | 1984-04-11 | Nec Corp | キヤリア位相制御装置 |
JPS6055763A (ja) * | 1983-09-06 | 1985-04-01 | Hitachi Denshi Ltd | 位相制御方法 |
JPS60141056A (ja) * | 1983-12-28 | 1985-07-26 | Hitachi Denshi Ltd | キヤリヤ位相制御装置 |
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US4599732A (en) * | 1984-04-17 | 1986-07-08 | Harris Corporation | Technique for acquiring timing and frequency synchronization for modem utilizing known (non-data) symbols as part of their normal transmitted data format |
DE3765947D1 (de) * | 1986-01-18 | 1990-12-13 | Hewlett Packard Ltd | Beeinflussungsfreier analysator zur erfassung von kanalstoerungen. |
US4873683A (en) * | 1987-12-04 | 1989-10-10 | Motorola, Inc. | TDMA radio system employing BPSK synchronization for QPSK signals subject to random phase variation and multipath fading |
US5121414A (en) * | 1990-08-09 | 1992-06-09 | Motorola, Inc. | Carrier frequency offset equalization |
FR2672454B1 (fr) * | 1991-01-31 | 1994-10-07 | Alcatel Telspace | Procede de demodulation coherente pour modulation a deplacement de phase et dispositif de mise en óoeuvre de ce procede. |
US5245611A (en) * | 1991-05-31 | 1993-09-14 | Motorola, Inc. | Method and apparatus for providing carrier frequency offset compensation in a tdma communication system |
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1993
- 1993-04-20 WO PCT/JP1993/000510 patent/WO1993022861A1/ja active IP Right Grant
- 1993-04-20 US US08/167,967 patent/US5602881A/en not_active Expired - Lifetime
- 1993-04-20 EP EP93908119A patent/EP0592686B1/en not_active Expired - Lifetime
- 1993-04-20 DE DE69332139T patent/DE69332139T2/de not_active Expired - Lifetime
- 1993-04-20 CA CA002112221A patent/CA2112221A1/en not_active Abandoned
-
1996
- 1996-10-25 US US08/736,767 patent/US5751776A/en not_active Expired - Lifetime
Patent Citations (3)
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JPS5963849A (ja) * | 1982-10-04 | 1984-04-11 | Nec Corp | キヤリア位相制御装置 |
JPS6055763A (ja) * | 1983-09-06 | 1985-04-01 | Hitachi Denshi Ltd | 位相制御方法 |
JPS60141056A (ja) * | 1983-12-28 | 1985-07-26 | Hitachi Denshi Ltd | キヤリヤ位相制御装置 |
Non-Patent Citations (1)
Title |
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See also references of EP0592686A4 * |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8532233B2 (en) | 2008-08-21 | 2013-09-10 | Fujitsu Limited | Apparatus and method for frequency offset estimation |
JP2022053144A (ja) * | 2020-09-24 | 2022-04-05 | 株式会社東芝 | 位相補正装置及び測距装置 |
Also Published As
Publication number | Publication date |
---|---|
US5602881A (en) | 1997-02-11 |
DE69332139T2 (de) | 2003-03-27 |
US5751776A (en) | 1998-05-12 |
DE69332139D1 (de) | 2002-08-29 |
EP0592686A4 (en) | 1999-09-15 |
EP0592686B1 (en) | 2002-07-24 |
CA2112221A1 (en) | 1993-11-11 |
EP0592686A1 (en) | 1994-04-20 |
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