US8004550B2 - Light-emitting element head, image forming apparatus and signal supply method - Google Patents

Light-emitting element head, image forming apparatus and signal supply method Download PDF

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US8004550B2
US8004550B2 US12/468,278 US46827809A US8004550B2 US 8004550 B2 US8004550 B2 US 8004550B2 US 46827809 A US46827809 A US 46827809A US 8004550 B2 US8004550 B2 US 8004550B2
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light
emitting element
element chips
emitting
signals
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US20100118100A1 (en
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Seiji Ohno
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Fujifilm Business Innovation Corp
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Fuji Xerox Co Ltd
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/435—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of radiation to a printing material or impression-transfer material
    • B41J2/447—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of radiation to a printing material or impression-transfer material using arrays of radiation sources
    • B41J2/45—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of radiation to a printing material or impression-transfer material using arrays of radiation sources using light-emitting diode [LED] or laser arrays
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03G—ELECTROGRAPHY; ELECTROPHOTOGRAPHY; MAGNETOGRAPHY
    • G03G15/00—Apparatus for electrographic processes using a charge pattern
    • G03G15/04—Apparatus for electrographic processes using a charge pattern for exposing, i.e. imagewise exposure by optically projecting the original image on a photoconductive recording material
    • G03G15/04036—Details of illuminating systems, e.g. lamps, reflectors
    • G03G15/04045—Details of illuminating systems, e.g. lamps, reflectors for exposing image information provided otherwise than by directly projecting the original image onto the photoconductive recording material, e.g. digital copiers
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03G—ELECTROGRAPHY; ELECTROPHOTOGRAPHY; MAGNETOGRAPHY
    • G03G15/00—Apparatus for electrographic processes using a charge pattern
    • G03G15/22—Apparatus for electrographic processes using a charge pattern involving the combination of more than one step according to groups G03G13/02 - G03G13/20
    • G03G15/32—Apparatus for electrographic processes using a charge pattern involving the combination of more than one step according to groups G03G13/02 - G03G13/20 in which the charge pattern is formed dotwise, e.g. by a thermal head
    • G03G15/326—Apparatus for electrographic processes using a charge pattern involving the combination of more than one step according to groups G03G13/02 - G03G13/20 in which the charge pattern is formed dotwise, e.g. by a thermal head by application of light, e.g. using a LED array
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K15/00—Arrangements for producing a permanent visual presentation of the output data, e.g. computer output printers
    • G06K15/02—Arrangements for producing a permanent visual presentation of the output data, e.g. computer output printers using printers
    • G06K15/12—Arrangements for producing a permanent visual presentation of the output data, e.g. computer output printers using printers by photographic printing, e.g. by laser printers
    • G06K15/1238—Arrangements for producing a permanent visual presentation of the output data, e.g. computer output printers using printers by photographic printing, e.g. by laser printers simultaneously exposing more than one point
    • G06K15/1242—Arrangements for producing a permanent visual presentation of the output data, e.g. computer output printers using printers by photographic printing, e.g. by laser printers simultaneously exposing more than one point on one main scanning line
    • G06K15/1247—Arrangements for producing a permanent visual presentation of the output data, e.g. computer output printers using printers by photographic printing, e.g. by laser printers simultaneously exposing more than one point on one main scanning line using an array of light sources, e.g. a linear array
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K15/00—Arrangements for producing a permanent visual presentation of the output data, e.g. computer output printers
    • G06K15/02—Arrangements for producing a permanent visual presentation of the output data, e.g. computer output printers using printers
    • G06K15/12—Arrangements for producing a permanent visual presentation of the output data, e.g. computer output printers using printers by photographic printing, e.g. by laser printers
    • G06K15/129—Colour printing

Definitions

  • the present invention relates to a light-emitting element head in which plural light-emitting element chips are arrayed, image forming apparatus including a light-emitting element head in which plural light-emitting element chips are arrayed, and a signal supply method.
  • an image is formed on a recording paper sheet as follows. Firstly, an electrostatic latent image is formed on a charged photoconductor by causing an optical recording unit to emit light on the basis of image information. Then, the electrostatic latent image is made visible by being developed with toner. Lastly, the toner image is transferred on and fixed to the recording paper sheet.
  • an optical recording unit in addition to an optical-scanning recording unit that performs exposure by laser scanning in a first scan direction using a laser beam, an optical recording unit using the following light-emitting element head has been employed in recent years.
  • This light-emitting element head includes a large number of light-emitting element chips arrayed in a first scan direction, and each light-emitting element chip includes a light-emitting element array formed of light-emitting elements such as light emitting diodes (LEDs) arrayed in a line.
  • LEDs light emitting diodes
  • Such a light-emitting element head including a large number of light-emitting element chips arrayed thereon requires as many lighting signals as correspond to the number of light-emitting element chips. Accordingly, in the light-emitting element head, the number of lighting signal bus lines increases as the number of light-emitting element chips increases. In addition, the number of current buffer circuits each having a large current drive capability also increases with increase in the number of light-emitting element chips since the lighting signals supply a current to the light-emitting elements.
  • a light-emitting element head including a large number of light-emitting element chips has the following problems: the size of a drive IC of the light-emitting element head increases as the number of light-emitting element chips increases in the light-emitting element head; and the printed circuit board of the light-emitting element head needs to have a larger width in order to allow a large number of low-resistance lighting signal bus lines to be arranged thereon.
  • the width of the printed circuit board may be reduced by employing a multi-layer printed circuit board, which however causes increase in cost.
  • a light-emitting element head including: a set of light-emitting element chips each having plural light-emitting elements; a lighting signal supply unit that supplies the set of light-emitting element chips with a lighting signal for causing the plural light-emitting elements included in each of the light-emitting element chips to emit light; a first control signal supply unit that supplies a first control signal in common to the light-emitting element chips, the first control signal being a signal for sequentially specifying the plural light-emitting elements included in each of the light-emitting element chips one by one as a control target for controlling whether or not to emit light; a second control signal supply unit that supplies second control signals to the set of light-emitting element chips so that each of the second control signals is supplied in common to plural light-emitting element chips belonging to each of N groups, each of the second control signals being a signal for giving an instruction to emit light or not to emit light to one of the light-emitting elements that is
  • FIG. 1 shows an overall configuration of an image forming apparatus to which the first exemplary embodiment is to be applied
  • FIG. 2 shows a structure of the exposure device to which the first exemplary embodiment is applied
  • FIG. 3A is a schematic view for explaining a structure of each light-emitting element chip to which the first exemplary embodiment is applied;
  • FIG. 3B is a schematic view for explaining a configuration of the light-emitting element head in the first exemplary embodiment
  • FIG. 4 is a circuit diagram of the light-emitting element head
  • FIG. 5 is a schematic view of an equivalent circuit and a planar layout of each light-emitting element chip
  • FIG. 6 is a time chart for explaining the operation of one group in each light-emitting element head, by taking, as an example, the group formed of 2 light-emitting element chips;
  • FIG. 7 is a state transition table for explaining the operation of each light-emitting element chip
  • FIG. 8 is a circuit diagram of the light-emitting element head by dividing the light-emitting element chips into groups each formed of 3 light-emitting element chips;
  • FIG. 9 is a time chart for explaining the operation of one group in each light-emitting element head, by taking, as an example, the group formed of 3 light-emitting element chips;
  • FIG. 10 is a schematic view for explaining a configuration of each light-emitting element head in the second exemplary embodiment
  • FIG. 11 is a time chart for explaining the operation of one group in each light-emitting element head in the second exemplary embodiment.
  • FIGS. 12A and 12B each are a circuit diagram for explaining an effect of reducing the number of signal bus lines in the light-emitting element head in the first exemplary embodiment.
  • FIG. 1 shows an overall configuration of an image forming apparatus to which the first exemplary embodiment is to be applied.
  • the image forming apparatus 1 shown in FIG. 1 is generally called a tandem type image forming apparatus.
  • the image forming apparatus 1 includes an image processing system 10 , an image output controller 30 and an image processor 40 .
  • the image processing system 10 forms an image in accordance with different color tone datasets.
  • the image output controller 30 controls the image processing system 10 .
  • the image processor 40 which is connected to devices such as a personal computer (PC) 2 and an image reading apparatus 3 , performs predetermined image processing on image data received from the above devices.
  • PC personal computer
  • the image processing system 10 includes image forming units 11 .
  • the image forming units 11 are formed of multiple engines arranged in parallel at intervals in the horizontal direction. Specifically, the image forming units 11 are composed of four units: a yellow (Y) image forming unit 11 Y, a magenta (M) image forming unit 11 M, a cyan (C) image forming unit 11 C and a black (K) image forming unit 11 K.
  • Each of the image forming units 11 Y, 11 M, 11 C and 11 K includes a photoconductive drum 12 , a charging device 13 , an exposure device 14 and a developing device 15 .
  • On the photoconductive drum 12 as an example of an image carrier, an electrostatic latent image is formed and thus a toner image is formed.
  • the charging device 13 as an example of a charging unit uniformly charges the outer surface of the photoconductive drum 12 .
  • the exposure device 14 as an example of an exposure unit exposes the photoconductive drum 12 charged by the charging device 13 .
  • the developing device 15 as an example of a developing unit develops a latent image formed by the exposure device 14 .
  • the image processing system 10 further includes a paper sheet transport belt 21 , a drive roll 22 , transfer rolls 23 and a fixing device 24 .
  • the paper sheet transport belt 21 transports a recording paper sheet so that color toner images (images) respectively formed on the photoconductive drums 12 of the image forming units 11 Y, 11 M, 11 C and 11 K are transferred on the recording paper sheet by multilayer transfer.
  • the recording paper sheet is an example of a transferred body.
  • the drive roll 22 drives the paper sheet transport belt 21 .
  • Each transfer roll 23 as an example of a transfer unit transfers the toner image formed on the corresponding photoconductive drum 12 onto a recording paper sheet.
  • the fixing device 24 fixes the toner images to the recording paper sheet.
  • FIG. 2 shows a structure of the exposure device 14 to which the first exemplary embodiment is applied.
  • the exposure device 14 includes light-emitting element chips 51 , a printed circuit board 50 and a rod lens array 53 .
  • Each light-emitting element chip 51 includes multiple light-emitting elements arrayed in a line.
  • the printed circuit board 50 supports the light-emitting element chips 51 .
  • a circuit that performs drive control on the light-emitting element chips 51 is mounted on the printed circuit board 50 .
  • the rod lens array 53 focuses a light output emitted by the light-emitting elements onto the photoconductive drum 12 .
  • the printed circuit board 50 and the rod lens array 53 are held by a housing 54 .
  • the light-emitting element chips 51 are arrayed so that as many light-emitting elements as the number of pixels are arrayed in the first scan direction.
  • the light-emitting element chips 51 and the printed circuit board 50 will be collectively referred to as a light-emitting element head 90 .
  • FIG. 3A is a schematic view for explaining a structure of each light-emitting element chip 51 to which the first exemplary embodiment is applied.
  • the light-emitting element chip 51 includes a substrate 105 , a light-emitting thyristor array 102 and terminals 101 a to 101 e .
  • the light-emitting thyristor array 102 is formed of light-emitting thyristors L 1 , L 2 , L 3 , . . . , which are an example of the light-emitting elements.
  • the light-emitting thyristors L 1 , L 2 , L 3 , . . . are arrayed in a line at equal intervals along a longer side of the rectangular substrate 105 .
  • the lighting signal terminal 101 a is supplied with a lighting signal ⁇ I for applying a voltage for causing the light-emitting thyristors L 1 , L 2 , L 3 , to emit light.
  • the first clock signal terminal 101 b is supplied with a first clock signal ⁇ 1 as an example of a first control signal, for sequentially specifying the light-emitting thyristors L 1 , L 2 , L 3 , . . . , as targets for controlling whether or not to emit light.
  • the second clock signal terminal 101 c is supplied with a second clock signal ⁇ 2 as an example of a second control signal, for giving an instruction to emit light or not to emit light to any of the light-emitting thyristors L 1 , L 2 , L 3 , . . . , which is specified as the control target based on the first clock signal ⁇ 1 .
  • the power supply terminal 101 d is supplied with a power supply voltage Vga.
  • the light-emission enable signal terminal 101 e is supplied with a light-emission enable signal En for allowing the light-emitting element chip 51 to receive the instructions to emit light or not to emit light.
  • FIG. 3B is a schematic view for explaining a configuration of the light-emitting element head 90 in the first exemplary embodiment.
  • the light-emitting element head 90 includes: the printed circuit board 50 ; the multiple light-emitting element chips 51 on the printed circuit board 50 ; and a signal generating circuit 110 .
  • the signal generating circuit 110 supplies the multiple light-emitting element chips 51 with signals for controlling light-emitting operations of the light-emitting element chips 51 .
  • FIG. 3B shows, as an example, the light-emitting element head 90 having eight light-emitting element chips 51 (# 1 to # 8 ).
  • the eight light-emitting element chips 51 are arrayed in a zigzag pattern in which each adjacent two of the light-emitting element chips 51 are faced each other so that the light-emitting thyristors L 1 , L 2 , L 3 , . . . , are arrayed in a line with equal intervals in a first scan direction.
  • the light-emitting element head 90 After writing (exposing to form) an image segment corresponding to each line that extends in the first scan direction on the photosensitive drum 12 , the light-emitting element head 90 writes another image segment corresponding to the next line on the photoconductive drum 12 which has rotated in the second scan direction. By repeating the writing operations in this way, the light-emitting element head 90 forms an image on the photoconductive drum 12 .
  • the eight light-emitting element chips 51 are divided into four groups each formed of two chips, as an example. Specifically, the four groups are: an A group of # 1 and # 3 of the light-emitting element chips 51 ; a B group of # 2 and # 4 ; a C group of # 5 and # 7 ; and a D group of # 6 and # 8 . Note that all the light-emitting element chips 51 have the same structure.
  • the signal generating circuit 110 From image signals (not shown in the figure) supplied by the image processor 40 provided in the image forming apparatus 1 , and a synchronizing signal and the like (not shown in the figure) supplied by the image output controller 30 , the signal generating circuit 110 generates the signals for controlling the light-emitting operations of the light-emitting element chips 51 .
  • the signal generating circuit 110 as an example of a first control signal supply unit, generates the first clock signal p 1 for sequentially specifying the light-emitting thyristors L 1 , L 2 , L 3 , . . . , as targets for controlling whether or not to emit light.
  • the signal generating circuit 110 also generates second clock signals ⁇ 2 for setting the light-emitting thyristors L 1 , L 2 , L 3 , . . . , ready to emit light.
  • the signal generating circuit 110 also generates lighting signals ⁇ I for applying a voltage for causing the light-emitting thyristors L 1 , L 2 , L 3 , . . . , to emit light.
  • the signal generating circuit 110 as an example of a light-emission enable signal supply unit, also generates light-emission enable signals En for allowing the light-emitting element chips 51 to receive the instructions to emit light or not to emit light.
  • four second clock signals ⁇ 2 different from each other that is, a 2 — 1-th clock signal ⁇ 2 _ 1 , a 2 — 2-th clock signal ⁇ 2 _ 2 , a 2 — 3-th clock signal ⁇ 2 _ 3 and a 2 — 4-th clock signal ⁇ 2 _ 4 , are used.
  • two lighting signals ⁇ I that is, a first lighting signal ⁇ I 1 and a second lighting signal ⁇ I 2 , are used.
  • FIG. 4 is a circuit diagram of the light-emitting element head 90 shown in FIG. 3B .
  • FIG. 4 schematically shows the connection relation of the eight light-emitting element chips 51 (# 1 to # 8 ) to the signal bus lines, which are shown in FIG. 3B . Note that, the connection relation of the light-emitting element chips 51 to the signal bus lines is maintained in FIG. 4 .
  • the signal generating circuit 110 supplies the first clock signal ⁇ 1 in common to all the light-emitting element chips 51 through a first clock signal bus line 202 .
  • the signal generating circuit 110 supplies the 2 — 1-th clock signal ⁇ 2 _ 1 to # 1 and # 3 of the light-emitting element chips 51 , which belong to the A group, through a 2 — 1-th clock signal bus line 203 .
  • the signal generating circuit 110 supplies the 2 — 2-th clock signal ⁇ 2 _ 2 to # 2 and # 4 of the light-emitting element chips 51 , which belong to the B group, through a 2 — 2-th clock signal bus line 204 .
  • the signal generating circuit 110 supplies the 2 — 3-th clock signal ⁇ 2 _ 3 to # 5 and # 7 of the light-emitting element chips 51 , which belong to the C group, through a 2 — 3-th clock signal bus line 205 .
  • the signal generating circuit 110 supplies the 2 — 4-th clock signal ⁇ 2 _ 4 to # 6 and # 8 of the light-emitting element chips 51 , which belong to the D group, through a 2 — 4-th clock signal bus line 206 .
  • the signal generating circuit 110 supplies one of the second clock signals ⁇ 2 in common to the light-emitting element chips 51 belonging to the same group, while supplying the different second clock signals ⁇ 2 to the light-emitting element chips 51 belonging to the different groups, respectively.
  • the signal generating circuit 110 supplies the first lighting signal ⁇ I 1 to # 1 , # 2 , # 5 and # 6 of the light-emitting element chips 51 , which respectively belong to the A to D groups, through a first lighting signal bus line 200 . Meanwhile, the signal generating circuit 110 supplies the second lighting signal ⁇ I 2 to # 3 , # 4 , # 7 and # 8 of the light-emitting element chips 51 , which respectively belong to the A to D groups, through a second lighting signal bus line 201 .
  • the signal generating circuit 110 supplies the lighting signals ⁇ I, which are different from each other, even to the respective light-emitting element chips 51 belonging to the same group, while supplying one of the lighting signals ⁇ I in common to the light-emitting element chips 51 respectively belonging to the groups different from one another.
  • the signal generating circuit 110 supplies a first light-emission enable signal En 1 to # 1 , # 2 , # 5 and # 6 of the light-emitting element chips 51 , which respectively belong to the A to D groups, through a first light-emission enable signal bus line 207 .
  • the signal generating circuit 110 supplies a second light-emission enable signal En 2 to # 3 , # 4 , # 7 and # 8 of the light-emitting element chips 51 , which respectively belong to the A to D groups, through a second light-emission enable signal bus line 208 .
  • the signal generating circuit 110 supplies the light-emission enable signals En, which are different from each other, even to the respective light-emitting element chips 51 belonging to the same group, while supplying one of the light-emission enable signals En in common to the light-emitting element chips 51 respectively belonging to the groups different from one another.
  • the signal generating circuit 110 supplies the power supply voltage Vga to all the light-emitting element chips 51 through a power supply bus line 209 . Moreover, the signal generating circuit 110 supplies a reference voltage Vsub to all the light-emitting element chips 51 through a reference voltage bus line 210 . Note that the power supply bus line 209 and the reference voltage bus line 210 are not shown in FIG. 4 .
  • the signal generating circuit 110 may be an LSI such as an application specific integrated circuit (ASIC), for example.
  • ASIC application specific integrated circuit
  • FIG. 5 is a schematic view of an equivalent circuit and a planar layout of each light-emitting element chip 51 .
  • the light-emitting element chip 51 includes: the substrate 105 ; the light-emitting thyristor array 102 formed of the light-emitting thyristors L 1 , L 2 , L 3 , . . . , arrayed in a line; a transfer thyristor array 103 formed of transfer thyristors T 1 , T 2 , T 3 , . . . , arrayed in a line; and a light-emission control thyristor array 104 formed of light-emission control thyristors C 1 , C 2 , C 3 , . . . , arrayed in a line.
  • the light-emitting element chip 51 further includes a light-emission enable thyristor Td, a start diode Ds, connecting diodes Dt 1 , Dt 2 , Dt 3 , connecting diodes Dc 1 , Dc 2 , Dc 3 , . . . , and multiple load resistors R.
  • the transfer thyristors T 1 , T 2 , T 3 , . . . are sequentially turned on to specify the light-emitting thyristors L 1 , L 2 , L 3 , . . . , as targets for controlling whether or not to emit light, respectively. Meanwhile, when turned on, each of the light-emission control thyristors C 1 , C 2 , C 3 , . . . , set one of the light-emitting thyristors L 1 , L 2 , L 3 , . . . , which is assigned the same number as that of the light-emission control thyristor, ready to emit light.
  • the light-emission enable thyristor Td controls whether or not to receive the instructions to cause or not to cause the light-emitting thyristors L 1 , L 2 , L 3 , . . . , to emit light.
  • the light-emitting thyristors L 1 , L 2 , L 3 , . . . , the transfer thyristors T 1 , T 2 , T 3 , . . . , the light-emission control thyristors C 1 , C 2 , C 3 , . . . , and the light-emission enable thyristor Td which have a pnpn structure formed of a GaAs-based semiconductor, each are a three-terminal thyristor having an anode electrode, a cathode electrode and a gate electrode.
  • the i-th light-emitting thyristor from the left of FIG. 5 (from the side closer to the terminals 101 a to 101 e ) will be expressed as light-emitting thyristor Li (i is an integer of 1 or more).
  • the transfer thyristors, the light-emission control thyristors and the connecting diodes will be represented in a similar manner.
  • the transfer thyristors Ti and the light-emission control thyristors Ci are alternately arrayed in a line.
  • the light-emitting thyristors Li are arrayed in a line and connected to the respective light-emission control thyristors Ci.
  • the number of light-emitting thyristors Li, the number of transfer thyristors Ti and the number of light-emission control thyristors Ci are the same as one another in the light-emitting element chip 51 .
  • each transfer thyristor Ti is connected to the gate electrode Gci of the light-emission control thyristor Ci adjacent to the transfer thyristor Ti via the corresponding connecting diode Dti.
  • each connecting diode Dti is connected with its orientation set to allow a current to flow from the gate electrode G 1 to the gate electrode Gci.
  • each light-emission control thyristor Ci is connected to the gate electrode G 1 +1 of the transfer thyristor Ti+1 adjacent to the light-emission control thyristor Ci via the corresponding connecting diode Dci.
  • each connecting diode Dci is connected with its orientation set to allow a current to flow from the gate electrode Gci to the gate electrode G 1 +1.
  • the connecting diodes Dti and the connecting diodes Dci are alternately arrayed so as to allow a current to flow in one direction therethrough.
  • the gate electrode Gci of each light-emission control thyristor Ci is connected to the gate electrode Gsi of the corresponding light-emitting thyristor Li via a resistor Rp.
  • the gate electrode G 1 of each transfer thyristor Ti and the gate electrode Gci of each light-emission control thyristor Ci are connected to a power supply line 71 via the respective load resistors R provided corresponding to these thyristors.
  • the power supply line 71 is connected to the power supply terminal 101 d.
  • the cathode electrode of each transfer thyristor Ti is connected to a first clock signal line 72 .
  • the first clock signal line 72 is connected to the first clock signal terminal 101 b via a resistor.
  • each light-emission control thyristor Ci is connected to a second clock signal line 73 .
  • the second clock signal line 73 is connected to the second clock signal terminal 101 c via a resistor.
  • each light-emitting thyristor Li is connected to a lighting signal line 74 .
  • the lighting signal line 74 is connected to the lighting signal terminal 101 a via a load resistor.
  • the cathode electrode of the light-emission enable thyristor Td is connected to the second clock signal line 73 . Meanwhile, the gate electrode Gt of the light-emission enable thyristor Td is connected to a light-emission enable signal line 75 , and is further connected to the light-emission enable signal terminal 101 e via a load resistor.
  • the anode electrode of each of the transfer thyristors Ti, the light-emission control thyristors Ci, the light-emitting thyristors Li and the light-emission enable thyristor Td is connected to a backside common electrode 81 of the substrate 105 .
  • the cathode electrode and the anode electrode of the start diode Ds are connected to the gate electrode G 1 of the transfer thyristor T 1 and the second clock signal line 73 , respectively.
  • the light-emission enable thyristor Td is connected in parallel to the light-emission control thyristors Ci.
  • the cathode electrode of the light-emission enable thyristor Td is connected to the second clock signal line 73 at a position closer to the second clock signal terminal 101 c than any of the light-emission control thyristors Ci is.
  • the lighting signal terminal 101 a , the first clock signal terminal 101 b , the second clock signal terminal 101 c and the light-emission enable signal terminal 101 e are supplied with one of the lighting signals ⁇ I, the first clock signal ⁇ 1 , one of the second clock signals ⁇ 2 and one of the light-emission enable signals En, respectively.
  • the power supply terminal 101 d and the backside common electrode 81 are supplied with the power supply voltage Vga (assumed here to be ⁇ 3.3 V), and the reference voltage Vsub (assumed here to be 0 V), respectively.
  • the light-emitting element head 90 drives the multiple light-emitting element chips 51 in groups as shown in FIGS. 3B and 4 so as to cause the groups different from each other to operate in parallel. Thus, an operation of one group will be firstly described.
  • FIG. 6 is a time chart for explaining the operation of one group in each light-emitting element head 90 , by taking, as an example, the A group formed of # 1 and # 3 of the light-emitting element chips 51 .
  • FIG. 6 illustrates light-emission control of the two light-emitting thyristors L 1 and L 2 among all the light-emitting thyristors L 1 , L 2 , . . . , provided in each of # 1 and # 3 of the light-emitting element chips 51 .
  • periods during which the light-emitting operations of the light-emitting thyristors L 1 , L 2 , . . . in each of # 1 and # 3 of the light-emitting element chips 51 are controlled will be referred to as periods T (L 1 ), T (L 2 ), respectively.
  • a period from a time point b to a time point q and a period from the time point q to a time point x are the periods T(L 1 ) and T(L 2 ), respectively.
  • the first clock signal ⁇ 1 which is supplied in common to all the light-emitting element chips 51 in the light-emitting element head 90 , is supplied in common to # 1 and # 3 of the light-emitting element chips 51 in the A group.
  • the 2 — 1-th clock signal ⁇ 2 _ 1 which is supplied only to the A group, is supplied in common to # 1 and # 3 of the light-emitting element chips 51 in the A group.
  • the first lighting signal ⁇ I 1 and the first light-emission enable signal En 1 are supplied to # 1 of the light-emitting element chips 51 .
  • the second lighting signal ⁇ I 2 and the second light-emission enable signal En 2 are supplied to # 3 of the light-emitting element chips 51 .
  • the light-emitting element chips 51 belonging to the same group are supplied with the respective different lighting signals ⁇ I, while supplied with the respective different light-emission enable signals En.
  • the first clock signal ⁇ 1 is at the low level (L level) during a period from the time point b to a time point o, at the high level (H level) during a period from the time point o to a time point p, and at the L level during a period from the time point p to the time point q.
  • the first lighting signal ⁇ I 1 is at the L level as an example of a second potential difference, during a period from a time point c to a time point l, and at the H level as an example of a first potential difference, during the other periods.
  • the second lighting signal ⁇ I 2 is at the L level during a period from a time point d to a time point m, and at the H level during the other periods.
  • the first lighting signal ⁇ I 1 and the second lighting signal ⁇ I 2 are set to the L level for the same-length period as each other, but transition from the H level to the L level at different timings from each other.
  • first and second lighting signals ⁇ I 1 and ⁇ I 2 transition from the H level to the L level after the first clock signal ⁇ 1 transitions from the H level to the L level
  • first and second lighting signals ⁇ I 1 and ⁇ I 2 transition from the L level to the H level before the first clock signal ⁇ 1 transitions from the L level to the H level.
  • the first light-emission enable signal En 1 is at the L level during a period from a time point e to a time point h, and at the H level during the other periods.
  • the second light-emission enable signal En 2 is at the L level during a period from the time point h to a time point k, and at the H level during the other periods.
  • the period during which the first light-emission enable signal En 1 is at the L level and the period during which the second light-emission enable signal En 2 is at the L level are provided to both lie within the period during which the first clock signal ⁇ 1 is at the L level while being displaced from each other in terms of time.
  • the first light-emission enable signal En 1 and the second light-emission enable signal En 2 which are supplied respectively to # 1 and # 3 of the light-emitting element chips 51 , has different supply timings (timings of supplying the periods of being at the L level) from each other.
  • Each of the first clock signal ⁇ 1 , the first and second light-emission enable signals En 1 and En 2 , and the first and second lighting signals ⁇ I 1 and ⁇ I 2 repeats the cycle of the period T(Li).
  • the 2 — 1-th clock signal ⁇ 2 _ 1 has periods of being at the L level each lying within the period during which any of the light-emission enable signals En (the first light-emission enable signal En 1 or the second light-emission enable signal En 2 ) is at the L level.
  • the 2 — 1-th clock signal ⁇ 2 _ 1 has a period (from a time point f to a time point g) of being at the L level in the period (from the time point e to the time point h) during which the first light-emission enable signal En 1 is at the L level, in the case of causing the light-emitting thyristor L 1 in # 1 of the light-emitting element chips 51 to emit light.
  • the 2 — 1-th clock signal ⁇ 2 _ 1 has a period (from a time point i to a time point j) of being at the L level in the period (from the time point h to the time point k) during which the second light-emission enable signal En 2 is at the L level, in the case of causing the light-emitting thyristor L 1 in # 3 of the light-emitting element chips 51 to emit light.
  • the 2 — 1-th clock signal ⁇ 2 _ 1 has a period (from a time point s to a time point t) of being at the L level in the period during which the first light-emission enable signal En 1 is at the L level, in the case of causing the light-emitting thyristor L 2 in # 1 of the light-emitting element chips 51 to emit light.
  • the 2 — 1-th clock signal ⁇ 2 _ 1 remains set to the H level instead of having a period (from a time point u to a time point v) of being at the L level even in the period during which the second light-emission enable signal En 2 is at the L level, in the case of causing the light-emitting thyristor L 2 in # 3 of the light-emitting element chips 51 not to emit light.
  • the 2 — 1-th clock signal ⁇ 2 _ 1 have at least one period of being at the L level in the case where the corresponding light-emitting thyristor Li of any of # 1 and # 3 of the light-emitting element chips 51 is caused to emit light.
  • the 2 — 1-th clock signal ⁇ 2 _ 1 is set to the L level in a period from a time point n to the time point q regardless of causing any of the light-emitting thyristors L 1 to emit light, as will be described later. In the rest of the periods, the 2 — 1-th clock signal ⁇ 2 _ 1 is at the H level.
  • the time chart in FIG. 6 may be applied to the B group (# 2 and # 4 ) shown in FIGS. 3B and 4 .
  • the first light-emission enable signal En 1 and the first lighting signal ⁇ I 1 which are supplied to # 1 in the A group, are also supplied to # 2 in the B group.
  • the second light-emission enable signal En 2 and the second lighting signal ⁇ I 2 which are supplied to # 3 in the A group, are also supplied to # 4 in the B group.
  • the time chart in FIG. 6 may be applied to the C group (# 5 and # 7 ).
  • the first light-emission enable signal En 1 and the first lighting signal ⁇ I 1 which are supplied in common to # 1 and # 2 in the respective A and B groups, are also supplied to # 5 in the C group.
  • the second light-emission enable signal En 2 and the second lighting signal ⁇ I 2 which are supplied in common to # 3 and # 4 in the respective A and B groups, are also supplied to # 7 in the C group.
  • the time chart in FIG. 6 may be applied to the D group (# 6 and # 8 ).
  • the first light-emission enable signal En 1 and the first lighting signal ⁇ I 1 which are supplied in common to # 1 , # 2 and # 5 in the respective A to C groups, are also supplied to # 6 in the D group.
  • the second light-emission enable signal En 2 and the second lighting signal ⁇ I 2 which are supplied in common to # 3 , # 4 and # 7 in the respective A to C groups, are also supplied to # 8 in the D group.
  • the groups (A to D) in the light-emitting element head 90 operate in parallel.
  • the multiple light-emitting element chips 51 belonging to the same group also operate in parallel as will be described later.
  • all the light-emitting element chips 51 in the light-emitting element head 90 operate in parallel.
  • # 1 of the light-emitting element chips 51 is supplied with the first clock signal ⁇ 1 , the 2 — 1-th clock signal ⁇ 2 _ 1 , the first light-emission enable signal En 1 and the first lighting signal ⁇ I 1 .
  • the first clock signal ⁇ 1 is supplied in common to all the light-emitting element chips 51 .
  • the 2 — 1-th clock signal ⁇ 2 _ 1 is supplied in common to the light-emitting element chips 51 in the A group (# 1 and # 3 ).
  • the first light-emission enable signal En 1 and the first lighting signal ⁇ I 1 are supplied only to # 1 among the light-emitting element chips 51 in the A group.
  • the light-emission enable thyristor Td and the light-emission control thyristors Ci play important roles. Accordingly, overall operations of the light-emission enable thyristor Td and the light-emission control thyristors Ci in each light-emitting element chip 51 will firstly be described with reference to FIG. 5 .
  • the light-emission enable thyristor Td and the light-emission control thyristors Ci are connected in parallel. Specifically, the cathode electrode of the light-emission enable thyristor Td and the cathode electrodes of the light-emission control thyristors Ci are connected to the second clock signal line 73 . Accordingly, what is important here is which one of the light-emission enable thyristor Td and the light-emission control thyristors Ci, gets turns on when the 2 — 1-th clock signal ⁇ 2 _ 1 is supplied.
  • the light-emission enable thyristor Td and the light-emission control thyristors Ci are connected in parallel, and the 2 — 1-th clock signal ⁇ 2 _ 1 is capable of turning on just one of the light-emission enable thyristor Td and the light-emission control thyristors Ci at a time.
  • the potential difference between the anode electrode and the cathode electrode of a thyristor for turning on the thyristor (the potential difference will be hereinafter referred to as ON voltage Von) is expressed by Von ⁇ Vg ⁇ Vd, where Vg denotes the potential of the gate electrode of the thyristor, and Vd denotes a forward threshold voltage of the pn junction.
  • the forward threshold voltage Vd of the pn junction may be considered to be 1.4 V on the basis of the properties of the light-emitting element chip 51 .
  • the light-emission enable thyristor Td is connected to the second clock signal line 73 at a position closer to the second clock signal terminal 101 c than any of the light-emission control thyristors Ci is. Accordingly, the 2 — 1-th clock signal ⁇ 2 _ 1 reaches the light-emission enable thyristor Td before reaching to any of the light-emission control thyristors Ci.
  • the ON voltage Von of the light-emission enable thyristor Td which serves as a threshold value for turning it on, is smaller in absolute value than that of any of the light-emission control thyristors Ci, as will be described later. For these reasons, the light-emission enable thyristor Td may be turned on in response to even a small potential difference in the 2 — 1-th clock signal ⁇ 2 _ 1 .
  • the light-emission enable thyristor Td preferentially gets turned on.
  • the potential of the cathode electrode of the light-emission enable thyristor Td drops to the forward threshold voltage Vd ( ⁇ 1.4 V) of the pn junction.
  • the second clock signal line 73 to which the cathode electrode of the light-emission enable thyristor Td is connected, is fixed at ⁇ 1.4 V.
  • the light-emission control thyristors Ci are not allowed to be turned on, and thus remain turned off since the ON voltage Von thereof is larger in absolute value than ⁇ 1.4 V.
  • the light-emission enable thyristor Td fixes the second clock signal line 73 at ⁇ 1.4 V, and thus functions to prevent, as long as being turned on, the light-emission control thyristors Ci from being turned on.
  • the light-emission enable thyristor Td does not fix the second clock signal line 73 at any voltage, so that its function preventing the light-emission control thyristors Ci from being turned on is disabled.
  • # 1 of the light-emitting element chips 51 will be described in order of time based on the time points shown in FIG. 6 . Assume here that time flows from the time point a to the time point x in alphabetical order.
  • the transfer thyristors Ti, the light-emission control thyristors Ci, the light-emitting thyristors Li and the light-emission enable thyristor Td are all turned off.
  • the first clock signal p 1 and the 2 — 1-th clock signal ⁇ 2 _ 1 are set to the H level.
  • the first lighting signal ⁇ I 1 and the first light-emission enable signal En 1 are also set to the H level.
  • the start diode Ds is forward biased, so that the potential of the gate electrode G 1 of the transfer thyristor T 1 takes a value obtained by subtracting, from the H level (0 V), the forward threshold voltage Vd (diffusion potential) of the pn junction of the start diode Ds.
  • the ON voltage Von of the light-emission control thyristor C 1 is ⁇ 4.2 V.
  • the potential of the gate electrode Gt of the light-emission enable thyristor Td is 0 V since the first light-emission enable signal En 1 is set to the H level. Accordingly, in the initial state, the ON voltage Von of the light-emission enable thyristor Td is ⁇ 1.4 V.
  • the potential of the gate electrode G 1 rises from ⁇ 1.4 V to approximately the H level of 0 V.
  • the effect of this potential rise is transmitted to the gate electrode Gc 1 through the connecting diode Dt 1 that gets forward biased.
  • the potential of the gate electrode Gc 1 rises from ⁇ 2.8 V to ⁇ 1.4 V, and thus the ON voltage Von of the light-emission control thyristor C 1 rises from ⁇ 4.2 V to ⁇ 2.8 V.
  • the potential of the gate electrode Gs 1 of the light-emitting thyristor L 1 becomes a voltage based on both the forward threshold voltage Vd of the pn junction in the connecting diode Dt 1 and a voltage drop ( ⁇ ) caused by the corresponding resistor Rp, that is, becomes ⁇ Vd+ ⁇ . Accordingly, the potential of the gate electrode Gs 1 of the light-emitting thyristor L 1 rises from ⁇ 3.3 V to ⁇ 2.2 V, and thus the ON voltage Von of the light-emitting thyristor L 1 rises from ⁇ 4.7 V to ⁇ 3.6 V, since ⁇ may be considered to be ⁇ 0.8 V based on the properties of the light-emitting element chip 51 .
  • the first lighting signal ⁇ I 1 transitions from the H level to the L level ( ⁇ 3.3 V).
  • the potential of the cathode electrode becomes lower than that of the anode electrode, namely, becomes ⁇ 3.3 V.
  • none of the light-emitting thyristors Li is turned on to emit light since the ON voltage Von of the light-emitting thyristor L 1 is ⁇ 3.6 V and the ON voltage Von of the light-emitting thyristors L 2 , L 3 , . . . , is ⁇ 4.7 V.
  • the first light-emission enable signal En 1 is set to the L level of ⁇ 3.3 V.
  • the ON voltage Von of the light-emission enable thyristor Td drops from ⁇ 1.4 V to ⁇ 4.7 V.
  • the 2 — 1-th clock signal ⁇ 2 _ 1 transitions to the L level.
  • the light-emission enable thyristor Td is not allowed to be turned on since its ON voltage Von is ⁇ 4.7 V.
  • the potential of the second clock signal line 73 changes in accordance with the 2 — 1-th clock signal ⁇ 2 _ 1 , thus becoming the L level ( ⁇ 3.3 V), which is lower than the ON voltage Von ( ⁇ 2.8 V) of the light-emission control thyristor C 1 but higher than the ON voltage Von ( ⁇ 4.7 V) of the other light-emission control thyristors C 2 , C 3 , . . . .
  • the light-emission control thyristor C 1 gets turned on at the time point f.
  • the potential of the gate electrode Gc 1 rises to approximately the H level (0 V).
  • the ON voltage Von of the light-emitting thyristor L 1 rises from ⁇ 3.6 V to ⁇ 2.2 V.
  • the first lighting signal ⁇ I 1 remains set to the L level ( ⁇ 3.3 V).
  • the first lighting signal ⁇ I 1 remains set to the L level ( ⁇ 3.3 V).
  • the potential of the gate electrode Gc 1 rises to approximately the H level of 0 V
  • the effect of this potential rise is transmitted to the gate electrode G 2 through the connecting diode Dc 1 that gets forward biased.
  • the potential of the gate electrode G 2 rises from ⁇ 2.8 V to ⁇ 1.4 V, and thus the ON voltage Von of the transfer thyristor T 2 rises from ⁇ 4.2 V to ⁇ 2.8 V.
  • the 2 — 1-th clock signal ⁇ 2 _ 1 transitions to the H level.
  • This causes the cathode electrode and the anode electrode of the light-emission control thyristor C 1 to have approximately the same potential as each other, so that the light-emission control thyristor C 1 gets turned off. Accordingly, the potential of the gate electrode Gc 1 drops back from 0 V to ⁇ 1.4 V, which further causes the ON voltage Von of the transfer thyristor T 2 to drop back from ⁇ 2.8 V to ⁇ 4.2 V.
  • the first lighting signal ⁇ I 1 set to the L level ( ⁇ 3.3 V) keeps the light-emitting thyristor L 1 turned on. In other words, even if the light-emission control thyristor C 1 gets turned off at the time point g, the light-emitting thyristor L 1 is kept turned on, and thus continues to emit light.
  • the first light-emission enable signal En 1 transitions to the H level.
  • the potential of the gate electrode Gt of the light-emission enable thyristor Td rises from ⁇ 3.3 V to 0 V, and thus the ON voltage Von of the light-emission enable thyristor Td rises from ⁇ 4.7 V to ⁇ 1.4 V.
  • the 2 — 1-th clock signal ⁇ 2 _ 1 transitions to the L level ( ⁇ 3.3 V).
  • This turns on not the light-emission control thyristor C 1 whose ON voltage Von is ⁇ 2.8 V but the light-emission enable thyristor Td whose ON voltage Von is ⁇ 1.4 V, as described above. Accordingly, the potential of the second clock signal line 73 is immediately caused to be fixed at ⁇ 1.4 V.
  • the light-emission control thyristor C 1 is not allowed to be turned on under that condition, and thus remains turned off.
  • the light-emitting thyristor L 1 still continues to emit light since the first lighting signal ⁇ I 1 set to the L level ( ⁇ 3.3 V) keeps the light-emitting thyristor L 1 turned on.
  • the 2 — 1-th clock signal ⁇ 2 _ 1 transitions to the H level.
  • the potential of the cathode electrode of the light-emission enable thyristor Td becomes the H level, which is the same as the potential of its anode electrode. Accordingly, the light-emission enable thyristor Td is no longer kept turned on, and thus gets turned off.
  • the light-emission control thyristor C 1 is also kept turned off since the 2 — 1-th clock signal ⁇ 2 _ 1 is at the H level (0 V).
  • the light-emitting thyristor L 1 still continues to emit light since the first lighting signal ⁇ I 1 set to the L level keeps the light-emitting thyristor L 1 turned on, as described above.
  • the first lighting signal ⁇ I 1 transitions from the L level to the H level. This causes the cathode electrode and the anode electrode of the light-emitting thyristor L 1 to have approximately the same potential as each other. As a result, the light-emitting thyristor L 1 is no longer kept turned on, and gets turned off. Thus, the light-emitting thyristor L 1 stops emitting light.
  • the following periods need to be repeated: a period during which the transfer thyristor Ti alone is turned on; a period during which the transfer thyristor Ti and the light-emission control thyristor Ci adjacent thereto are both turned on; a period during which the light-emission control thyristor Ci alone is turned on; a period during which the light-emission control thyristor Ci and the transfer thyristor Ti+1 adjacent thereto are both turned on; and a period during which the transfer thyristor Ti+1 alone is turned on.
  • the transfer thyristor T 1 is turned on, but the light-emission control thyristor C 1 remains turned off after the time point g.
  • the 2 — 1-th clock signal ⁇ 2 _ 1 is set to the L level, and thus the light-emission control thyristor C 1 gets turned on again.
  • the transfer thyristor T 1 and the light-emission control thyristor C 1 are both turned on.
  • the potential of the gate electrode G 2 rises from ⁇ 2.8 V to ⁇ 1.4 V, and thus the ON voltage Von of the transfer thyristor T 2 rises from ⁇ 4.2 V to ⁇ 2.8 V.
  • the first clock signal ⁇ 1 transitions to the H level, and thus the transfer thyristor T 1 gets turned off. Meanwhile, the light-emission control thyristor C 1 is kept turned on.
  • the first clock signal ⁇ 1 transitions to the L level, and thus the transfer thyristor T 2 gets turned on.
  • the light-emission control thyristor C 1 and the transfer thyristor T 2 are both turned on.
  • the 2 — 1-th clock signal ⁇ 2 _ 1 transitions to the H level, and thus the light-emission control thyristor C 1 gets turned off. Meanwhile the transfer thyristor T 2 is kept turned on.
  • the first lighting signal ⁇ I 1 is at the H level, so that none of the light-emitting thyristors Li emits light.
  • the period from the time point n to the time point q serves as a transition period from the period during which the transfer thyristor T 1 is turned on to the period during which the transfer thyristor T 2 is turned on.
  • the period T(L 1 ) for controlling the light-emitting operation of the light-emitting thyristor L 1 ends and the period T(L 2 ) for controlling the light-emitting operation of the light-emitting thyristor L 2 starts instead.
  • each second clock signal ⁇ 2 works with the first clock signal ⁇ 1 to perform a role of sequentially specifying the light-emitting thyristors L 1 , L 2 , L 3 , . . . , as targets for controlling whether or not to emit light.
  • the second clock signal ⁇ 2 is an example of the first control signal, as well as an example of the second control signal.
  • the period T(L 2 ) will be described not in detail but briefly since operations in the period T(L 2 ) may be achieved simply by repeating those in the period T(LI) except for those regarding the 2 — 1-th clock signal ⁇ 2 _ 1 .
  • the light-emitting thyristor L 2 gets turned on, and thus starts emitting light, like the light-emitting thyristor L 1 at the time point f.
  • the light-emitting thyristor L 2 gets turned off, and thus stops emitting light.
  • each period T(Li) it is only the corresponding one of the transfer thyristors Ti that is allowed to be turned on in the transfer thyristor array 103 .
  • the light-emission control thyristor C 1 is not allowed to be turned on even if the 2 — 1-th clock signal ⁇ 2 _ 1 transitions to the L level ( ⁇ 3.3 V).
  • the light-emitting thyristor L 1 is not allowed to be turned on and thus emits no light even if the first lighting signal ⁇ I 1 transitions to the L level.
  • control is performed such that, while the first clock signal ⁇ 1 set to the L level keeps one of the transfer thyristors Ti turned on, the second clock signal ⁇ 2 repeats transitions between the H level and the L level, and thus causes the corresponding light-emission control thyristor Ci to repeat transitions between on and off.
  • any of the transfer thyristors Ti is kept turned on at a timing when the light-emission control thyristor Ci transitions between an on state and an off state. This ensures that the position of the light-emitting thyristor Li set as a light-emission control target is not lost.
  • the transfer thyristors Ti function to hold position information of the light-emitting thyristors Li.
  • the ON voltage Von of the corresponding light-emitting thyristor Li rises.
  • the first lighting signal ⁇ I 1 is the L level
  • the potential difference between the anode electrode and the cathode electrode of the light-emitting thyristor Li is lower than its ON voltage Von, so that the light-emitting thyristor Li starts emitting light.
  • the potential difference between the anode electrode and the cathode electrode of the light-emitting thyristor Li is not lower than its ON voltage Von, so that the light-emitting thyristor Li continues to emit no light.
  • the light-emission control thyristor Ci functions to set the corresponding light-emitting thyristor Li ready to emit light.
  • the subsequent process in the period T(L 3 ) or later may be achieved simply by repeating the operations performed at and after the time point b.
  • # 3 of the light-emitting element chips 51 which belongs to the A group, will be described.
  • # 3 of the light-emitting element chips 51 operates parallel to # 1 of the light-emitting element chips 51 .
  • # 3 of the light-emitting element chips 51 is supplied with the first clock signal ⁇ 1 , the 2 — 1-th clock signal ⁇ 2 _ 1 , the second light-emission enable signal En 2 and the second lighting signal ⁇ I 2 .
  • the first clock signal ⁇ 1 is supplied in common to all the light-emitting element chips 51 .
  • the 2 — 1-th clock signal ⁇ 2 _ 1 is supplied in common to # 1 and # 3 in the A group.
  • the second light-emission enable signal En 2 and the second lighting signal ⁇ I 2 are supplied only to # 3 among the light-emitting element chips 51 in the A group.
  • # 3 of the light-emitting element chips 51 will be described in order of time based on the time points shown in FIG. 6 .
  • a description similar to that for # 1 of the light-emitting element chips 51 will be omitted.
  • the initial state (just before the time point a) of # 3 of the light-emitting element chips 51 is the same as that of # 1 .
  • the ON voltage Von of the light-emission enable thyristor Td is ⁇ 1.4 V.
  • the second lighting signal ⁇ I 2 transitions from the H level to the L level ( ⁇ 3.3 V).
  • the potential of the cathode electrode becomes lower than that of the anode electrode, namely, becomes ⁇ 3.3 V.
  • the 2 — 1-th clock signal ⁇ 2 _ 1 transitions to the L level ( ⁇ 3.3 V).
  • the light-emission enable thyristor Td which is connected in parallel to the light-emission control thyristors Ci, gets turned on since its ON voltage Von is ⁇ 1.4 V.
  • the potential of the cathode electrode of the light-emission enable thyristor Td drops from 0 V to ⁇ 1.4 V, which causes the potential of the second clock signal line 73 , to which the cathode electrode of the light-emission enable thyristor Td is connected, to immediately rise from ⁇ 3.3 V to ⁇ 1.4 V and be fixed at ⁇ 1.4 V.
  • the light-emission control thyristor C 1 remains turned off, and no change occurs in the ON voltage Von of any of the light-emitting thyristors Li, which thus emits no light.
  • the 2 — 1-th clock signal ⁇ 2 _ 1 transitions to the H level. This causes the cathode electrode and the anode electrode of the light-emission enable thyristor Td to have approximately the same potential as each other. As a result, the light-emission enable thyristor Td is no longer kept turned on, and thus gets turned off. Note that, at the time point g, the light-emission control thyristor C 1 is kept turned off since the 2 — 1-th clock signal ⁇ 2 _ 1 is at the H level.
  • the second light-emission enable signal En 2 is set to the L level of ⁇ 3.3V.
  • the ON voltage Von of the light-emission enable thyristor Td drops from ⁇ 1.4 V to ⁇ 4.7 V.
  • the 2 — 1-th clock signal ⁇ 2 _ 1 transitions to the L level.
  • the light-emission enable thyristor Td is not allowed to be turned on since its ON voltage Von is ⁇ 4.7 V.
  • the potential of the second clock signal line 73 changes in accordance with the 2 — 1-th clock signal ⁇ 2 _ 1 , thus becoming the L level ( ⁇ 3.3 V).
  • the light-emission control thyristor C 1 gets turned on at the time point i.
  • the ON voltage Von of the light-emitting thyristor L 1 rises from ⁇ 3.6 V to ⁇ 2.2 V. Meanwhile, the ON voltage Von of the light-emitting thyristors L 2 , L 3 , . . . , remains ⁇ 4.7 V. In addition, at the time point i, the second lighting signal ⁇ I 2 remains set to the L level ( ⁇ 3.3 V). Thus, among the light-emitting thyristors Li of the light-emitting thyristor array 102 , only the light-emitting thyristor L 1 gets turned on, and thus starts emitting light.
  • the second lighting signal ⁇ I 2 transitions from the L level to the H level. This causes the cathode electrode and the anode electrode of the light-emitting thyristor L 1 to have approximately the same potential as each other. As a result, the light-emitting thyristor L 1 is no longer kept turned on, and thus gets turned off to stop emitting light.
  • the 2 — 1-th clock signal ⁇ 2 _ 1 is not set to the L level. Accordingly, the light-emitting thyristor L 2 of # 3 of the light-emitting element chips 51 is not turned on, and thus emits no light.
  • the subsequent process in the period T(L 3 ) or later may be achieved simply by repeating the operations performed at and after the time point b.
  • # 1 and # 3 of the light-emitting element chips 51 will be collectively considered.
  • the light-emitting thyristors L 1 respectively of # 1 and # 3 of the light-emitting element chips 51 are caused to emit light in parallel.
  • the light-emitting thyristor L 2 of # 1 of the light-emitting element chips 51 is caused to emit light while the light-emitting thyristor L 2 of # 3 of the light-emitting element chips 51 is caused to emit no light.
  • one of the light-emitting thyristors Li gets turned on to start emitting light by performing the following operations: firstly setting the first clock signal ⁇ 1 to the L level to turn on the corresponding transfer thyristor Ti, and then setting the corresponding lighting signal ⁇ I to the L level; and secondly, setting the corresponding second clock signal ⁇ 2 to the L level to turn on the light-emission control thyristor Ci in the period during which the corresponding light-emission enable signal En is at the L level.
  • the light-emitting thyristor Li may be caused to continue to emit no light by keeping the second clock signal ⁇ 2 at the H level in the period during which the light-emission enable signal En is at the L level.
  • the light-emitting thyristor Li is controlled whether or not to emit light.
  • the difference between # 1 and # 3 of the light-emitting element chips 51 is in that each period during which the first light-emission enable signal En 1 is at the L level is provided to be displaced from the corresponding period during which the second light-emission enable signal En 2 is at the L level in terms of time.
  • each second clock signal ⁇ 2 is a data sequence in which the periods of being either at the L level or the H level are provided in time-series order in accordance with instruction datasets to emit light or not to emit light for the multiple light-emitting element chips 51 belonging to the same group. For example, suppose the case of causing both the light-emitting thyristors L 1 respectively of # 1 and # 3 of the light-emitting element chips 51 to emit light in the period T(L 1 ) for controlling the light-emitting operation of the light-emitting thyristors L 1 of # 1 and # 3 .
  • the 2 — 1-th clock signal ⁇ 2 _ 1 is provided with periods of being at the L level respectively in the period during which the first light-emission enable signal En 1 is at the L level, and in the period during which the second light-emission enable signal En 2 is at the L level.
  • the light-emitting thyristor L 1 of # 1 of the light-emitting element chips 51 to emit light while causing the light-emitting thyristor L 1 of # 3 of the light-emitting element chips 51 not to emit light.
  • the 2 — 1-th clock signal ⁇ 2 _ 1 is provided with a period of being at the L level in the period during which the first light-emission enable signal En 1 is at the L level, but the 2 — 1-th clock signal ⁇ 2 _ 1 remains set to the H level even in the period during which the second light-emission enable signal En 2 is at the L level. Still alternatively, suppose the case of causing the light-emitting thyristor L 1 of # 1 of the light-emitting element chips 51 not to emit light while causing the light-emitting thyristor L 1 of # 3 of the light-emitting element chips 51 to emit light.
  • the 2 — 1-th clock signal ⁇ 2 _ 1 remains set to the H level even in the period during which the first light-emission enable signal En 1 is at the L level, but the 2 — 1-th clock signal ⁇ 2 _ 1 is provided with a period of being at the L level in the period during which the second light-emission enable signal En 2 is at the L level. Still alternatively, suppose the case of causing both the light-emitting thyristors L 1 respectively of # 1 and # 3 of the light-emitting element chips 51 not to emit light.
  • the 2 — 1-th clock signal ⁇ 2 _ 1 remains at the H level even in the period during which the first light-emission enable signal En 1 is at the L level, as well as even in the period during which the second light-emission enable signal En 2 is at the L level.
  • each second clock signal ⁇ 2 is provided in time-series order with timings (time points of becoming the L level) each for giving an instruction to emit light or not to emit light to one of the light-emitting thyristors Li that is specified on the basis of the first clock signal ⁇ 1 .
  • each of the multiple light-emitting element chips 51 belonging to the same group to receive, from the second clock signal ⁇ 2 which is a data sequence, instruction datasets to emit light or not to emit light prepared for the chip in the respective periods during which the light-emission enable signal En supplied to the chip is at the L level.
  • the light-emitting thyristors Li in each of the light-emitting element chips 51 are caused to emit light or not to emit light.
  • each light-emitting element chip 51 receives none of instruction datasets to emit light or not to emit light prepared for the other one of the light-emitting element chips 51 belonging to the same group by setting the light-emission enable signal En supplied to itself to the H level.
  • each light-emission enable signal En functions as windows for allowing the corresponding one of the multiple light-emitting element chips 51 belonging to the same group to receive only the image datasets for the chip from a data sequence of the second clock signal ⁇ 2 that gives instructions to emit light or not to emit light to those multiple light-emitting element chips 51 in the same group.
  • a light-emitting thyristor Li starts emitting light in response to the transition to the L level of the corresponding second clock signal ⁇ 2 for giving instructions to emit light or not to emit light.
  • the light-emitting thyristor Li which has emitted light, stops emitting light in response to the transition to the H level of the corresponding lighting signal ⁇ I.
  • each second clock signal ⁇ 2 functions as a trigger for light-emission of the corresponding light-emitting thyristors Li.
  • This allows parallel control of light-emitting operations of the light-emitting thyristors Li assigned the same number of all the light-emitting element chips 51 belonging to the same group in the corresponding period T(Li).
  • the light-emitting operations of the light-emitting thyristors Li of all the light-emitting element chips 51 belonging to the same group may be controlled in numerical order while the light-emitting thyristors Li assigned the same number are controlled in parallel.
  • all the groups in the light-emitting element head 90 also operate in parallel, as has been described above. Accordingly, the groups in the light-emitting element head 90 are controlled such that the light-emitting thyristors Li assigned the same number of all the light-emitting element chips 51 in the light-emitting element head 90 operate in parallel. This allows the light-emitting element head 90 to provide a high light-emission duty.
  • each of the periods during which one of the light-emission enable signals En is at the L level needs only to be provided in a manner of allowing selective receipt of a period during which either of the second clock signals p 2 being data sequences is at the L level.
  • each of the periods during which one of the light-emission enable signals En is at the L level needs only to be provided so as to allow receipt of a timing when the second clock signal ⁇ 2 transitions from the H level to the L level.
  • the first exemplary embodiment when one of the second clock signals ⁇ 2 becomes the L level while one of the light-emission enable signals En is at the L level, in the corresponding light-emitting element chip 51 , one of the light-emission control thyristors Ci gets turned on, which causes the corresponding light-emitting thyristor Li to be turned on to start emitting light. This is because, once turned on, each light-emitting thyristor Li is made to continue to emit light by the corresponding lighting signal ⁇ I.
  • a period of being at the L level provided in one of the light-emission enable signals En respectively for the multiple light-emitting element chips 51 belonging to the same group may partially be set to overlap those of the other light-emission enable signals En. Moreover, such a period may be set shorter than a period during which the second clock signal ⁇ 2 is at the L level.
  • the lighting signals ⁇ I are configured to allow the light-emitting thyristors Li to have the same-length light-emitting period.
  • the lighting signals ⁇ I are configured such that the light-emitting period of the light-emitting thyristor L 1 of # 1 of the light-emitting element chips 51 has the same length as the light-emitting period of the light-emitting thyristor L 1 of # 3 .
  • the former light-emitting period is a period from the time point f when the 2 — 1-th clock signal ⁇ 2 _ 1 transitions from the H level to the L level, to the time point 1 when the first lighting signal ⁇ I 1 transitions from the L level to the H level.
  • the latter light-emitting period is a period from the time point i when the 2 — 1-th clock signal ⁇ 2 _ 1 transitions from the H level to the L level, to the time point m when the second lighting signal ⁇ I 2 transitions from the L level to the H level.
  • each second clock signal ⁇ 2 is formed of instruction datasets to emit light or not to emit light arranged in time-series order. Accordingly, in order to allow those light-emitting thyristors Li to have the same-length light-emitting period, the light-emitting element chips 51 in the same group are respectively provided with the different lighting signals ⁇ I, which specify timings of stopping emitting light in accordance with displacement between the time points of starting emitting light.
  • FIG. 7 is a state transition table for explaining the operation of each light-emitting element chip 51 . Note that FIG. 7 shows state transitions after the transfer thyristor Ti gets turned on in response to the transition to the L level of the first clock signal p 1 .
  • the light-emission enable thyristor Td does not get turned on.
  • the corresponding second clock signal ⁇ 2 transitions from the H level to the L level under this condition.
  • the light-emitting thyristor Li gets turned on to start emitting light (the time points f and respectively for # 1 and # 3 in FIG. 6 , for example), and, if the light-emitting thyristor Li is turned on, it is kept turned on.
  • the light-emission enable thyristor Td gets turned on. In this case, however, if the light-emitting thyristor Li is emitting light, it continues to emit light (the time point i for # 1 ), and, if the light-emitting thyristor Li is emitting no light, it continues to emit no light (the time point f for # 3 ).
  • the second clock signal ⁇ 2 then transitions from the L level to the H level under the condition where the lighting signal ⁇ I and the light-emission enable signal En are respectively set to the L level and the H level, the light-emission enable thyristor Td gets turned off.
  • the light-emitting thyristor Li is emitting light, it continues to emit light (the time point j for # 1 ), and, if the light-emitting thyristor Li is emitting no light, it continues to emit no light (the time point g for # 3 ).
  • FIG. 8 is a circuit diagram of the light-emitting element head 90 by dividing the light-emitting element chips 51 into groups each formed of 3 chips (# 1 , # 3 and # 5 in FIG. 3B , for example).
  • FIG. 8 shows an example in which the light-emitting element head 90 has twelve light-emitting element chips 51 (# 1 to # 12 ), which are divided into four groups (A to D) each formed of 3 chips.
  • FIG. 8 shows the light-emitting element chips 51 rearranged in a matrix with the connection relation of the light-emitting element chips 51 to the signal bus lines maintained. Note that the power supply bus line 209 and the reference voltage bus line 210 are not shown in FIG. 8 .
  • the light-emitting element chips 51 may be arrayed in a zigzag pattern, though FIG. 8 shows otherwise, and the signal bus lines may be provided on the basis of the connection relation shown in FIG. 8 .
  • four second clock signals ⁇ 2 (the 2 — 1-th clock signal ⁇ 2 _ 1 , the 2-2-th clock signal ⁇ 2 _ 2 , the 2 — 3-th clock signal ⁇ 2 _ 3 and the 2 — 4-th clock signal ⁇ 2 _ 4 ), each of which is supplied in common to the light-emitting element chips 51 belonging to the same group, are used.
  • three light-emission enable signals En (the first light-emission enable signal En 1 , the second light-emission enable signal En 2 and a third light-emission enable signal En 3 ) and three lighting signals ⁇ I (the first lighting signal ⁇ I 1 , the second lighting signal ⁇ I 2 and a third lighting signal ⁇ I 3 ) are used.
  • the light-emitting element chips 51 belonging to the same group are supplied respectively with the different light-emission enable signals En while supplied respectively with the different lighting signals ⁇ I.
  • the first clock signal ⁇ 1 is supplied in common to all the light-emitting element chips 51 in the light-emitting element head 90 .
  • the 2 — 1-th clock signal ⁇ 2 _ 1 is supplied in common to the light-emitting element chips 51 belonging to the A group (# 1 , # 3 and # 5 ).
  • the 2 — 2-th clock signal ⁇ 2 _ 2 is supplied in common to the light-emitting element chips 51 belonging to the B group (# 2 , # 4 and # 6 ).
  • the 2 — 3-th clock signal ⁇ 2 _ 3 is supplied in common to the light-emitting element chips 51 belonging to the C group (# 7 , # 9 and # 11 ), and the 2 — 4-th clock signal ⁇ 2 _ 4 is supplied in common to the light-emitting element chips 51 belonging to the D group (# 8 , # 10 and # 12 ).
  • the first lighting signal ⁇ I 1 and the first light-emission enable signal En 1 are supplied in common to # 1 , # 2 , # 7 and # 8 , which respectively belong to the different groups.
  • the second lighting signal ⁇ I 2 and the second light-emission enable signal En 2 are supplied in common to # 3 , # 4 , # 9 and # 10 , which respectively belong to the different groups, while the third lighting signal ⁇ I 3 and the third light-emission enable signal En 3 are supplied in common to # 5 , # 6 , # 11 and # 12 , which respectively belong to the different groups.
  • FIG. 9 is a time chart for explaining the operation of one group in each light-emitting element head 90 , by taking, as an example, the A group formed of # 1 , # 3 and # 5 of the light-emitting element chips 51 .
  • FIG. 9 illustrates light-emission control of the two light-emitting thyristors L 1 and L 2 among all the light-emitting thyristors L 1 , L 2 , . . . , provided in each of # 1 , # 3 and # 5 of the light-emitting element chips 51 .
  • Each of the first to third lighting signals ⁇ I 1 to ⁇ I 3 is configured to have a period of being at the L level in each period during which the first clock signal ⁇ 1 is at the L level. Moreover, each of the first to third light-emission enable signals En 1 to En 3 has periods of being at the L level in the respective periods during which the corresponding one of the first to third lighting signals ⁇ I 1 to ⁇ I 3 is at the L level.
  • T(Li) the periods during which the first to third light-emission enable signals En 1 to En 3 are at the L level are provided to be displaced from one another in terms of time.
  • the 2 — 1-th clock signal ⁇ 2 _ 1 is a data sequence formed of datasets each indicated by a period of being either at the H level or at the L level, and the datasets are provided to give instructions to emit light or not to emit light to the respective light-emitting thyristors Li of # 1 , # 3 and # 5 of the light-emitting element chips 51 .
  • FIG. 9 The detailed operations shown in FIG. 9 are basically the same as that described with reference to FIG. 6 , and thus will not be described.
  • the whole light-emitting element head 90 it is only necessary to use the different second clock signals ⁇ 2 (the 2 — 2-th to 2 — 4-th clock signals ⁇ 2 _ 2 to ⁇ 2 _ 4 ) respectively for the B to D groups, which are different from one another, while using the same lighting signals ⁇ I (the first to third lighting signals ⁇ I 1 to ⁇ I 3 ) and the same light-emission enable signals En (the first to third light-emission enable signals En 1 to En 3 ) for each of those different groups, as has been described above.
  • the light-emitting element chips 51 may be divided into groups each formed of four or more chips, and any number of groups may be employed.
  • FIG. 10 is a schematic view for explaining a configuration of each light-emitting element head 90 in the second exemplary embodiment.
  • FIG. 10 shows the light-emitting element head 90 having eight light-emitting element chips 51 (# 1 to # 8 ), which are divided into four groups (A to D) each formed of two chips, as an example.
  • the second exemplary embodiment is different from the first exemplary embodiment shown in FIG. 3B in that a single lighting signal ⁇ I is used in common in place of the first and second lighting signals ⁇ I 1 and ⁇ I 2 .
  • the lighting signal ⁇ I is supplied in common to all the light-emitting element chips 51 through the first lighting signal bus line 200 .
  • FIG. 11 is a time chart for explaining the operation of one group in each light-emitting element head 90 shown in FIG. 10 , by taking, as an example, the light-emitting element chips 51 (# 1 and # 3 ) belonging to the A group.
  • the time chart according to the second exemplary embodiment shown in FIG. 11 is different from that according to the first exemplary embodiment shown in FIG. 6 in that the lighting signal ⁇ I is supplied in common to all the light-emitting element chips 51 .
  • the light-emitting thyristors L 1 respectively of # 1 and # 3 of the light-emitting element chips 51 simultaneously stop emitting light at the time point l when the lighting signal ⁇ I transitions from the L level to the H level.
  • the light-emitting period (the period from the time point f to the time point l) of the light-emitting thyristor L 1 of # 1 differs in length from the light-emitting period (a period from the time point i to the time point 1 ) of the light-emitting thyristor L 1 of # 3 . More specifically, the light-emitting period of the light-emitting thyristor L 1 of # 1 is longer than that of the light-emitting thyristor L 1 of # 3 .
  • the periods during which the first and second light-emission enable signals En 1 and En 2 are at the L level, respectively are provided in the reverse order of that employed in the period T(L 1 ).
  • the periods during which the first and second light-emission enable signals En 1 and En 2 are at the L level, respectively are provided in this order, that is, in order according to the numbers assigned to the light-emitting element chips 51 (# 1 and # 3 ), in terms of time.
  • the periods during which the second and first light-emission enable signals En 2 and En 1 are at the L level, respectively, are provided in this order, that is, in the reverse numerical order.
  • the light-emitting period of the light-emitting thyristor L 2 of # 3 of the light-emitting element chips 51 is longer than that of the light-emitting thyristor L 2 of # 1 .
  • quality deterioration of the image to be formed may be prevented through equalization of average adjacent light-emitting lengths each obtained by averaging the light-emitting periods between two lines that are adjacent in the second scan direction shown in FIG. 10 .
  • This equalization is achieved by alternately repeating writing corresponding to two types of lines: one is obtained by providing the periods during which the light-emission enable signals En are at the L level, respectively, in order according to the numbers assigned to the light-emitting element chips 51 ; the other is obtained by providing the periods during which the light-emission enable signals En are at the L level, respectively, in the reverse numerical order.
  • the former measure of equalization in the first scan direction may be combined with the latter one in the second scan direction.
  • Each of the above measures is applicable to the light-emitting element head 90 shown in FIGS. 8 and 9 that includes three light-emitting element chips 51 in each group.
  • FIGS. 12A and 12B each are a circuit diagram for explaining an effect of reducing the number of signal bus lines in the light-emitting element head 90 in the first exemplary embodiment.
  • M ⁇ N light-emitting element chips 51 are arrayed, where M and N each are an integer of 1 or more.
  • FIG. 12A shows the case of driving the M ⁇ N light-emitting element chips 51 in groups by dividing the M ⁇ N light-emitting element chips 51 into N groups each formed of M chips.
  • FIG. 12B shows the case of driving the M ⁇ N light-emitting element chips 51 on a single chip basis.
  • FIGS. 12A and 12B show no line used in common for all the light-emitting element chips 51 , that is, neither a first clock signal bus line, a power supply bus line nor a reference voltage bus line.
  • the signal generating circuit 110 is not shown in FIGS. 12A and 12B .
  • # 11 to # 1 M of the light-emitting element chips 51 forms an A group
  • #N 1 to #NM of the light-emitting element chips 51 forms an N group.
  • N different second clock signals ⁇ 2 (the 2 — 1-th to 2_N-th clock signals ⁇ 2 _ 1 to ⁇ 2 _N) are used respectively for the different groups.
  • one of the second clock signals ⁇ 2 is supplied in common to the light-emitting element chips 51 belonging to the same group.
  • the light-emitting element chips 51 belonging to the same group are supplied with the respective different light-emission enable signals En (the first to M-th light-emission enable signals En 1 to EnM) and the respective different lighting signals ⁇ I (the first to M-th lighting signals ⁇ I 1 to ⁇ IM).
  • the light-emitting operations of all the M ⁇ N light-emitting element chips 51 are controlled in parallel, so that all the light-emitting thyristors Li assigned the same number in the respective light-emitting element chips 51 are controlled in parallel.
  • the number of signal bus lines required for supplying the second clock signals ⁇ 2 is N
  • the number of signal bus lines required for supplying the light-emission enable signals En is M
  • the number of signal bus lines required for supplying the lighting signals ⁇ I is M, too. Accordingly, the total required number of signal bus lines including a first clock signal bus line is 2M+N+1.
  • the expression that the light-emitting element chips 51 are driven on a single chip basis indicates a situation where all the light-emitting element chips 51 are caused to operate in numerical order so that a single light-emitting element chip 51 operates at a time, and where the light-emitting thyristors Li in each light-emitting element chip 51 are caused to operate in numerical order. Accordingly, in the case of driving the M ⁇ N light-emitting element chips 51 on a single chip basis, a light-emitting operation of one of the light-emitting thyristors Li of one of the light-emitting element chips 51 is controlled at a time.
  • the second clock signal ⁇ 2 is a data sequence formed of datasets that gives instructions to emit light or not to emit light to the respective light-emitting thyristors Li of the light-emitting element chips 51 in the light-emitting element head 90 .
  • the corresponding light-emission enable signal En is set to the L level. This allows each light-emitting element chip 51 to receive instruction datasets to emit light or not to emit light to the chip when the second clock signal ⁇ 2 reaches the chip while the chip is specified as the light-emission control target.
  • each light-emitting element chip 51 receives none of such instruction datasets to the other chips by setting the corresponding light-emission enable signal En to the H level.
  • a single second clock signal ⁇ 2 and a single lighting signal ⁇ I are used in common for all the light-emitting element chips 51 .
  • M ⁇ N different light-emission enable signals En that is, the first to M ⁇ N-th light-emission enable signals En 1 to EnM ⁇ N, are used respectively for the light-emitting element chips 51 .
  • the required number of light-emission enable signal bus lines is M ⁇ N, and thus the total required number of signal bus lines including first and second clock signal bus lines and a lighting signal bus line is M ⁇ N+3.
  • the number of signal bus lines is reduced in the case of driving the M ⁇ N light-emitting element chips 51 in groups as compared to the case of driving the M ⁇ N light-emitting element chips 51 on a single chip basis by M ⁇ N ⁇ (2M+N)+2.
  • the light-emitting element head 90 has 16 light-emitting element chips 51 divided into groups each formed of two chips, M is 2 and N is 8, so that the number of signal bus lines is 13. Meanwhile, in the case of driving the 16 light-emitting element chips 51 on a single chip basis, the number of signal bus lines is 19. Hence, driving the 16 light-emitting element chips 51 in groups leads to reduction of the signal bus lines by six.
  • the light-emitting element head 90 has 114 light-emitting element chips 51 divided into groups each formed of two chips, M is 2 and N is 57, so that the number of signal bus lines is 62. Meanwhile, in the case of driving the 114 light-emitting element chips 51 on a single chip basis, the number of signal bus lines is 117. Hence, driving the 114 light-emitting element chips 51 in groups leads to reduction of the signal bus lines by 55. As shown above, the measure of driving the light-emitting element chips 51 in groups leads to reduction of the signal bus lines by approximately half when applied to the light-emitting element head 90 having a large number of the light-emitting element chips 51 .
  • the common lighting signal ⁇ I is used in place of the first to M-th lighting signals ⁇ I 1 to ⁇ IM.
  • the number of signal bus lines required for supplying the second clock signals ⁇ 2 is N
  • the number of signal bus lines required for supplying the light-emission enable signals En is M
  • the number of signal bus lines required for supplying the lighting signals ⁇ I is 1. Accordingly, the total required number of signal bus lines including a first clock signal bus line is M+N+2.
  • the number of signal bus lines is reduced in the case of driving the M ⁇ N light-emitting element chips 51 in groups as compared to the case of driving the M ⁇ N light-emitting element chips 51 on a single chip basis by M ⁇ N ⁇ (M+N)+1.
  • the light-emitting element head 90 has 16 light-emitting element chips 51 divided into groups each formed of two chips, M is 2 and N is 8, so that the number of signal bus lines is 12. Meanwhile, in the case of driving the 16 light-emitting element chips 51 on a single chip basis, the number of signal bus lines is 19. Hence, driving the 16 light-emitting element chips 51 in groups leads to reduction of the signal bus lines by seven.
  • the light-emitting element head 90 has 114 light-emitting element chips 51 divided into groups each formed of two chips, M is 2 and N is 57, so that the number of signal bus lines is 61. Meanwhile, in the case of driving the 114 light-emitting element chips 51 on a single chip basis, the number of signal bus lines is 117. Hence, driving the 114 light-emitting element chips 51 in groups leads to reduction of the signal bus lines by 56. As shown above, the measure of driving the light-emitting element chips 51 in groups leads to reduction of the signal bus lines by approximately half when applied to the light-emitting element head 90 having a large number of the light-emitting element chips 51 .
  • the numbers calculated above such as the number of signal bus lines in the case of driving the light-emitting element chips 51 in groups, may be obtained for any other combination of: the number of the light-emitting element chips 51 belonging to each group; and the number of groups.
  • FIGS. 12A and 12B are provided in order to illustrate the effect of reducing the number of signal bus lines, and thus the M ⁇ N light-emitting element chips 51 are not arrayed in a zigzag pattern therein.
  • the light-emitting element head 90 as shown in FIG. 3B may be obtained by arraying the M ⁇ N light-emitting element chips 51 in a zigzag pattern, and by providing the signal bus lines on the basis of the connection relation shown in FIG. 12A or 12 B.
  • the number of light-emitting element chips 51 in each group is set to M herein. However, the number of light-emitting element chips 51 belonging to a group may vary among different groups. Alternatively, the number of light-emitting element chips 51 belonging to each group may be less than M.
  • each light-emitting element chip 51 have a single element set including the light-emitting thyristor array 102 , the transfer thyristor array 103 , the light-emission control thyristor array 104 and the light-emission enable thyristor Td.
  • each light-emitting element chip 51 may have multiple element sets.
  • each resistor Rp which is a parasitic resistance in the above exemplary embodiments, may be an additionally provided resister.
  • each of the light-emitting thyristors, the transfer thyristors, the light-emission control thyristors and the light-emission enable thyristor is a three-terminal thyristor having a pnpn structure whose anode electrode is supplied with the reference voltage Vsub.
  • Vsub the reference voltage
  • each of the light-emitting thyristors, the transfer thyristors, the light-emission control thyristors and the light-emission enable thyristor may be a three-terminal thyristor having an npnp structure with an anode electrode, a gate electrode and a cathode electrode that is supplied with the reference voltage Vsub.
  • the first clock signal ⁇ 1 is used as a first control signal for sequentially specifying the light-emitting thyristors L 1 , L 2 , L 3 , . . . , as targets for controlling whether or not to emit light
  • each second clock signal ⁇ 2 is used as a second control signal for giving an instruction to emit light or not to emit light to the light-emitting thyristors specified as the control target.
  • the second clock signal ⁇ 2 is also assigned a role as the first control signal of sequentially specifying the light-emitting thyristors L 1 , L 2 , L 3 , . . . , as targets for controlling whether or not to emit light.
  • the first and second control signals are not limited to these. Alternatively, two or more clock signals may be used as first control signals, or a second control signal may be provided as a separate signal from the one or more clock signals.
  • each light-emitting element chip 51 is not limited to that shown in FIG. 5 , either.
  • the connection relation among the elements such as the light-emitting thyristors, the transfer thyristors, the light-emission control thyristors and the light-emission enable thyristor, as well as the arrangement thereof, may be changed.
  • the light-emitting element chips 51 are formed of a GaAs-based semiconductor, but the material of the light-emitting element chips is not limited to this.
  • the light-emitting element chips 51 may be formed of another composite semiconductor, such as GaP, difficult to turn into a p-type semiconductor or an n-type semiconductor by ion implantation.

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JP4656227B2 (ja) 2011-03-23
CN101734021B (zh) 2013-08-07
EP2184172A1 (en) 2010-05-12
ATE494150T1 (de) 2011-01-15
EP2184172B1 (en) 2011-01-05

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